In spite of many errors that still need fixing, this is a major advance
over the previous commit. All verilog modules are in place more or less
as intended, with various functions such as the housekeeping SPI placed
on user area pads, with the ability to switch to user control from the
configuration. The pad control bits are local to the pads and loaded
via serial shift register, so that there are not hundreds of control wires
feeding into the user space. The user has three basic controls over each
pad: in, out, and outenb. Two timer/counters and an SPI master have been
added to the SoC. The SPI master shares I/O with the housekeeping SPI, so
that all housekeeping SPI registers can be accessed from the SoC directly.
diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h
index 68ef6b0..559151d 100644
--- a/verilog/dv/caravel/defs.h
+++ b/verilog/dv/caravel/defs.h
@@ -34,59 +34,67 @@
#define reg_la3_ena (*(volatile uint32_t*)0x2200001c)
// Mega Project Control (0x2300_0000)
-#define reg_mprj_io_0 (*(volatile uint32_t*)0x23000000)
-#define reg_mprj_io_1 (*(volatile uint32_t*)0x23000004)
-#define reg_mprj_io_2 (*(volatile uint32_t*)0x23000008)
-#define reg_mprj_io_3 (*(volatile uint32_t*)0x2300000c)
-#define reg_mprj_io_4 (*(volatile uint32_t*)0x23000010)
-#define reg_mprj_io_5 (*(volatile uint32_t*)0x23000014)
-#define reg_mprj_io_6 (*(volatile uint32_t*)0x23000018)
+#define reg_mprj_data (*(volatile uint32_t*)0x23000000)
+#define reg_mprj_xfer (*(volatile uint32_t*)0x23000004)
-#define reg_mprj_io_7 (*(volatile uint32_t*)0x2300001c)
-#define reg_mprj_io_8 (*(volatile uint32_t*)0x23000020)
-#define reg_mprj_io_9 (*(volatile uint32_t*)0x23000024)
-#define reg_mprj_io_10 (*(volatile uint32_t*)0x23000028)
+#define reg_mprj_io_0 (*(volatile uint32_t*)0x23000008)
+#define reg_mprj_io_1 (*(volatile uint32_t*)0x2300000c)
+#define reg_mprj_io_2 (*(volatile uint32_t*)0x23000010)
+#define reg_mprj_io_3 (*(volatile uint32_t*)0x23000014)
+#define reg_mprj_io_4 (*(volatile uint32_t*)0x23000018)
+#define reg_mprj_io_5 (*(volatile uint32_t*)0x2300001c)
+#define reg_mprj_io_6 (*(volatile uint32_t*)0x23000020)
-#define reg_mprj_io_11 (*(volatile uint32_t*)0x2300002c)
-#define reg_mprj_io_12 (*(volatile uint32_t*)0x23000030)
-#define reg_mprj_io_13 (*(volatile uint32_t*)0x23000034)
-#define reg_mprj_io_14 (*(volatile uint32_t*)0x23000038)
+#define reg_mprj_io_7 (*(volatile uint32_t*)0x23000024)
+#define reg_mprj_io_8 (*(volatile uint32_t*)0x23000028)
+#define reg_mprj_io_9 (*(volatile uint32_t*)0x2300002c)
+#define reg_mprj_io_10 (*(volatile uint32_t*)0x23000030)
-#define reg_mprj_io_15 (*(volatile uint32_t*)0x2300003c)
-#define reg_mprj_io_16 (*(volatile uint32_t*)0x23000040)
-#define reg_mprj_io_17 (*(volatile uint32_t*)0x23000044)
-#define reg_mprj_io_18 (*(volatile uint32_t*)0x23000048)
+#define reg_mprj_io_11 (*(volatile uint32_t*)0x23000034)
+#define reg_mprj_io_12 (*(volatile uint32_t*)0x23000038)
+#define reg_mprj_io_13 (*(volatile uint32_t*)0x2300003c)
+#define reg_mprj_io_14 (*(volatile uint32_t*)0x23000040)
-#define reg_mprj_io_19 (*(volatile uint32_t*)0x2300004c)
-#define reg_mprj_io_20 (*(volatile uint32_t*)0x23000050)
-#define reg_mprj_io_21 (*(volatile uint32_t*)0x23000054)
-#define reg_mprj_io_22 (*(volatile uint32_t*)0x23000058)
+#define reg_mprj_io_15 (*(volatile uint32_t*)0x23000044)
+#define reg_mprj_io_16 (*(volatile uint32_t*)0x23000048)
+#define reg_mprj_io_17 (*(volatile uint32_t*)0x2300004c)
+#define reg_mprj_io_18 (*(volatile uint32_t*)0x23000050)
-#define reg_mprj_io_23 (*(volatile uint32_t*)0x2300005c)
-#define reg_mprj_io_24 (*(volatile uint32_t*)0x23000060)
-#define reg_mprj_io_25 (*(volatile uint32_t*)0x23000064)
-#define reg_mprj_io_26 (*(volatile uint32_t*)0x23000068)
+#define reg_mprj_io_19 (*(volatile uint32_t*)0x23000054)
+#define reg_mprj_io_20 (*(volatile uint32_t*)0x23000058)
+#define reg_mprj_io_21 (*(volatile uint32_t*)0x2300005c)
+#define reg_mprj_io_22 (*(volatile uint32_t*)0x23000060)
-#define reg_mprj_io_27 (*(volatile uint32_t*)0x2300006c)
-#define reg_mprj_io_28 (*(volatile uint32_t*)0x23000070)
-#define reg_mprj_io_29 (*(volatile uint32_t*)0x23000074)
-#define reg_mprj_io_30 (*(volatile uint32_t*)0x23000078)
-#define reg_mprj_io_31 (*(volatile uint32_t*)0x2300007c)
+#define reg_mprj_io_23 (*(volatile uint32_t*)0x23000064)
+#define reg_mprj_io_24 (*(volatile uint32_t*)0x23000068)
+#define reg_mprj_io_25 (*(volatile uint32_t*)0x2300006c)
+#define reg_mprj_io_26 (*(volatile uint32_t*)0x23000070)
+
+#define reg_mprj_io_27 (*(volatile uint32_t*)0x23000074)
+#define reg_mprj_io_28 (*(volatile uint32_t*)0x23000078)
+#define reg_mprj_io_29 (*(volatile uint32_t*)0x2300007c)
+#define reg_mprj_io_30 (*(volatile uint32_t*)0x23000080)
+#define reg_mprj_io_31 (*(volatile uint32_t*)0x23000084)
// Mega Project Slaves (0x3000_0000)
#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
// Flash Control SPI Configuration (2D00_0000)
-#define reg_spictrl (*(volatile uint32_t*)0x2D000000)
+#define reg_spictrl (*(volatile uint32_t*)0x2d000000)
-// House-Keeping SPI Read-Only Registers (0x2E00_0000)
-#define reg_spi_config (*(volatile uint32_t*)0x2E000000)
-#define reg_spi_enables (*(volatile uint32_t*)0x2E000004)
-#define reg_spi_pll_config (*(volatile uint32_t*)0x2E000008)
-#define reg_spi_mfgr_id (*(volatile uint32_t*)0x2E00000c)
-#define reg_spi_prod_id (*(volatile uint32_t*)0x2E000010)
-#define reg_spi_mask_rev (*(volatile uint32_t*)0x2E000014)
-#define reg_spi_pll_bypass (*(volatile uint32_t*)0x2E000018)
+// Counter-Timer 0 Configuration
+#define reg_timer0_config (*(volatile uint32_t*)0x21100000)
+#define reg_timer0_value (*(volatile uint32_t*)0x21100004)
+#define reg_timer0_data (*(volatile uint32_t*)0x21100008)
+
+// Counter-Timer 1 Configuration
+#define reg_timer1_config (*(volatile uint32_t*)0x21200000)
+#define reg_timer1_value (*(volatile uint32_t*)0x21200004)
+#define reg_timer1_data (*(volatile uint32_t*)0x21200008)
+
+// SPI Master Configuration
+#define reg_spimaster_config (*(volatile uint32_t*)0x21300000)
+#define reg_spimaster_data (*(volatile uint32_t*)0x21300004)
// System Area (0x2F00_0000)
#define reg_pll_out_dest (*(volatile uint32_t*)0x2F00000c)
@@ -94,11 +102,22 @@
#define reg_irq7_source (*(volatile uint32_t*)0x2F000014)
#define reg_irq8_source (*(volatile uint32_t*)0x2F000018)
-// Crosbbar Slave Addresses (0x8000_0000 - 0xB000_0000)
+// Crossbar Slave Addresses (0x8000_0000 - 0xB000_0000)
#define qspi_ctrl_slave (*(volatile uint32_t*)0x80000000)
#define storage_area_slave (*(volatile uint32_t*)0x90000000)
#define mega_any_slave1 (*(volatile uint32_t*)0xA0000000)
#define mega_any_slave2 (*(volatile uint32_t*)0xB0000000)
+// Useful GPIO mode values
+#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
+#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0803
+#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c03
+#define GPIO_MODE_MGMT_STD_OUTPUT 0x1801
+
+#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
+#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0802
+#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c02
+#define GPIO_MODE_USER_STD_OUTPUT 0x1800
+
// --------------------------------------------------------
#endif
