In spite of many errors that still need fixing, this is a major advance
over the previous commit. All verilog modules are in place more or less
as intended, with various functions such as the housekeeping SPI placed
on user area pads, with the ability to switch to user control from the
configuration. The pad control bits are local to the pads and loaded
via serial shift register, so that there are not hundreds of control wires
feeding into the user space. The user has three basic controls over each
pad: in, out, and outenb. Two timer/counters and an SPI master have been
added to the SoC. The SPI master shares I/O with the housekeeping SPI, so
that all housekeeping SPI registers can be accessed from the SoC directly.
diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h
index 68ef6b0..559151d 100644
--- a/verilog/dv/caravel/defs.h
+++ b/verilog/dv/caravel/defs.h
@@ -34,59 +34,67 @@
#define reg_la3_ena (*(volatile uint32_t*)0x2200001c)
// Mega Project Control (0x2300_0000)
-#define reg_mprj_io_0 (*(volatile uint32_t*)0x23000000)
-#define reg_mprj_io_1 (*(volatile uint32_t*)0x23000004)
-#define reg_mprj_io_2 (*(volatile uint32_t*)0x23000008)
-#define reg_mprj_io_3 (*(volatile uint32_t*)0x2300000c)
-#define reg_mprj_io_4 (*(volatile uint32_t*)0x23000010)
-#define reg_mprj_io_5 (*(volatile uint32_t*)0x23000014)
-#define reg_mprj_io_6 (*(volatile uint32_t*)0x23000018)
+#define reg_mprj_data (*(volatile uint32_t*)0x23000000)
+#define reg_mprj_xfer (*(volatile uint32_t*)0x23000004)
-#define reg_mprj_io_7 (*(volatile uint32_t*)0x2300001c)
-#define reg_mprj_io_8 (*(volatile uint32_t*)0x23000020)
-#define reg_mprj_io_9 (*(volatile uint32_t*)0x23000024)
-#define reg_mprj_io_10 (*(volatile uint32_t*)0x23000028)
+#define reg_mprj_io_0 (*(volatile uint32_t*)0x23000008)
+#define reg_mprj_io_1 (*(volatile uint32_t*)0x2300000c)
+#define reg_mprj_io_2 (*(volatile uint32_t*)0x23000010)
+#define reg_mprj_io_3 (*(volatile uint32_t*)0x23000014)
+#define reg_mprj_io_4 (*(volatile uint32_t*)0x23000018)
+#define reg_mprj_io_5 (*(volatile uint32_t*)0x2300001c)
+#define reg_mprj_io_6 (*(volatile uint32_t*)0x23000020)
-#define reg_mprj_io_11 (*(volatile uint32_t*)0x2300002c)
-#define reg_mprj_io_12 (*(volatile uint32_t*)0x23000030)
-#define reg_mprj_io_13 (*(volatile uint32_t*)0x23000034)
-#define reg_mprj_io_14 (*(volatile uint32_t*)0x23000038)
+#define reg_mprj_io_7 (*(volatile uint32_t*)0x23000024)
+#define reg_mprj_io_8 (*(volatile uint32_t*)0x23000028)
+#define reg_mprj_io_9 (*(volatile uint32_t*)0x2300002c)
+#define reg_mprj_io_10 (*(volatile uint32_t*)0x23000030)
-#define reg_mprj_io_15 (*(volatile uint32_t*)0x2300003c)
-#define reg_mprj_io_16 (*(volatile uint32_t*)0x23000040)
-#define reg_mprj_io_17 (*(volatile uint32_t*)0x23000044)
-#define reg_mprj_io_18 (*(volatile uint32_t*)0x23000048)
+#define reg_mprj_io_11 (*(volatile uint32_t*)0x23000034)
+#define reg_mprj_io_12 (*(volatile uint32_t*)0x23000038)
+#define reg_mprj_io_13 (*(volatile uint32_t*)0x2300003c)
+#define reg_mprj_io_14 (*(volatile uint32_t*)0x23000040)
-#define reg_mprj_io_19 (*(volatile uint32_t*)0x2300004c)
-#define reg_mprj_io_20 (*(volatile uint32_t*)0x23000050)
-#define reg_mprj_io_21 (*(volatile uint32_t*)0x23000054)
-#define reg_mprj_io_22 (*(volatile uint32_t*)0x23000058)
+#define reg_mprj_io_15 (*(volatile uint32_t*)0x23000044)
+#define reg_mprj_io_16 (*(volatile uint32_t*)0x23000048)
+#define reg_mprj_io_17 (*(volatile uint32_t*)0x2300004c)
+#define reg_mprj_io_18 (*(volatile uint32_t*)0x23000050)
-#define reg_mprj_io_23 (*(volatile uint32_t*)0x2300005c)
-#define reg_mprj_io_24 (*(volatile uint32_t*)0x23000060)
-#define reg_mprj_io_25 (*(volatile uint32_t*)0x23000064)
-#define reg_mprj_io_26 (*(volatile uint32_t*)0x23000068)
+#define reg_mprj_io_19 (*(volatile uint32_t*)0x23000054)
+#define reg_mprj_io_20 (*(volatile uint32_t*)0x23000058)
+#define reg_mprj_io_21 (*(volatile uint32_t*)0x2300005c)
+#define reg_mprj_io_22 (*(volatile uint32_t*)0x23000060)
-#define reg_mprj_io_27 (*(volatile uint32_t*)0x2300006c)
-#define reg_mprj_io_28 (*(volatile uint32_t*)0x23000070)
-#define reg_mprj_io_29 (*(volatile uint32_t*)0x23000074)
-#define reg_mprj_io_30 (*(volatile uint32_t*)0x23000078)
-#define reg_mprj_io_31 (*(volatile uint32_t*)0x2300007c)
+#define reg_mprj_io_23 (*(volatile uint32_t*)0x23000064)
+#define reg_mprj_io_24 (*(volatile uint32_t*)0x23000068)
+#define reg_mprj_io_25 (*(volatile uint32_t*)0x2300006c)
+#define reg_mprj_io_26 (*(volatile uint32_t*)0x23000070)
+
+#define reg_mprj_io_27 (*(volatile uint32_t*)0x23000074)
+#define reg_mprj_io_28 (*(volatile uint32_t*)0x23000078)
+#define reg_mprj_io_29 (*(volatile uint32_t*)0x2300007c)
+#define reg_mprj_io_30 (*(volatile uint32_t*)0x23000080)
+#define reg_mprj_io_31 (*(volatile uint32_t*)0x23000084)
// Mega Project Slaves (0x3000_0000)
#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
// Flash Control SPI Configuration (2D00_0000)
-#define reg_spictrl (*(volatile uint32_t*)0x2D000000)
+#define reg_spictrl (*(volatile uint32_t*)0x2d000000)
-// House-Keeping SPI Read-Only Registers (0x2E00_0000)
-#define reg_spi_config (*(volatile uint32_t*)0x2E000000)
-#define reg_spi_enables (*(volatile uint32_t*)0x2E000004)
-#define reg_spi_pll_config (*(volatile uint32_t*)0x2E000008)
-#define reg_spi_mfgr_id (*(volatile uint32_t*)0x2E00000c)
-#define reg_spi_prod_id (*(volatile uint32_t*)0x2E000010)
-#define reg_spi_mask_rev (*(volatile uint32_t*)0x2E000014)
-#define reg_spi_pll_bypass (*(volatile uint32_t*)0x2E000018)
+// Counter-Timer 0 Configuration
+#define reg_timer0_config (*(volatile uint32_t*)0x21100000)
+#define reg_timer0_value (*(volatile uint32_t*)0x21100004)
+#define reg_timer0_data (*(volatile uint32_t*)0x21100008)
+
+// Counter-Timer 1 Configuration
+#define reg_timer1_config (*(volatile uint32_t*)0x21200000)
+#define reg_timer1_value (*(volatile uint32_t*)0x21200004)
+#define reg_timer1_data (*(volatile uint32_t*)0x21200008)
+
+// SPI Master Configuration
+#define reg_spimaster_config (*(volatile uint32_t*)0x21300000)
+#define reg_spimaster_data (*(volatile uint32_t*)0x21300004)
// System Area (0x2F00_0000)
#define reg_pll_out_dest (*(volatile uint32_t*)0x2F00000c)
@@ -94,11 +102,22 @@
#define reg_irq7_source (*(volatile uint32_t*)0x2F000014)
#define reg_irq8_source (*(volatile uint32_t*)0x2F000018)
-// Crosbbar Slave Addresses (0x8000_0000 - 0xB000_0000)
+// Crossbar Slave Addresses (0x8000_0000 - 0xB000_0000)
#define qspi_ctrl_slave (*(volatile uint32_t*)0x80000000)
#define storage_area_slave (*(volatile uint32_t*)0x90000000)
#define mega_any_slave1 (*(volatile uint32_t*)0xA0000000)
#define mega_any_slave2 (*(volatile uint32_t*)0xB0000000)
+// Useful GPIO mode values
+#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
+#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0803
+#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c03
+#define GPIO_MODE_MGMT_STD_OUTPUT 0x1801
+
+#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
+#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0802
+#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c02
+#define GPIO_MODE_USER_STD_OUTPUT 0x1800
+
// --------------------------------------------------------
#endif
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/README b/verilog/dv/caravel/mgmt_soc/gpio/README
new file mode 100644
index 0000000..f1935dd
--- /dev/null
+++ b/verilog/dv/caravel/mgmt_soc/gpio/README
@@ -0,0 +1,27 @@
+------------------------------------------------
+Caravel
+gpio testbench
+------------------------------------------------
+
+This testbench exercises the fundamental use of the Caravel
+management SoC to drive the I/O in the user area as general
+purpose I/O on startup.
+
+On startup, all GPIO are configured as input to the management
+region (so as to be high impedence to the external world) and
+decoupled from the user project area.
+
+To configure any GPIO as output, the appropriate memory-mapped
+location for the I/O must be properly configured. Since the
+I/O configuration is stored in two places, in the SoC, but
+also locally at each I/O pad, the "transfer" bit must be
+applied, which initiates a transfer of the configuration data
+around the padframe.
+
+The testbench takes 16 pins from the user area and checks
+functionality by applying input values on 8 of these pins from
+the testbench verilog, detecting them in the C program, then
+copying the values to the other 8 pins, and detecting those
+values in the testbench verilog.
+
+If any of that does not work, then the testbench will fail.
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio.c b/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
index 4dbacc6..bd6a17c 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
@@ -3,37 +3,96 @@
// --------------------------------------------------------
/*
- GPIO Test
- Tests PU and PD on the lower 2 pins while being driven from outside
- Tests Writing to the upper 2 pins
- Tests reading from the lower 2 pins
-*/
+ * GPIO Test
+ * Tests PU and PD on the lower 8 pins while being driven from outside
+ * Tests Writing to the upper 8 pins
+ * Tests reading from the lower 8 pins
+ */
+
void main()
{
int i;
- /* Lower 2 pins are input and upper 2 pins are o/p */
- reg_gpio_data = 0;
- reg_gpio_ena = 0x0003;
+ /* Set data out to zero */
+ reg_mprj_data = 0;
+
+ /* Lower 8 pins are input and upper 8 pins are output */
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ reg_mprj_xfer = 0;
// change the pull up and pull down (checked by the TB)
- reg_gpio_data = 0x0100;
- reg_gpio_pu = 0x0001;
- reg_gpio_pd = 0x0002;
+ reg_mprj_data = 0xa0000000;
- reg_gpio_data = 0x0300;
- reg_gpio_pu = 0x0002;
- reg_gpio_pd = 0x0001;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
- reg_gpio_pu = 0x0001;
- reg_gpio_pd = 0x0002;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
- // read the lower 2 pins, add 1 then o/p the result
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ reg_mprj_xfer = 0;
+
+ reg_mprj_data = 0x0b000000;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ reg_mprj_xfer = 0;
+
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
+
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ reg_mprj_xfer = 0;
+
+ // read the lower 8 pins, add 1 then o/p the result
// checked by the TB
- reg_gpio_data = 0x0100;
+ reg_mprj_data = 0xab000000;
+
while (1){
- int x = reg_gpio_data & 0x03;
- reg_gpio_data = (x+1) << 8;
+ int x = reg_mprj_data & 0xff0000;
+ reg_mprj_data = (x+1) << 24;
}
}
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio.hex b/verilog/dv/caravel/mgmt_soc/gpio/gpio.hex
index 667a214..adcdbdd 100755
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio.hex
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio.hex
@@ -6,7 +6,7 @@
13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00
13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00
13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00
-13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 45 16
+13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 45 3E
93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1
11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00
63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 71 28
@@ -20,12 +20,52 @@
23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC
FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08
A3 81 62 00 82 80 01 00 00 00 01 11 22 CE 00 10
-B7 07 00 21 23 A0 07 00 B7 07 00 21 91 07 0D 47
-98 C3 B7 07 00 21 13 07 00 10 98 C3 B7 07 00 21
-A1 07 05 47 98 C3 B7 07 00 21 B1 07 09 47 98 C3
-B7 07 00 21 13 07 00 30 98 C3 B7 07 00 21 A1 07
-09 47 98 C3 B7 07 00 21 B1 07 05 47 98 C3 B7 07
-00 21 A1 07 05 47 98 C3 B7 07 00 21 B1 07 09 47
-98 C3 B7 07 00 21 13 07 00 10 98 C3 B7 07 00 21
-9C 43 8D 8B 23 26 F4 FE 83 27 C4 FE 85 07 13 97
-87 00 B7 07 00 21 98 C3 D5 B7 00 00
+B7 07 00 23 23 A0 07 00 B7 07 00 23 93 87 47 08
+09 67 13 07 17 80 98 C3 B7 07 00 23 93 87 07 08
+09 67 13 07 17 80 98 C3 B7 07 00 23 93 87 C7 07
+09 67 13 07 17 80 98 C3 B7 07 00 23 93 87 87 07
+09 67 13 07 17 80 98 C3 B7 07 00 23 93 87 47 07
+09 67 13 07 17 80 98 C3 B7 07 00 23 93 87 07 07
+09 67 13 07 17 80 98 C3 B7 07 00 23 93 87 C7 06
+09 67 13 07 17 80 98 C3 B7 07 00 23 93 87 87 06
+09 67 13 07 17 80 98 C3 B7 07 00 23 93 87 47 06
+13 07 30 40 98 C3 B7 07 00 23 93 87 07 06 13 07
+30 40 98 C3 B7 07 00 23 93 87 C7 05 13 07 30 40
+98 C3 B7 07 00 23 93 87 87 05 13 07 30 40 98 C3
+B7 07 00 23 93 87 47 05 13 07 30 40 98 C3 B7 07
+00 23 93 87 07 05 13 07 30 40 98 C3 B7 07 00 23
+93 87 C7 04 13 07 30 40 98 C3 B7 07 00 23 93 87
+87 04 13 07 30 40 98 C3 B7 07 00 23 91 07 05 47
+98 C3 B7 07 00 23 91 07 23 A0 07 00 B7 07 00 23
+37 07 00 A0 98 C3 B7 07 00 23 93 87 47 06 05 67
+13 07 37 80 98 C3 B7 07 00 23 93 87 07 06 05 67
+13 07 37 80 98 C3 B7 07 00 23 93 87 C7 05 05 67
+13 07 37 80 98 C3 B7 07 00 23 93 87 87 05 05 67
+13 07 37 80 98 C3 B7 07 00 23 93 87 47 05 05 67
+13 07 37 C0 98 C3 B7 07 00 23 93 87 07 05 05 67
+13 07 37 C0 98 C3 B7 07 00 23 93 87 C7 04 05 67
+13 07 37 C0 98 C3 B7 07 00 23 93 87 87 04 05 67
+13 07 37 C0 98 C3 B7 07 00 23 91 07 05 47 98 C3
+B7 07 00 23 91 07 23 A0 07 00 B7 07 00 23 37 07
+00 0B 98 C3 B7 07 00 23 93 87 47 06 05 67 13 07
+37 C0 98 C3 B7 07 00 23 93 87 07 06 05 67 13 07
+37 C0 98 C3 B7 07 00 23 93 87 C7 05 05 67 13 07
+37 C0 98 C3 B7 07 00 23 93 87 87 05 05 67 13 07
+37 C0 98 C3 B7 07 00 23 93 87 47 05 05 67 13 07
+37 80 98 C3 B7 07 00 23 93 87 07 05 05 67 13 07
+37 80 98 C3 B7 07 00 23 93 87 C7 04 05 67 13 07
+37 80 98 C3 B7 07 00 23 93 87 87 04 05 67 13 07
+37 80 98 C3 B7 07 00 23 91 07 05 47 98 C3 B7 07
+00 23 91 07 23 A0 07 00 B7 07 00 23 93 87 47 06
+05 67 13 07 37 80 98 C3 B7 07 00 23 93 87 07 06
+05 67 13 07 37 80 98 C3 B7 07 00 23 93 87 C7 05
+05 67 13 07 37 80 98 C3 B7 07 00 23 93 87 87 05
+05 67 13 07 37 80 98 C3 B7 07 00 23 93 87 47 05
+05 67 13 07 37 C0 98 C3 B7 07 00 23 93 87 07 05
+05 67 13 07 37 C0 98 C3 B7 07 00 23 93 87 C7 04
+05 67 13 07 37 C0 98 C3 B7 07 00 23 93 87 87 04
+05 67 13 07 37 C0 98 C3 B7 07 00 23 91 07 05 47
+98 C3 B7 07 00 23 91 07 23 A0 07 00 B7 07 00 23
+37 07 00 AB 98 C3 B7 07 00 23 9C 43 3E 87 B7 07
+FF 00 F9 8F 23 26 F4 FE 83 27 C4 FE 85 07 13 97
+87 01 B7 07 00 23 98 C3 F9 BF 00 00
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index f823737..56781da 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -32,7 +32,7 @@
always #10 clock <= (clock === 1'b0);
initial begin
- clock = 0;
+ clock <= 0;
end
initial begin
@@ -64,7 +64,8 @@
wire flash_io1;
reg RSTB;
- wire CSB, SCK, SDI, SDO;
+ reg CSB, SCK, SDI;
+ wire SDO;
// Transactor
initial begin
@@ -99,6 +100,9 @@
end
initial begin
+ CSB <= 1'b1;
+ SCK <= 1'b0;
+ SDI <= 1'b0;
RSTB <= 1'b0;
#1000;
@@ -133,6 +137,9 @@
// apply {27'bz, SCK, CSB, SDI, SDO, 1'bz} to mprj_io (32 bits)
wire [11:0] noconnect;
+ wire [2:0] spi_sigs;
+
+ assign spi_sigs = 3'b010;
caravel uut (
.vdd3v3 (VDD3V3),
@@ -141,7 +148,8 @@
.clock (clock),
.gpio (gpio),
.mprj_io ({checkbits, noconnect[11:1],
- SCK, CSB, SDI, SDO, noconnect[0]}),
+ // SCK, CSB, SDI, SDO, noconnect[0]}),
+ spi_sigs, SDO, noconnect[0]}),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
