| Tim Edwards | c0cd7c2 | 2020-11-24 20:36:36 -0500 | [diff] [blame^] | 1 | * Simple testbench mainly to check SPICE model conversion from CDL |
| 2 | * Plots the transient response of the smallest inverter in the HD standard cell library |
| 3 | |
| 4 | .lib "/home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice" tt |
| 5 | .include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice" |
| 6 | |
| 7 | * .option TEMP=27 |
| 8 | |
| 9 | X0 in vss vss vdd vdd out sky130_fd_sc_hd__inv_1 |
| 10 | |
| 11 | V0 vdd vss PWL(0n 0.0 30n 1.8) |
| 12 | V1 vss 0 0.0 |
| 13 | |
| 14 | Vin in vss PWL(0n 0.0 100n 0.0 500n 1.8) |
| 15 | |
| 16 | * Transient analysis |
| 17 | .control |
| 18 | tran 1n 1u |
| 19 | plot V(in) V(out) |
| 20 | .endc |
| 21 | .end |
