Moved the simple_por ngspice simulations into directory ngspice/simple_por/.
Added new directory ngspice/digital_pll/ containing simulation testbenches for
the digital PLL and trimmable ring oscillator.  Added qflow directories for
both;  this was done only to get a valid xspice file for the controller and
a valid SPICE netlist for the ring oscillator.

ngspice/digital_pll/inverter_tb.spi

diff --git a/ngspice/digital_pll/inverter_tb.spi b/ngspice/digital_pll/inverter_tb.spi
new file mode 100644
index 0000000..bc57985
--- /dev/null
+++ b/ngspice/digital_pll/inverter_tb.spi
@@ -0,0 +1,21 @@
+* Simple testbench mainly to check SPICE model conversion from CDL
+* Plots the transient response of the smallest inverter in the HD standard cell library
+
+.lib "/home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
+.include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
+
+* .option TEMP=27
+
+X0 in vss vss vdd vdd out sky130_fd_sc_hd__inv_1
+
+V0 vdd vss PWL(0n 0.0 30n 1.8)
+V1 vss 0 0.0
+
+Vin in vss PWL(0n 0.0 100n 0.0 500n 1.8)
+
+* Transient analysis
+.control
+tran 1n 1u
+plot V(in) V(out)
+.endc
+.end