Matt Venn | 08cd6eb | 2020-11-16 12:01:14 +0100 | [diff] [blame^] | 1 | `default_nettype none |
Tim Edwards | 9eda80d | 2020-10-08 21:36:44 -0400 | [diff] [blame] | 2 | module mprj_io #( |
| 3 | parameter AREA1PADS = 18 // Highest numbered pad in area 1 |
| 4 | ) ( |
| 5 | inout vddio, |
| 6 | inout vssio, |
| 7 | inout vdda, |
| 8 | inout vssa, |
| 9 | inout vccd, |
| 10 | inout vssd, |
| 11 | |
| 12 | inout vdda1, |
| 13 | inout vdda2, |
| 14 | inout vssa1, |
| 15 | inout vssa2, |
| 16 | inout vccd1, |
| 17 | inout vccd2, |
| 18 | inout vssd1, |
| 19 | inout vssd2, |
| 20 | |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 21 | input vddio_q, |
| 22 | input vssio_q, |
| 23 | input analog_a, |
| 24 | input analog_b, |
Tim Edwards | 44bab47 | 2020-10-04 22:09:54 -0400 | [diff] [blame] | 25 | input porb_h, |
| 26 | input por, |
| 27 | inout [`MPRJ_IO_PADS-1:0] io, |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 28 | input [`MPRJ_IO_PADS-1:0] io_out, |
Tim Edwards | 44bab47 | 2020-10-04 22:09:54 -0400 | [diff] [blame] | 29 | input [`MPRJ_IO_PADS-1:0] oeb, |
shalan | 0d14e6e | 2020-08-31 16:50:48 +0200 | [diff] [blame] | 30 | input [`MPRJ_IO_PADS-1:0] hldh_n, |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 31 | input [`MPRJ_IO_PADS-1:0] enh, |
shalan | 0d14e6e | 2020-08-31 16:50:48 +0200 | [diff] [blame] | 32 | input [`MPRJ_IO_PADS-1:0] inp_dis, |
| 33 | input [`MPRJ_IO_PADS-1:0] ib_mode_sel, |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 34 | input [`MPRJ_IO_PADS-1:0] vtrip_sel, |
| 35 | input [`MPRJ_IO_PADS-1:0] slow_sel, |
| 36 | input [`MPRJ_IO_PADS-1:0] holdover, |
shalan | 0d14e6e | 2020-08-31 16:50:48 +0200 | [diff] [blame] | 37 | input [`MPRJ_IO_PADS-1:0] analog_en, |
| 38 | input [`MPRJ_IO_PADS-1:0] analog_sel, |
| 39 | input [`MPRJ_IO_PADS-1:0] analog_pol, |
| 40 | input [`MPRJ_IO_PADS*3-1:0] dm, |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 41 | output [`MPRJ_IO_PADS-1:0] io_in |
shalan | 0d14e6e | 2020-08-31 16:50:48 +0200 | [diff] [blame] | 42 | ); |
Tim Edwards | 9eda80d | 2020-10-08 21:36:44 -0400 | [diff] [blame] | 43 | |
| 44 | wire [`MPRJ_IO_PADS-1:0] loop1_io; |
| 45 | |
Tim Edwards | 4c73335 | 2020-10-12 16:32:36 -0400 | [diff] [blame] | 46 | sky130_ef_io__gpiov2_pad area1_io_pad [AREA1PADS - 1:0] ( |
Tim Edwards | 9eda80d | 2020-10-08 21:36:44 -0400 | [diff] [blame] | 47 | `USER1_ABUTMENT_PINS |
| 48 | `ifndef TOP_ROUTING |
Tim Edwards | 4c73335 | 2020-10-12 16:32:36 -0400 | [diff] [blame] | 49 | .PAD(io[AREA1PADS - 1:0]), |
Tim Edwards | 9eda80d | 2020-10-08 21:36:44 -0400 | [diff] [blame] | 50 | `endif |
Tim Edwards | 4c73335 | 2020-10-12 16:32:36 -0400 | [diff] [blame] | 51 | .OUT(io_out[AREA1PADS - 1:0]), |
| 52 | .OE_N(oeb[AREA1PADS - 1:0]), |
| 53 | .HLD_H_N(hldh_n[AREA1PADS - 1:0]), |
| 54 | .ENABLE_H(enh[AREA1PADS - 1:0]), |
| 55 | .ENABLE_INP_H(loop1_io[AREA1PADS - 1:0]), |
| 56 | .ENABLE_VDDA_H(porb_h), |
| 57 | .ENABLE_VSWITCH_H(vssio), |
| 58 | .ENABLE_VDDIO(vccd), |
| 59 | .INP_DIS(inp_dis[AREA1PADS - 1:0]), |
| 60 | .IB_MODE_SEL(ib_mode_sel[AREA1PADS - 1:0]), |
| 61 | .VTRIP_SEL(vtrip_sel[AREA1PADS - 1:0]), |
| 62 | .SLOW(slow_sel[AREA1PADS - 1:0]), |
| 63 | .HLD_OVR(holdover[AREA1PADS - 1:0]), |
| 64 | .ANALOG_EN(analog_en[AREA1PADS - 1:0]), |
| 65 | .ANALOG_SEL(analog_sel[AREA1PADS - 1:0]), |
| 66 | .ANALOG_POL(analog_pol[AREA1PADS - 1:0]), |
| 67 | .DM(dm[AREA1PADS*3 - 1:0]), |
| 68 | .PAD_A_NOESD_H(), |
| 69 | .PAD_A_ESD_0_H(), |
| 70 | .PAD_A_ESD_1_H(), |
| 71 | .IN(io_in[AREA1PADS - 1:0]), |
| 72 | .IN_H(), |
| 73 | .TIE_HI_ESD(), |
| 74 | .TIE_LO_ESD(loop1_io[AREA1PADS - 1:0]) |
Tim Edwards | 9eda80d | 2020-10-08 21:36:44 -0400 | [diff] [blame] | 75 | ); |
| 76 | |
Tim Edwards | 4c73335 | 2020-10-12 16:32:36 -0400 | [diff] [blame] | 77 | sky130_ef_io__gpiov2_pad area2_io_pad [`MPRJ_IO_PADS - AREA1PADS - 1:0] ( |
Tim Edwards | 9eda80d | 2020-10-08 21:36:44 -0400 | [diff] [blame] | 78 | `USER2_ABUTMENT_PINS |
| 79 | `ifndef TOP_ROUTING |
Tim Edwards | 4c73335 | 2020-10-12 16:32:36 -0400 | [diff] [blame] | 80 | .PAD(io[`MPRJ_IO_PADS - 1:AREA1PADS]), |
Tim Edwards | 9eda80d | 2020-10-08 21:36:44 -0400 | [diff] [blame] | 81 | `endif |
Tim Edwards | 4c73335 | 2020-10-12 16:32:36 -0400 | [diff] [blame] | 82 | .OUT(io_out[`MPRJ_IO_PADS - 1:AREA1PADS]), |
| 83 | .OE_N(oeb[`MPRJ_IO_PADS - 1:AREA1PADS]), |
| 84 | .HLD_H_N(hldh_n[`MPRJ_IO_PADS - 1:AREA1PADS]), |
| 85 | .ENABLE_H(enh[`MPRJ_IO_PADS - 1:AREA1PADS]), |
| 86 | .ENABLE_INP_H(loop1_io[`MPRJ_IO_PADS - 1:AREA1PADS]), |
| 87 | .ENABLE_VDDA_H(porb_h), |
| 88 | .ENABLE_VSWITCH_H(vssio), |
| 89 | .ENABLE_VDDIO(vccd), |
| 90 | .INP_DIS(inp_dis[`MPRJ_IO_PADS - 1:AREA1PADS]), |
| 91 | .IB_MODE_SEL(ib_mode_sel[`MPRJ_IO_PADS - 1:AREA1PADS]), |
| 92 | .VTRIP_SEL(vtrip_sel[`MPRJ_IO_PADS - 1:AREA1PADS]), |
| 93 | .SLOW(slow_sel[`MPRJ_IO_PADS - 1:AREA1PADS]), |
| 94 | .HLD_OVR(holdover[`MPRJ_IO_PADS - 1:AREA1PADS]), |
| 95 | .ANALOG_EN(analog_en[`MPRJ_IO_PADS - 1:AREA1PADS]), |
| 96 | .ANALOG_SEL(analog_sel[`MPRJ_IO_PADS - 1:AREA1PADS]), |
| 97 | .ANALOG_POL(analog_pol[`MPRJ_IO_PADS - 1:AREA1PADS]), |
| 98 | .DM(dm[`MPRJ_IO_PADS*3 - 1:AREA1PADS*3]), |
| 99 | .PAD_A_NOESD_H(), |
| 100 | .PAD_A_ESD_0_H(), |
| 101 | .PAD_A_ESD_1_H(), |
| 102 | .IN(io_in[`MPRJ_IO_PADS - 1:AREA1PADS]), |
| 103 | .IN_H(), |
| 104 | .TIE_HI_ESD(), |
| 105 | .TIE_LO_ESD(loop1_io[`MPRJ_IO_PADS - 1:AREA1PADS]) |
Tim Edwards | 9eda80d | 2020-10-08 21:36:44 -0400 | [diff] [blame] | 106 | ); |
shalan | 0d14e6e | 2020-08-31 16:50:48 +0200 | [diff] [blame] | 107 | |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 108 | endmodule |