blob: 124dbcda84bfabd85033a88558b42de446c75558 [file] [log] [blame]
Ganesh Gore18c630b2020-12-16 16:55:54 -07001# Run VPR for the 'and' design
2#--write_rr_graph example_rr_graph.xml
3vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --route_chan_width 200
4
5# Read OpenFPGA architecture definition
6read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
7
8# Read OpenFPGA simulation settings
9read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
10
11# Annotate the OpenFPGA architecture to VPR data base
12# to debug use --verbose options
13link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
14
15# Check and correct any naming conflicts in the BLIF netlist
16check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
17
18# Apply fix-up to clustering nets based on routing results
19pb_pin_fixup --verbose
20
21# Apply fix-up to Look-Up Table truth tables based on packing results
22lut_truth_table_fixup
23
24# Build the module graph
25# - Enabled compression on routing architecture modules
26# - Enable pin duplication on grid modules
27build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE}
28
29# Write the fabric hierarchy of module graph to a file
30# This is used by hierarchical PnR flows
31write_fabric_hierarchy --file ./fabric_hierarchy.txt
32
33# Repack the netlist to physical pbs
34# This must be done before bitstream generator and testbench generation
35# Strongly recommend it is done after all the fix-up have been applied
36repack #--verbose
37
38# Build the bitstream
39# - Output the fabric-independent bitstream to a file
40build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml
41
42build_fabric_bitstream
43
44# Build fabric-dependent bitstream
45build_fabric_bitstream
46write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
47write_fabric_bitstream --format xml --file fabric_bitstream.xml
48# Write the Verilog testbench for FPGA fabric
49# - We suggest the use of same output directory as fabric Verilog netlists
50# - Must specify the reference benchmark file if you want to output any testbenches
51# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
52# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
53# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
54write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
55
56# Write the SDC files for PnR backend
57# - Turn on every options here
58write_pnr_sdc --file ./SDC
59
60# Write SDC to disable timing for configure ports
61write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
62
63# Write the SDC to run timing analysis for a mapped FPGA fabric
64write_analysis_sdc --file ./SDC_analysis
65
66# Finish and exit OpenFPGA
67exit
68
69# Note :
70# To run verification at the end of the flow maintain source in ./SRC directory