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Matt Venn08cd6eb2020-11-16 12:01:14 +01001`default_nettype none
Tim Edwardscd64af52020-08-07 11:11:58 -04002// Tunable ring oscillator---synthesizable (physical) version.
3//
4// NOTE: This netlist cannot be simulated correctly due to lack
5// of accurate timing in the digital cell verilog models.
6
7module delay_stage(in, trim, out);
8 input in;
9 input [1:0] trim;
10 output out;
11
Tim Edwards581068f2020-11-19 12:45:25 -050012 wire d0, d1, d2, ts;
Tim Edwardscd64af52020-08-07 11:11:58 -040013
Tim Edwardsef8312e2020-09-22 17:20:06 -040014 sky130_fd_sc_hd__clkbuf_2 delaybuf0 (
Tim Edwardscd64af52020-08-07 11:11:58 -040015 .A(in),
16 .X(ts)
17 );
18
Tim Edwardsef8312e2020-09-22 17:20:06 -040019 sky130_fd_sc_hd__clkbuf_1 delaybuf1 (
Tim Edwardscd64af52020-08-07 11:11:58 -040020 .A(ts),
21 .X(d0)
22 );
23
Tim Edwardsef8312e2020-09-22 17:20:06 -040024 sky130_fd_sc_hd__einvp_2 delayen1 (
Tim Edwardscd64af52020-08-07 11:11:58 -040025 .A(d0),
26 .TE(trim[1]),
27 .Z(d1)
28 );
29
Tim Edwardsef8312e2020-09-22 17:20:06 -040030 sky130_fd_sc_hd__einvn_4 delayenb1 (
Tim Edwardscd64af52020-08-07 11:11:58 -040031 .A(ts),
Tim Edwardsc5265b82020-09-25 17:08:59 -040032 .TE_B(trim[1]),
Tim Edwardscd64af52020-08-07 11:11:58 -040033 .Z(d1)
34 );
35
Tim Edwardsef8312e2020-09-22 17:20:06 -040036 sky130_fd_sc_hd__clkinv_1 delayint0 (
Tim Edwardscd64af52020-08-07 11:11:58 -040037 .A(d1),
38 .Y(d2)
39 );
40
Tim Edwardsef8312e2020-09-22 17:20:06 -040041 sky130_fd_sc_hd__einvp_2 delayen0 (
Tim Edwardscd64af52020-08-07 11:11:58 -040042 .A(d2),
43 .TE(trim[0]),
44 .Z(out)
45 );
46
Tim Edwardsef8312e2020-09-22 17:20:06 -040047 sky130_fd_sc_hd__einvn_8 delayenb0 (
Tim Edwardscd64af52020-08-07 11:11:58 -040048 .A(ts),
Tim Edwardsc5265b82020-09-25 17:08:59 -040049 .TE_B(trim[0]),
Tim Edwardscd64af52020-08-07 11:11:58 -040050 .Z(out)
51 );
52
53endmodule
54
55module start_stage(in, trim, reset, out);
56 input in;
57 input [1:0] trim;
58 input reset;
59 output out;
60
61 wire d0, d1, d2, ctrl0, one;
62
Tim Edwardsef8312e2020-09-22 17:20:06 -040063 sky130_fd_sc_hd__clkbuf_1 delaybuf0 (
Tim Edwardscd64af52020-08-07 11:11:58 -040064 .A(in),
65 .X(d0)
66 );
67
Tim Edwardsef8312e2020-09-22 17:20:06 -040068 sky130_fd_sc_hd__einvp_2 delayen1 (
Tim Edwardscd64af52020-08-07 11:11:58 -040069 .A(d0),
70 .TE(trim[1]),
71 .Z(d1)
72 );
73
Tim Edwardsef8312e2020-09-22 17:20:06 -040074 sky130_fd_sc_hd__einvn_4 delayenb1 (
Tim Edwardscd64af52020-08-07 11:11:58 -040075 .A(in),
Tim Edwardsc5265b82020-09-25 17:08:59 -040076 .TE_B(trim[1]),
Tim Edwardscd64af52020-08-07 11:11:58 -040077 .Z(d1)
78 );
79
Tim Edwardsef8312e2020-09-22 17:20:06 -040080 sky130_fd_sc_hd__clkinv_1 delayint0 (
Tim Edwardscd64af52020-08-07 11:11:58 -040081 .A(d1),
82 .Y(d2)
83 );
84
Tim Edwardsef8312e2020-09-22 17:20:06 -040085 sky130_fd_sc_hd__einvp_2 delayen0 (
Tim Edwardscd64af52020-08-07 11:11:58 -040086 .A(d2),
87 .TE(trim[0]),
88 .Z(out)
89 );
90
Tim Edwardsef8312e2020-09-22 17:20:06 -040091 sky130_fd_sc_hd__einvn_8 delayenb0 (
Tim Edwardscd64af52020-08-07 11:11:58 -040092 .A(in),
Tim Edwardsc5265b82020-09-25 17:08:59 -040093 .TE_B(ctrl0),
Tim Edwardscd64af52020-08-07 11:11:58 -040094 .Z(out)
95 );
96
Tim Edwardsef8312e2020-09-22 17:20:06 -040097 sky130_fd_sc_hd__einvp_1 reseten0 (
Tim Edwardscd64af52020-08-07 11:11:58 -040098 .A(one),
99 .TE(reset),
100 .Z(out)
101 );
102
Tim Edwardsef8312e2020-09-22 17:20:06 -0400103 sky130_fd_sc_hd__or2_2 ctrlen0 (
Tim Edwardscd64af52020-08-07 11:11:58 -0400104 .A(reset),
105 .B(trim[0]),
106 .X(ctrl0)
107 );
108
Tim Edwardsef8312e2020-09-22 17:20:06 -0400109 sky130_fd_sc_hd__conb_1 const1 (
Tim Edwardscd64af52020-08-07 11:11:58 -0400110 .HI(one),
111 .LO()
112 );
113
114endmodule
115
116// Ring oscillator with 13 stages, each with two trim bits delay
117// (see above). Trim is not binary: For trim[1:0], lower bit
118// trim[0] is primary trim and must be applied first; upper
119// bit trim[1] is secondary trim and should only be applied
120// after the primary trim is applied, or it has no effect.
121//
122// Total effective number of inverter stages in this oscillator
123// ranges from 13 at trim 0 to 65 at trim 24. The intention is
124// to cover a range greater than 2x so that the midrange can be
125// reached over all PVT conditions.
126//
127// Frequency of this ring oscillator under SPICE simulations at
128// nominal PVT is maximum 214 MHz (trim 0), minimum 90 MHz (trim 24).
129
130module ring_osc2x13(reset, trim, clockp);
131 input reset;
132 input [25:0] trim;
133 output[1:0] clockp;
134
Tim Edwardsbb3cd692020-10-09 22:00:23 -0400135`ifdef FUNCTIONAL // i.e., behavioral model below
136
137 reg [1:0] clockp;
138 reg hiclock;
139 integer i;
140 real delay;
141 wire [5:0] bcount;
142
143 assign bcount = trim[0] + trim[1] + trim[2]
144 + trim[3] + trim[4] + trim[5] + trim[6] + trim[7]
145 + trim[8] + trim[9] + trim[10] + trim[11] + trim[12]
146 + trim[13] + trim[14] + trim[15] + trim[16] + trim[17]
147 + trim[18] + trim[19] + trim[20] + trim[21] + trim[22]
148 + trim[23] + trim[24] + trim[25];
149
150 initial begin
151 hiclock <= 1'b0;
152 delay = 3.0;
153 end
154
155 // Fastest operation is 214 MHz = 4.67ns
156 // Delay per trim is 0.02385
157 // Run "hiclock" at 2x this rate, then use positive and negative
158 // edges to derive the 0 and 90 degree phase clocks.
159
160 always #delay begin
161 hiclock <= (hiclock === 1'b0);
162 end
163
164 always @(trim) begin
165 // Implement trim as a variable delay, one delay per trim bit
166 delay = 1.168 + 0.012 * $itor(bcount);
167 end
168
169 always @(posedge hiclock or posedge reset) begin
170 if (reset == 1'b1) begin
171 clockp[0] <= 1'b0;
172 end else begin
173 clockp[0] <= (clockp[0] === 1'b0);
174 end
175 end
176
177 always @(negedge hiclock or posedge reset) begin
178 if (reset == 1'b1) begin
179 clockp[1] <= 1'b0;
180 end else begin
181 clockp[1] <= (clockp[1] === 1'b0);
182 end
183 end
184
185`else // !FUNCTIONAL; i.e., gate level netlist below
186
Tim Edwardscd64af52020-08-07 11:11:58 -0400187 wire [1:0] clockp;
Tim Edwardsbb3cd692020-10-09 22:00:23 -0400188 wire [12:0] d;
Tim Edwardscd64af52020-08-07 11:11:58 -0400189 wire [1:0] c;
190
191 // Main oscillator loop stages
192
193 genvar i;
194 generate
195 for (i = 0; i < 12; i = i + 1) begin : dstage
196 delay_stage id (
197 .in(d[i]),
198 .trim({trim[i+13], trim[i]}),
199 .out(d[i+1])
200 );
201 end
202 endgenerate
203
204 // Reset/startup stage
205
206 start_stage iss (
207 .in(d[12]),
208 .trim({trim[25], trim[12]}),
209 .reset(reset),
210 .out(d[0])
211 );
212
213 // Buffered outputs a 0 and 90 degrees phase (approximately)
214
Tim Edwardsef8312e2020-09-22 17:20:06 -0400215 sky130_fd_sc_hd__clkinv_2 ibufp00 (
Tim Edwardscd64af52020-08-07 11:11:58 -0400216 .A(d[0]),
217 .Y(c[0])
218 );
Tim Edwardsef8312e2020-09-22 17:20:06 -0400219 sky130_fd_sc_hd__clkinv_8 ibufp01 (
Tim Edwardscd64af52020-08-07 11:11:58 -0400220 .A(c[0]),
221 .Y(clockp[0])
222 );
Tim Edwardsef8312e2020-09-22 17:20:06 -0400223 sky130_fd_sc_hd__clkinv_2 ibufp10 (
Tim Edwardscd64af52020-08-07 11:11:58 -0400224 .A(d[6]),
225 .Y(c[1])
226 );
Tim Edwardsef8312e2020-09-22 17:20:06 -0400227 sky130_fd_sc_hd__clkinv_8 ibufp11 (
Tim Edwardscd64af52020-08-07 11:11:58 -0400228 .A(c[1]),
229 .Y(clockp[1])
230 );
231
Tim Edwardsbb3cd692020-10-09 22:00:23 -0400232`endif // !FUNCTIONAL
233
Tim Edwardscd64af52020-08-07 11:11:58 -0400234endmodule
Tim Edwards581068f2020-11-19 12:45:25 -0500235`default_nettype wire