Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-001
/
slot-015
/
268de7250086afccd29be9c0c7f421866abfae0e
/
verilog
/
rtl
/
ring_osc2x13.v
581068f
Corrected the mess caused by introducing default_nettype none into the design
by Tim Edwards
· 4 years, 2 months ago
08cd6eb
add default nettype none
by Matt Venn
· 4 years, 2 months ago
bb3cd69
Added a behavioral model for the ring oscillator, and a testbench
by Tim Edwards
· 4 years, 3 months ago
c5265b8
Corrected some things from the initial pass of removing unused GPIO
by Tim Edwards
· 4 years, 4 months ago
ef8312e
Caravel 2nd phase (branch phase2): First pass at removing the analog
by Tim Edwards
· 4 years, 4 months ago
fd13eb5
initial commit
by shalan
· 4 years, 5 months ago
cd64af5
Started adding RTL for the Caravel project
by Tim Edwards
· 4 years, 6 months ago