| Ahmed Ghazy | 7215439 | 2020-11-11 14:56:52 +0200 | [diff] [blame^] | 1 | set script_dir [file dirname [file normalize [info script]]] |
| 2 | |||||
| 3 | set ::env(DESIGN_NAME) user_proj_example | ||||
| 4 | |||||
| 5 | set ::env(VERILOG_FILES) "\ | ||||
| 6 | $script_dir/../../verilog/rtl/defines.v \ | ||||
| 7 | $script_dir/../../verilog/rtl/user_proj_example.v" | ||||
| 8 | |||||
| 9 | set ::env(CLOCK_NET) "counter.clk" | ||||
| 10 | set ::env(CLOCK_PERIOD) "10" | ||||
| 11 | |||||
| 12 | set ::env(FP_SIZING) absolute | ||||
| 13 | set ::env(DIE_AREA) "0 0 250 250" | ||||
| 14 | set ::env(PL_BASIC_PLACEMENT) 1 | ||||
| 15 | set ::env(PL_TARGET_DENSITY) 0.15 | ||||