Update and add the rest of design configs
- Some are placeholders for macros that will be hand-designed
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
new file mode 100644
index 0000000..5528fc9
--- /dev/null
+++ b/openlane/user_proj_example/config.tcl
@@ -0,0 +1,15 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) user_proj_example
+
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/user_proj_example.v"
+
+set ::env(CLOCK_NET) "counter.clk"
+set ::env(CLOCK_PERIOD) "10"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 250 250"
+set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(PL_TARGET_DENSITY) 0.15
