iverilog does not like registers named 'config', though other verilog tools don't seem to have a problem with it
diff --git a/test/README.md b/test/README.md
index 12954f4..ad9f7dc 100644
--- a/test/README.md
+++ b/test/README.md
@@ -27,4 +27,6 @@
### test003ycconfig.v
-This tests the configuration circuit by manually shifting in 3 bits at a time and listing the outputs
+This tests the configuration circuit by manually shifting in 3 bits at a time and listing the outputs. It adds a comment about which state the configuration is in after the 3 bits.
+
+A second configuration circuit is cascaded with the first in this test. Every time the first circuit has a valid configuration, the second one should have the previous valid configuration of the first circuit.
diff --git a/test/test003ycconfig.v b/test/test003ycconfig.v
index 320a210..068aeac 100644
--- a/test/test003ycconfig.v
+++ b/test/test003ycconfig.v
@@ -30,12 +30,21 @@
empty,
hblock, hbypass, hmatch0, hmatch1,
vblock, vbypass, vmatch0, vmatch1);
- wire [9:0] ans;
- assign ans = {cbitout, empty,
- hblock, hbypass, hmatch0, hmatch1,
- vblock, vbypass, vmatch0, vmatch1};
+ // adds a second device cascade with the main one being tested to
+ // see if the expected timing (always holds the previous configuration
+ // of the first device) is present
+ wire cbitout2;
+ wire empty2;
+ wire hblock2, hbypass2, hmatch02, hmatch12;
+ wire vblock2, vbypass2, vmatch02, vmatch12;
+
+ ycconfig DUT2 (confclk, cbitout, cbitout2,
+ empty2,
+ hblock2, hbypass2, hmatch02, hmatch12,
+ vblock2, vbypass2, vmatch02, vmatch12);
+
initial
begin
confclk = 0; cbitin = 0;
@@ -57,12 +66,70 @@
#10 cbitin = 1; // lsb
#10 confclk = 1;
#10 confclk = 0; $display("configuration = +");
+ #10 cbitin = 0; // msb
+ #10 confclk = 1;
+ #10 confclk = 0;
+ #10 cbitin = 1;
+ #10 confclk = 1;
+ #10 confclk = 0;
+ #10 cbitin = 0; // lsb
+ #10 confclk = 1;
+ #10 confclk = 0; $display("configuration = -");
+ #10 cbitin = 0; // msb
+ #10 confclk = 1;
+ #10 confclk = 0;
+ #10 cbitin = 1;
+ #10 confclk = 1;
+ #10 confclk = 0;
+ #10 cbitin = 1; // lsb
+ #10 confclk = 1;
+ #10 confclk = 0; $display("configuration = |");
+ #10 cbitin = 1; // msb
+ #10 confclk = 1;
+ #10 confclk = 0;
+ #10 cbitin = 0;
+ #10 confclk = 1;
+ #10 confclk = 0;
+ #10 cbitin = 0; // lsb
+ #10 confclk = 1;
+ #10 confclk = 0; $display("configuration = 1");
+ #10 cbitin = 1; // msb
+ #10 confclk = 1;
+ #10 confclk = 0;
+ #10 cbitin = 0;
+ #10 confclk = 1;
+ #10 confclk = 0;
+ #10 cbitin = 1; // lsb
+ #10 confclk = 1;
+ #10 confclk = 0; $display("configuration = 0");
+ #10 cbitin = 1; // msb
+ #10 confclk = 1;
+ #10 confclk = 0;
+ #10 cbitin = 1;
+ #10 confclk = 1;
+ #10 confclk = 0;
+ #10 cbitin = 0; // lsb
+ #10 confclk = 1;
+ #10 confclk = 0; $display("configuration = Y");
+ #10 cbitin = 1; // msb
+ #10 confclk = 1;
+ #10 confclk = 0;
+ #10 cbitin = 1;
+ #10 confclk = 1;
+ #10 confclk = 0;
+ #10 cbitin = 1; // lsb
+ #10 confclk = 1;
+ #10 confclk = 0; $display("configuration = N");
#10;
end
initial
- $monitor($time,,confclk,,cbitin,,ans);
+ $monitor($time,,confclk,cbitin,cbitout,,empty,,
+ hblock, hbypass, hmatch0, hmatch1,,
+ vblock, vbypass, vmatch0, vmatch1,,
+ cbitout2,,empty2,,
+ hblock2, hbypass2, hmatch02, hmatch12,,
+ vblock2, vbypass2, vmatch02, vmatch12);
- end
endmodule
diff --git a/verilog/morphlelogic.v b/verilog/morphlelogic.v
index 4496743..88f59d8 100644
--- a/verilog/morphlelogic.v
+++ b/verilog/morphlelogic.v
@@ -89,12 +89,12 @@
assign {empty,hblock,hbypass, hmatch0, hmatch1,
vblock, vbypass, vmatch0, vmatch1} = r;
- reg [2:0] config;
- always @(posedge confclk) config = {config[1:0],cbitin}; // shift to msb
- assign cbitout = config[2]; // shifted to next cell
+ reg [2:0] cnfg;
+ always @(posedge confclk) cnfg = {cnfg[1:0],cbitin}; // shift to msb
+ assign cbitout = cnfg[2]; // shifted to next cell
- always @(config)
- case(config)
+ always @(cnfg)
+ case(cnfg)
3'b000: r = 9'b110001000; // space is empty and blocked
3'b001: r = 9'b000110011; // + sync with don't cares
3'b010: r = 9'b001001000; // - horizontal short circuit
