Update config.tcl for user wrapper
diff --git a/.gitmodules b/.gitmodules index 5398bb7..a3e724d 100644 --- a/.gitmodules +++ b/.gitmodules
@@ -1,3 +1,3 @@ -[submodule "verilog/rtl/hs32cpu"] - path = verilog/rtl/hs32cpu - url = https://github.com/HomebrewSiliconClub/hs32core-rtl +[submodule "verilog/rtl/hs32cpu"] + path = verilog/rtl/hs32cpu + url = https://github.com/hsc-latte/hs32core-rtl.git
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index e60639f..b6442e1 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -1,106 +1,53 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -# Base Configurations. Don't Touch -# section begin -set script_dir [file dirname [file normalize [info script]]] -set ::env(DESIGN_NAME) user_project_wrapper -#section end - - -# User Configurations - -## Source Verilog Files -set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_project_wrapper.v" - -## Clock configurations -set ::env(CLOCK_PORT) "user_clock2" -set ::env(CLOCK_NET) "mprj.clk" - -set ::env(CLOCK_PERIOD) "10" - -## Internal Macros -### Macro Placement -set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg - -### Black-box verilog and views -set ::env(VERILOG_FILES_BLACKBOX) "\ - $script_dir/../../verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_proj_example.v" - -set ::env(EXTRA_LEFS) "\ - $script_dir/../../lef/user_proj_example.lef" - -set ::env(EXTRA_GDS_FILES) "\ - $script_dir/../../gds/user_proj_example.gds" - - -# The following is because there are no std cells in the example wrapper project. -set ::env(SYNTH_TOP_LEVEL) 1 -set ::env(PL_RANDOM_GLB_PLACEMENT) 1 -set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0 -set ::env(DIODE_INSERTION_STRATEGY) 0 -set ::env(FILL_INSERTION) 0 -set ::env(TAP_DECAP_INSERTION) 0 -set ::env(CLOCK_TREE_SYNTH) 0 - - -# DON'T TOUCH THE FOLLOWING SECTIONS - -# This makes sure that the core rings are outside the boundaries -# of your block. -set ::env(MAGIC_ZEROIZE_ORIGIN) 0 - -# Area Configurations. DON'T TOUCH. -set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 2920 3520" - -# Power & Pin Configurations. DON'T TOUCH. -set ::env(FP_PDN_CORE_RING) 1 -set ::env(FP_PDN_CORE_RING_VWIDTH) 3 -set ::env(FP_PDN_CORE_RING_HWIDTH) $::env(FP_PDN_CORE_RING_VWIDTH) -set ::env(FP_PDN_CORE_RING_VOFFSET) 14 -set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET) -set ::env(FP_PDN_CORE_RING_VSPACING) 1.7 -set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING) - -set ::env(FP_PDN_VWIDTH) 3 -set ::env(FP_PDN_HWIDTH) 3 -set ::env(FP_PDN_VOFFSET) 0 -set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET) -set ::env(FP_PDN_VPITCH) 180 -set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH) -set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)] -set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)] - -set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}] -set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}] -set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS" - -set ::env(RUN_CVC) 0 - -# Pin Configurations. DON'T TOUCH -set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg -set ::env(FP_DEF_TEMPLATE) $script_dir/../../def/user_project_wrapper_empty.def -set ::unit 2.4 -set ::env(FP_IO_VEXTEND) [expr 2*$::unit] -set ::env(FP_IO_HEXTEND) [expr 2*$::unit] -set ::env(FP_IO_VLENGTH) $::unit -set ::env(FP_IO_HLENGTH) $::unit - -set ::env(FP_IO_VTHICKNESS_MULT) 4 -set ::env(FP_IO_HTHICKNESS_MULT) 4 +set script_dir [file dirname [file normalize [info script]]] + +set ::env(ROUTING_CORES) 16 + +set ::env(DESIGN_NAME) user_project_wrapper +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg + +set ::env(PDN_CFG) $script_dir/pdn.tcl +set ::env(FP_PDN_CORE_RING) 1 +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 2920 3520" + +set ::unit 2.4 +set ::env(FP_IO_VEXTEND) [expr 2*$::unit] +set ::env(FP_IO_HEXTEND) [expr 2*$::unit] +set ::env(FP_IO_VLENGTH) $::unit +set ::env(FP_IO_HLENGTH) $::unit + +set ::env(FP_IO_VTHICKNESS_MULT) 4 +set ::env(FP_IO_HTHICKNESS_MULT) 4 + +set ::env(CLOCK_PORT) "user_clock2" +set ::env(CLOCK_NET) "core1.wb_clk_i" + +set ::env(CLOCK_PERIOD) "20" + +set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0 +set ::env(DIODE_INSERTION_STRATEGY) 1 + +# Because of sram +set ::env(MAGIC_DRC_USE_GDS) 0 + +# Need to fix a FastRoute bug for this to work, but it's good +# for a sense of "isolation" +set ::env(MAGIC_ZEROIZE_ORIGIN) 0 +set ::env(MAGIC_WRITE_FULL_LEF) 1 + +set ::env(VERILOG_FILES) "\ + $script_dir/../../verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/hs32_user_proj/hs32_wrapper.v" + +set ::env(VERILOG_FILES_BLACKBOX) "\ + $script_dir/../../verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/hs32_user_proj/hs32_core1.v \ + $script_dir/../../verilog/rtl/sram_1rw1r_32_256_8_sky130.v" + +set ::env(EXTRA_LEFS) "\ + $script_dir/../../lef/hs32_core1.lef \ + $script_dir/../../macros/lef/sram_1rw1r_32_256_8_sky130_lp1.lef" + +set ::env(EXTRA_GDS_FILES) "\ + $script_dir/../../gds/hs32_core1.gds \ + $script_dir/../../macros/gds/sram_1rw1r_32_256_8_sky130.gds"
diff --git a/openlane/user_project_wrapper/gen_pdn.tcl b/openlane/user_project_wrapper/gen_pdn.tcl new file mode 100644 index 0000000..8c3de92 --- /dev/null +++ b/openlane/user_project_wrapper/gen_pdn.tcl
@@ -0,0 +1,32 @@ +read_lef $::env(MERGED_LEF_UNPADDED) +read_def $::env(CURRENT_DEF) + +set ::env(_SPACING) 1.7 +set ::env(_WIDTH) 3 + +set power_domains [list {vccd1 vssd1} {vccd2 vssd2} {vdda1 vssa1} {vdda2 vssa2}] + +set ::env(_VDD_NET_NAME) vccd1 +set ::env(_GND_NET_NAME) vssd1 +set ::env(_V_OFFSET) 14 +set ::env(_H_OFFSET) $::env(_V_OFFSET) +set ::env(_V_PITCH) 180 +set ::env(_H_PITCH) 180 +set ::env(_V_PDN_OFFSET) 0 +set ::env(_H_PDN_OFFSET) 0 + +foreach domain $power_domains { + set ::env(_VDD_NET_NAME) [lindex $domain 0] + set ::env(_GND_NET_NAME) [lindex $domain 1] + + pdngen $::env(PDN_CFG) -verbose + + set ::env(_V_OFFSET) \ + [expr $::env(_V_OFFSET) + 2*($::env(_WIDTH)+$::env(_SPACING))] + set ::env(_H_OFFSET) \ + [expr $::env(_H_OFFSET) + 2*($::env(_WIDTH)+$::env(_SPACING))] + set ::env(_V_PDN_OFFSET) [expr $::env(_V_PDN_OFFSET)+6*$::env(_WIDTH)] + set ::env(_H_PDN_OFFSET) [expr $::env(_H_PDN_OFFSET)+6*$::env(_WIDTH)] +} + +write_def $::env(pdn_tmp_file_tag).def
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl new file mode 100644 index 0000000..9af67f1 --- /dev/null +++ b/openlane/user_project_wrapper/interactive.tcl
@@ -0,0 +1,50 @@ +package require openlane +set script_dir [file dirname [file normalize [info script]]] + +prep -design $script_dir -tag user_project_wrapper -overwrite +set save_path $script_dir/../.. + +verilog_elaborate + +init_floorplan + +place_io_ol + +set ::env(FP_DEF_TEMPATE) $script_dir/../../def/user_project_wrapper_empty.def + +apply_def_template + +add_macro_placement core0 1550 400 N +add_macro_placement core1 300 1600 N +add_macro_placement sram0 300 2800 N +add_macro_placement sram1 950 2800 N +add_macro_placement sram2 1550 2800 N +add_macro_placement sram3 2200 2800 N + +add_macro_placement sram4 1550 1600 S; # RX buffer for core1 +add_macro_placement sram5 2200 1600 N; # RX buffer for core0 + + +manual_macro_placement f + +exec -ignorestderr openroad -exit $script_dir/gen_pdn.tcl +set_def $::env(pdn_tmp_file_tag).def + +global_routing_or +detailed_routing + +run_magic +run_magic_spice_export + +save_views -lef_path $::env(magic_result_file_tag).lef \ + -def_path $::env(tritonRoute_result_file_tag).def \ + -gds_path $::env(magic_result_file_tag).gds \ + -mag_path $::env(magic_result_file_tag).mag \ + -save_path $save_path \ + -tag $::env(RUN_TAG) + +run_magic_drc + +run_lvs; # requires run_magic_spice_export + +run_antenna_check
diff --git a/openlane/user_project_wrapper/pdn.tcl b/openlane/user_project_wrapper/pdn.tcl new file mode 100644 index 0000000..075334d --- /dev/null +++ b/openlane/user_project_wrapper/pdn.tcl
@@ -0,0 +1,64 @@ +# Power nets +set ::power_nets $::env(_VDD_NET_NAME) +set ::ground_nets $::env(_GND_NET_NAME) + +pdngen::specify_grid stdcell { + name grid + core_ring { + met5 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_H_OFFSET)} + met4 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_V_OFFSET)} + } + rails { + } + straps { + met4 {width $::env(_WIDTH) pitch $::env(_V_PITCH) offset $::env(_V_PDN_OFFSET)} + met5 {width $::env(_WIDTH) pitch $::env(_H_PITCH) offset $::env(_H_PDN_OFFSET)} + } + connect {{met4 met5}} +} + +pdngen::specify_grid macro { + instance "obs_core_obs" + power_pins $::env(_VDD_NET_NAME) + ground_pins $::env(_GND_NET_NAME) + blockages "li1 met1 met2 met3 met4 met5" + straps { + } + connect {} +} + +#pdngen::specify_grid macro { +# power_pins $::env(_VDD_NET_NAME) +# ground_pins $::env(_GND_NET_NAME) +# blockages "" +# straps { +# } +# connect { } +#} + +pdngen::specify_grid macro { + power_pins "VPWR" + ground_pins "VGND" + blockages "li1 met1 met2 met3 met4" + straps { + } + connect { { met4_PIN_ver met5 } } +} + +pdngen::specify_grid macro { + macro "sram_1rw1r_32_256_8_sky130" + power_pins "vdd" + ground_pins "gnd" + blockages "li1 met1 met2 met3 met4" + straps { + } + connect { { met4_PIN_ver met5 } } +} + +set ::halo 15 + +# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area +set ::rails_start_with "POWER" ; + +# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area +set ::stripes_start_with "POWER" ;