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Muhammad Hadir Khan31ce5392020-12-05 13:23:49 +05001# ابتدا(Ibtida) SoC - Google SKY130 Shuttle
2An Soc designed to be included inside the Caravel, a template SoC for Google SKY130 free shuttles.
shalan0d14e6e2020-08-31 16:50:48 +02003
Muhammad Hadir Khan2db7cad2020-11-29 00:55:20 +05004ابتدا means the start of something. This is a minimal SoC built around a RISC-V based 5 stage pipelined core Buraq-Mini. Both the SoC and the core are made from scratch using CHISEL HDL. The CHISEL source code as well as the emitted verilog are provided in the relvant folders. It is still Work In Progress (WIP). The current SoC architecture is given below.
shalan0d14e6e2020-08-31 16:50:48 +02005
6<p align=”center”>
Muhammad Hadir Khan67ee2c82020-12-05 01:21:49 +05007<img src="/doc/ibtida-soc.png" >
shalan0d14e6e2020-08-31 16:50:48 +02008</p>
9
Muhammad Hadir Khaneb02afc2020-12-05 01:38:28 +050010## Design hierarchy
shalan0d14e6e2020-08-31 16:50:48 +020011
Muhammad Hadir Khan31ce5392020-12-05 13:23:49 +050012Chisel source code is available here:
Muhammad Hadir Khaneb02afc2020-12-05 01:38:28 +050013```
14chisel/
Muhammad Hadir Khan2052be12020-12-05 12:58:59 +050015├── Buraq-Mini (core source)
Muhammad Hadir Khaneb02afc2020-12-05 01:38:28 +050016│ │–– RV32i
Muhammad Hadir Khan2052be12020-12-05 12:58:59 +050017│ └── src
18│–– TileLink (bus source)
19│ └── src
20└── src (SoC source)
Muhammad Hadir Khan31ce5392020-12-05 13:23:49 +050021```
22The emitted verilog is present here:
23```
24verilog/
25├── rtl
26│ ├──ibtida-soc
27│ │ └── Ibtida_top_dffram_cv.v
agorararmarddc723a62020-11-26 20:00:29 +020028
Muhammad Hadir Khan31ce5392020-12-05 13:23:49 +050029```
30The synthesized netlist is present here:
31```
32verilog/
33├── gl
34│ └── Ibtida_top_dffram_cv.v
35```
36The hardened macros are placed here:
37```
38def/
39└── Ibtida_top_dffram_cv.def.gz
40```
41```
42lef/
43└── Ibtida_top_dffram_cv.lef
44```
45```
46gds/
47└── Ibtida_top_dffram_cv.gds.gz
Muhammad Hadir Khaneb02afc2020-12-05 01:38:28 +050048```
Muhammad Hadir Khan8a479452020-12-09 11:57:18 +050049
50## Todo
51- [ ] Change the repo name to integrate "caravel_".
52- [ ] Update the project with the caravel mpw-one-a branch.
53- [ ] Update the openlane with the mpw-one-a branch.
54- [ ] Verify the synthesized netlist.
55- [ ] Harden the design macro with 0 drc/lvs violations.
56- [ ] Harden the user project wrapper with 0 drc/lvs violations.
57- [ ] On-board the user project to Caravel.
58- [ ] Pass all the pre-checks.
59- [ ] Update the request to "Submitter Confirmed".
60
Hadir Khanf78084f2020-12-03 20:25:49 +050061## Contributors
Muhammad Hadir Khan2db7cad2020-11-29 00:55:20 +050062Main contributors are:
Muhammad Hadir Khan31ce5392020-12-05 13:23:49 +0500631. Engr. Muhammad Hadir Khan (RTL design based on CHISEL) (__Owner__).
Muhammad Hadir Khan2db7cad2020-11-29 00:55:20 +0500642. Sajjad Ahmed (RTL design based on CHISEL).
Muhammad Hadir Khan31ce5392020-12-05 13:23:49 +0500653. Engr. Aireen Amir Jalal (APR flow with OpenLANE RTL-GDSII).
agorararmard7d6fadb2020-11-25 20:23:20 +020066
Muhammad Hadir Khan2db7cad2020-11-29 00:55:20 +050067Other contributors:
Muhammad Hadir Khan8a479452020-12-09 11:57:18 +050068
Muhammad Hadir Khan31ce5392020-12-05 13:23:49 +0500694. Dr. Roomi Naqvi (Supervisor).
705. Dr. Ali Ahmed (Supervisor).
Muhammad Hadir Khan8a479452020-12-09 11:57:18 +0500716. Usman Zain