| commit | 2052be16455a36c0dbb827a2528e1614fc03d783 | [log] [tgz] |
|---|---|---|
| author | Muhammad Hadir Khan <41375553+hadirkhan10@users.noreply.github.com> | Sat Dec 05 12:58:59 2020 +0500 |
| committer | GitHub <noreply@github.com> | Sat Dec 05 12:58:59 2020 +0500 |
| tree | 53c33f8ec529eef4f9799c77a908fff1be28ba14 | |
| parent | eb02afcfd684087820273766da99a33563181693 [diff] |
Update README.md
ابتدا means the start of something. This is a minimal SoC built around a RISC-V based 5 stage pipelined core Buraq-Mini. Both the SoC and the core are made from scratch using CHISEL HDL. The CHISEL source code as well as the emitted verilog are provided in the relvant folders. It is still Work In Progress (WIP). The current SoC architecture is given below.
Chisel source code is available here
chisel/ ├── Buraq-Mini (core source) │ │–– RV32i │ └── src │–– TileLink (bus source) │ └── src └── src (SoC source)
Main contributors are:
Other contributors: