Added another option of including the netlist inside caravel to simulate it. Commented for now

verilog/rtl/caravel.v

diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 5d12e12..2ac370d 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -63,6 +63,7 @@
 /* Include user project here	*/
 /*------------------------------*/
 `include "ibtida-soc/Ibtida_top_dffram_cv.v"
+//`include "../gl/Ibtida_top_dffram_cv.v"
 
 // `ifdef USE_OPENRAM
 //     `include "sram_1rw1r_32_256_8_sky130.v"