| commit | 39c58a457c92c45d3659d6b307922c353afd02e6 | [log] [tgz] |
|---|---|---|
| author | hadirkhan10 <hadirkhan10@gmail.com> | Wed Dec 09 08:39:37 2020 +0000 |
| committer | hadirkhan10 <hadirkhan10@gmail.com> | Wed Dec 09 08:39:37 2020 +0000 |
| tree | eb8b45f44796bd3b2862b9fc5afeb8f1b3133326 | |
| parent | b100ccd7ab791997a694a517a456ea879dc0c893 [diff] |
Created a new test program
An Soc designed to be included inside the Caravel, a template SoC for Google SKY130 free shuttles.
ابتدا means the start of something. This is a minimal SoC built around a RISC-V based 5 stage pipelined core Buraq-Mini. Both the SoC and the core are made from scratch using CHISEL HDL. The CHISEL source code as well as the emitted verilog are provided in the relvant folders. It is still Work In Progress (WIP). The current SoC architecture is given below.
<<<<<<< HEAD
Chisel source code is available here:
chisel/ ├── Buraq-Mini (core source) │ │–– RV32i │ └── src │–– TileLink (bus source) │ └── src └── src (SoC source)
The emitted verilog is present here:
verilog/ ├── rtl │ ├──ibtida-soc │ │ └── Ibtida_top_dffram_cv.v
The synthesized netlist is present here:
verilog/ ├── gl │ └── Ibtida_top_dffram_cv.v
The hardened macros are placed here:
def/ └── Ibtida_top_dffram_cv.def.gz
lef/ └── Ibtida_top_dffram_cv.lef
gds/ └── Ibtida_top_dffram_cv.gds.gz
Main contributors are:
Other contributors: 4. Dr. Roomi Naqvi (Supervisor). 5. Dr. Ali Ahmed (Supervisor). 6. Usman Zain