| commit | 0bb8103a23d34f12506e77e92c66d09cdb217e3f | [log] [tgz] |
|---|---|---|
| author | hadirkhan10 <hadirkhan10@gmail.com> | Wed Dec 09 08:40:35 2020 +0000 |
| committer | hadirkhan10 <hadirkhan10@gmail.com> | Wed Dec 09 08:40:35 2020 +0000 |
| tree | 21cf6043ce3375a68b392d97fd79b395f2f4f05b | |
| parent | 39c58a457c92c45d3659d6b307922c353afd02e6 [diff] |
Added another option of including the netlist inside caravel to simulate it. Commented for now
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 5d12e12..2ac370d 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v
@@ -63,6 +63,7 @@ /* Include user project here */ /*------------------------------*/ `include "ibtida-soc/Ibtida_top_dffram_cv.v" +//`include "../gl/Ibtida_top_dffram_cv.v" // `ifdef USE_OPENRAM // `include "sram_1rw1r_32_256_8_sky130.v"