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agorararmarde5780bf2020-12-09 21:27:56 +00001/*
agorararmard6c766a82020-12-10 18:13:12 +02002 * SPDX-FileCopyrightText: 2020 Efabless Corporation
agorararmarde5780bf2020-12-09 21:27:56 +00003 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
agorararmardafa96ea2020-12-09 23:37:31 +020015 * SPDX-License-Identifier: Apache-2.0
agorararmarde5780bf2020-12-09 21:27:56 +000016 */
17
shalanfd13eb52020-08-21 16:48:07 +020018#ifndef _STRIVE_H_
19#define _STRIVE_H_
20
21#include <stdint.h>
22#include <stdbool.h>
23
24// a pointer to this is a null pointer, but the compiler does not
25// know that because "sram" is a linker symbol from sections.lds.
26extern uint32_t sram;
27
28// Pointer to firmware flash routines
29extern uint32_t flashio_worker_begin;
30extern uint32_t flashio_worker_end;
31
Manar55ec3692020-10-30 16:32:18 +020032// Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
Manarffe6cad2020-11-09 19:09:04 +020033#define reg_rw_block0 (*(volatile uint32_t*)0x01000000)
34#define reg_rw_block1 (*(volatile uint32_t*)0x01100000)
35#define reg_ro_block0 (*(volatile uint32_t*)0x02000000)
Manar14d35ac2020-10-21 22:47:15 +020036
shalan0d14e6e2020-08-31 16:50:48 +020037// UART (0x2000_0000)
shalanfd13eb52020-08-21 16:48:07 +020038#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
39#define reg_uart_data (*(volatile uint32_t*)0x20000004)
Tim Edwardsca2f3182020-10-06 10:05:11 -040040#define reg_uart_enable (*(volatile uint32_t*)0x20000008)
shalanfd13eb52020-08-21 16:48:07 +020041
shalan0d14e6e2020-08-31 16:50:48 +020042// GPIO (0x2100_0000)
shalanfd13eb52020-08-21 16:48:07 +020043#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
44#define reg_gpio_ena (*(volatile uint32_t*)0x21000004)
45#define reg_gpio_pu (*(volatile uint32_t*)0x21000008)
46#define reg_gpio_pd (*(volatile uint32_t*)0x2100000c)
47
shalan0d14e6e2020-08-31 16:50:48 +020048// Logic Analyzer (0x2200_0000)
Tim Edwards856b0922020-10-09 16:30:22 -040049#define reg_la0_data (*(volatile uint32_t*)0x25000000)
50#define reg_la1_data (*(volatile uint32_t*)0x25000004)
51#define reg_la2_data (*(volatile uint32_t*)0x25000008)
52#define reg_la3_data (*(volatile uint32_t*)0x2500000c)
shalanfd13eb52020-08-21 16:48:07 +020053
Tim Edwards856b0922020-10-09 16:30:22 -040054#define reg_la0_ena (*(volatile uint32_t*)0x25000010)
55#define reg_la1_ena (*(volatile uint32_t*)0x25000014)
56#define reg_la2_ena (*(volatile uint32_t*)0x25000018)
57#define reg_la3_ena (*(volatile uint32_t*)0x2500001c)
shalanfd13eb52020-08-21 16:48:07 +020058
Tim Edwardsba328902020-10-27 15:03:22 -040059// User Project Control (0x2300_0000)
60#define reg_mprj_xfer (*(volatile uint32_t*)0x26000000)
61#define reg_mprj_pwr (*(volatile uint32_t*)0x26000004)
62#define reg_mprj_datal (*(volatile uint32_t*)0x26000008)
63#define reg_mprj_datah (*(volatile uint32_t*)0x2600000c)
shalan0d14e6e2020-08-31 16:50:48 +020064
Tim Edwardsba328902020-10-27 15:03:22 -040065#define reg_mprj_io_0 (*(volatile uint32_t*)0x26000020)
66#define reg_mprj_io_1 (*(volatile uint32_t*)0x26000024)
67#define reg_mprj_io_2 (*(volatile uint32_t*)0x26000028)
68#define reg_mprj_io_3 (*(volatile uint32_t*)0x2600002c)
69#define reg_mprj_io_4 (*(volatile uint32_t*)0x26000030)
70#define reg_mprj_io_5 (*(volatile uint32_t*)0x26000034)
71#define reg_mprj_io_6 (*(volatile uint32_t*)0x26000038)
shalan0d14e6e2020-08-31 16:50:48 +020072
Tim Edwardsba328902020-10-27 15:03:22 -040073#define reg_mprj_io_7 (*(volatile uint32_t*)0x2600003c)
74#define reg_mprj_io_8 (*(volatile uint32_t*)0x26000040)
75#define reg_mprj_io_9 (*(volatile uint32_t*)0x26000044)
76#define reg_mprj_io_10 (*(volatile uint32_t*)0x26000048)
shalan0d14e6e2020-08-31 16:50:48 +020077
Tim Edwardsba328902020-10-27 15:03:22 -040078#define reg_mprj_io_11 (*(volatile uint32_t*)0x2600004c)
79#define reg_mprj_io_12 (*(volatile uint32_t*)0x26000050)
80#define reg_mprj_io_13 (*(volatile uint32_t*)0x26000054)
81#define reg_mprj_io_14 (*(volatile uint32_t*)0x26000058)
shalan0d14e6e2020-08-31 16:50:48 +020082
Tim Edwardsba328902020-10-27 15:03:22 -040083#define reg_mprj_io_15 (*(volatile uint32_t*)0x2600005c)
84#define reg_mprj_io_16 (*(volatile uint32_t*)0x26000060)
85#define reg_mprj_io_17 (*(volatile uint32_t*)0x26000064)
86#define reg_mprj_io_18 (*(volatile uint32_t*)0x26000068)
shalan0d14e6e2020-08-31 16:50:48 +020087
Tim Edwardsba328902020-10-27 15:03:22 -040088#define reg_mprj_io_19 (*(volatile uint32_t*)0x2600006c)
89#define reg_mprj_io_20 (*(volatile uint32_t*)0x26000070)
90#define reg_mprj_io_21 (*(volatile uint32_t*)0x26000074)
91#define reg_mprj_io_22 (*(volatile uint32_t*)0x26000078)
shalan0d14e6e2020-08-31 16:50:48 +020092
Tim Edwardsba328902020-10-27 15:03:22 -040093#define reg_mprj_io_23 (*(volatile uint32_t*)0x2600007c)
94#define reg_mprj_io_24 (*(volatile uint32_t*)0x26000080)
95#define reg_mprj_io_25 (*(volatile uint32_t*)0x26000084)
96#define reg_mprj_io_26 (*(volatile uint32_t*)0x26000088)
Tim Edwards44bab472020-10-04 22:09:54 -040097
Tim Edwardsba328902020-10-27 15:03:22 -040098#define reg_mprj_io_27 (*(volatile uint32_t*)0x2600008c)
99#define reg_mprj_io_28 (*(volatile uint32_t*)0x26000090)
100#define reg_mprj_io_29 (*(volatile uint32_t*)0x26000094)
101#define reg_mprj_io_30 (*(volatile uint32_t*)0x26000098)
102#define reg_mprj_io_31 (*(volatile uint32_t*)0x2600009c)
Tim Edwards856b0922020-10-09 16:30:22 -0400103
Tim Edwardsba328902020-10-27 15:03:22 -0400104#define reg_mprj_io_32 (*(volatile uint32_t*)0x260000a0)
105#define reg_mprj_io_33 (*(volatile uint32_t*)0x260000a4)
106#define reg_mprj_io_34 (*(volatile uint32_t*)0x260000a8)
107#define reg_mprj_io_35 (*(volatile uint32_t*)0x260000ac)
108#define reg_mprj_io_36 (*(volatile uint32_t*)0x260000b0)
109#define reg_mprj_io_37 (*(volatile uint32_t*)0x260000b4)
shalan0d14e6e2020-08-31 16:50:48 +0200110
Tim Edwardsba328902020-10-27 15:03:22 -0400111// User Project Slaves (0x3000_0000)
shalan0d14e6e2020-08-31 16:50:48 +0200112#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
113
shalanfd13eb52020-08-21 16:48:07 +0200114// Flash Control SPI Configuration (2D00_0000)
Tim Edwards44bab472020-10-04 22:09:54 -0400115#define reg_spictrl (*(volatile uint32_t*)0x2d000000)
shalanfd13eb52020-08-21 16:48:07 +0200116
Tim Edwardsba328902020-10-27 15:03:22 -0400117// Bit fields for Flash SPI control
118#define FLASH_BITBANG_IO0 0x00000001
119#define FLASH_BITBANG_IO1 0x00000002
120#define FLASH_BITBANG_CLK 0x00000010
121#define FLASH_BITBANG_CSB 0x00000020
122#define FLASH_BITBANG_OEB0 0x00000100
123#define FLASH_BITBANG_OEB1 0x00000200
124#define FLASH_ENABLE 0x80000000
125
Tim Edwards44bab472020-10-04 22:09:54 -0400126// Counter-Timer 0 Configuration
Tim Edwards856b0922020-10-09 16:30:22 -0400127#define reg_timer0_config (*(volatile uint32_t*)0x22000000)
128#define reg_timer0_value (*(volatile uint32_t*)0x22000004)
129#define reg_timer0_data (*(volatile uint32_t*)0x22000008)
Tim Edwards44bab472020-10-04 22:09:54 -0400130
131// Counter-Timer 1 Configuration
Tim Edwards856b0922020-10-09 16:30:22 -0400132#define reg_timer1_config (*(volatile uint32_t*)0x23000000)
133#define reg_timer1_value (*(volatile uint32_t*)0x23000004)
134#define reg_timer1_data (*(volatile uint32_t*)0x23000008)
Tim Edwards44bab472020-10-04 22:09:54 -0400135
Tim Edwardsba328902020-10-27 15:03:22 -0400136// Bit fields for Counter-timer configuration
137#define TIMER_ENABLE 0x01
138#define TIMER_ONESHOT 0x02
139#define TIMER_UPCOUNT 0x04
140#define TIMER_CHAIN 0x08
141#define TIMER_IRQ_ENABLE 0x10
142
Tim Edwards44bab472020-10-04 22:09:54 -0400143// SPI Master Configuration
Tim Edwards856b0922020-10-09 16:30:22 -0400144#define reg_spimaster_config (*(volatile uint32_t*)0x24000000)
145#define reg_spimaster_data (*(volatile uint32_t*)0x24000004)
shalanfd13eb52020-08-21 16:48:07 +0200146
Tim Edwardsba328902020-10-27 15:03:22 -0400147// Bit fields for SPI master configuration
148#define SPI_MASTER_DIV_MASK 0x00ff
149#define SPI_MASTER_MLB 0x0100
150#define SPI_MASTER_INV_CSB 0x0200
151#define SPI_MASTER_INV_CLK 0x0400
152#define SPI_MASTER_MODE_1 0x0800
153#define SPI_MASTER_STREAM 0x1000
154#define SPI_MASTER_ENABLE 0x2000
155#define SPI_MASTER_IRQ_ENABLE 0x4000
156#define SPI_HOUSEKEEPING_CONN 0x8000
shalanfd13eb52020-08-21 16:48:07 +0200157
Tim Edwardsba328902020-10-27 15:03:22 -0400158// System Area (0x2F00_0000)
159#define reg_power_good (*(volatile uint32_t*)0x2F000000)
160#define reg_clk_out_dest (*(volatile uint32_t*)0x2F000004)
161#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000008)
162#define reg_irq_source (*(volatile uint32_t*)0x2F00000C)
163
164// Bit fields for reg_power_good
165#define USER1_VCCD_POWER_GOOD 0x01
166#define USER2_VCCD_POWER_GOOD 0x02
167#define USER1_VDDA_POWER_GOOD 0x04
168#define USER2_VDDA_POWER_GOOD 0x08
169
170// Bit fields for reg_clk_out_dest
171#define CLOCK1_MONITOR 0x01
172#define CLOCK2_MONITOR 0x02
173
174// Bit fields for reg_irq_source
175#define IRQ7_SOURCE 0x01
176#define IRQ8_SOURCE 0x02
177
178// Individual bit fields for the GPIO pad control
179#define MGMT_ENABLE 0x0001
180#define OUTPUT_DISABLE 0x0002
181#define HOLD_OVERRIDE 0x0004
182#define INPUT_DISABLE 0x0008
183#define MODE_SELECT 0x0010
184#define ANALOG_ENABLE 0x0020
185#define ANALOG_SELECT 0x0040
186#define ANALOG_POLARITY 0x0080
187#define SLOW_SLEW_MODE 0x0100
188#define TRIPPOINT_SEL 0x0200
189#define DIGITAL_MODE_MASK 0x1c00
shalanfd13eb52020-08-21 16:48:07 +0200190
Tim Edwards44bab472020-10-04 22:09:54 -0400191// Useful GPIO mode values
192#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
193#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0803
194#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c03
Tim Edwardsf51dd082020-10-05 16:30:24 -0400195#define GPIO_MODE_MGMT_STD_OUTPUT 0x1809
Tim Edwards44bab472020-10-04 22:09:54 -0400196
197#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
198#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0802
199#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c02
Tim Edwardsf51dd082020-10-05 16:30:24 -0400200#define GPIO_MODE_USER_STD_OUTPUT 0x1808
Tim Edwards44bab472020-10-04 22:09:54 -0400201
shalanfd13eb52020-08-21 16:48:07 +0200202// --------------------------------------------------------
203#endif