| commit | ba3289096e696a0449bb485d8a28f8559fa3066a | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Tue Oct 27 15:03:22 2020 -0400 |
| committer | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Wed Oct 28 22:58:29 2020 +0200 |
| tree | 87bf8e962274e494688b945d44775f2ba996c32c | |
| parent | e6eda804fa840f8ccb66a5af2188044e5c23731b [diff] |
Revised the mprj_ctrl to treat the power control as a single bit read/write per power domain, not part of the serial load chain. This greatly simplifies the code in the mprj_ctrl module. Also brought the power control pins up to the top level, in case we want to use them for internally enabling/disabling the user area power supplies (may be an experimental function on one or more versions). Also: Corrected a few entries in the defs.h header file, and added definitions for the bit fields in a number of registers that have individual bitmask entries.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware that can be used to:
The memory map of the management SoC is given below
(NOTE: This needs updating; see the README file for an updated list.)
This is the user space. It has limited silicon area (TBD, about 2.8mm x 2.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: