[DATA]sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped views
diff --git a/gds/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.gds b/gds/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.gds
new file mode 100644
index 0000000..bd4cfac
--- /dev/null
+++ b/gds/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.gds
Binary files differ
diff --git a/lef/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lef b/lef/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lef
new file mode 100644
index 0000000..c8f4ad2
--- /dev/null
+++ b/lef/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lef
@@ -0,0 +1,60 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+ CLASS BLOCK ;
+ FOREIGN sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ;
+ ORIGIN 0.000 -0.005 ;
+ SIZE 25.620 BY 25.415 ;
+ PIN A
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 21.550 21.420 21.830 25.420 ;
+ END
+ END A
+ PIN X
+ DIRECTION OUTPUT TRISTATE ;
+ PORT
+ LAYER met2 ;
+ RECT 3.310 0.420 3.590 4.420 ;
+ END
+ END X
+ PIN VPWR
+ DIRECTION INPUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.330 16.445 25.290 16.955 ;
+ END
+ END VPWR
+ PIN VGND
+ DIRECTION INPUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.330 24.585 25.290 25.095 ;
+ END
+ END VGND
+ OBS
+ LAYER li1 ;
+ RECT 0.330 0.335 25.290 20.855 ;
+ LAYER met1 ;
+ RECT 0.330 17.235 25.290 20.885 ;
+ RECT 0.330 0.165 25.290 16.165 ;
+ LAYER met2 ;
+ RECT 3.320 21.140 21.270 25.095 ;
+ RECT 22.110 21.140 22.300 25.095 ;
+ RECT 3.320 4.700 22.300 21.140 ;
+ RECT 3.870 0.165 22.300 4.700 ;
+ LAYER met3 ;
+ RECT 3.695 0.255 21.960 25.005 ;
+ LAYER met4 ;
+ RECT 3.695 0.165 21.960 25.095 ;
+ LAYER met5 ;
+ RECT 0.330 3.530 25.290 21.795 ;
+ END
+END sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+END LIBRARY
+
diff --git a/mag/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag b/mag/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag
new file mode 100644
index 0000000..4f27c19
--- /dev/null
+++ b/mag/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag
@@ -0,0 +1,940 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1606497726
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+rect 991 56 1047 112
+rect 1047 56 1051 112
+rect 987 52 1051 56
+rect 2414 112 2478 116
+rect 2414 56 2418 112
+rect 2418 56 2474 112
+rect 2474 56 2478 112
+rect 2414 52 2478 56
+rect 2494 112 2558 116
+rect 2494 56 2498 112
+rect 2498 56 2554 112
+rect 2554 56 2558 112
+rect 2494 52 2558 56
+rect 2574 112 2638 116
+rect 2574 56 2578 112
+rect 2578 56 2634 112
+rect 2634 56 2638 112
+rect 2574 52 2638 56
+rect 2654 112 2718 116
+rect 2654 56 2658 112
+rect 2658 56 2714 112
+rect 2714 56 2718 112
+rect 2654 52 2718 56
+rect 4080 112 4144 116
+rect 4080 56 4084 112
+rect 4084 56 4140 112
+rect 4140 56 4144 112
+rect 4080 52 4144 56
+rect 4160 112 4224 116
+rect 4160 56 4164 112
+rect 4164 56 4220 112
+rect 4220 56 4224 112
+rect 4160 52 4224 56
+rect 4240 112 4304 116
+rect 4240 56 4244 112
+rect 4244 56 4300 112
+rect 4300 56 4304 112
+rect 4240 52 4304 56
+rect 4320 112 4384 116
+rect 4320 56 4324 112
+rect 4324 56 4380 112
+rect 4380 56 4384 112
+rect 4320 52 4384 56
+<< metal4 >>
+rect 739 4317 1059 5019
+rect 739 4081 781 4317
+rect 1017 4081 1059 4317
+rect 739 3372 1059 4081
+rect 739 3308 747 3372
+rect 811 3308 827 3372
+rect 891 3308 907 3372
+rect 971 3308 987 3372
+rect 1051 3308 1059 3372
+rect 739 2651 1059 3308
+rect 739 2415 781 2651
+rect 1017 2415 1059 2651
+rect 739 984 1059 2415
+rect 739 748 781 984
+rect 1017 748 1059 984
+rect 739 116 1059 748
+rect 739 52 747 116
+rect 811 52 827 116
+rect 891 52 907 116
+rect 971 52 987 116
+rect 1051 52 1059 116
+rect 739 33 1059 52
+rect 1572 5000 1892 5019
+rect 1572 4936 1580 5000
+rect 1644 4936 1660 5000
+rect 1724 4936 1740 5000
+rect 1804 4936 1820 5000
+rect 1884 4936 1892 5000
+rect 1572 3484 1892 4936
+rect 1572 3248 1614 3484
+rect 1850 3248 1892 3484
+rect 1572 1817 1892 3248
+rect 1572 1744 1614 1817
+rect 1850 1744 1892 1817
+rect 1572 1680 1580 1744
+rect 1884 1680 1892 1744
+rect 1572 1581 1614 1680
+rect 1850 1581 1892 1680
+rect 1572 33 1892 1581
+rect 2406 4317 2726 5019
+rect 2406 4081 2448 4317
+rect 2684 4081 2726 4317
+rect 2406 3372 2726 4081
+rect 2406 3308 2414 3372
+rect 2478 3308 2494 3372
+rect 2558 3308 2574 3372
+rect 2638 3308 2654 3372
+rect 2718 3308 2726 3372
+rect 2406 2651 2726 3308
+rect 2406 2415 2448 2651
+rect 2684 2415 2726 2651
+rect 2406 984 2726 2415
+rect 2406 748 2448 984
+rect 2684 748 2726 984
+rect 2406 116 2726 748
+rect 2406 52 2414 116
+rect 2478 52 2494 116
+rect 2558 52 2574 116
+rect 2638 52 2654 116
+rect 2718 52 2726 116
+rect 2406 33 2726 52
+rect 3239 5000 3559 5019
+rect 3239 4936 3247 5000
+rect 3311 4936 3327 5000
+rect 3391 4936 3407 5000
+rect 3471 4936 3487 5000
+rect 3551 4936 3559 5000
+rect 3239 3484 3559 4936
+rect 3239 3248 3281 3484
+rect 3517 3248 3559 3484
+rect 3239 1817 3559 3248
+rect 3239 1744 3281 1817
+rect 3517 1744 3559 1817
+rect 3239 1680 3247 1744
+rect 3551 1680 3559 1744
+rect 3239 1581 3281 1680
+rect 3517 1581 3559 1680
+rect 3239 33 3559 1581
+rect 4072 4317 4392 5019
+rect 4072 4081 4114 4317
+rect 4350 4081 4392 4317
+rect 4072 3372 4392 4081
+rect 4072 3308 4080 3372
+rect 4144 3308 4160 3372
+rect 4224 3308 4240 3372
+rect 4304 3308 4320 3372
+rect 4384 3308 4392 3372
+rect 4072 2651 4392 3308
+rect 4072 2415 4114 2651
+rect 4350 2415 4392 2651
+rect 4072 984 4392 2415
+rect 4072 748 4114 984
+rect 4350 748 4392 984
+rect 4072 116 4392 748
+rect 4072 52 4080 116
+rect 4144 52 4160 116
+rect 4224 52 4240 116
+rect 4304 52 4320 116
+rect 4384 52 4392 116
+rect 4072 33 4392 52
+<< via4 >>
+rect 781 4081 1017 4317
+rect 781 2415 1017 2651
+rect 781 748 1017 984
+rect 1614 3248 1850 3484
+rect 1614 1744 1850 1817
+rect 1614 1680 1644 1744
+rect 1644 1680 1660 1744
+rect 1660 1680 1724 1744
+rect 1724 1680 1740 1744
+rect 1740 1680 1804 1744
+rect 1804 1680 1820 1744
+rect 1820 1680 1850 1744
+rect 1614 1581 1850 1680
+rect 2448 4081 2684 4317
+rect 2448 2415 2684 2651
+rect 2448 748 2684 984
+rect 3281 3248 3517 3484
+rect 3281 1744 3517 1817
+rect 3281 1680 3311 1744
+rect 3311 1680 3327 1744
+rect 3327 1680 3391 1744
+rect 3391 1680 3407 1744
+rect 3407 1680 3471 1744
+rect 3471 1680 3487 1744
+rect 3487 1680 3517 1744
+rect 3281 1581 3517 1680
+rect 4114 4081 4350 4317
+rect 4114 2415 4350 2651
+rect 4114 748 4350 984
+<< metal5 >>
+rect 66 4317 5058 4359
+rect 66 4081 781 4317
+rect 1017 4081 2448 4317
+rect 2684 4081 4114 4317
+rect 4350 4081 5058 4317
+rect 66 4039 5058 4081
+rect 66 3484 5058 3526
+rect 66 3248 1614 3484
+rect 1850 3248 3281 3484
+rect 3517 3248 5058 3484
+rect 66 3206 5058 3248
+rect 66 2651 5058 2693
+rect 66 2415 781 2651
+rect 1017 2415 2448 2651
+rect 2684 2415 4114 2651
+rect 4350 2415 5058 2651
+rect 66 2373 5058 2415
+rect 66 1817 5058 1859
+rect 66 1581 1614 1817
+rect 1850 1581 3281 1817
+rect 3517 1581 5058 1817
+rect 66 1539 5058 1581
+rect 66 984 5058 1026
+rect 66 748 781 984
+rect 1017 748 2448 984
+rect 2684 748 4114 984
+rect 4350 748 5058 984
+rect 66 706 5058 748
+use sky130_fd_sc_hvl__decap_8 FILLER_1_39
+timestamp 1606497726
+transform 1 0 3810 0 1 1712
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_4 FILLER_1_47
+timestamp 1606497726
+transform 1 0 4578 0 1 1712
+box -66 -23 450 897
+use sky130_fd_sc_hvl__fill_1 FILLER_1_51
+timestamp 1606497726
+transform 1 0 4962 0 1 1712
+box -66 -23 162 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_40
+timestamp 1606497726
+transform 1 0 3906 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_4 FILLER_2_48
+timestamp 1606497726
+transform 1 0 4674 0 -1 4154
+box -66 -23 450 897
+use sky130_fd_sc_hvl__decap_8 FILLER_1_31
+timestamp 1606497726
+transform 1 0 3042 0 1 1712
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_24
+timestamp 1606497726
+transform 1 0 2370 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_32
+timestamp 1606497726
+transform 1 0 3138 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__lsbufhv2lv_1 lvlshiftdown
+timestamp 1606497726
+transform 1 0 1410 0 1 1712
+box -66 -23 1698 1651
+use sky130_fd_sc_hvl__decap_8 FILLER_1_0
+timestamp 1606497726
+transform 1 0 66 0 1 1712
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_4 FILLER_1_8
+timestamp 1606497726
+transform 1 0 834 0 1 1712
+box -66 -23 450 897
+use sky130_fd_sc_hvl__fill_2 FILLER_1_12
+timestamp 1606497726
+transform 1 0 1218 0 1 1712
+box -66 -23 258 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_0
+timestamp 1606497726
+transform 1 0 66 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_8
+timestamp 1606497726
+transform 1 0 834 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_16
+timestamp 1606497726
+transform 1 0 1602 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_40
+timestamp 1606497726
+transform 1 0 3906 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_4 FILLER_0_48
+timestamp 1606497726
+transform 1 0 4674 0 -1 898
+box -66 -23 450 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_24
+timestamp 1606497726
+transform 1 0 2370 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_32
+timestamp 1606497726
+transform 1 0 3138 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_0
+timestamp 1606497726
+transform 1 0 66 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_8
+timestamp 1606497726
+transform 1 0 834 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_16
+timestamp 1606497726
+transform 1 0 1602 0 -1 898
+box -66 -23 834 897
+<< labels >>
+rlabel metal2 s 4310 4284 4366 5084 4 A
+port 1 nsew
+rlabel metal2 s 662 84 718 884 4 X
+port 2 nsew
+rlabel metal1 s 66 3289 5058 3391 4 VPWR
+port 3 nsew
+rlabel metal1 s 66 4917 5058 5019 4 VGND
+port 4 nsew
+<< properties >>
+string FIXED_BBOX 0 1 5124 5084
+string GDS_FILE /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.gds
+string GDS_END 50278
+string GDS_START 35870
+<< end >>
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/cmds.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/cmds.log
new file mode 100644
index 0000000..63a0920
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/cmds.log
@@ -0,0 +1,76 @@
+Fri Nov 27 17:21:58 UTC 2020 - Executing "/openLANE_flow/scripts/mergeLef.py -i /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/techlef/sky130_fd_sc_hvl.tlef /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lef/sky130_fd_sc_hvl.lef -o /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef |& tee >&@stdout"
+
+Fri Nov 27 17:21:58 UTC 2020 - Executing "/openLANE_flow/scripts/libtrim.pl { /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib } /home/xrex/usr/devel/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hvl/no_synth.cells > /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/trimmed.lib"
+
+Fri Nov 27 17:21:58 UTC 2020 - Executing "yosys -c /openLANE_flow/scripts/synth.tcl -l /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/synthesis/yosys.log |& tee >&@stdout"
+
+Fri Nov 27 17:21:58 UTC 2020 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/project\/openlane\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\/runs\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\/results\/synthesis\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis.v/} /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl"
+
+Fri Nov 27 17:21:58 UTC 2020 - Executing "sed -i -e {s/\(set ::env(PREV_NETLIST)\).*/\1 0/} /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl"
+
+Fri Nov 27 17:21:58 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_floorplan.tcl |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/verilog2def.openroad.log"
+
+Fri Nov 27 17:21:59 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_ioplacer.tcl |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/ioPlacer.log"
+
+Fri Nov 27 17:21:59 UTC 2020 - Executing "python3 /openLANE_flow/scripts/random_place.py --lef /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef --input-def /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/ioPlacer.def --output-def /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/placement/replace.def |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/replace.log"
+
+Fri Nov 27 17:21:59 UTC 2020 - Executing "/openLANE_flow/scripts/libtrim.pl /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ss_150C_1v65.lib /home/xrex/usr/devel/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hvl/no_synth.cells > /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/opt.lib"
+
+Fri Nov 27 17:21:59 UTC 2020 - Executing "Psn /openLANE_flow/scripts/openPhySyn.tcl |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/openphysyn.log"
+
+Fri Nov 27 17:22:00 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_write_verilog.tcl |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/write_verilog.log"
+
+Fri Nov 27 17:22:00 UTC 2020 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/project\/openlane\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\/runs\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\/results\/synthesis\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis_optimized.v/} /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl"
+
+Fri Nov 27 17:22:00 UTC 2020 - Executing "sed -i -e {s/\(set ::env(PREV_NETLIST)\).*/\1 \/project\/openlane\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\/runs\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\/results\/synthesis\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis.v/} /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl"
+
+Fri Nov 27 17:22:00 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_opendp.tcl |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/opendp.log"
+
+Fri Nov 27 17:22:01 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/new_pdn.tcl |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/pdn.log"
+
+Fri Nov 27 17:22:01 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_route.tcl |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/fastroute.log"
+
+Fri Nov 27 17:22:02 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_route.tcl |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/fastroute_post_antenna.log"
+
+Fri Nov 27 17:22:02 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_fill.tcl |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/addspacers.log"
+
+Fri Nov 27 17:22:03 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_write_verilog.tcl |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/write_verilog.log"
+
+Fri Nov 27 17:22:03 UTC 2020 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/project\/openlane\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\/runs\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\/results\/synthesis\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis_preroute.v/} /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl"
+
+Fri Nov 27 17:22:03 UTC 2020 - Executing "sed -i -e {s/\(set ::env(PREV_NETLIST)\).*/\1 \/project\/openlane\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\/runs\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\/results\/synthesis\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis_optimized.v/} /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl"
+
+Fri Nov 27 17:22:03 UTC 2020 - Executing "envsubst < /openLANE_flow/scripts/tritonRoute.param > /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/routing/tritonRoute.param"
+
+Fri Nov 27 17:22:03 UTC 2020 - Executing "TritonRoute /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/routing/tritonRoute.param |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/tritonRoute.log"
+
+Fri Nov 27 17:22:04 UTC 2020 - Executing "python3 /openLANE_flow/scripts/tr2klayout.py -i /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/routing/tritonRoute.drc -o /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/routing/tritonRoute.klayout.xml --design-name sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
+
+Fri Nov 27 17:22:05 UTC 2020 - Executing "python3 /openLANE_flow/scripts/spef_extractor/main.py -l /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef -d /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def -mw PI -ec 1 |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/spef_extraction.log"
+
+Fri Nov 27 17:22:05 UTC 2020 - Executing "python3 /openLANE_flow/scripts/write_powered_def.py -d /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def -l /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged.lef -v VPWR -g VGND -o /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.powered.def |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/lvs/write_powered_verilog.log"
+
+Fri Nov 27 17:22:05 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_write_verilog.tcl |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/write_verilog.log"
+
+Fri Nov 27 17:22:05 UTC 2020 - Executing "yosys -c /openLANE_flow/scripts/yosys_rewrite_verilog.tcl -l /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/synthesis/yosys_rewrite_verilog.log"
+
+Fri Nov 27 17:22:05 UTC 2020 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/project\/openlane\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\/runs\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\/results\/lvs\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.powered.v/} /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl"
+
+Fri Nov 27 17:22:05 UTC 2020 - Executing "sed -i -e {s/\(set ::env(PREV_NETLIST)\).*/\1 \/project\/openlane\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\/runs\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped\/results\/synthesis\/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis_preroute.v/} /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl"
+
+Fri Nov 27 17:22:05 UTC 2020 - Executing "magic -noconsole -dnull -rcfile /home/xrex/usr/devel/pdks/sky130A/libs.tech/magic/sky130A.magicrc /openLANE_flow/scripts/magic.tcl </dev/null |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.log"
+
+Fri Nov 27 17:22:06 UTC 2020 - Executing "magic -noconsole -dnull -rcfile /home/xrex/usr/devel/pdks/sky130A/libs.tech/magic/sky130A.magicrc /openLANE_flow/scripts/magic_mag.tcl </dev/null |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.log"
+
+Fri Nov 27 17:22:06 UTC 2020 - Executing "magic -noconsole -dnull -rcfile /home/xrex/usr/devel/pdks/sky130A/libs.tech/magic/sky130A.magicrc /openLANE_flow/scripts/magic_maglef.tcl </dev/null |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.maglef.log"
+
+Fri Nov 27 17:22:06 UTC 2020 - Executing "magic -noconsole -dnull -rcfile /home/xrex/usr/devel/pdks/sky130A/libs.tech/magic/sky130A.magicrc /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/magic_spice.tcl </dev/null |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic_spice.log"
+
+Fri Nov 27 17:22:06 UTC 2020 - Executing "magic -noconsole -dnull -rcfile /home/xrex/usr/devel/pdks/sky130A/libs.tech/magic/sky130A.magicrc /openLANE_flow/scripts/magic_drc.tcl </dev/null |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.drc.log"
+
+Fri Nov 27 17:22:07 UTC 2020 - Executing "netgen -batch lvs {/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.spice sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped} {/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.powered.v sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped} /home/xrex/usr/devel/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.log -json |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/lvs/lvs.log"
+
+Fri Nov 27 17:22:07 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_antenna_check.tcl |& tee >&@stdout /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/or_antenna.log"
+
+Fri Nov 27 17:22:08 UTC 2020 - Executing "python3 /openLANE_flow/report_generation_wrapper.py -d /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped -dn sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped -t sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped -o /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/final_summary_report.csv -r /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
+
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl
new file mode 100644
index 0000000..33a7929
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl
@@ -0,0 +1,83 @@
+# General config
+set ::env(PDK) "sky130A"
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hvl"
+set ::env(PDK_ROOT) "/home/xrex/usr/devel/pdks"
+set ::env(CELL_PAD) "0"
+set ::env(MERGED_LEF) "/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged.lef"
+set ::env(MERGED_LEF_UNPADDED) "/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef"
+set ::env(TRACKS_INFO_FILE) "/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/tracks_copy.info"
+set ::env(TECH_LEF) "/home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/techlef/sky130_fd_sc_hvl.tlef"
+# Design config
+set ::env(CLOCK_PERIOD) "10"
+# Synthesis config
+set ::env(LIB_SYNTH) "/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/trimmed.lib"
+set ::env(LIB_SYNTH_COMPLETE) " /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib "
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hvl__inv_16"
+set ::env(SYNTH_CAP_LOAD) "35.49"
+set ::env(SYNTH_MAX_FANOUT) "5"
+set ::env(SYNTH_NO_FLAT) "0"
+set ::env(SYNTH_MAX_TRAN) "[expr {0.1*10}]"
+set ::env(LIB_FASTEST) "/home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ff_n40C_5v50.lib"
+set ::env(LIB_SLOWEST) "/home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ss_150C_1v65.lib"
+set ::env(LIB_TYPICAL) " /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib "
+set ::env(SYNTH_SCRIPT) "/openLANE_flow/scripts/synth.tcl"
+set ::env(SYNTH_STRATEGY) "2"
+set ::env(CLOCK_BUFFER_FANOUT) "16"
+set ::env(BASE_SDC_FILE) "/openLANE_flow/scripts/base.sdc"
+# Floorplan config
+set ::env(FP_CORE_UTIL) "50"
+set ::env(FP_ASPECT_RATIO) "1"
+set ::env(FP_CORE_MARGIN) "0"
+set ::env(FP_IO_HMETAL) "4"
+set ::env(FP_IO_VMETAL) "3"
+set ::env(FP_ENDCAP_CELL) "sky130_fd_sc_hvl__decap_4"
+set ::env(FP_PDN_VOFFSET) "16.32"
+set ::env(FP_PDN_VPITCH) "153.6"
+set ::env(FP_PDN_HOFFSET) "16.65"
+set ::env(FP_PDN_HPITCH) "153.18"
+set ::env(FP_TAPCELL_DIST) "14"
+# Placement config
+set ::env(PL_TARGET_DENSITY) "0.55"
+set ::env(PL_TIME_DRIVEN) "0"
+set ::env(PL_LIB) " /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib "
+set ::env(PL_BASIC_PLACEMENT) "0"
+set ::env(PL_SKIP_INITIAL_PLACEMENT) "0"
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) "1"
+set ::env(PSN_ENABLE_RESIZING) "1"
+set ::env(PSN_ENABLE_PIN_SWAP) "1"
+set ::env(PL_RESIZER_OVERBUFFER) "0"
+# CTS config
+set ::env(CTS_TARGET_SKEW) "200"
+set ::env(CTS_ROOT_BUFFER) "sky130_fd_sc_hvl__buf_16"
+set ::env(CTS_TECH_DIR) "N/A"
+set ::env(CTS_TOLERANCE) "100"
+# Routing config
+set ::env(GLB_RT_MAXLAYER) "6"
+set ::env(GLB_RT_ADJUSTMENT) "0"
+set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
+set ::env(GLB_RT_L2_ADJUSTMENT) "0"
+set ::env(GLB_RT_MINLAYER) "1"
+set ::env(GLB_RT_MAXLAYER) "6"
+set ::env(GLB_RT_UNIDIRECTIONAL) "1"
+set ::env(GLB_RT_ALLOW_CONGESTION) "0"
+set ::env(GLB_RT_OVERFLOW_ITERS) "50"
+set ::env(GLB_RT_TILES) "15"
+set ::env(GLB_RT_ESTIMATE_PARASITICS) "0"
+set ::env(GLB_RT_MAX_DIODE_INS_ITERS) "1"
+set ::env(DIODE_PADDING) "2"
+set ::env(SPEF_WIRE_MODEL) "PI"
+set ::env(SPEF_EDGE_CAP_FACTOR) "1"
+# Flow control config
+set ::env(RUN_SIMPLE_CTS) "0"
+set ::env(RUN_ROUTING_DETAILED) "1"
+set ::env(CLOCK_TREE_SYNTH) "0"
+set ::env(LEC_ENABLE) "0"
+set ::env(FILL_INSERTION) "1"
+set ::env(DIODE_INSERTION_STRATEGY) "3"
+set ::env(CHECK_ASSIGN_STATEMENTS) "0"
+set ::env(CHECK_UNMAPPED_CELLS) "1"
+set ::env(USE_ARC_ANTENNA_CHECK) "1"
+set ::env(RUN_SPEF_EXTRACTION) "1"
+set ::env(CURRENT_DEF) /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def
+set ::env(CURRENT_NETLIST) /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.powered.v
+set ::env(PREV_NETLIST) /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/synthesis/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis_preroute.v
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/cts/cts.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/cts/cts.log
new file mode 100644
index 0000000..86ce643
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/cts/cts.log
@@ -0,0 +1 @@
+SKIPPED!
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/ioPlacer.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/ioPlacer.log
new file mode 100644
index 0000000..485a036
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/ioPlacer.log
@@ -0,0 +1,33 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Notice 0: Reading LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 69 library cells
+Notice 0: Finished LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged.lef
+Notice 0:
+Reading DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/verilog2def_openroad.def
+Notice 0: Design: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Notice 0: Created 2 pins.
+Notice 0: Created 1 components and 7 component-terminals.
+Notice 0: Created 2 nets and 2 connections.
+Notice 0: Finished DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/verilog2def_openroad.def
+#Macro blocks found: 0
+Using 5u default boundaries offset
+Using 2 tracks default min distance between IO pins
+ > Running IO placement
+ * Num of slots 62
+ * Num of I/O 2
+ * Num of I/O w/sink 2
+ * Num of I/O w/o sink 0
+ * Slots Per Section 200
+ * Slots Increase Factor 0.01
+ * Usage Per Section 0.8
+ * Usage Increase Factor 0.01
+ * Force Pin Spread 1
+
+Random pin placement
+RandomMode Even
+ > IO placement done.
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/ioPlacer_runtime.txt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/ioPlacer_runtime.txt
new file mode 100644
index 0000000..ca36d43
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/ioPlacer_runtime.txt
@@ -0,0 +1 @@
+0h0m0s426ms
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/pdn.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/pdn.log
new file mode 100644
index 0000000..080fb7b
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/pdn.log
@@ -0,0 +1,35 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Notice 0: Reading LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 69 library cells
+Notice 0: Finished LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/placement/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.placement.def
+Notice 0: Design: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Notice 0: Created 2 pins.
+Notice 0: Created 1 components and 7 component-terminals.
+Notice 0: Created 2 nets and 2 connections.
+Notice 0: Finished DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/placement/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.placement.def
+[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
+[INFO] [PDNG-0016] config: /home/xrex/usr/devel/pdks/sky130A/libs.tech/openlane/common_pdn.tcl
+[INFO] [PDNG-0008] Design Name is sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+[INFO] [PDNG-0009] Reading technology data
+[INFO] [PDNG-0011] ****** INFO ******
+Type: stdcell, grid
+ Stdcell Rails
+ Layer: met1 - width: 0.510 pitch: 8.140 offset: 0.000
+ Straps
+ Layer: met4 - width: 1.600 pitch: 8.333 offset: 4.167
+ Layer: met5 - width: 1.600 pitch: 8.333 offset: 4.167
+ Connect: {met1 met4} {met4 met5}
+Type: macro, macro_1
+ Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
+ Straps
+ Connect: {met4_PIN_ver met5}
+[INFO] [PDNG-0012] **** END INFO ****
+[INFO] [PDNG-0013] Inserting stdcell grid - grid
+[INFO] [PDNG-0015] Writing to database
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/pdn_runtime.txt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/pdn_runtime.txt
new file mode 100644
index 0000000..71ddd64
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/pdn_runtime.txt
@@ -0,0 +1 @@
+0h0m0s465ms
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/verilog2def.openroad.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/verilog2def.openroad.log
new file mode 100644
index 0000000..17ec292
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/verilog2def.openroad.log
@@ -0,0 +1,12 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib, line 35 default_operating_condition tt_025C_3v30 not found.
+Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib, line 31 default_operating_condition tt_025C_3v30_lv1v80 not found.
+Notice 0: Reading LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 69 library cells
+Notice 0: Finished LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Info: Added 3 rows of 52 sites.
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/verilog2def_openroad_runtime.txt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/verilog2def_openroad_runtime.txt
new file mode 100644
index 0000000..469915f
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/floorplan/verilog2def_openroad_runtime.txt
@@ -0,0 +1 @@
+0h0m0s551ms
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/lvs/lvs.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/lvs/lvs.log
new file mode 100644
index 0000000..5ce5569
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/lvs/lvs.log
@@ -0,0 +1,38 @@
+Netgen 1.5.157 compiled on Fri Oct 9 13:50:13 UTC 2020
+Warning: netgen command 'format' use fully-qualified name '::netgen::format'
+Warning: netgen command 'global' use fully-qualified name '::netgen::global'
+Generating JSON file result
+Reading netlist file /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.spice
+Reading netlist file /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.powered.v
+Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match.
+Creating placeholder cell definition for module sky130_fd_sc_hvl__decap_8.
+Creating placeholder cell definition for module sky130_fd_sc_hvl__decap_4.
+Creating placeholder cell definition for module sky130_fd_sc_hvl__fill_2.
+Creating placeholder cell definition for module sky130_fd_sc_hvl__fill_1.
+Creating placeholder cell definition for module sky130_fd_sc_hvl__lsbufhv2lv_1.
+Reading setup file /home/xrex/usr/devel/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl
+Comparison output logged to file /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.log
+Logging to file "/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.log" enabled
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hvl__lsbufhv2lv_1'
+Circuit sky130_fd_sc_hvl__lsbufhv2lv_1 contains 0 device instances.
+Circuit contains 0 nets, and 7 disconnected pins.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hvl__lsbufhv2lv_1'
+Circuit sky130_fd_sc_hvl__lsbufhv2lv_1 contains 0 device instances.
+Circuit contains 0 nets.
+
+Circuit sky130_fd_sc_hvl__lsbufhv2lv_1 contains no devices.
+Contents of circuit 1: Circuit: 'sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'
+Circuit sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped contains 1 device instances.
+ Class: sky130_fd_sc_hvl__lsbufhv2lv_1 instances: 1
+Circuit contains 13 nets.
+Contents of circuit 2: Circuit: 'sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'
+Circuit sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped contains 1 device instances.
+ Class: sky130_fd_sc_hvl__lsbufhv2lv_1 instances: 1
+Circuit contains 4 nets.
+
+Circuit 1 contains 1 devices, Circuit 2 contains 1 devices.
+Circuit 1 contains 6 nets, Circuit 2 contains 4 nets. *** MISMATCH ***
+
+Result: Netlists do not match.
+Logging to file "/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.log" disabled
+LVS Done.
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/lvs/write_powered_verilog.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/lvs/write_powered_verilog.log
new file mode 100644
index 0000000..05f382b
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/lvs/write_powered_verilog.log
@@ -0,0 +1,19 @@
+Notice 0: Reading LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 69 library cells
+Notice 0: Finished LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged.lef
+Notice 0:
+Reading DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def
+Notice 0: Design: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Notice 0: Created 4 pins.
+Notice 0: Created 22 components and 91 component-terminals.
+Notice 0: Created 2 special nets and 89 connections.
+Notice 0: Created 2 nets and 2 connections.
+Notice 0: Finished DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def
+Top-level design name: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Found port VPWR of type SIGNAL
+Found port VGND of type SIGNAL
+Power net: VPWR
+Ground net: VGND
+Modified power connections of 22 cells (Remaining: 0 ).
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.drc b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.drc
new file mode 100644
index 0000000..f853e1a
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.drc
@@ -0,0 +1,58 @@
+sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+----------------------------------------
+N-Diffusion spacing to N-well < 0.34um (diff/tap.9)
+----------------------------------------
+ 7.720 16.285 8.495 16.335
+ 8.495 16.285 8.995 16.335
+ 8.995 16.285 9.275 16.335
+ 9.275 16.285 9.775 16.335
+ 9.775 16.285 10.055 16.335
+ 10.055 16.285 10.555 16.335
+ 10.555 16.285 10.820 16.335
+ 10.820 16.285 11.160 16.335
+----------------------------------------
+MV diffusion to LV nwell spacing < 0.825um (hvi.5 + nsd/psd.5)
+----------------------------------------
+ 10.580 13.370 10.865 14.135
+ 10.580 10.910 10.865 11.735
+ 10.580 10.485 10.865 10.685
+ 10.580 13.370 10.865 14.135
+ 10.580 12.485 10.865 13.310
+ 10.580 10.910 10.865 13.310
+ 10.580 11.435 10.865 12.260
+ 10.580 10.485 10.865 12.260
+ 10.580 10.485 10.865 10.840
+ 10.580 10.485 10.865 10.840
+ 10.580 10.485 10.865 10.730
+ 10.580 10.485 10.865 10.725
+ 9.775 14.195 10.040 14.945
+ 9.775 11.735 10.040 12.485
+ 9.775 10.685 10.040 11.435
+ 9.775 9.660 10.040 10.015
+ 9.775 9.660 10.040 10.015
+ 9.775 14.195 10.040 14.945
+----------------------------------------
+Can't overlap those layers
+----------------------------------------
+ 7.050 16.615 15.210 16.785
+ 7.050 16.615 15.210 16.785
+----------------------------------------
+Spacing of HV nwell to LV nwell < 2.0um (nwell.8)
+----------------------------------------
+ 10.580 14.030 12.050 14.135
+ 8.580 16.030 10.580 16.135
+ 8.580 16.030 14.050 16.135
+ 12.050 16.030 14.050 16.135
+----------------------------------------
+Spacing of HV nwell to HV nwell < 2.0um (nwell.8)
+----------------------------------------
+ 6.720 14.030 8.580 14.815
+ 14.050 14.030 15.540 14.815
+ 4.720 16.030 8.580 16.815
+ 12.050 16.030 15.540 16.815
+ 8.580 16.030 10.580 16.815
+ 15.540 16.030 17.540 16.815
+----------------------------------------
+[INFO]: COUNT: 38
+[INFO]: Should be divided by 3 or 4
+
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.drc.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.drc.log
new file mode 100644
index 0000000..a1c1d13
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.drc.log
@@ -0,0 +1,36 @@
+
+Magic 8.3 revision 87 - Compiled on Mon Nov 23 17:53:03 UTC 2020.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130: scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/openLANE_flow/scripts/magic_drc.tcl" from command line.
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Reading "sky130_fd_sc_hvl__decap_8".
+CIF file read warning: CIF style sky130: units rescaled by factor of 5 / 1
+Error while reading cell "sky130_fd_sc_hvl__decap_8" (byte position 6932): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hvl__decap_4".
+Error while reading cell "sky130_fd_sc_hvl__decap_4" (byte position 9116): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hvl__fill_2".
+Error while reading cell "sky130_fd_sc_hvl__fill_2" (byte position 13344): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
+Error while reading cell "sky130_fd_sc_hvl__lsbufhv2lv_1" (byte position 29090): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hvl__fill_1".
+Error while reading cell "sky130_fd_sc_hvl__fill_1" (byte position 34916): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped".
+[INFO]: Loading sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+[INFO]: COUNT: 38
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.drc)
+[INFO]: Saving mag view with DRC errors(/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.drc.mag)
+[INFO]: Saved
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.log
new file mode 100644
index 0000000..b14821f
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.log
@@ -0,0 +1,25 @@
+
+Magic 8.3 revision 87 - Compiled on Mon Nov 23 17:53:03 UTC 2020.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130: scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/openLANE_flow/scripts/magic_mag.tcl" from command line.
+Box tool must be present
+[INFO]: Saving .mag view With BBox Values:
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Reading "sky130_fd_sc_hvl__decap_8".
+CIF file read warning: CIF style sky130: units rescaled by factor of 5 / 1
+Reading "sky130_fd_sc_hvl__decap_4".
+Reading "sky130_fd_sc_hvl__fill_2".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
+Reading "sky130_fd_sc_hvl__fill_1".
+Reading "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped".
+[INFO]: MAGIC TAPEOUT STEP DONE
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.maglef.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.maglef.log
new file mode 100644
index 0000000..830317d
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic.maglef.log
@@ -0,0 +1,16 @@
+
+Magic 8.3 revision 87 - Compiled on Mon Nov 23 17:53:03 UTC 2020.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130: scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/openLANE_flow/scripts/magic_maglef.tcl" from command line.
+Reading LEF data from file /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lef.
+This action cannot be undone.
+LEF read: Processed 59 lines.
+[INFO]: DONE GENERATING MAGLEF VIEW
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic_ext2spice.feedback.txt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic_ext2spice.feedback.txt
new file mode 100644
index 0000000..a317441
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic_ext2spice.feedback.txt
@@ -0,0 +1,22 @@
+box 1344 1605 1401 1651
+feedback add "Illegal overlap (types do not connect)" medium
+box 1399 1605 1544 1651
+feedback add "Illegal overlap (types do not connect)" medium
+box 1544 1605 1596 1651
+feedback add "Illegal overlap (types do not connect)" medium
+box 1596 1605 1608 1651
+feedback add "Illegal overlap (types do not connect)" medium
+box 1608 1605 1660 1651
+feedback add "Illegal overlap (types do not connect)" medium
+box 1660 1605 1672 1651
+feedback add "Illegal overlap (types do not connect)" medium
+box 1672 1605 1724 1651
+feedback add "Illegal overlap (types do not connect)" medium
+box 1724 1605 1736 1651
+feedback add "Illegal overlap (types do not connect)" medium
+box 1736 1605 1788 1651
+feedback add "Illegal overlap (types do not connect)" medium
+box 1788 1605 2801 1651
+feedback add "Illegal overlap (types do not connect)" medium
+box 2799 1605 2976 1651
+feedback add "Illegal overlap (types do not connect)" medium
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic_spice.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic_spice.log
new file mode 100644
index 0000000..20eb0bc
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic_spice.log
@@ -0,0 +1,47 @@
+
+Magic 8.3 revision 87 - Compiled on Mon Nov 23 17:53:03 UTC 2020.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130: scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/magic_spice.tcl" from command line.
+Reading LEF data from file /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/techlef/sky130_fd_sc_hvl.tlef.
+This action cannot be undone.
+LEF read, Line 64 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 77 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 98 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
+LEF read, Line 99 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 111 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 137 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
+LEF read, Line 138 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 155 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 174 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 191 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 209 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 227 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read, Line 246 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
+LEF read, Line 263 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
+LEF read: Processed 769 lines.
+Reading DEF data from file /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def.
+This action cannot be undone.
+ Processed 6 vias total.
+ Processed 22 subcell instances total.
+ Processed 4 pins total.
+ Processed 2 special nets total.
+ Processed 2 nets total.
+DEF read: Processed 198 lines.
+Extracting sky130_fd_sc_hvl__fill_1 into sky130_fd_sc_hvl__fill_1.ext:
+Extracting sky130_fd_sc_hvl__fill_2 into sky130_fd_sc_hvl__fill_2.ext:
+Extracting sky130_fd_sc_hvl__decap_4 into sky130_fd_sc_hvl__decap_4.ext:
+Extracting sky130_fd_sc_hvl__decap_8 into sky130_fd_sc_hvl__decap_8.ext:
+Extracting sky130_fd_sc_hvl__lsbufhv2lv_1 into sky130_fd_sc_hvl__lsbufhv2lv_1.ext:
+Extracting sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped into sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.ext:
+sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped: 11 fatal errors
+Total of 11 fatal errors.
+exttospice finished.
+Using technology "sky130A", version 1.0.73-5-g748e1a9
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/opendp.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/opendp.log
new file mode 100644
index 0000000..160c02d
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/opendp.log
@@ -0,0 +1,40 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Notice 0: Reading LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 69 library cells
+Notice 0: Finished LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/placement/openphysyn.def
+Notice 0: Design: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Notice 0: Created 2 pins.
+Notice 0: Created 1 components and 7 component-terminals.
+Notice 0: Created 2 nets and 2 connections.
+Notice 0: Finished DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/placement/openphysyn.def
+Warning: could not find power special net
+Design Stats
+--------------------------------
+total instances 1
+multi row instances 0
+fixed instances 0
+nets 2
+design area 609.5 u^2
+fixed area 0.0 u^2
+movable area 66.4 u^2
+utilization 11 %
+utilization padded 11 %
+rows 3
+row height 8.1 u
+
+Placement Analysis
+--------------------------------
+total displacement 6.6 u
+average displacement 6.6 u
+max displacement 6.6 u
+original HPWL 39.0 u
+legalized HPWL 39.0 u
+delta HPWL 0 %
+
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/opendp_runtime.txt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/opendp_runtime.txt
new file mode 100644
index 0000000..ba5b78d
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/opendp_runtime.txt
@@ -0,0 +1 @@
+0h0m0s440ms
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/openphysyn.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/openphysyn.log
new file mode 100644
index 0000000..6658ce8
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/openphysyn.log
@@ -0,0 +1,55 @@
+[OpenPhySyn] [2020-11-27 17:21:59.963] [info] Loaded 6 transforms.
+[OpenPhySyn] [2020-11-27 17:22:00.338] [info] OpenPhySyn: 1.8.1
+Warning: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/opt.lib, line 36 default_operating_condition ss_150C_1v65 not found.
+Notice 0: Reading LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 69 library cells
+Notice 0: Finished LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/placement/replace.def
+Notice 0: Design: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Notice 0: Created 2 pins.
+Notice 0: Created 1 components and 7 component-terminals.
+Notice 0: Created 2 nets and 2 connections.
+Notice 0: Finished DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/placement/replace.def
+Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
+=============== Initial Reports =============
+No paths found.
+Capacitance violations: 0
+Transition violations: 0
+wns 0.00
+tns 0.00
+Initial area: 664 um2
+OpenPhySyn timing repair:
+[OpenPhySyn] [2020-11-27 17:22:00.415] [info] Invoking repair_timing transform
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Buffer library: sky130_fd_sc_hvl__buf_16, sky130_fd_sc_hvl__buf_32, sky130_fd_sc_hvl__buf_4
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Inverter library: None
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Buffering: enabled
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Driver sizing: enabled
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Pin-swapping: enabled
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Mode: Timing-Driven
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Iteration 1
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] No more violations or cannot find more optimal buffer
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Runtime: 0s
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Buffers: 0
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Resize up: 0
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Resize down: 0
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Pin Swap: 0
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Buffered nets: 0
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Fanout violations: 0
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Transition violations: 0
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Capacitance violations: 0
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Slack gain: 0.0
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Initial area: 66
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] New area: 66
+[OpenPhySyn] [2020-11-27 17:22:00.424] [info] Finished repair_timing transform (0)
+Added/updated 0 cells
+=============== Final Reports =============
+No paths found.
+Capacitance violations: 0
+Transition violations: 0
+wns 0.00
+tns 0.00
+Final area: 664 um2
+Export optimized design
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/openphysyn_runtime.txt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/openphysyn_runtime.txt
new file mode 100644
index 0000000..a9f7066
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/openphysyn_runtime.txt
@@ -0,0 +1 @@
+0h0m0s960ms
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/replace.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/replace.log
new file mode 100644
index 0000000..6ecce37
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/replace.log
@@ -0,0 +1,16 @@
+Notice 0: Reading LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 69 library cells
+Notice 0: Finished LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/ioPlacer.def
+Notice 0: Design: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Notice 0: Created 2 pins.
+Notice 0: Created 1 components and 7 component-terminals.
+Notice 0: Created 2 nets and 2 connections.
+Notice 0: Finished DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/ioPlacer.def
+Design name: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Core Area Boundaries: 0 0 24960 24420
+Number of instances 1
+Placed 1 instances
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/replace_runtime.txt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/replace_runtime.txt
new file mode 100644
index 0000000..ffdf9c0
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/placement/replace_runtime.txt
@@ -0,0 +1 @@
+0h0m0s137ms
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/addspacers.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/addspacers.log
new file mode 100644
index 0000000..6e6cbc5
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/addspacers.log
@@ -0,0 +1,18 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Notice 0: Reading LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 69 library cells
+Notice 0: Finished LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/routing/fastroute.def
+Notice 0: Design: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Notice 0: Created 4 pins.
+Notice 0: Created 1 components and 7 component-terminals.
+Notice 0: Created 2 special nets and 5 connections.
+Notice 0: Created 2 nets and 2 connections.
+Notice 0: Finished DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/routing/fastroute.def
+Placed 21 filler instances.
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/addspacers_runtime.txt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/addspacers_runtime.txt
new file mode 100644
index 0000000..d7cb996
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/addspacers_runtime.txt
@@ -0,0 +1 @@
+0h0m0s419ms
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/fastroute.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/fastroute.log
new file mode 100644
index 0000000..61c74ae
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/fastroute.log
@@ -0,0 +1,191 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib, line 35 default_operating_condition tt_025C_3v30 not found.
+Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib, line 31 default_operating_condition tt_025C_3v30_lv1v80 not found.
+Notice 0: Reading LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 69 library cells
+Notice 0: Finished LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/pdn.def
+Notice 0: Design: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Notice 0: Created 16 pins.
+Notice 0: Created 1 components and 7 component-terminals.
+Notice 0: Created 2 special nets and 5 connections.
+Notice 0: Created 2 nets and 2 connections.
+Notice 0: Finished DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/pdn.def
+[PARAMS] Min routing layer: 2
+[PARAMS] Max routing layer: 6
+[PARAMS] Global adjustment: 0
+[PARAMS] Unidirectional routing: 1
+[PARAMS] Grid origin: (-1, -1)
+[INFO] #DB Obstructions: 0
+[INFO] #DB Obstacles: 94
+[INFO] #DB Macros: 0
+[WARNING] Net VPWR has wires outside die area
+[WARNING] Net VPWR has wires outside die area
+[WARNING] Net VPWR has wires outside die area
+[WARNING] Net VPWR has wires outside die area
+[WARNING] Net VGND has wires outside die area
+[WARNING] Net VGND has wires outside die area
+[INFO] Found 0 clock nets
+[INFO] Minimum degree: 2
+[INFO] Maximum degree: 2
+[INFO] Processing 39 obstacles on layer 1
+[INFO] Processing 12 obstacles on layer 2
+[INFO] Processing 5 obstacles on layer 5
+[INFO] Processing 5 obstacles on layer 6
+[INFO] Reducing resources of layer 1 by 99%
+[INFO] WIRELEN : 4, WIRELEN1 : 0
+[INFO] NumSeg : 2
+[INFO] NumShift: 0
+First L Route
+[INFO] WIRELEN : 4, WIRELEN1 : 4
+[INFO] NumSeg : 2
+[INFO] NumShift: 0
+[Overflow Report] Total hCap : 146
+[Overflow Report] Total vCap : 138
+[Overflow Report] Total Usage : 4
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+Second L Route
+[Overflow Report] Total hCap : 146
+[Overflow Report] Total vCap : 138
+[Overflow Report] Total Usage : 4
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+First Z Route
+[Overflow Report] Total hCap : 146
+[Overflow Report] Total vCap : 138
+[Overflow Report] Total Usage : 4
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+[INFO] LV routing round 0, enlarge 10
+[INFO] 10 threshold, 10 expand
+[Overflow Report] total Usage : 4
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+[INFO] LV routing round 1, enlarge 15
+[INFO] 5 threshold, 15 expand
+[Overflow Report] total Usage : 4
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+[INFO] LV routing round 2, enlarge 20
+[INFO] 1 threshold, 20 expand
+[Overflow Report] total Usage : 4
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+Usage checked
+Maze routing finished
+[INFO] P3 runtime: 0.000000 sec
+[INFO] Final 2D results:
+[Overflow Report] total Usage : 4
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+Layer Assignment Begins
+Layer assignment finished
+[INFO] 2D + Layer Assignment Runtime: 0.000000 sec
+Post Processing Begins
+Post Processsing finished
+ Starting via filling
+[INFO] Via related to pin nodes 6
+[INFO] Via related stiner nodes 0
+Via filling finished
+
+Final usage/overflow report:
+[INFO] Usage per layer:
+ Layer 1 usage: 0
+ Layer 2 usage: 2
+ Layer 3 usage: 2
+ Layer 4 usage: 0
+ Layer 5 usage: 0
+ Layer 6 usage: 0
+
+[INFO] Capacity per layer:
+ Layer 1 capacity: 0
+ Layer 2 capacity: 70
+ Layer 3 capacity: 100
+ Layer 4 capacity: 64
+ Layer 5 capacity: 38
+ Layer 6 capacity: 12
+
+[INFO] Use percentage per layer:
+ Layer 1 use percentage: 0.0%
+ Layer 2 use percentage: 2.86%
+ Layer 3 use percentage: 2.00%
+ Layer 4 use percentage: 0.00%
+ Layer 5 use percentage: 0.00%
+ Layer 6 use percentage: 0.00%
+
+[INFO] Overflow per layer:
+ Layer 1 overflow: 0
+ Layer 2 overflow: 0
+ Layer 3 overflow: 0
+ Layer 4 overflow: 0
+ Layer 5 overflow: 0
+ Layer 6 overflow: 0
+
+[Overflow Report] Total Usage : 4
+[Overflow Report] Total Capacity: 284
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+[INFO] Final usage : 4
+[INFO] Final number of vias : 8
+[INFO] Final usage 3D : 28
+[INFO] Total wirelength: 100 um
+Notice 0: Split top of 1 T shapes.
+Repairing antennas...
+[WARNING]No OR_DEFAULT vias defined
+[INFO] #Antenna violations: 0
+[INFO] Num routed nets: 2
+[WARN]: No CLOCK_PORT found. Skipping STA...
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/fastroute_post_antenna.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/fastroute_post_antenna.log
new file mode 100644
index 0000000..395dbbd
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/fastroute_post_antenna.log
@@ -0,0 +1,187 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib, line 35 default_operating_condition tt_025C_3v30 not found.
+Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib, line 31 default_operating_condition tt_025C_3v30_lv1v80 not found.
+Notice 0: Reading LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 69 library cells
+Notice 0: Finished LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/routing/fastroute.def
+Notice 0: Design: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Notice 0: Created 4 pins.
+Notice 0: Created 1 components and 7 component-terminals.
+Notice 0: Created 2 special nets and 5 connections.
+Notice 0: Created 2 nets and 2 connections.
+Notice 0: Finished DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/routing/fastroute.def
+[PARAMS] Min routing layer: 2
+[PARAMS] Max routing layer: 6
+[PARAMS] Global adjustment: 0
+[PARAMS] Unidirectional routing: 1
+[PARAMS] Grid origin: (-1, -1)
+[INFO] #DB Obstructions: 0
+[INFO] #DB Obstacles: 94
+[INFO] #DB Macros: 0
+[WARNING] Net VPWR has wires outside die area
+[WARNING] Net VPWR has wires outside die area
+[WARNING] Net VPWR has wires outside die area
+[WARNING] Net VPWR has wires outside die area
+[WARNING] Net VGND has wires outside die area
+[WARNING] Net VGND has wires outside die area
+[INFO] Found 0 clock nets
+[INFO] Minimum degree: 2
+[INFO] Maximum degree: 2
+[INFO] Processing 39 obstacles on layer 1
+[INFO] Processing 12 obstacles on layer 2
+[INFO] Processing 5 obstacles on layer 5
+[INFO] Processing 5 obstacles on layer 6
+[INFO] Reducing resources of layer 1 by 99%
+[INFO] WIRELEN : 4, WIRELEN1 : 0
+[INFO] NumSeg : 2
+[INFO] NumShift: 0
+First L Route
+[INFO] WIRELEN : 4, WIRELEN1 : 4
+[INFO] NumSeg : 2
+[INFO] NumShift: 0
+[Overflow Report] Total hCap : 146
+[Overflow Report] Total vCap : 138
+[Overflow Report] Total Usage : 4
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+Second L Route
+[Overflow Report] Total hCap : 146
+[Overflow Report] Total vCap : 138
+[Overflow Report] Total Usage : 4
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+First Z Route
+[Overflow Report] Total hCap : 146
+[Overflow Report] Total vCap : 138
+[Overflow Report] Total Usage : 4
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+[INFO] LV routing round 0, enlarge 10
+[INFO] 10 threshold, 10 expand
+[Overflow Report] total Usage : 4
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+[INFO] LV routing round 1, enlarge 15
+[INFO] 5 threshold, 15 expand
+[Overflow Report] total Usage : 4
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+[INFO] LV routing round 2, enlarge 20
+[INFO] 1 threshold, 20 expand
+[Overflow Report] total Usage : 4
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+Usage checked
+Maze routing finished
+[INFO] P3 runtime: 0.000000 sec
+[INFO] Final 2D results:
+[Overflow Report] total Usage : 4
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] Num Overflow e: 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+Layer Assignment Begins
+Layer assignment finished
+[INFO] 2D + Layer Assignment Runtime: 0.000000 sec
+Post Processing Begins
+Post Processsing finished
+ Starting via filling
+[INFO] Via related to pin nodes 6
+[INFO] Via related stiner nodes 0
+Via filling finished
+
+Final usage/overflow report:
+[INFO] Usage per layer:
+ Layer 1 usage: 0
+ Layer 2 usage: 2
+ Layer 3 usage: 2
+ Layer 4 usage: 0
+ Layer 5 usage: 0
+ Layer 6 usage: 0
+
+[INFO] Capacity per layer:
+ Layer 1 capacity: 0
+ Layer 2 capacity: 70
+ Layer 3 capacity: 100
+ Layer 4 capacity: 64
+ Layer 5 capacity: 38
+ Layer 6 capacity: 12
+
+[INFO] Use percentage per layer:
+ Layer 1 use percentage: 0.0%
+ Layer 2 use percentage: 2.86%
+ Layer 3 use percentage: 2.00%
+ Layer 4 use percentage: 0.00%
+ Layer 5 use percentage: 0.00%
+ Layer 6 use percentage: 0.00%
+
+[INFO] Overflow per layer:
+ Layer 1 overflow: 0
+ Layer 2 overflow: 0
+ Layer 3 overflow: 0
+ Layer 4 overflow: 0
+ Layer 5 overflow: 0
+ Layer 6 overflow: 0
+
+[Overflow Report] Total Usage : 4
+[Overflow Report] Total Capacity: 284
+[Overflow Report] Max H Overflow: 0
+[Overflow Report] Max V Overflow: 0
+[Overflow Report] Max Overflow : 0
+[Overflow Report] H Overflow : 0
+[Overflow Report] V Overflow : 0
+[Overflow Report] Final Overflow: 0
+
+[INFO] Final usage : 4
+[INFO] Final number of vias : 8
+[INFO] Final usage 3D : 28
+[INFO] Total wirelength: 100 um
+[INFO] Num routed nets: 2
+[WARN]: No CLOCK_PORT found. Skipping STA...
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/fastroute_runtime.txt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/fastroute_runtime.txt
new file mode 100644
index 0000000..d94c259
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/fastroute_runtime.txt
@@ -0,0 +1 @@
+0h0m1s182ms
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/or_antenna.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/or_antenna.log
new file mode 100644
index 0000000..cbd396b
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/or_antenna.log
@@ -0,0 +1,20 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Notice 0: Reading LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 69 library cells
+Notice 0: Finished LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def
+Notice 0: Design: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Notice 0: Created 4 pins.
+Notice 0: Created 22 components and 91 component-terminals.
+Notice 0: Created 2 special nets and 89 connections.
+Notice 0: Created 2 nets and 2 connections.
+Notice 0: Finished DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def
+Number of pins violated: 0
+Number of nets violated: 0
+Total number of nets: 2
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/spef_extraction.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/spef_extraction.log
new file mode 100644
index 0000000..6dae333
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/spef_extraction.log
@@ -0,0 +1,12 @@
+Start parsing LEF file...
+Parsing LEF file done.
+Start parsing DEF file...
+Parsing DEF file done.
+
+Parameters Used:
+Edge Capacitance Factor: 1.0
+Wire model: PI
+
+RC Extraction is done
+Start writing SPEF file
+Writing SPEF is done
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/tritonRoute.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/tritonRoute.log
new file mode 100644
index 0000000..ce150f6
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/tritonRoute.log
@@ -0,0 +1,480 @@
+
+reading lef ...
+
+units: 1000
+#layers: 13
+#macros: 69
+#vias: 25
+#viarulegen: 25
+
+reading def ...
+
+design: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+die area: ( 0 0 ) ( 25000 25000 )
+trackPts: 12
+defvias: 4
+#components: 22
+#terminals: 4
+#snets: 2
+#nets: 2
+
+reading guide ...
+
+#guides: 9
+Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
+Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
+done initConstraintLayerIdx
+List of default vias:
+ Layer mcon
+ default via: L1M1_PR_MR
+ Layer via
+ default via: M1M2_PR
+ Layer via2
+ default via: via2_FR
+ Layer via3
+ default via: M3M4_PR_M
+ Layer via4
+ default via: via4_FR
+Writing reference output def...
+
+libcell analysis ...
+
+instance analysis ...
+#unique instances = 7
+
+init region query ...
+ complete FR_MASTERSLICE
+ complete FR_VIA
+ complete li1
+ complete mcon
+ complete met1
+ complete via
+ complete met2
+ complete via2
+ complete met3
+ complete via3
+ complete met4
+ complete via4
+ complete met5
+
+FR_MASTERSLICE shape region query size = 0
+FR_VIA shape region query size = 0
+li1 shape region query size = 191
+mcon shape region query size = 540
+met1 shape region query size = 108
+via shape region query size = 40
+met2 shape region query size = 22
+via2 shape region query size = 40
+met3 shape region query size = 20
+via3 shape region query size = 40
+met4 shape region query size = 28
+via4 shape region query size = 13
+met5 shape region query size = 18
+
+
+start pin access
+ complete 2 pins
+ complete 5 unique inst patterns
+ complete 1 groups
+Expt1 runtime (pin-level access point gen): 0.0226711
+Expt2 runtime (design-level access pattern gen): 0.000787974
+#scanned instances = 22
+#unique instances = 7
+#stdCellGenAp = 10
+#stdCellValidPlanarAp = 0
+#stdCellValidViaAp = 8
+#stdCellPinNoAp = 0
+#stdCellPinCnt = 2
+#instTermValidViaApCnt = 0
+#macroGenAp = 0
+#macroValidPlanarAp = 0
+#macroValidViaAp = 0
+#macroNoAp = 0
+
+complete pin access
+cpu time = 00:00:00, elapsed time = 00:00:00, memory = 6.67 (MB), peak = 6.94 (MB)
+
+post process guides ...
+GCELLGRID X -1 DO 3 STEP 7200 ;
+GCELLGRID Y -1 DO 3 STEP 7200 ;
+ complete FR_MASTERSLICE
+ complete FR_VIA
+ complete li1
+ complete mcon
+ complete met1
+ complete via
+ complete met2
+ complete via2
+ complete met3
+ complete via3
+ complete met4
+ complete via4
+ complete met5
+
+building cmap ...
+
+init guide query ...
+ complete FR_MASTERSLICE (guide)
+ complete FR_VIA (guide)
+ complete li1 (guide)
+ complete mcon (guide)
+ complete met1 (guide)
+ complete via (guide)
+ complete met2 (guide)
+ complete via2 (guide)
+ complete met3 (guide)
+ complete via3 (guide)
+ complete met4 (guide)
+ complete via4 (guide)
+ complete met5 (guide)
+
+FR_MASTERSLICE guide region query size = 0
+FR_VIA guide region query size = 0
+li1 guide region query size = 2
+mcon guide region query size = 0
+met1 guide region query size = 3
+via guide region query size = 0
+met2 guide region query size = 3
+via2 guide region query size = 0
+met3 guide region query size = 0
+via3 guide region query size = 0
+met4 guide region query size = 0
+via4 guide region query size = 0
+met5 guide region query size = 0
+
+init gr pin query ...
+
+
+start track assignment
+Done with 5 vertical wires in 1 frboxes and 3 horizontal wires in 1 frboxes.
+Done with 0 vertical wires in 1 frboxes and 0 horizontal wires in 1 frboxes.
+
+complete track assignment
+cpu time = 00:00:00, elapsed time = 00:00:00, memory = 6.94 (MB), peak = 7.12 (MB)
+
+post processing ...
+
+start routing data preparation
+initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
+initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
+initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
+initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
+initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
+initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
+initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
+initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
+initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
+initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
+initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
+initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
+initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
+initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
+initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
+initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
+initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
+initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
+initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
+initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
+initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
+initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
+initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
+initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
+initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
+initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
+initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
+initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
+initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
+initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
+initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
+initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
+initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
+initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
+initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
+initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
+cpu time = 00:00:00, elapsed time = 00:00:00, memory = 7.17 (MB), peak = 7.17 (MB)
+
+start detail routing ...
+start 0th optimization iteration ...
+ completing 10% with 0 violations
+ elapsed time = 00:00:00, memory = 8.50 (MB)
+ number of violations = 0
+cpu time = 00:00:00, elapsed time = 00:00:00, memory = 8.57 (MB), peak = 372.27 (MB)
+total wire length = 35 um
+total wire length on LAYER li1 = 0 um
+total wire length on LAYER met1 = 21 um
+total wire length on LAYER met2 = 14 um
+total wire length on LAYER met3 = 0 um
+total wire length on LAYER met4 = 0 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 4
+up-via summary (total 4):
+
+--------------------
+ FR_MASTERSLICE 0
+ li1 2
+ met1 2
+ met2 0
+ met3 0
+ met4 0
+--------------------
+ 4
+
+
+start 1st optimization iteration ...
+ completing 10% with 0 violations
+ elapsed time = 00:00:00, memory = 9.16 (MB)
+ number of violations = 0
+cpu time = 00:00:00, elapsed time = 00:00:00, memory = 15.16 (MB), peak = 372.93 (MB)
+total wire length = 35 um
+total wire length on LAYER li1 = 0 um
+total wire length on LAYER met1 = 21 um
+total wire length on LAYER met2 = 14 um
+total wire length on LAYER met3 = 0 um
+total wire length on LAYER met4 = 0 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 4
+up-via summary (total 4):
+
+--------------------
+ FR_MASTERSLICE 0
+ li1 2
+ met1 2
+ met2 0
+ met3 0
+ met4 0
+--------------------
+ 4
+
+
+start 2nd optimization iteration ...
+ completing 10% with 0 violations
+ elapsed time = 00:00:00, memory = 15.16 (MB)
+ completing 20% with 0 violations
+ elapsed time = 00:00:00, memory = 15.54 (MB)
+ completing 30% with 0 violations
+ elapsed time = 00:00:00, memory = 15.71 (MB)
+ completing 40% with 0 violations
+ elapsed time = 00:00:00, memory = 15.86 (MB)
+ number of violations = 0
+cpu time = 00:00:00, elapsed time = 00:00:00, memory = 15.86 (MB), peak = 372.93 (MB)
+total wire length = 35 um
+total wire length on LAYER li1 = 0 um
+total wire length on LAYER met1 = 21 um
+total wire length on LAYER met2 = 14 um
+total wire length on LAYER met3 = 0 um
+total wire length on LAYER met4 = 0 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 4
+up-via summary (total 4):
+
+--------------------
+ FR_MASTERSLICE 0
+ li1 2
+ met1 2
+ met2 0
+ met3 0
+ met4 0
+--------------------
+ 4
+
+
+start 17th optimization iteration ...
+ completing 10% with 0 violations
+ elapsed time = 00:00:00, memory = 15.86 (MB)
+ number of violations = 0
+cpu time = 00:00:00, elapsed time = 00:00:00, memory = 15.86 (MB), peak = 372.93 (MB)
+total wire length = 35 um
+total wire length on LAYER li1 = 0 um
+total wire length on LAYER met1 = 21 um
+total wire length on LAYER met2 = 14 um
+total wire length on LAYER met3 = 0 um
+total wire length on LAYER met4 = 0 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 4
+up-via summary (total 4):
+
+--------------------
+ FR_MASTERSLICE 0
+ li1 2
+ met1 2
+ met2 0
+ met3 0
+ met4 0
+--------------------
+ 4
+
+
+start 25th optimization iteration ...
+ completing 10% with 0 violations
+ elapsed time = 00:00:00, memory = 15.86 (MB)
+ number of violations = 0
+cpu time = 00:00:00, elapsed time = 00:00:00, memory = 15.86 (MB), peak = 372.93 (MB)
+total wire length = 35 um
+total wire length on LAYER li1 = 0 um
+total wire length on LAYER met1 = 21 um
+total wire length on LAYER met2 = 14 um
+total wire length on LAYER met3 = 0 um
+total wire length on LAYER met4 = 0 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 4
+up-via summary (total 4):
+
+--------------------
+ FR_MASTERSLICE 0
+ li1 2
+ met1 2
+ met2 0
+ met3 0
+ met4 0
+--------------------
+ 4
+
+
+start 33rd optimization iteration ...
+ completing 10% with 0 violations
+ elapsed time = 00:00:00, memory = 15.86 (MB)
+ completing 20% with 0 violations
+ elapsed time = 00:00:00, memory = 15.86 (MB)
+ completing 30% with 0 violations
+ elapsed time = 00:00:00, memory = 15.86 (MB)
+ completing 40% with 0 violations
+ elapsed time = 00:00:00, memory = 15.86 (MB)
+ number of violations = 0
+cpu time = 00:00:00, elapsed time = 00:00:00, memory = 15.86 (MB), peak = 372.93 (MB)
+total wire length = 35 um
+total wire length on LAYER li1 = 0 um
+total wire length on LAYER met1 = 21 um
+total wire length on LAYER met2 = 14 um
+total wire length on LAYER met3 = 0 um
+total wire length on LAYER met4 = 0 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 4
+up-via summary (total 4):
+
+--------------------
+ FR_MASTERSLICE 0
+ li1 2
+ met1 2
+ met2 0
+ met3 0
+ met4 0
+--------------------
+ 4
+
+
+start 41st optimization iteration ...
+ completing 10% with 0 violations
+ elapsed time = 00:00:00, memory = 15.86 (MB)
+ completing 20% with 0 violations
+ elapsed time = 00:00:00, memory = 15.86 (MB)
+ completing 30% with 0 violations
+ elapsed time = 00:00:00, memory = 15.86 (MB)
+ completing 40% with 0 violations
+ elapsed time = 00:00:00, memory = 15.86 (MB)
+ number of violations = 0
+cpu time = 00:00:00, elapsed time = 00:00:00, memory = 15.86 (MB), peak = 372.93 (MB)
+total wire length = 35 um
+total wire length on LAYER li1 = 0 um
+total wire length on LAYER met1 = 21 um
+total wire length on LAYER met2 = 14 um
+total wire length on LAYER met3 = 0 um
+total wire length on LAYER met4 = 0 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 4
+up-via summary (total 4):
+
+--------------------
+ FR_MASTERSLICE 0
+ li1 2
+ met1 2
+ met2 0
+ met3 0
+ met4 0
+--------------------
+ 4
+
+
+start 49th optimization iteration ...
+ completing 10% with 0 violations
+ elapsed time = 00:00:00, memory = 15.86 (MB)
+ number of violations = 0
+cpu time = 00:00:00, elapsed time = 00:00:00, memory = 15.86 (MB), peak = 372.93 (MB)
+total wire length = 35 um
+total wire length on LAYER li1 = 0 um
+total wire length on LAYER met1 = 21 um
+total wire length on LAYER met2 = 14 um
+total wire length on LAYER met3 = 0 um
+total wire length on LAYER met4 = 0 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 4
+up-via summary (total 4):
+
+--------------------
+ FR_MASTERSLICE 0
+ li1 2
+ met1 2
+ met2 0
+ met3 0
+ met4 0
+--------------------
+ 4
+
+
+start 57th optimization iteration ...
+ completing 10% with 0 violations
+ elapsed time = 00:00:00, memory = 15.79 (MB)
+ completing 20% with 0 violations
+ elapsed time = 00:00:00, memory = 16.03 (MB)
+ completing 30% with 0 violations
+ elapsed time = 00:00:00, memory = 16.03 (MB)
+ completing 40% with 0 violations
+ elapsed time = 00:00:00, memory = 16.03 (MB)
+ number of violations = 0
+cpu time = 00:00:00, elapsed time = 00:00:00, memory = 16.03 (MB), peak = 372.93 (MB)
+total wire length = 35 um
+total wire length on LAYER li1 = 0 um
+total wire length on LAYER met1 = 21 um
+total wire length on LAYER met2 = 14 um
+total wire length on LAYER met3 = 0 um
+total wire length on LAYER met4 = 0 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 4
+up-via summary (total 4):
+
+--------------------
+ FR_MASTERSLICE 0
+ li1 2
+ met1 2
+ met2 0
+ met3 0
+ met4 0
+--------------------
+ 4
+
+
+complete detail routing
+total wire length = 35 um
+total wire length on LAYER li1 = 0 um
+total wire length on LAYER met1 = 21 um
+total wire length on LAYER met2 = 14 um
+total wire length on LAYER met3 = 0 um
+total wire length on LAYER met4 = 0 um
+total wire length on LAYER met5 = 0 um
+total number of vias = 4
+up-via summary (total 4):
+
+--------------------
+ FR_MASTERSLICE 0
+ li1 2
+ met1 2
+ met2 0
+ met3 0
+ met4 0
+--------------------
+ 4
+
+cpu time = 00:00:00, elapsed time = 00:00:00, memory = 16.03 (MB), peak = 372.93 (MB)
+
+post processing ...
+
+Runtime taken (hrt): 1.09807
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/tritonRoute_runtime.txt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/tritonRoute_runtime.txt
new file mode 100644
index 0000000..309d017
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/routing/tritonRoute_runtime.txt
@@ -0,0 +1 @@
+0h0m1s103ms
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/synthesis/yosys.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/synthesis/yosys.log
new file mode 100644
index 0000000..26e7e02
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/synthesis/yosys.log
@@ -0,0 +1,596 @@
+
+ /----------------------------------------------------------------------------\
+ | |
+ | yosys -- Yosys Open SYnthesis Suite |
+ | |
+ | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
+ | |
+ | Permission to use, copy, modify, and/or distribute this software for any |
+ | purpose with or without fee is hereby granted, provided that the above |
+ | copyright notice and this permission notice appear in all copies. |
+ | |
+ | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
+ | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
+ | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
+ | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
+ | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
+ | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
+ | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
+ | |
+ \----------------------------------------------------------------------------/
+
+ Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
+
+[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
+
+1. Executing Liberty frontend.
+Imported 57 cell types from liberty file.
+
+2. Executing Liberty frontend.
+Imported 8 cell types from liberty file.
+
+3. Executing Verilog-2005 frontend: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/../../verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
+Parsing SystemVerilog input from `/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/../../verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v' to AST representation.
+Generating RTLIL representation for module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Successfully finished Verilog frontend.
+
+4. Generating Graphviz representation of design.
+Writing dot description to `/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/synthesis/hierarchy.dot'.
+Dumping module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped to page 1.
+
+5. Executing HIERARCHY pass (managing design hierarchy).
+
+5.1. Analyzing design hierarchy..
+Top module: \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+
+5.2. Analyzing design hierarchy..
+Top module: \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Removed 0 unused modules.
+
+6. Executing SYNTH pass.
+
+6.1. Executing HIERARCHY pass (managing design hierarchy).
+
+6.1.1. Analyzing design hierarchy..
+Top module: \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+
+6.1.2. Analyzing design hierarchy..
+Top module: \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Removed 0 unused modules.
+
+6.2. Executing PROC pass (convert processes to netlists).
+
+6.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Cleaned up 0 empty switches.
+
+6.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
+Removed a total of 0 dead cases.
+
+6.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
+Removed 0 redundant assignments.
+Promoted 0 assignments to connections.
+
+6.2.4. Executing PROC_INIT pass (extract init attributes).
+
+6.2.5. Executing PROC_ARST pass (detect async resets in processes).
+
+6.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
+
+6.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).
+
+6.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
+
+6.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Cleaned up 0 empty switches.
+
+6.3. Executing FLATTEN pass (flatten design).
+
+6.4. Executing OPT_EXPR pass (perform const folding).
+Optimizing module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+
+6.5. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+6.6. Executing CHECK pass (checking for obvious problems).
+checking module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+found and reported 0 problems.
+
+6.7. Executing OPT pass (performing simple optimizations).
+
+6.7.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+
+6.7.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Removed a total of 0 cells.
+
+6.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+ Creating internal representation of mux trees.
+ No muxes found in this module.
+Removed 0 multiplexer ports.
+
+6.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+Performed a total of 0 changes.
+
+6.7.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Removed a total of 0 cells.
+
+6.7.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+6.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+6.7.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+
+6.7.9. Finished OPT passes. (There is nothing left to do.)
+
+6.8. Executing FSM pass (extract and optimize FSM).
+
+6.8.1. Executing FSM_DETECT pass (finding FSMs in design).
+
+6.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
+
+6.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
+
+6.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+6.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
+
+6.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
+
+6.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
+
+6.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
+
+6.9. Executing OPT pass (performing simple optimizations).
+
+6.9.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+
+6.9.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Removed a total of 0 cells.
+
+6.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+ Creating internal representation of mux trees.
+ No muxes found in this module.
+Removed 0 multiplexer ports.
+
+6.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+Performed a total of 0 changes.
+
+6.9.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Removed a total of 0 cells.
+
+6.9.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+6.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+6.9.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+
+6.9.9. Finished OPT passes. (There is nothing left to do.)
+
+6.10. Executing WREDUCE pass (reducing word size of cells).
+
+6.11. Executing PEEPOPT pass (run peephole optimizers).
+
+6.12. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+6.13. Executing ALUMACC pass (create $alu and $macc cells).
+Extracting $alu and $macc cells in module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped:
+ created 0 $alu and 0 $macc cells.
+
+6.14. Executing SHARE pass (SAT-based resource sharing).
+
+6.15. Executing OPT pass (performing simple optimizations).
+
+6.15.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+
+6.15.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Removed a total of 0 cells.
+
+6.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+ Creating internal representation of mux trees.
+ No muxes found in this module.
+Removed 0 multiplexer ports.
+
+6.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+Performed a total of 0 changes.
+
+6.15.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Removed a total of 0 cells.
+
+6.15.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+6.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+6.15.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+
+6.15.9. Finished OPT passes. (There is nothing left to do.)
+
+6.16. Executing MEMORY pass.
+
+6.16.1. Executing OPT_MEM pass (optimize memories).
+Performed a total of 0 transformations.
+
+6.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
+
+6.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+6.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
+
+6.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+6.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).
+
+6.17. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+6.18. Executing OPT pass (performing simple optimizations).
+
+6.18.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+
+6.18.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Removed a total of 0 cells.
+
+6.18.3. Executing OPT_DFF pass (perform DFF optimizations).
+
+6.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+6.18.5. Finished fast OPT passes.
+
+6.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
+
+6.20. Executing OPT pass (performing simple optimizations).
+
+6.20.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+
+6.20.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Removed a total of 0 cells.
+
+6.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+ Creating internal representation of mux trees.
+ No muxes found in this module.
+Removed 0 multiplexer ports.
+
+6.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+Performed a total of 0 changes.
+
+6.20.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Removed a total of 0 cells.
+
+6.20.6. Executing OPT_SHARE pass.
+
+6.20.7. Executing OPT_DFF pass (perform DFF optimizations).
+
+6.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+6.20.9. Executing OPT_EXPR pass (perform const folding).
+Optimizing module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+
+6.20.10. Finished OPT passes. (There is nothing left to do.)
+
+6.21. Executing TECHMAP pass (map to technology primitives).
+
+6.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
+Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
+Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
+Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
+Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
+Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
+Generating RTLIL representation for module `\_90_simplemap_various'.
+Generating RTLIL representation for module `\_90_simplemap_registers'.
+Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
+Generating RTLIL representation for module `\_90_shift_shiftx'.
+Generating RTLIL representation for module `\_90_fa'.
+Generating RTLIL representation for module `\_90_lcu'.
+Generating RTLIL representation for module `\_90_alu'.
+Generating RTLIL representation for module `\_90_macc'.
+Generating RTLIL representation for module `\_90_alumacc'.
+Generating RTLIL representation for module `\$__div_mod_u'.
+Generating RTLIL representation for module `\$__div_mod_trunc'.
+Generating RTLIL representation for module `\_90_div'.
+Generating RTLIL representation for module `\_90_mod'.
+Generating RTLIL representation for module `\$__div_mod_floor'.
+Generating RTLIL representation for module `\_90_divfloor'.
+Generating RTLIL representation for module `\_90_modfloor'.
+Generating RTLIL representation for module `\_90_pow'.
+Generating RTLIL representation for module `\_90_pmux'.
+Generating RTLIL representation for module `\_90_lut'.
+Successfully finished Verilog frontend.
+
+6.21.2. Continuing TECHMAP pass.
+No more expansions possible.
+<suppressed ~67 debug messages>
+
+6.22. Executing OPT pass (performing simple optimizations).
+
+6.22.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+
+6.22.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Removed a total of 0 cells.
+
+6.22.3. Executing OPT_DFF pass (perform DFF optimizations).
+
+6.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+6.22.5. Finished fast OPT passes.
+
+6.23. Executing ABC pass (technology mapping using ABC).
+
+6.23.1. Extracting gate netlist of module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped' to `<abc-temp-dir>/input.blif'..
+Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
+Don't call ABC as there is nothing to map.
+Removing temp directory.
+
+6.24. Executing OPT pass (performing simple optimizations).
+
+6.24.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+
+6.24.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Removed a total of 0 cells.
+
+6.24.3. Executing OPT_DFF pass (perform DFF optimizations).
+
+6.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+6.24.5. Finished fast OPT passes.
+
+6.25. Executing HIERARCHY pass (managing design hierarchy).
+
+6.25.1. Analyzing design hierarchy..
+Top module: \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+
+6.25.2. Analyzing design hierarchy..
+Top module: \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Removed 0 unused modules.
+
+6.26. Printing statistics.
+
+=== sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ===
+
+ Number of wires: 2
+ Number of wire bits: 2
+ Number of public wires: 2
+ Number of public wire bits: 2
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 1
+ sky130_fd_sc_hvl__lsbufhv2lv_1 1
+
+6.27. Executing CHECK pass (checking for obvious problems).
+checking module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+found and reported 0 problems.
+
+7. Executing SHARE pass (SAT-based resource sharing).
+
+8. Executing OPT pass (performing simple optimizations).
+
+8.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+
+8.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Removed a total of 0 cells.
+
+8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+ Creating internal representation of mux trees.
+ No muxes found in this module.
+Removed 0 multiplexer ports.
+
+8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+ Optimizing cells in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+Performed a total of 0 changes.
+
+8.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Removed a total of 0 cells.
+
+8.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+8.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.
+
+8.9. Finished OPT passes. (There is nothing left to do.)
+
+9. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+10. Printing statistics.
+
+=== sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ===
+
+ Number of wires: 2
+ Number of wire bits: 2
+ Number of public wires: 2
+ Number of public wire bits: 2
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 1
+ sky130_fd_sc_hvl__lsbufhv2lv_1 1
+
+11. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
+ cell sky130_fd_sc_hvl__dfxtp_1 (noninv, pins=3, area=48.84) is a direct match for cell type $_DFF_P_.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
+ cell sky130_fd_sc_hvl__dfrtp_1 (noninv, pins=4, area=62.52) is a direct match for cell type $_DFF_PN0_.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
+ cell sky130_fd_sc_hvl__dfstp_1 (noninv, pins=4, area=60.56) is a direct match for cell type $_DFF_PN1_.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
+Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
+ final dff cell mappings:
+ unmapped dff cell: $_DFF_N_
+ \sky130_fd_sc_hvl__dfxtp_1 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
+ unmapped dff cell: $_DFF_NN0_
+ unmapped dff cell: $_DFF_NN1_
+ unmapped dff cell: $_DFF_NP0_
+ unmapped dff cell: $_DFF_NP1_
+ \sky130_fd_sc_hvl__dfrtp_1 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
+ \sky130_fd_sc_hvl__dfstp_1 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
+ unmapped dff cell: $_DFF_PP0_
+ unmapped dff cell: $_DFF_PP1_
+ unmapped dff cell: $_DFFSR_NNN_
+ unmapped dff cell: $_DFFSR_NNP_
+ unmapped dff cell: $_DFFSR_NPN_
+ unmapped dff cell: $_DFFSR_NPP_
+ unmapped dff cell: $_DFFSR_PNN_
+ unmapped dff cell: $_DFFSR_PNP_
+ unmapped dff cell: $_DFFSR_PPN_
+ unmapped dff cell: $_DFFSR_PPP_
+
+11.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
+Mapping DFF cells in module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped':
+
+12. Printing statistics.
+
+=== sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ===
+
+ Number of wires: 2
+ Number of wire bits: 2
+ Number of public wires: 2
+ Number of public wire bits: 2
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 1
+ sky130_fd_sc_hvl__lsbufhv2lv_1 1
+
+13. Executing ABC pass (technology mapping using ABC).
+
+13.1. Extracting gate netlist of module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped' to `/tmp/yosys-abc-CQv2Mf/input.blif'..
+Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
+Don't call ABC as there is nothing to map.
+Removing temp directory.
+
+14. Executing SETUNDEF pass (replace undef values with defined constants).
+
+15. Executing HILOMAP pass (mapping to constant drivers).
+
+16. Executing SPLITNETS pass (splitting up multi-bit signals).
+
+17. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+
+18. Executing INSBUF pass (insert buffer cells for connected wires).
+
+19. Executing CHECK pass (checking for obvious problems).
+checking module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+found and reported 0 problems.
+
+20. Printing statistics.
+
+=== sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ===
+
+ Number of wires: 2
+ Number of wire bits: 2
+ Number of public wires: 2
+ Number of public wire bits: 2
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 1
+ sky130_fd_sc_hvl__lsbufhv2lv_1 1
+
+ Area for cell type \sky130_fd_sc_hvl__lsbufhv2lv_1 is unknown!
+
+21. Executing Verilog backend.
+Dumping module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+
+Warnings: 6 unique messages, 54 total
+End of script. Logfile hash: f13c65bf9b, CPU: user 0.45s system 0.00s, MEM: 22.36 MB peak
+Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
+Time spent: 29% 4x read_liberty (0 sec), 27% 1x dfflibmap (0 sec), ...
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/synthesis/yosys_rewrite_verilog.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/synthesis/yosys_rewrite_verilog.log
new file mode 100644
index 0000000..dba9004
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/synthesis/yosys_rewrite_verilog.log
@@ -0,0 +1,40 @@
+
+ /----------------------------------------------------------------------------\
+ | |
+ | yosys -- Yosys Open SYnthesis Suite |
+ | |
+ | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
+ | |
+ | Permission to use, copy, modify, and/or distribute this software for any |
+ | purpose with or without fee is hereby granted, provided that the above |
+ | copyright notice and this permission notice appear in all copies. |
+ | |
+ | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
+ | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
+ | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
+ | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
+ | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
+ | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
+ | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
+ | |
+ \----------------------------------------------------------------------------/
+
+ Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
+
+[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
+[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
+
+1. Executing Verilog-2005 frontend: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.powered.v
+Parsing Verilog input from `/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.powered.v' to AST representation.
+Generating RTLIL representation for module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+Successfully finished Verilog frontend.
+
+2. Executing Verilog backend.
+Dumping module `\sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped'.
+
+End of script. Logfile hash: 204ccb7fea, CPU: user 0.02s system 0.00s, MEM: 7.59 MB peak
+Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
+Time spent: 77% 2x write_verilog (0 sec), 22% 2x read_verilog (0 sec)
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/synthesis/yosys_runtime.txt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/synthesis/yosys_runtime.txt
new file mode 100644
index 0000000..2f909da
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/synthesis/yosys_runtime.txt
@@ -0,0 +1 @@
+0h0m0s457ms
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/write_verilog.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/write_verilog.log
new file mode 100644
index 0000000..2428119
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/write_verilog.log
@@ -0,0 +1,17 @@
+OpenROAD 0.9.0 d03ebfc244
+This program is licensed under the BSD-3 license. See the LICENSE file for details.
+Components of this program may be licensed under more restrictive licenses which must be honored.
+Error: cannot open '/.openroad'.
+Notice 0: Reading LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0: Created 13 technology layers
+Notice 0: Created 25 technology vias
+Notice 0: Created 69 library cells
+Notice 0: Finished LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef
+Notice 0:
+Reading DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.powered.def
+Notice 0: Design: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+Notice 0: Created 4 pins.
+Notice 0: Created 22 components and 91 component-terminals.
+Notice 0: Created 2 special nets and 89 connections.
+Notice 0: Created 2 nets and 2 connections.
+Notice 0: Finished DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.powered.def
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/final_summary_report.csv b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/final_summary_report.csv
new file mode 100644
index 0000000..cc3ba6b
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped,sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped,sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped,0h0m8s,0.000625,1600.0,3200.0,11,372.93,1,0,0,0,0,0,0,10,0,3,35,4,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0.0,2.86,2.0,0.0,0.0,0.0,2,2,2,2,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,2,5,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hvl,0,3
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/floorplan/verilog2def.core_area.rpt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/floorplan/verilog2def.core_area.rpt
new file mode 100644
index 0000000..977778a
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/floorplan/verilog2def.core_area.rpt
@@ -0,0 +1 @@
+0.0 0.0 25.0 25.0
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/floorplan/verilog2def.die_area.rpt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/floorplan/verilog2def.die_area.rpt
new file mode 100644
index 0000000..8d19301
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/floorplan/verilog2def.die_area.rpt
@@ -0,0 +1 @@
+0 0 25 25
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/placement/openphysyn_allchecks.rpt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/placement/openphysyn_allchecks.rpt
new file mode 100644
index 0000000..804fb12
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/placement/openphysyn_allchecks.rpt
@@ -0,0 +1 @@
+No paths found.
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/placement/openphysyn_tns.rpt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/placement/openphysyn_tns.rpt
new file mode 100644
index 0000000..53df237
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/placement/openphysyn_tns.rpt
@@ -0,0 +1 @@
+tns 0.00
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/placement/openphysyn_violators.rpt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/placement/openphysyn_violators.rpt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/placement/openphysyn_violators.rpt
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/placement/openphysyn_wns.rpt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/placement/openphysyn_wns.rpt
new file mode 100644
index 0000000..3196164
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/placement/openphysyn_wns.rpt
@@ -0,0 +1 @@
+wns 0.00
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/routing/antenna.rpt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/routing/antenna.rpt
new file mode 100644
index 0000000..750c330
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/routing/antenna.rpt
@@ -0,0 +1,36 @@
+Warning - class CORE ANTENNACELL is not found. This msg can be ignored if not in the antenna-avoid flow
+
+Net - A
+ lvlshiftdown (sky130_fd_sc_hvl__lsbufhv2lv_1) A
+[1] met2:
+ PAR: 2.86 Ratio: 0.00 (Area)
+ PAR: 14.99 Ratio: 400.00 (S.Area)
+ CAR: 7.58 Ratio: 0.00 (C.Area)
+ CAR: 38.70 Ratio: 0.00 (C.S.Area)
+
+[1] met1:
+ PAR: 4.69 Ratio: 0.00 (Area)
+ PAR: 23.67 Ratio: 400.00 (S.Area)
+ CAR: 4.72 Ratio: 0.00 (C.Area)
+ CAR: 23.71 Ratio: 0.00 (C.S.Area)
+
+[1] li1:
+ PAR: 0.03 Ratio: 0.00 (Area)
+ PAR: 0.04 Ratio: 75.00 (S.Area)
+ CAR: 0.03 Ratio: 0.00 (C.Area)
+ CAR: 0.04 Ratio: 0.00 (C.S.Area)
+
+[1] M1M2_PR:
+ PAR: 0.05 Ratio: 6.00 (Area)
+ CAR: 0.12 Ratio: 0.00 (C.Area)
+
+[1] L1M1_PR_MR:
+ PAR: 0.07 Ratio: 3.00 (Area)
+ CAR: 0.07 Ratio: 0.00 (C.Area)
+
+
+Net - X
+ No sinks on this net
+Number of pins violated: 0
+Number of nets violated: 0
+Total number of unspecial nets: 2
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/routing/tritonRoute.drc b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/routing/tritonRoute.drc
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/routing/tritonRoute.drc
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/routing/tritonRoute.klayout.xml b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/routing/tritonRoute.klayout.xml
new file mode 100644
index 0000000..d7983e8
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/routing/tritonRoute.klayout.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/runtime.txt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/runtime.txt
new file mode 100644
index 0000000..6e3022a
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/runtime.txt
@@ -0,0 +1 @@
+Routing completed for sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/27-11_17-21 in 0h0m8s
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/synthesis/yosys_2.chk.rpt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/synthesis/yosys_2.chk.rpt
new file mode 100644
index 0000000..6c4159e
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/synthesis/yosys_2.chk.rpt
@@ -0,0 +1,4 @@
+
+19. Executing CHECK pass (checking for obvious problems).
+checking module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped..
+found and reported 0 problems.
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/synthesis/yosys_2.stat.rpt b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/synthesis/yosys_2.stat.rpt
new file mode 100644
index 0000000..3624ea0
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/synthesis/yosys_2.stat.rpt
@@ -0,0 +1,17 @@
+
+20. Printing statistics.
+
+=== sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ===
+
+ Number of wires: 2
+ Number of wire bits: 2
+ Number of public wires: 2
+ Number of public wire bits: 2
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 1
+ sky130_fd_sc_hvl__lsbufhv2lv_1 1
+
+ Area for cell type \sky130_fd_sc_hvl__lsbufhv2lv_1 is unknown!
+
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/synthesis/yosys_dff.stat b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/synthesis/yosys_dff.stat
new file mode 100644
index 0000000..48d06ef
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/synthesis/yosys_dff.stat
@@ -0,0 +1,15 @@
+
+12. Printing statistics.
+
+=== sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ===
+
+ Number of wires: 2
+ Number of wire bits: 2
+ Number of public wires: 2
+ Number of public wire bits: 2
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 1
+ sky130_fd_sc_hvl__lsbufhv2lv_1 1
+
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/synthesis/yosys_pre.stat b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/synthesis/yosys_pre.stat
new file mode 100644
index 0000000..4222761
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/reports/synthesis/yosys_pre.stat
@@ -0,0 +1,15 @@
+
+10. Printing statistics.
+
+=== sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ===
+
+ Number of wires: 2
+ Number of wire bits: 2
+ Number of public wires: 2
+ Number of public wire bits: 2
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 1
+ sky130_fd_sc_hvl__lsbufhv2lv_1 1
+
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/cts/merged_unpadded.lef b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/cts/merged_unpadded.lef
new file mode 120000
index 0000000..c48782e
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/cts/merged_unpadded.lef
@@ -0,0 +1 @@
+../../tmp/merged_unpadded.lef
\ No newline at end of file
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/floorplan/merged_unpadded.lef b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/floorplan/merged_unpadded.lef
new file mode 120000
index 0000000..c48782e
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/floorplan/merged_unpadded.lef
@@ -0,0 +1 @@
+../../tmp/merged_unpadded.lef
\ No newline at end of file
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/merged_unpadded.lef b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/merged_unpadded.lef
new file mode 120000
index 0000000..c48782e
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/merged_unpadded.lef
@@ -0,0 +1 @@
+../../tmp/merged_unpadded.lef
\ No newline at end of file
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.json b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.json
new file mode 100644
index 0000000..0797e3d
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.json
@@ -0,0 +1,87 @@
+[
+ {
+ "pins": [
+ [
+ "A",
+ "LVPWR",
+ "VGND",
+ "VNB",
+ "VPB",
+ "VPWR",
+ "X"
+ ], [
+ "A",
+ "LVPWR",
+ "VGND",
+ "VNB",
+ "VPB",
+ "VPWR",
+ "X"
+ ]
+ ]
+ },
+ {
+ "name": [
+ "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped",
+ "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
+ ],
+ "devices": [
+ [
+ ["sky130_fd_sc_hvl__lsbufhv2lv_1", 1 ]
+ ], [
+ ["sky130_fd_sc_hvl__lsbufhv2lv_1", 1 ]
+ ]
+ ],
+ "nets": [
+ 6,
+ 4
+ ],
+ "badnets": [
+ [
+ [
+ [
+ "FILLER_1_8/VPB",
+ [
+ [ "sky130_fd_sc_hvl__lsbufhv2lv_1", "VPB", 1 ]
+ ]
+ ],
+ [
+ "lvlshiftdown/LVPWR",
+ [
+ [ "sky130_fd_sc_hvl__lsbufhv2lv_1", "LVPWR", 1 ]
+ ]
+ ],
+ [
+ "lvlshiftdown/VPWR",
+ [
+ [ "sky130_fd_sc_hvl__lsbufhv2lv_1", "VPWR", 1 ]
+ ]
+ ]
+ ], [
+ [
+ "VPWR",
+ [
+ [ "sky130_fd_sc_hvl__lsbufhv2lv_1", "LVPWR", 1 ],
+ [ "sky130_fd_sc_hvl__lsbufhv2lv_1", "VPB", 1 ],
+ [ "sky130_fd_sc_hvl__lsbufhv2lv_1", "VPWR", 1 ]
+ ]
+ ],
+ [
+ "(no matching net)",
+ [
+ [ "", "", 0 ]
+ ]
+ ],
+ [
+ "(no matching net)",
+ [
+ [ "", "", 0 ]
+ ]
+ ]
+ ]
+ ]
+ ],
+ "badelements": [
+ ]
+ }
+]
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.log
new file mode 100644
index 0000000..ce04967
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.log
@@ -0,0 +1,48 @@
+
+Cell sky130_fd_sc_hvl__lsbufhv2lv_1 disconnected node: A
+Cell sky130_fd_sc_hvl__lsbufhv2lv_1 disconnected node: LVPWR
+Cell sky130_fd_sc_hvl__lsbufhv2lv_1 disconnected node: VGND
+Cell sky130_fd_sc_hvl__lsbufhv2lv_1 disconnected node: VNB
+Cell sky130_fd_sc_hvl__lsbufhv2lv_1 disconnected node: VPB
+Cell sky130_fd_sc_hvl__lsbufhv2lv_1 disconnected node: VPWR
+Cell sky130_fd_sc_hvl__lsbufhv2lv_1 disconnected node: X
+Warning: Equate pins: cell sky130_fd_sc_hvl__lsbufhv2lv_1 has no definition, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hvl__lsbufhv2lv_1 |Circuit 2: sky130_fd_sc_hvl__lsbufhv2lv_1
+-------------------------------------------|-------------------------------------------
+A |A
+LVPWR |LVPWR
+VGND |VGND
+VNB |VNB
+VPB |VPB
+VPWR |VPWR
+X |X
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hvl__lsbufhv2lv_1 and sky130_fd_sc_hvl__lsbufhv2lv_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hvl__lsbufhv2lv_1_ |Circuit 2: sky130_fd_sc_hvl__lsbufhv2lv_1_
+-------------------------------------------|-------------------------------------------
+sky130_fd_sc_hvl__lsbufhv2lv_1 (1) |sky130_fd_sc_hvl__lsbufhv2lv_1 (1)
+Number of devices: 1 |Number of devices: 1
+Number of nets: 6 **Mismatch** |Number of nets: 4 **Mismatch**
+---------------------------------------------------------------------------------------
+NET mismatches: Class fragments follow (with fanout counts):
+Circuit 1: sky130_fd_sc_hvl__lsbufhv2lv_1_ |Circuit 2: sky130_fd_sc_hvl__lsbufhv2lv_1_
+
+---------------------------------------------------------------------------------------
+Net: FILLER_1_8/VPB |Net: VPWR
+ sky130_fd_sc_hvl__lsbufhv2lv_1/VPB = 1 | sky130_fd_sc_hvl__lsbufhv2lv_1/LVPWR = 1
+ | sky130_fd_sc_hvl__lsbufhv2lv_1/VPB = 1
+ | sky130_fd_sc_hvl__lsbufhv2lv_1/VPWR = 1
+ |
+Net: lvlshiftdown/LVPWR |(no matching net)
+ sky130_fd_sc_hvl__lsbufhv2lv_1/LVPWR = 1 |
+ |
+Net: lvlshiftdown/VPWR |(no matching net)
+ sky130_fd_sc_hvl__lsbufhv2lv_1/VPWR = 1 |
+---------------------------------------------------------------------------------------
+Netlists do not match.
+Netlists do not match.
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.powered.v b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.powered.v
new file mode 100644
index 0000000..856b665
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs.powered.v
@@ -0,0 +1,143 @@
+/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
+
+module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped(A, X, VPWR, VGND);
+ input A;
+ input VGND;
+ input VPWR;
+ output X;
+ sky130_fd_sc_hvl__decap_8 FILLER_0_0 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_0_16 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_0_24 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_0_32 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_0_40 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_4 FILLER_0_48 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_0_8 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_1_0 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__fill_2 FILLER_1_12 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_1_31 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_1_39 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_4 FILLER_1_47 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__fill_1 FILLER_1_51 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_4 FILLER_1_8 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_2_0 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_2_16 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_2_24 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_2_32 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_2_40 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_4 FILLER_2_48 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__decap_8 FILLER_2_8 (
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hvl__lsbufhv2lv_1 lvlshiftdown (
+ .A(A),
+ .LVPWR(VPWR),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR),
+ .X(X)
+ );
+endmodule
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs_parsed.log b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs_parsed.log
new file mode 100644
index 0000000..e836368
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lvs_parsed.log
@@ -0,0 +1,9 @@
+LVS reports:
+ net count difference = 2
+ device count difference = 0
+ unmatched nets = 1
+ unmatched devices = 0
+ unmatched pins = 0
+ property failures = 0
+
+Total errors = 3
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/.magicrc b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/.magicrc
new file mode 100644
index 0000000..05a1f94
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/.magicrc
@@ -0,0 +1,75 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "/home/xrex/usr/devel/pdks/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/current/sky130A.tech
+
+# load device generator
+source $PDKPATH/libs.tech/magic/current/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/current/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/merged_unpadded.lef b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/merged_unpadded.lef
new file mode 120000
index 0000000..c48782e
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/merged_unpadded.lef
@@ -0,0 +1 @@
+../../tmp/merged_unpadded.lef
\ No newline at end of file
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__decap_4.ext b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__decap_4.ext
new file mode 100644
index 0000000..1298e11
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__decap_4.ext
@@ -0,0 +1,28 @@
+timestamp 1606262283
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+abstract
+port "VNB" 2 0 -23 384 23 m1
+port "VGND" 1 0 51 384 125 m1
+port "VPWR" 4 0 689 384 763 m1
+port "VPB" 3 0 791 384 837 m1
+node "li_353_n17#" 0 0 353 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_257_n17#" 0 0 257 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_161_n17#" 0 0 161 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_65_n17#" 0 0 65 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VNB" 0 0 0 -23 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_0_n17#" 0 0 0 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 0 0 0 51 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_34_73#" 0 0 34 73 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 0 0 0 689 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_50_537#" 0 0 50 537 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_353_797#" 0 0 353 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_257_797#" 0 0 257 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_161_797#" 0 0 161 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_65_797#" 0 0 65 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPB" 0 0 0 791 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_0_797#" 0 0 0 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__decap_8.ext b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__decap_8.ext
new file mode 100644
index 0000000..7c65432
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__decap_8.ext
@@ -0,0 +1,36 @@
+timestamp 1606262283
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+abstract
+port "VNB" 2 0 -23 768 23 m1
+port "VGND" 1 0 51 768 125 m1
+port "VPWR" 4 0 689 768 763 m1
+port "VPB" 3 0 791 768 837 m1
+node "li_737_n17#" 0 0 737 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_641_n17#" 0 0 641 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_545_n17#" 0 0 545 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_449_n17#" 0 0 449 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_353_n17#" 0 0 353 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_257_n17#" 0 0 257 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_161_n17#" 0 0 161 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_65_n17#" 0 0 65 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VNB" 0 0 0 -23 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_0_n17#" 0 0 0 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 0 0 0 51 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_115_72#" 0 0 115 72 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPWR" 0 0 0 689 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_100_536#" 0 0 100 536 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_737_797#" 0 0 737 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_641_797#" 0 0 641 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_545_797#" 0 0 545 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_449_797#" 0 0 449 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_353_797#" 0 0 353 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_257_797#" 0 0 257 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_161_797#" 0 0 161 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_65_797#" 0 0 65 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VPB" 0 0 0 791 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_0_797#" 0 0 0 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__fill_1.ext b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__fill_1.ext
new file mode 100644
index 0000000..1c343ac
--- /dev/null
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+<< via2 >>
+rect 1584 4994 1640 4996
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+rect 1824 4994 1880 4996
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+<< metal3 >>
+rect 1572 5000 1892 5001
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+<< via3 >>
+rect 1580 4996 1644 5000
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+<< metal4 >>
+rect 739 4317 1059 5019
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+<< via4 >>
+rect 781 4081 1017 4317
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+rect 1614 3248 1850 3484
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+<< metal5 >>
+rect 66 4317 5058 4359
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+rect 4350 748 5058 984
+rect 66 706 5058 748
+use sky130_fd_sc_hvl__decap_8 FILLER_0_16
+timestamp 1606497727
+transform 1 0 1602 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_8
+timestamp 1606497727
+transform 1 0 834 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_0
+timestamp 1606497727
+transform 1 0 66 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_32
+timestamp 1606497727
+transform 1 0 3138 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_24
+timestamp 1606497727
+transform 1 0 2370 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_4 FILLER_0_48
+timestamp 1606497727
+transform 1 0 4674 0 -1 898
+box -66 -23 450 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_40
+timestamp 1606497727
+transform 1 0 3906 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_16
+timestamp 1606497727
+transform 1 0 1602 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_8
+timestamp 1606497727
+transform 1 0 834 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_0
+timestamp 1606497727
+transform 1 0 66 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__fill_2 FILLER_1_12
+timestamp 1606497727
+transform 1 0 1218 0 1 1712
+box -66 -23 258 897
+use sky130_fd_sc_hvl__decap_4 FILLER_1_8
+timestamp 1606497727
+transform 1 0 834 0 1 1712
+box -66 -23 450 897
+use sky130_fd_sc_hvl__decap_8 FILLER_1_0
+timestamp 1606497727
+transform 1 0 66 0 1 1712
+box -66 -23 834 897
+use sky130_fd_sc_hvl__lsbufhv2lv_1 lvlshiftdown
+timestamp 1606497727
+transform 1 0 1410 0 1 1712
+box -66 -23 1698 1651
+use sky130_fd_sc_hvl__decap_8 FILLER_2_32
+timestamp 1606497727
+transform 1 0 3138 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_24
+timestamp 1606497727
+transform 1 0 2370 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_1_31
+timestamp 1606497727
+transform 1 0 3042 0 1 1712
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_4 FILLER_2_48
+timestamp 1606497727
+transform 1 0 4674 0 -1 4154
+box -66 -23 450 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_40
+timestamp 1606497727
+transform 1 0 3906 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__fill_1 FILLER_1_51
+timestamp 1606497727
+transform 1 0 4962 0 1 1712
+box -66 -23 162 897
+use sky130_fd_sc_hvl__decap_4 FILLER_1_47
+timestamp 1606497727
+transform 1 0 4578 0 1 1712
+box -66 -23 450 897
+use sky130_fd_sc_hvl__decap_8 FILLER_1_39
+timestamp 1606497727
+transform 1 0 3810 0 1 1712
+box -66 -23 834 897
+<< labels >>
+rlabel metal2 s 4310 4284 4366 5084 4 A
+port 1 nsew
+rlabel metal2 s 662 84 718 884 4 X
+port 2 nsew
+rlabel metal1 s 66 3289 5058 3391 4 VPWR
+port 3 nsew
+rlabel metal1 s 66 4917 5058 5019 4 VGND
+port 4 nsew
+<< properties >>
+string FIXED_BBOX 0 1 5124 5084
+<< end >>
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.ext b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.ext
new file mode 100644
index 0000000..3257241
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.ext
@@ -0,0 +1,195 @@
+timestamp 1606497726
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_sc_hvl__lsbufhv2lv_1 lvlshiftdown 1 0 1344 0 1 1628
+use sky130_fd_sc_hvl__decap_8 FILLER_0_0 1 0 0 0 -1 814
+use sky130_fd_sc_hvl__decap_8 FILLER_0_8 1 0 768 0 -1 814
+use sky130_fd_sc_hvl__decap_8 FILLER_0_16 1 0 1536 0 -1 814
+use sky130_fd_sc_hvl__decap_8 FILLER_1_0 1 0 0 0 1 1628
+use sky130_fd_sc_hvl__decap_4 FILLER_1_8 1 0 768 0 1 1628
+use sky130_fd_sc_hvl__fill_2 FILLER_1_12 1 0 1152 0 1 1628
+use sky130_fd_sc_hvl__decap_8 FILLER_0_24 1 0 2304 0 -1 814
+use sky130_fd_sc_hvl__decap_8 FILLER_0_32 1 0 3072 0 -1 814
+use sky130_fd_sc_hvl__decap_8 FILLER_1_31 1 0 2976 0 1 1628
+use sky130_fd_sc_hvl__decap_8 FILLER_0_40 1 0 3840 0 -1 814
+use sky130_fd_sc_hvl__decap_4 FILLER_0_48 1 0 4608 0 -1 814
+use sky130_fd_sc_hvl__decap_8 FILLER_1_39 1 0 3744 0 1 1628
+use sky130_fd_sc_hvl__decap_4 FILLER_1_47 1 0 4512 0 1 1628
+use sky130_fd_sc_hvl__fill_1 FILLER_1_51 1 0 4896 0 1 1628
+use sky130_fd_sc_hvl__decap_8 FILLER_2_0 1 0 0 0 -1 4070
+use sky130_fd_sc_hvl__decap_8 FILLER_2_8 1 0 768 0 -1 4070
+use sky130_fd_sc_hvl__decap_8 FILLER_2_16 1 0 1536 0 -1 4070
+use sky130_fd_sc_hvl__decap_8 FILLER_2_24 1 0 2304 0 -1 4070
+use sky130_fd_sc_hvl__decap_8 FILLER_2_32 1 0 3072 0 -1 4070
+use sky130_fd_sc_hvl__decap_8 FILLER_2_40 1 0 3840 0 -1 4070
+use sky130_fd_sc_hvl__decap_4 FILLER_2_48 1 0 4608 0 -1 4070
+port "VPWR" 2 0 3205 4992 3307 m1
+port "VGND" 3 0 4833 4992 4935 m1
+port "X" 1 596 0 652 800 m2
+port "A" 0 4244 4200 4300 5000 m2
+node "VPWR" 0 0 0 3205 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "VGND" 0 0 0 4833 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "X" 0 0 596 0 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "A" 0 0 4244 4200 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_24/li_353_797#" "lvlshiftdown/li_1313_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_16/li_161_797#" "lvlshiftdown/li_353_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_0_48/VGND" "FILLER_0_40/VGND" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_0_40/VGND" "FILLER_0_32/VGND"
+merge "FILLER_0_32/VGND" "FILLER_0_24/VGND"
+merge "FILLER_0_24/VGND" "FILLER_0_16/VGND"
+merge "FILLER_0_16/VGND" "FILLER_0_8/VGND"
+merge "FILLER_0_8/VGND" "FILLER_0_0/VGND"
+merge "FILLER_0_48/VNB" "FILLER_0_40/VNB" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_0_40/VNB" "FILLER_0_32/VNB"
+merge "FILLER_0_32/VNB" "FILLER_0_24/VNB"
+merge "FILLER_0_24/VNB" "FILLER_0_16/VNB"
+merge "FILLER_0_16/VNB" "FILLER_0_8/VNB"
+merge "FILLER_0_8/VNB" "FILLER_0_0/VNB"
+merge "FILLER_2_24/li_545_797#" "lvlshiftdown/li_1505_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_48/VSUBS" "FILLER_2_40/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_40/VSUBS" "FILLER_2_32/VSUBS"
+merge "FILLER_2_32/VSUBS" "FILLER_2_24/VSUBS"
+merge "FILLER_2_24/VSUBS" "FILLER_2_16/VSUBS"
+merge "FILLER_2_16/VSUBS" "FILLER_2_8/VSUBS"
+merge "FILLER_2_8/VSUBS" "FILLER_2_0/VSUBS"
+merge "FILLER_2_0/VSUBS" "FILLER_1_51/VSUBS"
+merge "FILLER_1_51/VSUBS" "FILLER_1_47/VSUBS"
+merge "FILLER_1_47/VSUBS" "FILLER_1_39/VSUBS"
+merge "FILLER_1_39/VSUBS" "FILLER_1_31/VSUBS"
+merge "FILLER_1_31/VSUBS" "FILLER_1_12/VSUBS"
+merge "FILLER_1_12/VSUBS" "FILLER_1_8/VSUBS"
+merge "FILLER_1_8/VSUBS" "FILLER_1_0/VSUBS"
+merge "FILLER_1_0/VSUBS" "lvlshiftdown/VSUBS"
+merge "lvlshiftdown/VSUBS" "FILLER_0_48/VSUBS"
+merge "FILLER_0_48/VSUBS" "FILLER_0_40/VSUBS"
+merge "FILLER_0_40/VSUBS" "FILLER_0_32/VSUBS"
+merge "FILLER_0_32/VSUBS" "FILLER_0_24/VSUBS"
+merge "FILLER_0_24/VSUBS" "FILLER_0_16/VSUBS"
+merge "FILLER_0_16/VSUBS" "FILLER_0_8/VSUBS"
+merge "FILLER_0_8/VSUBS" "FILLER_0_0/VSUBS"
+merge "FILLER_0_0/VSUBS" "VSUBS"
+merge "FILLER_2_48/VPWR" "FILLER_2_48/VPB" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_48/VPB" "FILLER_2_40/VPWR"
+merge "FILLER_2_40/VPWR" "FILLER_2_40/VPB"
+merge "FILLER_2_40/VPB" "FILLER_2_32/VPWR"
+merge "FILLER_2_32/VPWR" "FILLER_2_32/VPB"
+merge "FILLER_2_32/VPB" "FILLER_2_24/VPWR"
+merge "FILLER_2_24/VPWR" "FILLER_2_24/VPB"
+merge "FILLER_2_24/VPB" "FILLER_2_16/VPWR"
+merge "FILLER_2_16/VPWR" "FILLER_2_16/VPB"
+merge "FILLER_2_16/VPB" "FILLER_2_8/VPWR"
+merge "FILLER_2_8/VPWR" "FILLER_2_8/VPB"
+merge "FILLER_2_8/VPB" "FILLER_2_0/VPWR"
+merge "FILLER_2_0/VPWR" "FILLER_2_0/VPB"
+merge "FILLER_2_0/VPB" "lvlshiftdown/VGND"
+merge "lvlshiftdown/VGND" "lvlshiftdown/VNB"
+merge "lvlshiftdown/VNB" "FILLER_0_48/VPWR"
+merge "FILLER_0_48/VPWR" "FILLER_0_48/VPB"
+merge "FILLER_0_48/VPB" "FILLER_0_40/VPWR"
+merge "FILLER_0_40/VPWR" "FILLER_0_40/VPB"
+merge "FILLER_0_40/VPB" "FILLER_0_32/VPWR"
+merge "FILLER_0_32/VPWR" "FILLER_0_32/VPB"
+merge "FILLER_0_32/VPB" "FILLER_0_24/VPWR"
+merge "FILLER_0_24/VPWR" "FILLER_0_24/VPB"
+merge "FILLER_0_24/VPB" "FILLER_0_16/VPWR"
+merge "FILLER_0_16/VPWR" "FILLER_0_16/VPB"
+merge "FILLER_0_16/VPB" "FILLER_0_8/VPWR"
+merge "FILLER_0_8/VPWR" "FILLER_0_8/VPB"
+merge "FILLER_0_8/VPB" "FILLER_0_0/VPWR"
+merge "FILLER_0_0/VPWR" "FILLER_0_0/VPB"
+merge "FILLER_0_0/VPB" "VPWR"
+merge "FILLER_2_40/li_0_797#" "FILLER_2_32/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_51/VGND" "FILLER_1_51/VNB" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_51/VNB" "FILLER_1_47/VGND"
+merge "FILLER_1_47/VGND" "FILLER_1_47/VNB"
+merge "FILLER_1_47/VNB" "FILLER_1_39/VGND"
+merge "FILLER_1_39/VGND" "FILLER_1_39/VNB"
+merge "FILLER_1_39/VNB" "FILLER_1_31/VGND"
+merge "FILLER_1_31/VGND" "FILLER_1_31/VNB"
+merge "FILLER_1_31/VNB" "FILLER_1_12/VGND"
+merge "FILLER_1_12/VGND" "FILLER_1_12/VNB"
+merge "FILLER_1_12/VNB" "FILLER_1_8/VGND"
+merge "FILLER_1_8/VGND" "FILLER_1_8/VNB"
+merge "FILLER_1_8/VNB" "FILLER_1_0/VGND"
+merge "FILLER_1_0/VGND" "FILLER_1_0/VNB"
+merge "FILLER_1_0/VNB" "VGND"
+merge "FILLER_2_48/VNB" "FILLER_2_40/VNB" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_40/VNB" "FILLER_2_32/VNB"
+merge "FILLER_2_32/VNB" "FILLER_2_24/VNB"
+merge "FILLER_2_24/VNB" "FILLER_2_16/VNB"
+merge "FILLER_2_16/VNB" "FILLER_2_8/VNB"
+merge "FILLER_2_8/VNB" "FILLER_2_0/VNB"
+merge "FILLER_2_40/li_0_n17#" "FILLER_2_32/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_0_24/li_0_797#" "FILLER_0_16/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_51/VPB" "FILLER_1_47/VPB" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_47/VPB" "FILLER_1_39/VPB"
+merge "FILLER_1_39/VPB" "FILLER_1_31/VPB"
+merge "FILLER_1_31/VPB" "FILLER_1_12/VPB"
+merge "FILLER_1_12/VPB" "FILLER_1_8/VPB"
+merge "FILLER_1_8/VPB" "FILLER_1_0/VPB"
+merge "FILLER_1_0/VPB" "lvlshiftdown/VPB"
+merge "FILLER_1_51/VPWR" "FILLER_1_47/VPWR" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_47/VPWR" "FILLER_1_39/VPWR"
+merge "FILLER_1_39/VPWR" "FILLER_1_31/VPWR"
+merge "FILLER_0_24/li_0_n17#" "FILLER_0_16/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_12/li_0_797#" "FILLER_1_8/li_353_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_16/li_65_797#" "lvlshiftdown/li_257_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_8/li_0_797#" "FILLER_2_0/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_0_40/li_0_797#" "FILLER_0_32/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_32/li_0_797#" "FILLER_2_24/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_24/li_257_797#" "lvlshiftdown/li_1217_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_24/li_641_797#" "lvlshiftdown/li_1601_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_16/li_449_797#" "lvlshiftdown/li_641_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_12/li_0_n17#" "FILLER_1_8/li_353_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_8/li_0_n17#" "FILLER_2_0/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_47/li_0_797#" "FILLER_1_39/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_0_40/li_0_n17#" "FILLER_0_32/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_32/li_0_n17#" "FILLER_2_24/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_8/li_545_797#" "lvlshiftdown/li_0_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_31/li_0_797#" "lvlshiftdown/li_1601_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_47/li_0_n17#" "FILLER_1_39/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_0_48/li_0_797#" "FILLER_0_40/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_16/li_641_797#" "lvlshiftdown/li_833_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_8/li_0_797#" "FILLER_1_0/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_31/li_0_n17#" "FILLER_1_12/li_161_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_12/li_161_n17#" "lvlshiftdown/li_0_n17#"
+merge "FILLER_2_48/VGND" "FILLER_2_40/VGND" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_40/VGND" "FILLER_2_32/VGND"
+merge "FILLER_2_32/VGND" "FILLER_2_24/VGND"
+merge "FILLER_2_24/VGND" "FILLER_2_16/VGND"
+merge "FILLER_2_16/VGND" "FILLER_2_8/VGND"
+merge "FILLER_2_8/VGND" "FILLER_2_0/VGND"
+merge "FILLER_0_8/li_0_797#" "FILLER_0_0/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_0_48/li_0_n17#" "FILLER_0_40/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_8/li_0_n17#" "FILLER_1_0/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_39/li_0_797#" "FILLER_1_31/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_0_8/li_0_n17#" "FILLER_0_0/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_16/li_353_797#" "lvlshiftdown/li_545_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_39/li_0_n17#" "FILLER_1_31/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_48/li_0_797#" "FILLER_2_40/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_48/li_0_n17#" "FILLER_2_40/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_0_32/li_0_797#" "FILLER_0_24/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_8/li_641_797#" "lvlshiftdown/li_65_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_16/li_0_797#" "FILLER_2_8/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_8/li_737_797#" "lvlshiftdown/li_161_1611#"
+merge "FILLER_0_32/li_0_n17#" "FILLER_0_24/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_24/li_449_797#" "lvlshiftdown/li_1409_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_16/li_257_797#" "lvlshiftdown/li_449_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_16/li_0_n17#" "FILLER_2_8/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "lvlshiftdown/X" "X" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_12/VPWR" "FILLER_1_8/VPWR" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_8/VPWR" "FILLER_1_0/VPWR"
+merge "FILLER_2_24/li_161_797#" "lvlshiftdown/li_1121_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_16/li_545_797#" "lvlshiftdown/li_737_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_24/li_0_797#" "FILLER_2_16/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_16/li_737_797#" "lvlshiftdown/li_929_1611#"
+merge "FILLER_2_24/li_0_n17#" "FILLER_2_16/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_1_12/li_161_797#" "lvlshiftdown/li_0_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_2_24/li_65_797#" "lvlshiftdown/li_1025_1611#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_0_16/li_0_797#" "FILLER_0_8/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "FILLER_0_16/li_0_n17#" "FILLER_0_8/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "lvlshiftdown/A" "A" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.gds b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.gds
new file mode 100644
index 0000000..bd4cfac
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.gds
Binary files differ
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lef b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lef
new file mode 100644
index 0000000..c8f4ad2
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lef
@@ -0,0 +1,60 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+ CLASS BLOCK ;
+ FOREIGN sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ;
+ ORIGIN 0.000 -0.005 ;
+ SIZE 25.620 BY 25.415 ;
+ PIN A
+ DIRECTION INPUT ;
+ PORT
+ LAYER met2 ;
+ RECT 21.550 21.420 21.830 25.420 ;
+ END
+ END A
+ PIN X
+ DIRECTION OUTPUT TRISTATE ;
+ PORT
+ LAYER met2 ;
+ RECT 3.310 0.420 3.590 4.420 ;
+ END
+ END X
+ PIN VPWR
+ DIRECTION INPUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.330 16.445 25.290 16.955 ;
+ END
+ END VPWR
+ PIN VGND
+ DIRECTION INPUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.330 24.585 25.290 25.095 ;
+ END
+ END VGND
+ OBS
+ LAYER li1 ;
+ RECT 0.330 0.335 25.290 20.855 ;
+ LAYER met1 ;
+ RECT 0.330 17.235 25.290 20.885 ;
+ RECT 0.330 0.165 25.290 16.165 ;
+ LAYER met2 ;
+ RECT 3.320 21.140 21.270 25.095 ;
+ RECT 22.110 21.140 22.300 25.095 ;
+ RECT 3.320 4.700 22.300 21.140 ;
+ RECT 3.870 0.165 22.300 4.700 ;
+ LAYER met3 ;
+ RECT 3.695 0.255 21.960 25.005 ;
+ LAYER met4 ;
+ RECT 3.695 0.165 21.960 25.095 ;
+ LAYER met5 ;
+ RECT 0.330 3.530 25.290 21.795 ;
+ END
+END sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+END LIBRARY
+
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lef.mag b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lef.mag
new file mode 100644
index 0000000..7e88a6f
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.lef.mag
@@ -0,0 +1,44 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1606497726
+<< obsli1 >>
+rect 66 67 5058 4171
+<< metal1 >>
+rect 66 4917 5058 5019
+rect 66 3289 5058 3391
+<< obsm1 >>
+rect 66 3447 5058 4177
+rect 66 33 5058 3233
+<< metal2 >>
+rect 4310 4284 4366 5084
+rect 662 84 718 884
+<< obsm2 >>
+rect 664 4228 4254 5019
+rect 4422 4228 4460 5019
+rect 664 940 4460 4228
+rect 774 33 4460 940
+<< obsm3 >>
+rect 739 51 4392 5001
+<< obsm4 >>
+rect 739 33 4392 5019
+<< obsm5 >>
+rect 66 706 5058 4359
+<< labels >>
+rlabel metal2 s 4310 4284 4366 5084 6 A
+port 1 nsew default input
+rlabel metal2 s 662 84 718 884 6 X
+port 2 nsew default output
+rlabel metal1 s 66 3289 5058 3391 6 VPWR
+port 3 nsew power input
+rlabel metal1 s 66 4917 5058 5019 6 VGND
+port 4 nsew ground input
+<< properties >>
+string LEFclass BLOCK
+string FIXED_BBOX 0 1 5124 5084
+string LEFview TRUE
+string GDS_FILE /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.gds
+string GDS_END 50278
+string GDS_START 35870
+<< end >>
+
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag
new file mode 100644
index 0000000..4f27c19
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag
@@ -0,0 +1,940 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1606497726
+<< checkpaint >>
+rect -1260 -1259 6384 6344
+<< viali >>
+rect 1633 2694 1667 2728
+rect 2113 1880 2147 1914
+<< metal1 >>
+rect 66 4994 5058 5019
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+<< via4 >>
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+rect 4114 748 4350 984
+<< metal5 >>
+rect 66 4317 5058 4359
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+rect 4350 4081 5058 4317
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+rect 4350 748 5058 984
+rect 66 706 5058 748
+use sky130_fd_sc_hvl__decap_8 FILLER_1_39
+timestamp 1606497726
+transform 1 0 3810 0 1 1712
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_4 FILLER_1_47
+timestamp 1606497726
+transform 1 0 4578 0 1 1712
+box -66 -23 450 897
+use sky130_fd_sc_hvl__fill_1 FILLER_1_51
+timestamp 1606497726
+transform 1 0 4962 0 1 1712
+box -66 -23 162 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_40
+timestamp 1606497726
+transform 1 0 3906 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_4 FILLER_2_48
+timestamp 1606497726
+transform 1 0 4674 0 -1 4154
+box -66 -23 450 897
+use sky130_fd_sc_hvl__decap_8 FILLER_1_31
+timestamp 1606497726
+transform 1 0 3042 0 1 1712
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_24
+timestamp 1606497726
+transform 1 0 2370 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_32
+timestamp 1606497726
+transform 1 0 3138 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__lsbufhv2lv_1 lvlshiftdown
+timestamp 1606497726
+transform 1 0 1410 0 1 1712
+box -66 -23 1698 1651
+use sky130_fd_sc_hvl__decap_8 FILLER_1_0
+timestamp 1606497726
+transform 1 0 66 0 1 1712
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_4 FILLER_1_8
+timestamp 1606497726
+transform 1 0 834 0 1 1712
+box -66 -23 450 897
+use sky130_fd_sc_hvl__fill_2 FILLER_1_12
+timestamp 1606497726
+transform 1 0 1218 0 1 1712
+box -66 -23 258 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_0
+timestamp 1606497726
+transform 1 0 66 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_8
+timestamp 1606497726
+transform 1 0 834 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_2_16
+timestamp 1606497726
+transform 1 0 1602 0 -1 4154
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_40
+timestamp 1606497726
+transform 1 0 3906 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_4 FILLER_0_48
+timestamp 1606497726
+transform 1 0 4674 0 -1 898
+box -66 -23 450 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_24
+timestamp 1606497726
+transform 1 0 2370 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_32
+timestamp 1606497726
+transform 1 0 3138 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_0
+timestamp 1606497726
+transform 1 0 66 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_8
+timestamp 1606497726
+transform 1 0 834 0 -1 898
+box -66 -23 834 897
+use sky130_fd_sc_hvl__decap_8 FILLER_0_16
+timestamp 1606497726
+transform 1 0 1602 0 -1 898
+box -66 -23 834 897
+<< labels >>
+rlabel metal2 s 4310 4284 4366 5084 4 A
+port 1 nsew
+rlabel metal2 s 662 84 718 884 4 X
+port 2 nsew
+rlabel metal1 s 66 3289 5058 3391 4 VPWR
+port 3 nsew
+rlabel metal1 s 66 4917 5058 5019 4 VGND
+port 4 nsew
+<< properties >>
+string FIXED_BBOX 0 1 5124 5084
+string GDS_FILE /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.gds
+string GDS_END 50278
+string GDS_START 35870
+<< end >>
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.spice b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.spice
new file mode 100644
index 0000000..40c0d9f
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.spice
@@ -0,0 +1,47 @@
+* NGSPICE file created from sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.ext - technology: sky130A
+
+* Black-box entry subcircuit for sky130_fd_sc_hvl__decap_8 abstract view
+.subckt sky130_fd_sc_hvl__decap_8 VGND VNB VPB VPWR
+.ends
+
+* Black-box entry subcircuit for sky130_fd_sc_hvl__decap_4 abstract view
+.subckt sky130_fd_sc_hvl__decap_4 VGND VNB VPB VPWR
+.ends
+
+* Black-box entry subcircuit for sky130_fd_sc_hvl__fill_1 abstract view
+.subckt sky130_fd_sc_hvl__fill_1 VGND VNB VPB VPWR
+.ends
+
+* Black-box entry subcircuit for sky130_fd_sc_hvl__fill_2 abstract view
+.subckt sky130_fd_sc_hvl__fill_2 VGND VNB VPB VPWR
+.ends
+
+* Black-box entry subcircuit for sky130_fd_sc_hvl__lsbufhv2lv_1 abstract view
+.subckt sky130_fd_sc_hvl__lsbufhv2lv_1 A LVPWR VGND VNB VPB VPWR X
+.ends
+
+.subckt sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped A X VPWR VGND
+XFILLER_0_24 FILLER_0_0/VGND FILLER_0_0/VNB VPWR VPWR sky130_fd_sc_hvl__decap_8
+XFILLER_0_48 FILLER_0_0/VGND FILLER_0_0/VNB VPWR VPWR sky130_fd_sc_hvl__decap_4
+XFILLER_1_0 VGND VGND FILLER_1_8/VPB FILLER_1_0/VPWR sky130_fd_sc_hvl__decap_8
+XFILLER_0_16 FILLER_0_0/VGND FILLER_0_0/VNB VPWR VPWR sky130_fd_sc_hvl__decap_8
+XFILLER_1_51 VGND VGND FILLER_1_8/VPB FILLER_1_51/VPWR sky130_fd_sc_hvl__fill_1
+XFILLER_1_31 VGND VGND FILLER_1_8/VPB FILLER_1_51/VPWR sky130_fd_sc_hvl__decap_8
+XFILLER_1_8 VGND VGND FILLER_1_8/VPB FILLER_1_0/VPWR sky130_fd_sc_hvl__decap_4
+XFILLER_1_12 VGND VGND FILLER_1_8/VPB FILLER_1_0/VPWR sky130_fd_sc_hvl__fill_2
+XFILLER_1_47 VGND VGND FILLER_1_8/VPB FILLER_1_51/VPWR sky130_fd_sc_hvl__decap_4
+XFILLER_1_39 VGND VGND FILLER_1_8/VPB FILLER_1_51/VPWR sky130_fd_sc_hvl__decap_8
+XFILLER_2_40 FILLER_2_0/VGND FILLER_2_0/VNB VPWR VPWR sky130_fd_sc_hvl__decap_8
+XFILLER_2_0 FILLER_2_0/VGND FILLER_2_0/VNB VPWR VPWR sky130_fd_sc_hvl__decap_8
+XFILLER_2_32 FILLER_2_0/VGND FILLER_2_0/VNB VPWR VPWR sky130_fd_sc_hvl__decap_8
+XFILLER_0_0 FILLER_0_0/VGND FILLER_0_0/VNB VPWR VPWR sky130_fd_sc_hvl__decap_8
+XFILLER_2_24 FILLER_2_0/VGND FILLER_2_0/VNB VPWR VPWR sky130_fd_sc_hvl__decap_8
+XFILLER_2_48 FILLER_2_0/VGND FILLER_2_0/VNB VPWR VPWR sky130_fd_sc_hvl__decap_4
+XFILLER_2_16 FILLER_2_0/VGND FILLER_2_0/VNB VPWR VPWR sky130_fd_sc_hvl__decap_8
+XFILLER_2_8 FILLER_2_0/VGND FILLER_2_0/VNB VPWR VPWR sky130_fd_sc_hvl__decap_8
+XFILLER_0_8 FILLER_0_0/VGND FILLER_0_0/VNB VPWR VPWR sky130_fd_sc_hvl__decap_8
+Xlvlshiftdown A lvlshiftdown/LVPWR VPWR VPWR FILLER_1_8/VPB lvlshiftdown/VPWR X sky130_fd_sc_hvl__lsbufhv2lv_1
+XFILLER_0_40 FILLER_0_0/VGND FILLER_0_0/VNB VPWR VPWR sky130_fd_sc_hvl__decap_8
+XFILLER_0_32 FILLER_0_0/VGND FILLER_0_0/VNB VPWR VPWR sky130_fd_sc_hvl__decap_8
+.ends
+
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/placement/merged_unpadded.lef b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/placement/merged_unpadded.lef
new file mode 120000
index 0000000..c48782e
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/placement/merged_unpadded.lef
@@ -0,0 +1 @@
+../../tmp/merged_unpadded.lef
\ No newline at end of file
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/placement/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.placement.def b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/placement/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.placement.def
new file mode 100644
index 0000000..8a40183
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/placement/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.placement.def
@@ -0,0 +1,33 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 25000 25000 ) ;
+ROW ROW_0 unithvdbl 0 0 FS DO 52 BY 1 STEP 480 0 ;
+ROW ROW_1 unithvdbl 0 8140 N DO 52 BY 1 STEP 480 0 ;
+ROW ROW_2 unithvdbl 0 16280 FS DO 52 BY 1 STEP 480 0 ;
+TRACKS X 240 DO 52 STEP 480 LAYER li1 ;
+TRACKS Y 240 DO 52 STEP 480 LAYER li1 ;
+TRACKS X 185 DO 68 STEP 370 LAYER met1 ;
+TRACKS Y 185 DO 68 STEP 370 LAYER met1 ;
+TRACKS X 240 DO 52 STEP 480 LAYER met2 ;
+TRACKS Y 240 DO 52 STEP 480 LAYER met2 ;
+TRACKS X 370 DO 34 STEP 740 LAYER met3 ;
+TRACKS Y 370 DO 34 STEP 740 LAYER met3 ;
+TRACKS X 480 DO 26 STEP 960 LAYER met4 ;
+TRACKS Y 480 DO 26 STEP 960 LAYER met4 ;
+TRACKS X 1665 DO 8 STEP 3330 LAYER met5 ;
+TRACKS Y 1665 DO 8 STEP 3330 LAYER met5 ;
+COMPONENTS 1 ;
+ - lvlshiftdown sky130_fd_sc_hvl__lsbufhv2lv_1 + PLACED ( 6720 8140 ) N ;
+END COMPONENTS
+PINS 2 ;
+ - A + NET A + DIRECTION INPUT + USE SIGNAL + PLACED ( 21360 23000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
+ - X + NET X + DIRECTION OUTPUT + USE SIGNAL + PLACED ( 3120 2000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
+END PINS
+NETS 2 ;
+ - A ( PIN A ) ( lvlshiftdown A ) + USE SIGNAL ;
+ - X ( PIN X ) ( lvlshiftdown X ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/merged_unpadded.lef b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/merged_unpadded.lef
new file mode 120000
index 0000000..c48782e
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/merged_unpadded.lef
@@ -0,0 +1 @@
+../../tmp/merged_unpadded.lef
\ No newline at end of file
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def
new file mode 100644
index 0000000..3e54bd4
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def
@@ -0,0 +1,198 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ;
+UNITS DISTANCE MICRONS 1000 ;
+
+DIEAREA ( 0 0 ) ( 25000 25000 ) ;
+
+ROW ROW_0 unithvdbl 0 0 FS DO 52 BY 1 STEP 480 0
+ ;
+ROW ROW_1 unithvdbl 0 8140 N DO 52 BY 1 STEP 480 0
+ ;
+ROW ROW_2 unithvdbl 0 16280 FS DO 52 BY 1 STEP 480 0
+ ;
+TRACKS X 240 DO 52 STEP 480 LAYER li1 ;
+TRACKS Y 240 DO 52 STEP 480 LAYER li1 ;
+TRACKS X 185 DO 68 STEP 370 LAYER met1 ;
+TRACKS Y 185 DO 68 STEP 370 LAYER met1 ;
+TRACKS X 240 DO 52 STEP 480 LAYER met2 ;
+TRACKS Y 240 DO 52 STEP 480 LAYER met2 ;
+TRACKS X 370 DO 34 STEP 740 LAYER met3 ;
+TRACKS Y 370 DO 34 STEP 740 LAYER met3 ;
+TRACKS X 480 DO 26 STEP 960 LAYER met4 ;
+TRACKS Y 480 DO 26 STEP 960 LAYER met4 ;
+TRACKS X 1665 DO 8 STEP 3330 LAYER met5 ;
+TRACKS Y 1665 DO 8 STEP 3330 LAYER met5 ;
+
+VIAS 6 ;
+- via2_FR
++ RECT met2 ( -140 -185 ) ( 140 185 )
++ RECT via2 ( -100 -100 ) ( 100 100 )
++ RECT met3 ( -165 -165 ) ( 165 165 )
+
+ ;
+- via4_FR
++ RECT met4 ( -590 -590 ) ( 590 590 )
++ RECT via4 ( -400 -400 ) ( 400 400 )
++ RECT met5 ( -710 -710 ) ( 710 710 )
+
+ ;
+- via_1600x510
+
++ VIARULE M1M2_PR
+ + CUTSIZE 150 150
+ + LAYERS met1 via met2
+ + CUTSPACING 170 170
+ + ENCLOSURE 245 180 55 180
+ + ROWCOL 1 4
+ ;
+- via2_1600x510
+
++ VIARULE M2M3_PR
+ + CUTSIZE 200 200
+ + LAYERS met2 via2 met3
+ + CUTSPACING 200 200
+ + ENCLOSURE 40 155 100 65
+ + ROWCOL 1 4
+ ;
+- via3_1600x510
+
++ VIARULE M3M4_PR
+ + CUTSIZE 200 200
+ + LAYERS met3 via3 met4
+ + CUTSPACING 200 200
+ + ENCLOSURE 100 60 100 155
+ + ROWCOL 1 4
+ ;
+- via4_1600x1600
+
++ VIARULE M4M5_PR
+ + CUTSIZE 800 800
+ + LAYERS met4 via4 met5
+ + CUTSPACING 800 800
+ + ENCLOSURE 400 400 400 400
+ ;
+END VIAS
+
+COMPONENTS 22 ;
+- lvlshiftdown sky130_fd_sc_hvl__lsbufhv2lv_1 + PLACED ( 6720 8140 ) N ;
+- FILLER_0_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 0 0 ) FS ;
+- FILLER_0_8 sky130_fd_sc_hvl__decap_8 + PLACED ( 3840 0 ) FS ;
+- FILLER_0_16 sky130_fd_sc_hvl__decap_8 + PLACED ( 7680 0 ) FS ;
+- FILLER_0_24 sky130_fd_sc_hvl__decap_8 + PLACED ( 11520 0 ) FS ;
+- FILLER_0_32 sky130_fd_sc_hvl__decap_8 + PLACED ( 15360 0 ) FS ;
+- FILLER_0_40 sky130_fd_sc_hvl__decap_8 + PLACED ( 19200 0 ) FS ;
+- FILLER_0_48 sky130_fd_sc_hvl__decap_4 + PLACED ( 23040 0 ) FS ;
+- FILLER_1_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 0 8140 ) N ;
+- FILLER_1_8 sky130_fd_sc_hvl__decap_4 + PLACED ( 3840 8140 ) N ;
+- FILLER_1_12 sky130_fd_sc_hvl__fill_2 + PLACED ( 5760 8140 ) N ;
+- FILLER_1_31 sky130_fd_sc_hvl__decap_8 + PLACED ( 14880 8140 ) N ;
+- FILLER_1_39 sky130_fd_sc_hvl__decap_8 + PLACED ( 18720 8140 ) N ;
+- FILLER_1_47 sky130_fd_sc_hvl__decap_4 + PLACED ( 22560 8140 ) N ;
+- FILLER_1_51 sky130_fd_sc_hvl__fill_1 + PLACED ( 24480 8140 ) N ;
+- FILLER_2_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 0 16280 ) FS ;
+- FILLER_2_8 sky130_fd_sc_hvl__decap_8 + PLACED ( 3840 16280 ) FS ;
+- FILLER_2_16 sky130_fd_sc_hvl__decap_8 + PLACED ( 7680 16280 ) FS ;
+- FILLER_2_24 sky130_fd_sc_hvl__decap_8 + PLACED ( 11520 16280 ) FS ;
+- FILLER_2_32 sky130_fd_sc_hvl__decap_8 + PLACED ( 15360 16280 ) FS ;
+- FILLER_2_40 sky130_fd_sc_hvl__decap_8 + PLACED ( 19200 16280 ) FS ;
+- FILLER_2_48 sky130_fd_sc_hvl__decap_4 + PLACED ( 23040 16280 ) FS ;
+END COMPONENTS
+
+PINS 4 ;
+- A + NET A + DIRECTION INPUT + USE SIGNAL
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 21360 23000 ) N ;
+- X + NET X + DIRECTION OUTPUT + USE SIGNAL
+ + LAYER met2 ( -140 -2000 ) ( 140 2000 )
+ + PLACED ( 3120 2000 ) N ;
+- VPWR + NET VPWR + DIRECTION INPUT + USE SIGNAL
+ + LAYER met1 ( -12480 -255 ) ( 12480 255 )
+ + FIXED ( 12480 16280 ) N + SPECIAL ;
+- VGND + NET VGND + DIRECTION INPUT + USE SIGNAL
+ + LAYER met1 ( -12480 -255 ) ( 12480 255 )
+ + FIXED ( 12480 24420 ) N + SPECIAL ;
+END PINS
+
+SPECIALNETS 2 ;
+- VPWR ( PIN VPWR ) ( * VPWR ) ( * VPB ) ( * LVPWR )
+ + ROUTED met4 0 + SHAPE STRIPE ( 20833 20578 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 12500 20578 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 4167 20578 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 20833 12245 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 12500 12245 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 4167 12245 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 20833 3912 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 12500 3912 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 4167 3912 ) via4_1600x1600
+ NEW met3 0 + SHAPE STRIPE ( 20833 16280 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 20833 16280 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 20833 16280 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 12500 16280 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 12500 16280 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 12500 16280 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 4167 16280 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 4167 16280 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 4167 16280 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 20833 0 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 20833 0 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 20833 0 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 12500 0 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 12500 0 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 12500 0 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 4167 0 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 4167 0 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 4167 0 ) via_1600x510
+ NEW met5 1600 + SHAPE STRIPE ( 0 20578 ) ( 24960 20578 )
+ NEW met5 1600 + SHAPE STRIPE ( 0 12245 ) ( 24960 12245 )
+ NEW met5 1600 + SHAPE STRIPE ( 0 3912 ) ( 24960 3912 )
+ NEW met4 1600 + SHAPE STRIPE ( 20833 -255 ) ( 20833 24675 )
+ NEW met4 1600 + SHAPE STRIPE ( 12500 -255 ) ( 12500 24675 )
+ NEW met4 1600 + SHAPE STRIPE ( 4167 -255 ) ( 4167 24675 )
+ NEW met1 510 + SHAPE FOLLOWPIN ( 0 16280 ) ( 24960 16280 )
+ NEW met1 510 + SHAPE FOLLOWPIN ( 0 0 ) ( 24960 0 )
+ + USE POWER ;
+- VGND ( PIN VGND ) ( * VNB ) ( * VGND )
+ + ROUTED met4 0 + SHAPE STRIPE ( 16666 16411 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 8333 16411 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 16666 8078 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 8333 8078 ) via4_1600x1600
+ NEW met3 0 + SHAPE STRIPE ( 16666 24420 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 16666 24420 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 16666 24420 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 8333 24420 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 8333 24420 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 8333 24420 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 16666 8140 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 16666 8140 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 16666 8140 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 8333 8140 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 8333 8140 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 8333 8140 ) via_1600x510
+ NEW met5 1600 + SHAPE STRIPE ( 0 16411 ) ( 24960 16411 )
+ NEW met5 1600 + SHAPE STRIPE ( 0 8078 ) ( 24960 8078 )
+ NEW met4 1600 + SHAPE STRIPE ( 16666 -255 ) ( 16666 24675 )
+ NEW met4 1600 + SHAPE STRIPE ( 8333 -255 ) ( 8333 24675 )
+ NEW met1 510 + SHAPE FOLLOWPIN ( 0 24420 ) ( 24960 24420 )
+ NEW met1 510 + SHAPE FOLLOWPIN ( 0 8140 ) ( 24960 8140 )
+ + USE GROUND ;
+END SPECIALNETS
+
+NETS 2 ;
+- A ( PIN A ) ( lvlshiftdown A )
+ + ROUTED met1 ( 7920 13135 ) ( 21840 13135 )
+ NEW met2 ( 21840 13135 ) ( 21840 17390 )
+ NEW met2 ( 21360 17390 ) ( 21840 17390 )
+ NEW met2 ( 21360 17390 ) ( 21360 21090 0 )
+ NEW li1 ( 7920 13135 ) L1M1_PR_MR
+ NEW met1 ( 21840 13135 ) M1M2_PR
++ USE SIGNAL ;
+- X ( PIN X ) ( lvlshiftdown X )
+ + ROUTED met2 ( 3120 3330 0 ) ( 3120 9065 )
+ NEW met1 ( 3120 9065 ) ( 10320 9065 )
+ NEW met1 ( 3120 9065 ) M1M2_PR
+ NEW li1 ( 10320 9065 ) L1M1_PR_MR
++ USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def.ref b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def.ref
new file mode 100644
index 0000000..69be62d
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def.ref
@@ -0,0 +1,134 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 25000 25000 ) ;
+ROW ROW_0 unithvdbl 0 0 FS DO 52 BY 1 STEP 480 0 ;
+ROW ROW_1 unithvdbl 0 8140 N DO 52 BY 1 STEP 480 0 ;
+ROW ROW_2 unithvdbl 0 16280 FS DO 52 BY 1 STEP 480 0 ;
+TRACKS X 240 DO 52 STEP 480 LAYER li1 ;
+TRACKS Y 240 DO 52 STEP 480 LAYER li1 ;
+TRACKS X 185 DO 68 STEP 370 LAYER met1 ;
+TRACKS Y 185 DO 68 STEP 370 LAYER met1 ;
+TRACKS X 240 DO 52 STEP 480 LAYER met2 ;
+TRACKS Y 240 DO 52 STEP 480 LAYER met2 ;
+TRACKS X 370 DO 34 STEP 740 LAYER met3 ;
+TRACKS Y 370 DO 34 STEP 740 LAYER met3 ;
+TRACKS X 480 DO 26 STEP 960 LAYER met4 ;
+TRACKS Y 480 DO 26 STEP 960 LAYER met4 ;
+TRACKS X 1665 DO 8 STEP 3330 LAYER met5 ;
+TRACKS Y 1665 DO 8 STEP 3330 LAYER met5 ;
+
+VIAS 6 ;
+- via2_FR
+ + RECT met2 ( -140 -185 ) ( 140 185 )
+ + RECT via2 ( -100 -100 ) ( 100 100 )
+ + RECT met3 ( -165 -165 ) ( 165 165 )
+ ;
+- via4_FR
+ + RECT met4 ( -590 -590 ) ( 590 590 )
+ + RECT via4 ( -400 -400 ) ( 400 400 )
+ + RECT met5 ( -710 -710 ) ( 710 710 )
+ ;
+ - via_1600x510 + VIARULE M1M2_PR + CUTSIZE 150 150 + LAYERS met1 via met2 + CUTSPACING 170 170 + ENCLOSURE 245 180 55 180 + ROWCOL 1 4 ;
+ - via2_1600x510 + VIARULE M2M3_PR + CUTSIZE 200 200 + LAYERS met2 via2 met3 + CUTSPACING 200 200 + ENCLOSURE 40 155 100 65 + ROWCOL 1 4 ;
+ - via3_1600x510 + VIARULE M3M4_PR + CUTSIZE 200 200 + LAYERS met3 via3 met4 + CUTSPACING 200 200 + ENCLOSURE 100 60 100 155 + ROWCOL 1 4 ;
+ - via4_1600x1600 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 400 400 400 400 ;
+END VIAS
+COMPONENTS 22 ;
+ - lvlshiftdown sky130_fd_sc_hvl__lsbufhv2lv_1 + PLACED ( 6720 8140 ) N ;
+ - FILLER_0_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 0 0 ) FS ;
+ - FILLER_0_8 sky130_fd_sc_hvl__decap_8 + PLACED ( 3840 0 ) FS ;
+ - FILLER_0_16 sky130_fd_sc_hvl__decap_8 + PLACED ( 7680 0 ) FS ;
+ - FILLER_0_24 sky130_fd_sc_hvl__decap_8 + PLACED ( 11520 0 ) FS ;
+ - FILLER_0_32 sky130_fd_sc_hvl__decap_8 + PLACED ( 15360 0 ) FS ;
+ - FILLER_0_40 sky130_fd_sc_hvl__decap_8 + PLACED ( 19200 0 ) FS ;
+ - FILLER_0_48 sky130_fd_sc_hvl__decap_4 + PLACED ( 23040 0 ) FS ;
+ - FILLER_1_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 0 8140 ) N ;
+ - FILLER_1_8 sky130_fd_sc_hvl__decap_4 + PLACED ( 3840 8140 ) N ;
+ - FILLER_1_12 sky130_fd_sc_hvl__fill_2 + PLACED ( 5760 8140 ) N ;
+ - FILLER_1_31 sky130_fd_sc_hvl__decap_8 + PLACED ( 14880 8140 ) N ;
+ - FILLER_1_39 sky130_fd_sc_hvl__decap_8 + PLACED ( 18720 8140 ) N ;
+ - FILLER_1_47 sky130_fd_sc_hvl__decap_4 + PLACED ( 22560 8140 ) N ;
+ - FILLER_1_51 sky130_fd_sc_hvl__fill_1 + PLACED ( 24480 8140 ) N ;
+ - FILLER_2_0 sky130_fd_sc_hvl__decap_8 + PLACED ( 0 16280 ) FS ;
+ - FILLER_2_8 sky130_fd_sc_hvl__decap_8 + PLACED ( 3840 16280 ) FS ;
+ - FILLER_2_16 sky130_fd_sc_hvl__decap_8 + PLACED ( 7680 16280 ) FS ;
+ - FILLER_2_24 sky130_fd_sc_hvl__decap_8 + PLACED ( 11520 16280 ) FS ;
+ - FILLER_2_32 sky130_fd_sc_hvl__decap_8 + PLACED ( 15360 16280 ) FS ;
+ - FILLER_2_40 sky130_fd_sc_hvl__decap_8 + PLACED ( 19200 16280 ) FS ;
+ - FILLER_2_48 sky130_fd_sc_hvl__decap_4 + PLACED ( 23040 16280 ) FS ;
+END COMPONENTS
+PINS 4 ;
+ - A + NET A + DIRECTION INPUT + USE SIGNAL + PLACED ( 21360 23000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
+ - X + NET X + DIRECTION OUTPUT + USE SIGNAL + PLACED ( 3120 2000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
+ - VPWR + NET VPWR + SPECIAL + DIRECTION INPUT + USE SIGNAL + FIXED ( 12480 16280 ) N + LAYER met1 ( -12480 -255 ) ( 12480 255 ) ;
+ - VGND + NET VGND + SPECIAL + DIRECTION INPUT + USE SIGNAL + FIXED ( 12480 24420 ) N + LAYER met1 ( -12480 -255 ) ( 12480 255 ) ;
+END PINS
+SPECIALNETS 2 ;
+ - VPWR ( PIN VPWR ) ( * VPWR ) ( * VPB ) ( * LVPWR ) + USE POWER
+ + ROUTED met4 0 + SHAPE STRIPE ( 20833 20578 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 12500 20578 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 4167 20578 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 20833 12245 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 12500 12245 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 4167 12245 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 20833 3912 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 12500 3912 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 4167 3912 ) via4_1600x1600
+ NEW met3 0 + SHAPE STRIPE ( 20833 16280 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 20833 16280 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 20833 16280 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 12500 16280 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 12500 16280 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 12500 16280 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 4167 16280 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 4167 16280 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 4167 16280 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 20833 0 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 20833 0 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 20833 0 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 12500 0 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 12500 0 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 12500 0 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 4167 0 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 4167 0 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 4167 0 ) via_1600x510
+ NEW met5 1600 + SHAPE STRIPE ( 0 20578 ) ( 24960 20578 )
+ NEW met5 1600 + SHAPE STRIPE ( 0 12245 ) ( 24960 12245 )
+ NEW met5 1600 + SHAPE STRIPE ( 0 3912 ) ( 24960 3912 )
+ NEW met4 1600 + SHAPE STRIPE ( 20833 -255 ) ( 20833 24675 )
+ NEW met4 1600 + SHAPE STRIPE ( 12500 -255 ) ( 12500 24675 )
+ NEW met4 1600 + SHAPE STRIPE ( 4167 -255 ) ( 4167 24675 )
+ NEW met1 510 + SHAPE FOLLOWPIN ( 0 16280 ) ( 24960 16280 )
+ NEW met1 510 + SHAPE FOLLOWPIN ( 0 0 ) ( 24960 0 ) ;
+ - VGND ( PIN VGND ) ( * VNB ) ( * VGND ) + USE GROUND
+ + ROUTED met4 0 + SHAPE STRIPE ( 16666 16411 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 8333 16411 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 16666 8078 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 8333 8078 ) via4_1600x1600
+ NEW met3 0 + SHAPE STRIPE ( 16666 24420 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 16666 24420 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 16666 24420 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 8333 24420 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 8333 24420 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 8333 24420 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 16666 8140 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 16666 8140 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 16666 8140 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 8333 8140 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 8333 8140 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 8333 8140 ) via_1600x510
+ NEW met5 1600 + SHAPE STRIPE ( 0 16411 ) ( 24960 16411 )
+ NEW met5 1600 + SHAPE STRIPE ( 0 8078 ) ( 24960 8078 )
+ NEW met4 1600 + SHAPE STRIPE ( 16666 -255 ) ( 16666 24675 )
+ NEW met4 1600 + SHAPE STRIPE ( 8333 -255 ) ( 8333 24675 )
+ NEW met1 510 + SHAPE FOLLOWPIN ( 0 24420 ) ( 24960 24420 )
+ NEW met1 510 + SHAPE FOLLOWPIN ( 0 8140 ) ( 24960 8140 ) ;
+END SPECIALNETS
+NETS 2 ;
+ - A ( PIN A ) ( lvlshiftdown A ) + USE SIGNAL ;
+ - X ( PIN X ) ( lvlshiftdown X ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.spef b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.spef
new file mode 100644
index 0000000..b50a3ff
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.spef
@@ -0,0 +1,56 @@
+*SPEF "IEEE 1481-1998"
+*DESIGN "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
+*DATE "Fri Nov 27 17:22:05 2020"
+*VENDOR "AUC CSCE Department"
+*PROGRAM "SPEF Extractor"
+*VERSION "1.0"
+*DESIGN_FLOW "PIN_CAP NONE"
+*DIVIDER /
+*DELIMITER :
+*BUS_DELIMITER []
+*T_UNIT 1.00000 NS
+*C_UNIT 1.00000 PF
+*R_UNIT 1.00000 OHM
+*L_UNIT 1.00000 HENRY
+
+
+*NAME_MAP
+*0 A
+*1 X
+
+*D_NET *0 0.0018797000379900002
+*CONN
+*P A I
+*I lvlshiftdown:A I
+*CAP
+0 lvlshiftdown:A 0.00059549049296
+1 *0:1 0.00059549049296
+2 *0:2 0.00017099706905500002
+3 *0:3 0.000194976910335
+4 *0:4 0.00017336245698000002
+5 *0:5 0.00014938261570000003
+*RES
+0 lvlshiftdown:A *0:1 12.428571428571427
+1 *0:2 *0:3 3.7991071428571423
+2 *0:4 *0:3 0.4285714285714285
+3 *0:4 *0:5 3.3035714285714284
+4 lvlshiftdown:A lvlshiftdown:A 0
+5 *0:1 *0:2 0
+*END
+
+*D_NET *1 0.0010787794098700001
+*CONN
+*P X O
+*I lvlshiftdown:X O
+*CAP
+6 *1:1 0.00022863561133500002
+7 *1:2 0.00022863561133500002
+8 *1:3 0.0003107540936
+9 lvlshiftdown:X 0.0003107540936
+*RES
+6 *1:1 *1:2 5.120535714285714
+7 *1:3 lvlshiftdown:X 6.428571428571428
+8 *1:3 *1:2 0
+9 lvlshiftdown:X lvlshiftdown:X 0
+*END
+
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/synthesis/merged_unpadded.lef b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/synthesis/merged_unpadded.lef
new file mode 120000
index 0000000..c48782e
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/synthesis/merged_unpadded.lef
@@ -0,0 +1 @@
+../../tmp/merged_unpadded.lef
\ No newline at end of file
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/synthesis/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis.v b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/synthesis/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis.v
new file mode 100644
index 0000000..67f21a8
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/synthesis/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis.v
@@ -0,0 +1,10 @@
+/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
+
+module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped(X, A);
+ input A;
+ output X;
+ sky130_fd_sc_hvl__lsbufhv2lv_1 lvlshiftdown (
+ .A(A),
+ .X(X)
+ );
+endmodule
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/synthesis/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis_optimized.v b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/synthesis/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis_optimized.v
new file mode 100644
index 0000000..d55995d
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/synthesis/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis_optimized.v
@@ -0,0 +1,8 @@
+module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped (A,
+ X);
+ input A;
+ output X;
+
+ sky130_fd_sc_hvl__lsbufhv2lv_1 lvlshiftdown (.A(A),
+ .X(X));
+endmodule
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/synthesis/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis_preroute.v b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/synthesis/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis_preroute.v
new file mode 100644
index 0000000..338c650
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/synthesis/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.synthesis_preroute.v
@@ -0,0 +1,101 @@
+module sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped (A,
+ X,
+ VPWR,
+ VGND);
+ input A;
+ output X;
+ input VPWR;
+ input VGND;
+
+ sky130_fd_sc_hvl__lsbufhv2lv_1 lvlshiftdown (.A(A),
+ .X(X),
+ .LVPWR(VPWR),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_0_0 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_0_8 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_0_16 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_0_24 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_0_32 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_0_40 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_4 FILLER_0_48 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_1_0 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_4 FILLER_1_8 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__fill_2 FILLER_1_12 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_1_31 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_1_39 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_4 FILLER_1_47 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__fill_1 FILLER_1_51 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_2_0 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_2_8 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_2_16 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_2_24 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_2_32 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_8 FILLER_2_40 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+ sky130_fd_sc_hvl__decap_4 FILLER_2_48 (.VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR));
+endmodule
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/cts/merged_unpadded.lef b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/cts/merged_unpadded.lef
new file mode 120000
index 0000000..c48782e
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/cts/merged_unpadded.lef
@@ -0,0 +1 @@
+../../tmp/merged_unpadded.lef
\ No newline at end of file
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/ioPlacer.def b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/ioPlacer.def
new file mode 100644
index 0000000..dd479e8
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/ioPlacer.def
@@ -0,0 +1,33 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 25000 25000 ) ;
+ROW ROW_0 unithvdbl 0 0 FS DO 52 BY 1 STEP 480 0 ;
+ROW ROW_1 unithvdbl 0 8140 N DO 52 BY 1 STEP 480 0 ;
+ROW ROW_2 unithvdbl 0 16280 FS DO 52 BY 1 STEP 480 0 ;
+TRACKS X 240 DO 52 STEP 480 LAYER li1 ;
+TRACKS Y 240 DO 52 STEP 480 LAYER li1 ;
+TRACKS X 185 DO 68 STEP 370 LAYER met1 ;
+TRACKS Y 185 DO 68 STEP 370 LAYER met1 ;
+TRACKS X 240 DO 52 STEP 480 LAYER met2 ;
+TRACKS Y 240 DO 52 STEP 480 LAYER met2 ;
+TRACKS X 370 DO 34 STEP 740 LAYER met3 ;
+TRACKS Y 370 DO 34 STEP 740 LAYER met3 ;
+TRACKS X 480 DO 26 STEP 960 LAYER met4 ;
+TRACKS Y 480 DO 26 STEP 960 LAYER met4 ;
+TRACKS X 1665 DO 8 STEP 3330 LAYER met5 ;
+TRACKS Y 1665 DO 8 STEP 3330 LAYER met5 ;
+COMPONENTS 1 ;
+ - lvlshiftdown sky130_fd_sc_hvl__lsbufhv2lv_1 ;
+END COMPONENTS
+PINS 2 ;
+ - A + NET A + DIRECTION INPUT + USE SIGNAL + PLACED ( 21360 23000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
+ - X + NET X + DIRECTION OUTPUT + USE SIGNAL + PLACED ( 3120 2000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
+END PINS
+NETS 2 ;
+ - A ( PIN A ) ( lvlshiftdown A ) + USE SIGNAL ;
+ - X ( PIN X ) ( lvlshiftdown X ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/merged_unpadded.lef b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/merged_unpadded.lef
new file mode 120000
index 0000000..c48782e
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/merged_unpadded.lef
@@ -0,0 +1 @@
+../../tmp/merged_unpadded.lef
\ No newline at end of file
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/pdn.def b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/pdn.def
new file mode 100644
index 0000000..d5ff027
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/pdn.def
@@ -0,0 +1,114 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 25000 25000 ) ;
+ROW ROW_0 unithvdbl 0 0 FS DO 52 BY 1 STEP 480 0 ;
+ROW ROW_1 unithvdbl 0 8140 N DO 52 BY 1 STEP 480 0 ;
+ROW ROW_2 unithvdbl 0 16280 FS DO 52 BY 1 STEP 480 0 ;
+TRACKS X 240 DO 52 STEP 480 LAYER li1 ;
+TRACKS Y 240 DO 52 STEP 480 LAYER li1 ;
+TRACKS X 185 DO 68 STEP 370 LAYER met1 ;
+TRACKS Y 185 DO 68 STEP 370 LAYER met1 ;
+TRACKS X 240 DO 52 STEP 480 LAYER met2 ;
+TRACKS Y 240 DO 52 STEP 480 LAYER met2 ;
+TRACKS X 370 DO 34 STEP 740 LAYER met3 ;
+TRACKS Y 370 DO 34 STEP 740 LAYER met3 ;
+TRACKS X 480 DO 26 STEP 960 LAYER met4 ;
+TRACKS Y 480 DO 26 STEP 960 LAYER met4 ;
+TRACKS X 1665 DO 8 STEP 3330 LAYER met5 ;
+TRACKS Y 1665 DO 8 STEP 3330 LAYER met5 ;
+VIAS 4 ;
+ - via_1600x510 + VIARULE M1M2_PR + CUTSIZE 150 150 + LAYERS met1 via met2 + CUTSPACING 170 170 + ENCLOSURE 245 180 55 180 + ROWCOL 1 4 ;
+ - via2_1600x510 + VIARULE M2M3_PR + CUTSIZE 200 200 + LAYERS met2 via2 met3 + CUTSPACING 200 200 + ENCLOSURE 40 155 100 65 + ROWCOL 1 4 ;
+ - via3_1600x510 + VIARULE M3M4_PR + CUTSIZE 200 200 + LAYERS met3 via3 met4 + CUTSPACING 200 200 + ENCLOSURE 100 60 100 155 + ROWCOL 1 4 ;
+ - via4_1600x1600 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 400 400 400 400 ;
+END VIAS
+COMPONENTS 1 ;
+ - lvlshiftdown sky130_fd_sc_hvl__lsbufhv2lv_1 + PLACED ( 6720 8140 ) N ;
+END COMPONENTS
+PINS 16 ;
+ - A + NET A + DIRECTION INPUT + USE SIGNAL + PLACED ( 21360 23000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
+ - X + NET X + DIRECTION OUTPUT + USE SIGNAL + PLACED ( 3120 2000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
+ - VPWR + NET VPWR + DIRECTION INPUT + USE SIGNAL + FIXED ( 12480 16280 ) N + LAYER met1 ( -12480 -255 ) ( 12480 255 ) ;
+ - VPWR + NET VPWR + DIRECTION INPUT + USE SIGNAL + FIXED ( 12480 0 ) N + LAYER met1 ( -12480 -255 ) ( 12480 255 ) ;
+ - VPWR + NET VPWR + DIRECTION INPUT + USE SIGNAL + FIXED ( 20833 12210 ) N + LAYER met4 ( -800 -12465 ) ( 800 12465 ) ;
+ - VPWR + NET VPWR + DIRECTION INPUT + USE SIGNAL + FIXED ( 12500 12210 ) N + LAYER met4 ( -800 -12465 ) ( 800 12465 ) ;
+ - VPWR + NET VPWR + DIRECTION INPUT + USE SIGNAL + FIXED ( 4167 12210 ) N + LAYER met4 ( -800 -12465 ) ( 800 12465 ) ;
+ - VPWR + NET VPWR + DIRECTION INPUT + USE SIGNAL + FIXED ( 12480 20578 ) N + LAYER met5 ( -12480 -800 ) ( 12480 800 ) ;
+ - VPWR + NET VPWR + DIRECTION INPUT + USE SIGNAL + FIXED ( 12480 12245 ) N + LAYER met5 ( -12480 -800 ) ( 12480 800 ) ;
+ - VPWR + NET VPWR + DIRECTION INPUT + USE SIGNAL + FIXED ( 12480 3912 ) N + LAYER met5 ( -12480 -800 ) ( 12480 800 ) ;
+ - VGND + NET VGND + DIRECTION INPUT + USE SIGNAL + FIXED ( 12480 24420 ) N + LAYER met1 ( -12480 -255 ) ( 12480 255 ) ;
+ - VGND + NET VGND + DIRECTION INPUT + USE SIGNAL + FIXED ( 12480 8140 ) N + LAYER met1 ( -12480 -255 ) ( 12480 255 ) ;
+ - VGND + NET VGND + DIRECTION INPUT + USE SIGNAL + FIXED ( 16666 12210 ) N + LAYER met4 ( -800 -12465 ) ( 800 12465 ) ;
+ - VGND + NET VGND + DIRECTION INPUT + USE SIGNAL + FIXED ( 8333 12210 ) N + LAYER met4 ( -800 -12465 ) ( 800 12465 ) ;
+ - VGND + NET VGND + DIRECTION INPUT + USE SIGNAL + FIXED ( 12480 16411 ) N + LAYER met5 ( -12480 -800 ) ( 12480 800 ) ;
+ - VGND + NET VGND + DIRECTION INPUT + USE SIGNAL + FIXED ( 12480 8078 ) N + LAYER met5 ( -12480 -800 ) ( 12480 800 ) ;
+END PINS
+SPECIALNETS 2 ;
+ - VPWR ( PIN VPWR ) ( * VPWR ) ( * VPB ) ( * LVPWR ) + USE POWER
+ + ROUTED met4 0 + SHAPE STRIPE ( 20833 20578 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 12500 20578 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 4167 20578 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 20833 12245 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 12500 12245 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 4167 12245 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 20833 3912 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 12500 3912 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 4167 3912 ) via4_1600x1600
+ NEW met3 0 + SHAPE STRIPE ( 20833 16280 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 20833 16280 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 20833 16280 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 12500 16280 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 12500 16280 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 12500 16280 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 4167 16280 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 4167 16280 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 4167 16280 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 20833 0 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 20833 0 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 20833 0 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 12500 0 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 12500 0 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 12500 0 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 4167 0 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 4167 0 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 4167 0 ) via_1600x510
+ NEW met5 1600 + SHAPE STRIPE ( 0 20578 ) ( 24960 20578 )
+ NEW met5 1600 + SHAPE STRIPE ( 0 12245 ) ( 24960 12245 )
+ NEW met5 1600 + SHAPE STRIPE ( 0 3912 ) ( 24960 3912 )
+ NEW met4 1600 + SHAPE STRIPE ( 20833 -255 ) ( 20833 24675 )
+ NEW met4 1600 + SHAPE STRIPE ( 12500 -255 ) ( 12500 24675 )
+ NEW met4 1600 + SHAPE STRIPE ( 4167 -255 ) ( 4167 24675 )
+ NEW met1 510 + SHAPE FOLLOWPIN ( 0 16280 ) ( 24960 16280 )
+ NEW met1 510 + SHAPE FOLLOWPIN ( 0 0 ) ( 24960 0 ) ;
+ - VGND ( PIN VGND ) ( * VNB ) ( * VGND ) + USE GROUND
+ + ROUTED met4 0 + SHAPE STRIPE ( 16666 16411 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 8333 16411 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 16666 8078 ) via4_1600x1600
+ NEW met4 0 + SHAPE STRIPE ( 8333 8078 ) via4_1600x1600
+ NEW met3 0 + SHAPE STRIPE ( 16666 24420 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 16666 24420 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 16666 24420 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 8333 24420 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 8333 24420 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 8333 24420 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 16666 8140 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 16666 8140 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 16666 8140 ) via_1600x510
+ NEW met3 0 + SHAPE STRIPE ( 8333 8140 ) via3_1600x510
+ NEW met2 0 + SHAPE STRIPE ( 8333 8140 ) via2_1600x510
+ NEW met1 0 + SHAPE STRIPE ( 8333 8140 ) via_1600x510
+ NEW met5 1600 + SHAPE STRIPE ( 0 16411 ) ( 24960 16411 )
+ NEW met5 1600 + SHAPE STRIPE ( 0 8078 ) ( 24960 8078 )
+ NEW met4 1600 + SHAPE STRIPE ( 16666 -255 ) ( 16666 24675 )
+ NEW met4 1600 + SHAPE STRIPE ( 8333 -255 ) ( 8333 24675 )
+ NEW met1 510 + SHAPE FOLLOWPIN ( 0 24420 ) ( 24960 24420 )
+ NEW met1 510 + SHAPE FOLLOWPIN ( 0 8140 ) ( 24960 8140 ) ;
+END SPECIALNETS
+NETS 2 ;
+ - A ( PIN A ) ( lvlshiftdown A ) + USE SIGNAL ;
+ - X ( PIN X ) ( lvlshiftdown X ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/verilog2def_openroad.def b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/verilog2def_openroad.def
new file mode 100644
index 0000000..d6a2b98
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/floorplan/verilog2def_openroad.def
@@ -0,0 +1,33 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 25000 25000 ) ;
+ROW ROW_0 unithvdbl 0 0 FS DO 52 BY 1 STEP 480 0 ;
+ROW ROW_1 unithvdbl 0 8140 N DO 52 BY 1 STEP 480 0 ;
+ROW ROW_2 unithvdbl 0 16280 FS DO 52 BY 1 STEP 480 0 ;
+TRACKS X 240 DO 52 STEP 480 LAYER li1 ;
+TRACKS Y 240 DO 52 STEP 480 LAYER li1 ;
+TRACKS X 185 DO 68 STEP 370 LAYER met1 ;
+TRACKS Y 185 DO 68 STEP 370 LAYER met1 ;
+TRACKS X 240 DO 52 STEP 480 LAYER met2 ;
+TRACKS Y 240 DO 52 STEP 480 LAYER met2 ;
+TRACKS X 370 DO 34 STEP 740 LAYER met3 ;
+TRACKS Y 370 DO 34 STEP 740 LAYER met3 ;
+TRACKS X 480 DO 26 STEP 960 LAYER met4 ;
+TRACKS Y 480 DO 26 STEP 960 LAYER met4 ;
+TRACKS X 1665 DO 8 STEP 3330 LAYER met5 ;
+TRACKS Y 1665 DO 8 STEP 3330 LAYER met5 ;
+COMPONENTS 1 ;
+ - lvlshiftdown sky130_fd_sc_hvl__lsbufhv2lv_1 ;
+END COMPONENTS
+PINS 2 ;
+ - A + NET A + DIRECTION INPUT + USE SIGNAL ;
+ - X + NET X + DIRECTION OUTPUT + USE SIGNAL ;
+END PINS
+NETS 2 ;
+ - A ( PIN A ) ( lvlshiftdown A ) + USE SIGNAL ;
+ - X ( PIN X ) ( lvlshiftdown X ) + USE SIGNAL ;
+END NETS
+END DESIGN
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/lvs/merged_unpadded.lef b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/lvs/merged_unpadded.lef
new file mode 120000
index 0000000..c48782e
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/lvs/merged_unpadded.lef
@@ -0,0 +1 @@
+../../tmp/merged_unpadded.lef
\ No newline at end of file
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/magic/merged_unpadded.lef b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/magic/merged_unpadded.lef
new file mode 120000
index 0000000..c48782e
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/magic/merged_unpadded.lef
@@ -0,0 +1 @@
+../../tmp/merged_unpadded.lef
\ No newline at end of file
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/magic_spice.tcl b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/magic_spice.tcl
new file mode 100644
index 0000000..24f6086
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/magic_spice.tcl
@@ -0,0 +1,24 @@
+
+lef read /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/techlef/sky130_fd_sc_hvl.tlef
+if { [info exist ::env(EXTRA_LEFS)] } {
+ set lefs_in $::env(EXTRA_LEFS)
+ foreach lef_file $lefs_in {
+ lef read $lef_file
+ }
+}
+def read /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/routing/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.def
+load sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped -dereference
+cd /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/
+extract do local
+extract no capacitance
+extract no coupling
+extract no resistance
+extract no adjust
+# extract warn all
+extract
+
+ext2spice lvs
+ext2spice sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.ext
+feedback save /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/logs/magic/magic_ext2spice.feedback.txt
+# exec cp sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.spice /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/results/magic/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.spice
+
diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged.lef b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged.lef
new file mode 100644
index 0000000..448e6e4
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged.lef
@@ -0,0 +1,12841 @@
+# Copyright 2020 The SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+VERSION 5.7 ;
+
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+UNITS
+ TIME NANOSECONDS 1 ;
+ CAPACITANCE PICOFARADS 1 ;
+ RESISTANCE OHMS 1 ;
+ DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+PROPERTYDEFINITIONS
+ LAYER LEF58_TYPE STRING ;
+END PROPERTYDEFINITIONS
+
+# High voltage, single height
+SITE unithv
+ SYMMETRY Y ;
+ CLASS CORE ;
+ SIZE 0.48 BY 4.07 ;
+END unithv
+
+# High voltage, double height
+SITE unithvdbl
+ SYMMETRY Y ;
+ CLASS CORE ;
+ SIZE 0.48 BY 8.14 ;
+END unithvdbl
+
+LAYER nwell
+ TYPE MASTERSLICE ;
+ PROPERTY LEF58_TYPE "TYPE NWELL ;" ;
+END nwell
+
+LAYER pwell
+ TYPE MASTERSLICE ;
+ PROPERTY LEF58_TYPE "TYPE NWELL ;" ;
+END pwell
+
+LAYER li1
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.48 ;
+ MINWIDTH 0.17 ;
+
+ WIDTH 0.17 ; # LI 1
+ # SPACING 0.17 ; # LI 2
+ SPACINGTABLE
+ PARALLELRUNLENGTH 0
+ WIDTH 0 0.17 ;
+ AREA 0.0561 ; # LI 6
+ THICKNESS 0.1 ;
+ EDGECAPACITANCE 40.697E-6 ;
+ CAPACITANCE CPERSQDIST 36.9866E-6 ;
+ RESISTANCE RPERSQ 12.2 ;
+
+ ANTENNADIFFSIDEAREARATIO PWL ( ( 0 75 ) ( 0.0125 75 ) ( 0.0225 85.125 ) ( 22.5 10200 ) ) ;
+END li1
+
+LAYER mcon
+ TYPE CUT ;
+
+ WIDTH 0.17 ; # Mcon 1
+ SPACING 0.19 ; # Mcon 2
+ ENCLOSURE BELOW 0 0 ; # Mcon 4
+ ENCLOSURE ABOVE 0.03 0.06 ; # Met1 4 / Met1 5
+
+ ANTENNADIFFAREARATIO PWL ( ( 0 3 ) ( 0.0125 3 ) ( 0.0225 3.405 ) ( 22.5 408 ) ) ;
+ DCCURRENTDENSITY AVERAGE 0.36 ; # mA per via Iavg_max at Tj = 90oC
+
+END mcon
+
+LAYER met1
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.37 ;
+ MINENCLOSEDAREA 0.14 ;
+ MINWIDTH 0.14 ;
+
+ WIDTH 0.14 ; # Met1 1
+ # SPACING 0.14 ; # Met1 2
+ # SPACING 0.28 RANGE 3.001 100 ; # Met1 3b
+ SPACINGTABLE
+ PARALLELRUNLENGTH 0
+ WIDTH 0 0.14
+ WIDTH 3 0.28 ;
+ AREA 0.083 ; # Met1 6
+ THICKNESS 0.35 ;
+
+ ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
+
+ EDGECAPACITANCE 40.567E-6 ;
+ CAPACITANCE CPERSQDIST 25.7784E-6 ;
+ DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC
+ ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC
+
+ RESISTANCE RPERSQ 0.125 ;
+END met1
+
+LAYER via
+ TYPE CUT ;
+ WIDTH 0.15 ; # Via 1a
+ SPACING 0.17 ; # Via 2
+ ENCLOSURE BELOW 0.055 0.085 ; # Via 4a / Via 5a
+ ENCLOSURE ABOVE 0.055 0.085 ; # Met2 4 / Met2 5
+
+ ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
+ DCCURRENTDENSITY AVERAGE 0.29 ; # mA per via Iavg_max at Tj = 90oC
+END via
+
+LAYER met2
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.48 ;
+ MINENCLOSEDAREA 0.14 ;
+ MINWIDTH 0.14 ;
+
+ WIDTH 0.14 ; # Met2 1
+ # SPACING 0.14 ; # Met2 2
+ # SPACING 0.28 RANGE 3.001 100 ; # Met2 3b
+ SPACINGTABLE
+ PARALLELRUNLENGTH 0
+ WIDTH 0 0.14
+ WIDTH 3 0.28 ;
+ AREA 0.0676 ; # Met2 6
+ THICKNESS 0.35 ;
+
+ EDGECAPACITANCE 37.759E-6 ;
+ CAPACITANCE CPERSQDIST 16.9423E-6 ;
+ RESISTANCE RPERSQ 0.125 ;
+ DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC
+ ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC
+ ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
+END met2
+
+# ******** Layer via2, type routing, number 44 **************
+LAYER via2
+ TYPE CUT ;
+ WIDTH 0.2 ; # Via2 1
+ SPACING 0.2 ; # Via2 2
+ ENCLOSURE BELOW 0.04 0.085 ; # Via2 4
+ ENCLOSURE ABOVE 0.065 0.065 ; # Met3 4
+ ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
+ DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC
+END via2
+
+LAYER met3
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 0.74 ;
+ MINWIDTH 0.3 ;
+
+ WIDTH 0.3 ; # Met3 1
+ # SPACING 0.3 ; # Met3 2
+ SPACINGTABLE
+ PARALLELRUNLENGTH 0
+ WIDTH 0 0.3
+ WIDTH 3 0.4 ;
+ AREA 0.24 ; # Met3 6
+ THICKNESS 0.8 ;
+
+ EDGECAPACITANCE 40.989E-6 ;
+ CAPACITANCE CPERSQDIST 12.3729E-6 ;
+ RESISTANCE RPERSQ 0.047 ;
+ DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC
+ ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC
+
+ ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
+END met3
+
+LAYER via3
+ TYPE CUT ;
+ WIDTH 0.2 ; # Via3 1
+ SPACING 0.2 ; # Via3 2
+ ENCLOSURE BELOW 0.06 0.09 ; # Via3 4 / Via3 5
+ ENCLOSURE ABOVE 0.065 0.065 ; # Met4 3
+ ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
+ DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC
+END via3
+
+LAYER met4
+ TYPE ROUTING ;
+ DIRECTION VERTICAL ;
+
+ PITCH 0.96 ;
+ MINWIDTH 0.3 ;
+
+ WIDTH 0.3 ; # Met4 1
+ # SPACING 0.3 ; # Met4 2
+ SPACINGTABLE
+ PARALLELRUNLENGTH 0
+ WIDTH 0 0.3
+ WIDTH 3 0.4 ;
+ AREA 0.24 ; # Met4 4a
+
+ THICKNESS 0.8 ;
+
+ EDGECAPACITANCE 36.676E-6 ;
+ CAPACITANCE CPERSQDIST 8.41537E-6 ;
+ RESISTANCE RPERSQ 0.047 ;
+ DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC
+ ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC
+
+ ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
+END met4
+
+LAYER via4
+ TYPE CUT ;
+
+ WIDTH 0.8 ; # Via4 1
+ SPACING 0.8 ; # Via4 2
+ ENCLOSURE BELOW 0.19 0.19 ; # Via4 4
+ ENCLOSURE ABOVE 0.31 0.31 ; # Met5 3
+ ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
+ DCCURRENTDENSITY AVERAGE 2.49 ; # mA per via Iavg_max at Tj = 90oC
+END via4
+
+LAYER met5
+ TYPE ROUTING ;
+ DIRECTION HORIZONTAL ;
+
+ PITCH 3.33 ;
+ MINWIDTH 1.6 ;
+
+ WIDTH 1.6 ; # Met5 1
+ #SPACING 1.6 ; # Met5 2
+ SPACINGTABLE
+ PARALLELRUNLENGTH 0
+ WIDTH 0 1.6 ;
+ AREA 4 ; # Met5 4
+
+ THICKNESS 1.2 ;
+
+ EDGECAPACITANCE 38.851E-6 ;
+ CAPACITANCE CPERSQDIST 6.32063E-6 ;
+ RESISTANCE RPERSQ 0.0285 ;
+ DCCURRENTDENSITY AVERAGE 10.17 ; # mA/um Iavg_max at Tj = 90oC
+ ACCURRENTDENSITY RMS 22.34 ; # mA/um Irms_max at Tj = 90oC
+
+ ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
+END met5
+
+
+### Routing via cells section ###
+# Plus via rule, metals are along the prefered direction
+VIA L1M1_PR DEFAULT
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR
+
+VIARULE L1M1_PR GENERATE
+ LAYER li1 ;
+ ENCLOSURE 0 0 ;
+ LAYER met1 ;
+ ENCLOSURE 0.06 0.03 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ SPACING 0.36 BY 0.36 ;
+END L1M1_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA L1M1_PR_R DEFAULT
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_R
+
+VIARULE L1M1_PR_R GENERATE
+ LAYER li1 ;
+ ENCLOSURE 0 0 ;
+ LAYER met1 ;
+ ENCLOSURE 0.03 0.06 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ SPACING 0.36 BY 0.36 ;
+END L1M1_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA L1M1_PR_M DEFAULT
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_M
+
+VIARULE L1M1_PR_M GENERATE
+ LAYER li1 ;
+ ENCLOSURE 0 0 ;
+ LAYER met1 ;
+ ENCLOSURE 0.03 0.06 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ SPACING 0.36 BY 0.36 ;
+END L1M1_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA L1M1_PR_MR DEFAULT
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIARULE L1M1_PR_MR GENERATE
+ LAYER li1 ;
+ ENCLOSURE 0 0 ;
+ LAYER met1 ;
+ ENCLOSURE 0.06 0.03 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ SPACING 0.36 BY 0.36 ;
+END L1M1_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA L1M1_PR_C DEFAULT
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER li1 ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ LAYER met1 ;
+ RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIARULE L1M1_PR_C GENERATE
+ LAYER li1 ;
+ ENCLOSURE 0 0 ;
+ LAYER met1 ;
+ ENCLOSURE 0.06 0.06 ;
+ LAYER mcon ;
+ RECT -0.085 -0.085 0.085 0.085 ;
+ SPACING 0.36 BY 0.36 ;
+END L1M1_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M1M2_PR DEFAULT
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIARULE M1M2_PR GENERATE
+ LAYER met1 ;
+ ENCLOSURE 0.085 0.055 ;
+ LAYER met2 ;
+ ENCLOSURE 0.055 0.085 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ SPACING 0.32 BY 0.32 ;
+END M1M2_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M1M2_PR_R DEFAULT
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIARULE M1M2_PR_R GENERATE
+ LAYER met1 ;
+ ENCLOSURE 0.055 0.085 ;
+ LAYER met2 ;
+ ENCLOSURE 0.085 0.055 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ SPACING 0.32 BY 0.32 ;
+END M1M2_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M1M2_PR_M DEFAULT
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met1 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+ LAYER met2 ;
+ RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIARULE M1M2_PR_M GENERATE
+ LAYER met1 ;
+ ENCLOSURE 0.085 0.055 ;
+ LAYER met2 ;
+ ENCLOSURE 0.085 0.055 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ SPACING 0.32 BY 0.32 ;
+END M1M2_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M1M2_PR_MR DEFAULT
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met1 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+ LAYER met2 ;
+ RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIARULE M1M2_PR_MR GENERATE
+ LAYER met1 ;
+ ENCLOSURE 0.055 0.085 ;
+ LAYER met2 ;
+ ENCLOSURE 0.055 0.085 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ SPACING 0.32 BY 0.32 ;
+END M1M2_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA M1M2_PR_C DEFAULT
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ LAYER met1 ;
+ RECT -0.16 -0.16 0.16 0.16 ;
+ LAYER met2 ;
+ RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIARULE M1M2_PR_C GENERATE
+ LAYER met1 ;
+ ENCLOSURE 0.085 0.085 ;
+ LAYER met2 ;
+ ENCLOSURE 0.085 0.085 ;
+ LAYER via ;
+ RECT -0.075 -0.075 0.075 0.075 ;
+ SPACING 0.32 BY 0.32 ;
+END M1M2_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M2M3_PR DEFAULT
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met2 ;
+ RECT -0.14 -0.185 0.14 0.185 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIARULE M2M3_PR GENERATE
+ LAYER met2 ;
+ ENCLOSURE 0.04 0.085 ;
+ LAYER met3 ;
+ ENCLOSURE 0.065 0.065 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ SPACING 0.4 BY 0.4 ;
+END M2M3_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M2M3_PR_R DEFAULT
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met2 ;
+ RECT -0.185 -0.14 0.185 0.14 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIARULE M2M3_PR_R GENERATE
+ LAYER met2 ;
+ ENCLOSURE 0.085 0.04 ;
+ LAYER met3 ;
+ ENCLOSURE 0.065 0.065 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ SPACING 0.4 BY 0.4 ;
+END M2M3_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M2M3_PR_M DEFAULT
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met2 ;
+ RECT -0.14 -0.185 0.14 0.185 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIARULE M2M3_PR_M GENERATE
+ LAYER met2 ;
+ ENCLOSURE 0.04 0.085 ;
+ LAYER met3 ;
+ ENCLOSURE 0.065 0.065 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ SPACING 0.4 BY 0.4 ;
+END M2M3_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M2M3_PR_MR DEFAULT
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met2 ;
+ RECT -0.185 -0.14 0.185 0.14 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIARULE M2M3_PR_MR GENERATE
+ LAYER met2 ;
+ ENCLOSURE 0.085 0.04 ;
+ LAYER met3 ;
+ ENCLOSURE 0.065 0.065 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ SPACING 0.4 BY 0.4 ;
+END M2M3_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA M2M3_PR_C DEFAULT
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met2 ;
+ RECT -0.185 -0.185 0.185 0.185 ;
+ LAYER met3 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIARULE M2M3_PR_C GENERATE
+ LAYER met2 ;
+ ENCLOSURE 0.085 0.085 ;
+ LAYER met3 ;
+ ENCLOSURE 0.065 0.065 ;
+ LAYER via2 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ SPACING 0.4 BY 0.4 ;
+END M2M3_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M3M4_PR DEFAULT
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.19 -0.16 0.19 0.16 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIARULE M3M4_PR GENERATE
+ LAYER met3 ;
+ ENCLOSURE 0.09 0.06 ;
+ LAYER met4 ;
+ ENCLOSURE 0.065 0.065 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ SPACING 0.4 BY 0.4 ;
+END M3M4_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M3M4_PR_R DEFAULT
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.16 -0.19 0.16 0.19 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIARULE M3M4_PR_R GENERATE
+ LAYER met3 ;
+ ENCLOSURE 0.06 0.09 ;
+ LAYER met4 ;
+ ENCLOSURE 0.065 0.065 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ SPACING 0.4 BY 0.4 ;
+END M3M4_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M3M4_PR_M DEFAULT
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.19 -0.16 0.19 0.16 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIARULE M3M4_PR_M GENERATE
+ LAYER met3 ;
+ ENCLOSURE 0.09 0.06 ;
+ LAYER met4 ;
+ ENCLOSURE 0.065 0.065 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ SPACING 0.4 BY 0.4 ;
+END M3M4_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M3M4_PR_MR DEFAULT
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.16 -0.19 0.16 0.19 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIARULE M3M4_PR_MR GENERATE
+ LAYER met3 ;
+ ENCLOSURE 0.06 0.09 ;
+ LAYER met4 ;
+ ENCLOSURE 0.065 0.065 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ SPACING 0.4 BY 0.4 ;
+END M3M4_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA M3M4_PR_C DEFAULT
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ LAYER met3 ;
+ RECT -0.19 -0.19 0.19 0.19 ;
+ LAYER met4 ;
+ RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIARULE M3M4_PR_C GENERATE
+ LAYER met3 ;
+ ENCLOSURE 0.09 0.09 ;
+ LAYER met4 ;
+ ENCLOSURE 0.065 0.065 ;
+ LAYER via3 ;
+ RECT -0.1 -0.1 0.1 0.1 ;
+ SPACING 0.4 BY 0.4 ;
+END M3M4_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M4M5_PR DEFAULT
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIARULE M4M5_PR GENERATE
+ LAYER met4 ;
+ ENCLOSURE 0.19 0.19 ;
+ LAYER met5 ;
+ ENCLOSURE 0.31 0.31 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ SPACING 1.6 BY 1.6 ;
+END M4M5_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M4M5_PR_R DEFAULT
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIARULE M4M5_PR_R GENERATE
+ LAYER met4 ;
+ ENCLOSURE 0.19 0.19 ;
+ LAYER met5 ;
+ ENCLOSURE 0.31 0.31 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ SPACING 1.6 BY 1.6 ;
+END M4M5_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M4M5_PR_M DEFAULT
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIARULE M4M5_PR_M GENERATE
+ LAYER met4 ;
+ ENCLOSURE 0.19 0.19 ;
+ LAYER met5 ;
+ ENCLOSURE 0.31 0.31 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ SPACING 1.6 BY 1.6 ;
+END M4M5_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M4M5_PR_MR DEFAULT
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIARULE M4M5_PR_MR GENERATE
+ LAYER met4 ;
+ ENCLOSURE 0.19 0.19 ;
+ LAYER met5 ;
+ ENCLOSURE 0.31 0.31 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ SPACING 1.6 BY 1.6 ;
+END M4M5_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA M4M5_PR_C DEFAULT
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ LAYER met4 ;
+ RECT -0.59 -0.59 0.59 0.59 ;
+ LAYER met5 ;
+ RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+VIARULE M4M5_PR_C GENERATE
+ LAYER met4 ;
+ ENCLOSURE 0.19 0.19 ;
+ LAYER met5 ;
+ ENCLOSURE 0.31 0.31 ;
+ LAYER via4 ;
+ RECT -0.4 -0.4 0.4 0.4 ;
+ SPACING 1.6 BY 1.6 ;
+END M4M5_PR_C
+### end of single via cells ###
+
+
+MACRO sky130_fd_sc_hvl__dfsbp_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__dfsbp_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 17.76000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN D
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.525000 1.515000 2.875000 2.145000 ;
+ END
+ END D
+ PIN Q
+ ANTENNADIFFAREA 0.498750 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 17.300000 0.495000 17.635000 1.325000 ;
+ RECT 17.300000 2.355000 17.635000 3.435000 ;
+ RECT 17.405000 1.325000 17.635000 2.355000 ;
+ END
+ END Q
+ PIN Q_N
+ ANTENNADIFFAREA 0.641250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 15.015000 0.495000 15.375000 3.755000 ;
+ END
+ END Q_N
+ PIN SET_B
+ ANTENNAGATEAREA 0.840000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 6.985000 1.155000 10.330000 1.325000 ;
+ RECT 10.160000 1.325000 10.330000 1.605000 ;
+ RECT 10.160000 1.605000 10.885000 1.775000 ;
+ RECT 10.715000 1.775000 10.885000 1.975000 ;
+ RECT 10.715000 1.975000 12.830000 2.145000 ;
+ RECT 12.150000 1.555000 12.830000 1.975000 ;
+ END
+ END SET_B
+ PIN CLK
+ ANTENNAGATEAREA 0.585000 ;
+ DIRECTION INPUT ;
+ USE CLOCK ;
+ PORT
+ LAYER li1 ;
+ RECT 0.560000 1.550000 0.890000 2.520000 ;
+ END
+ END CLK
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 17.760000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 17.760000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 17.760000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 17.760000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 17.760000 0.085000 ;
+ RECT 0.000000 3.985000 17.760000 4.155000 ;
+ RECT 0.110000 0.540000 0.360000 1.200000 ;
+ RECT 0.110000 1.200000 1.590000 1.370000 ;
+ RECT 0.110000 1.370000 0.380000 3.450000 ;
+ RECT 0.540000 0.365000 1.490000 1.020000 ;
+ RECT 0.650000 2.700000 1.240000 3.705000 ;
+ RECT 1.260000 1.370000 1.590000 1.870000 ;
+ RECT 1.420000 1.870000 1.590000 3.630000 ;
+ RECT 1.420000 3.630000 2.290000 3.800000 ;
+ RECT 1.670000 0.540000 2.000000 1.000000 ;
+ RECT 1.770000 1.000000 2.000000 1.165000 ;
+ RECT 1.770000 1.165000 2.820000 1.335000 ;
+ RECT 1.770000 1.335000 1.940000 3.450000 ;
+ RECT 2.120000 2.325000 3.025000 2.495000 ;
+ RECT 2.120000 2.495000 2.290000 3.630000 ;
+ RECT 2.220000 0.365000 2.470000 0.985000 ;
+ RECT 2.470000 2.675000 2.675000 3.705000 ;
+ RECT 2.650000 0.265000 4.460000 0.435000 ;
+ RECT 2.650000 0.435000 2.820000 1.165000 ;
+ RECT 2.855000 2.495000 3.025000 3.355000 ;
+ RECT 2.855000 3.355000 5.500000 3.525000 ;
+ RECT 3.000000 0.615000 3.375000 1.005000 ;
+ RECT 3.205000 1.005000 3.375000 2.675000 ;
+ RECT 3.205000 2.675000 3.545000 3.175000 ;
+ RECT 3.555000 1.105000 3.725000 2.225000 ;
+ RECT 3.555000 2.225000 4.800000 2.395000 ;
+ RECT 3.725000 2.395000 3.895000 3.355000 ;
+ RECT 3.780000 0.615000 4.110000 0.925000 ;
+ RECT 3.905000 0.925000 4.075000 1.855000 ;
+ RECT 3.905000 1.855000 8.060000 2.025000 ;
+ RECT 4.075000 2.675000 4.405000 3.005000 ;
+ RECT 4.075000 3.005000 5.150000 3.175000 ;
+ RECT 4.255000 1.105000 4.585000 1.505000 ;
+ RECT 4.255000 1.505000 9.470000 1.675000 ;
+ RECT 4.290000 0.435000 4.460000 1.105000 ;
+ RECT 4.585000 2.395000 4.800000 2.555000 ;
+ RECT 4.650000 0.365000 5.600000 0.905000 ;
+ RECT 4.945000 1.085000 6.150000 1.325000 ;
+ RECT 4.980000 2.025000 5.150000 3.005000 ;
+ RECT 5.330000 2.205000 7.025000 2.375000 ;
+ RECT 5.330000 2.555000 6.595000 2.725000 ;
+ RECT 5.330000 2.725000 5.500000 3.355000 ;
+ RECT 5.680000 2.905000 6.245000 3.705000 ;
+ RECT 5.820000 0.515000 6.150000 1.085000 ;
+ RECT 6.425000 2.725000 6.595000 3.355000 ;
+ RECT 6.425000 3.355000 7.675000 3.525000 ;
+ RECT 6.775000 2.375000 7.025000 3.175000 ;
+ RECT 6.785000 0.365000 7.735000 0.975000 ;
+ RECT 7.505000 2.545000 9.120000 2.715000 ;
+ RECT 7.505000 2.715000 7.675000 3.355000 ;
+ RECT 7.730000 2.025000 8.060000 2.365000 ;
+ RECT 7.855000 2.895000 8.805000 3.705000 ;
+ RECT 8.185000 0.375000 11.110000 0.545000 ;
+ RECT 8.185000 0.545000 8.515000 0.975000 ;
+ RECT 8.755000 0.725000 10.680000 0.975000 ;
+ RECT 8.870000 1.885000 9.120000 2.545000 ;
+ RECT 9.300000 1.675000 9.470000 2.305000 ;
+ RECT 9.300000 2.305000 10.185000 2.475000 ;
+ RECT 9.345000 2.675000 9.675000 3.585000 ;
+ RECT 9.345000 3.585000 10.535000 3.755000 ;
+ RECT 9.650000 1.505000 9.980000 1.955000 ;
+ RECT 9.650000 1.955000 10.535000 2.125000 ;
+ RECT 9.855000 2.475000 10.185000 2.555000 ;
+ RECT 10.365000 2.125000 10.535000 2.325000 ;
+ RECT 10.365000 2.325000 13.180000 2.495000 ;
+ RECT 10.365000 2.495000 10.535000 3.585000 ;
+ RECT 10.510000 0.975000 10.680000 1.255000 ;
+ RECT 10.510000 1.255000 11.460000 1.425000 ;
+ RECT 10.715000 2.675000 11.665000 3.705000 ;
+ RECT 10.860000 0.545000 11.110000 1.075000 ;
+ RECT 11.290000 0.515000 11.660000 0.975000 ;
+ RECT 11.290000 0.975000 11.460000 1.255000 ;
+ RECT 11.640000 1.155000 11.970000 1.205000 ;
+ RECT 11.640000 1.205000 14.395000 1.375000 ;
+ RECT 11.640000 1.375000 11.970000 1.795000 ;
+ RECT 12.035000 2.495000 13.180000 3.175000 ;
+ RECT 12.200000 0.365000 13.150000 0.975000 ;
+ RECT 13.010000 1.555000 14.045000 1.725000 ;
+ RECT 13.010000 1.725000 13.180000 2.325000 ;
+ RECT 13.360000 1.905000 14.395000 2.075000 ;
+ RECT 13.360000 2.075000 13.690000 2.675000 ;
+ RECT 13.390000 0.825000 13.720000 1.205000 ;
+ RECT 13.870000 2.255000 14.820000 3.755000 ;
+ RECT 13.900000 0.365000 14.835000 1.025000 ;
+ RECT 14.225000 1.375000 14.395000 1.905000 ;
+ RECT 15.625000 0.825000 15.975000 1.505000 ;
+ RECT 15.625000 1.505000 17.175000 1.675000 ;
+ RECT 15.625000 1.675000 15.955000 3.185000 ;
+ RECT 16.135000 2.355000 17.085000 3.705000 ;
+ RECT 16.155000 0.365000 17.105000 1.305000 ;
+ RECT 16.845000 1.675000 17.175000 2.175000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.570000 0.395000 0.740000 0.565000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.680000 3.505000 0.850000 3.675000 ;
+ RECT 0.930000 0.395000 1.100000 0.565000 ;
+ RECT 1.040000 3.505000 1.210000 3.675000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.290000 0.395000 1.460000 0.565000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.250000 0.395000 2.420000 0.565000 ;
+ RECT 2.490000 3.505000 2.660000 3.675000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.680000 0.395000 4.850000 0.565000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ RECT 5.040000 0.395000 5.210000 0.565000 ;
+ RECT 5.400000 0.395000 5.570000 0.565000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 3.985000 5.605000 4.155000 ;
+ RECT 5.695000 3.505000 5.865000 3.675000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 3.985000 6.085000 4.155000 ;
+ RECT 6.055000 3.505000 6.225000 3.675000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 3.985000 6.565000 4.155000 ;
+ RECT 6.815000 0.395000 6.985000 0.565000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 3.985000 7.045000 4.155000 ;
+ RECT 7.175000 0.395000 7.345000 0.565000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 3.985000 7.525000 4.155000 ;
+ RECT 7.535000 0.395000 7.705000 0.565000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 3.985000 8.005000 4.155000 ;
+ RECT 7.885000 3.505000 8.055000 3.675000 ;
+ RECT 8.245000 3.505000 8.415000 3.675000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 3.985000 8.485000 4.155000 ;
+ RECT 8.605000 3.505000 8.775000 3.675000 ;
+ RECT 8.795000 -0.085000 8.965000 0.085000 ;
+ RECT 8.795000 3.985000 8.965000 4.155000 ;
+ RECT 9.275000 -0.085000 9.445000 0.085000 ;
+ RECT 9.275000 3.985000 9.445000 4.155000 ;
+ RECT 9.755000 -0.085000 9.925000 0.085000 ;
+ RECT 9.755000 3.985000 9.925000 4.155000 ;
+ RECT 10.235000 -0.085000 10.405000 0.085000 ;
+ RECT 10.235000 3.985000 10.405000 4.155000 ;
+ RECT 10.715000 -0.085000 10.885000 0.085000 ;
+ RECT 10.715000 3.985000 10.885000 4.155000 ;
+ RECT 10.745000 3.505000 10.915000 3.675000 ;
+ RECT 11.105000 3.505000 11.275000 3.675000 ;
+ RECT 11.195000 -0.085000 11.365000 0.085000 ;
+ RECT 11.195000 3.985000 11.365000 4.155000 ;
+ RECT 11.465000 3.505000 11.635000 3.675000 ;
+ RECT 11.675000 -0.085000 11.845000 0.085000 ;
+ RECT 11.675000 3.985000 11.845000 4.155000 ;
+ RECT 12.155000 -0.085000 12.325000 0.085000 ;
+ RECT 12.155000 3.985000 12.325000 4.155000 ;
+ RECT 12.230000 0.395000 12.400000 0.565000 ;
+ RECT 12.590000 0.395000 12.760000 0.565000 ;
+ RECT 12.635000 -0.085000 12.805000 0.085000 ;
+ RECT 12.635000 3.985000 12.805000 4.155000 ;
+ RECT 12.950000 0.395000 13.120000 0.565000 ;
+ RECT 13.115000 -0.085000 13.285000 0.085000 ;
+ RECT 13.115000 3.985000 13.285000 4.155000 ;
+ RECT 13.595000 -0.085000 13.765000 0.085000 ;
+ RECT 13.595000 3.985000 13.765000 4.155000 ;
+ RECT 13.900000 3.505000 14.070000 3.675000 ;
+ RECT 13.920000 0.395000 14.090000 0.565000 ;
+ RECT 14.075000 -0.085000 14.245000 0.085000 ;
+ RECT 14.075000 3.985000 14.245000 4.155000 ;
+ RECT 14.260000 3.505000 14.430000 3.675000 ;
+ RECT 14.280000 0.395000 14.450000 0.565000 ;
+ RECT 14.555000 -0.085000 14.725000 0.085000 ;
+ RECT 14.555000 3.985000 14.725000 4.155000 ;
+ RECT 14.620000 3.505000 14.790000 3.675000 ;
+ RECT 14.640000 0.395000 14.810000 0.565000 ;
+ RECT 15.035000 -0.085000 15.205000 0.085000 ;
+ RECT 15.035000 3.985000 15.205000 4.155000 ;
+ RECT 15.515000 -0.085000 15.685000 0.085000 ;
+ RECT 15.515000 3.985000 15.685000 4.155000 ;
+ RECT 15.995000 -0.085000 16.165000 0.085000 ;
+ RECT 15.995000 3.985000 16.165000 4.155000 ;
+ RECT 16.165000 3.505000 16.335000 3.675000 ;
+ RECT 16.185000 0.395000 16.355000 0.565000 ;
+ RECT 16.475000 -0.085000 16.645000 0.085000 ;
+ RECT 16.475000 3.985000 16.645000 4.155000 ;
+ RECT 16.525000 3.505000 16.695000 3.675000 ;
+ RECT 16.545000 0.395000 16.715000 0.565000 ;
+ RECT 16.885000 3.505000 17.055000 3.675000 ;
+ RECT 16.905000 0.395000 17.075000 0.565000 ;
+ RECT 16.955000 -0.085000 17.125000 0.085000 ;
+ RECT 16.955000 3.985000 17.125000 4.155000 ;
+ RECT 17.435000 -0.085000 17.605000 0.085000 ;
+ RECT 17.435000 3.985000 17.605000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__dfsbp_1
+MACRO sky130_fd_sc_hvl__dfrtp_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__dfrtp_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 15.36000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN D
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 3.415000 0.810000 3.745000 2.105000 ;
+ END
+ END D
+ PIN Q
+ ANTENNADIFFAREA 0.611250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 14.900000 0.665000 15.235000 3.735000 ;
+ END
+ END Q
+ PIN RESET_B
+ ANTENNAGATEAREA 1.260000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.695000 1.620000 3.235000 2.490000 ;
+ RECT 3.065000 0.460000 6.010000 0.630000 ;
+ RECT 3.065000 0.630000 3.235000 1.620000 ;
+ RECT 5.840000 0.630000 6.010000 1.125000 ;
+ RECT 5.840000 1.125000 8.460000 1.295000 ;
+ RECT 6.605000 1.825000 8.460000 1.995000 ;
+ RECT 8.290000 0.265000 10.950000 0.435000 ;
+ RECT 8.290000 0.435000 8.460000 1.125000 ;
+ RECT 8.290000 1.295000 8.460000 1.825000 ;
+ RECT 10.780000 0.435000 10.950000 1.095000 ;
+ RECT 10.780000 1.095000 11.785000 1.265000 ;
+ RECT 11.455000 1.265000 11.785000 1.655000 ;
+ END
+ END RESET_B
+ PIN CLK
+ ANTENNAGATEAREA 0.585000 ;
+ DIRECTION INPUT ;
+ USE CLOCK ;
+ PORT
+ LAYER li1 ;
+ RECT 0.560000 1.175000 0.890000 2.150000 ;
+ END
+ END CLK
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 15.360000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 15.360000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 15.360000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 15.360000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 15.360000 0.085000 ;
+ RECT 0.000000 3.985000 15.360000 4.155000 ;
+ RECT 0.110000 0.495000 0.380000 2.355000 ;
+ RECT 0.110000 2.355000 1.570000 2.525000 ;
+ RECT 0.110000 2.525000 0.440000 3.455000 ;
+ RECT 0.560000 0.365000 1.510000 0.995000 ;
+ RECT 0.630000 2.725000 1.220000 3.705000 ;
+ RECT 1.240000 1.855000 1.570000 2.355000 ;
+ RECT 1.400000 2.525000 1.570000 3.635000 ;
+ RECT 1.400000 3.635000 2.840000 3.805000 ;
+ RECT 1.690000 0.495000 2.020000 0.995000 ;
+ RECT 1.750000 0.995000 2.020000 1.920000 ;
+ RECT 1.750000 1.920000 2.275000 2.150000 ;
+ RECT 1.750000 2.150000 2.000000 3.455000 ;
+ RECT 2.200000 0.365000 2.790000 1.245000 ;
+ RECT 2.240000 2.670000 4.050000 2.840000 ;
+ RECT 2.240000 2.840000 2.490000 3.455000 ;
+ RECT 2.670000 3.020000 3.700000 3.190000 ;
+ RECT 2.670000 3.190000 2.840000 3.635000 ;
+ RECT 3.020000 3.370000 3.350000 3.705000 ;
+ RECT 3.530000 3.190000 3.700000 3.635000 ;
+ RECT 3.530000 3.635000 5.270000 3.805000 ;
+ RECT 3.880000 2.320000 4.100000 2.490000 ;
+ RECT 3.880000 2.490000 4.050000 2.670000 ;
+ RECT 3.880000 2.840000 4.050000 3.455000 ;
+ RECT 3.930000 0.825000 4.200000 1.325000 ;
+ RECT 3.930000 1.325000 4.100000 2.320000 ;
+ RECT 4.230000 2.670000 4.450000 3.000000 ;
+ RECT 4.280000 1.920000 5.305000 2.150000 ;
+ RECT 4.280000 2.150000 4.450000 2.670000 ;
+ RECT 4.580000 3.200000 4.910000 3.455000 ;
+ RECT 4.630000 2.330000 5.660000 2.500000 ;
+ RECT 4.630000 2.500000 4.800000 3.200000 ;
+ RECT 4.650000 0.825000 4.980000 1.075000 ;
+ RECT 4.650000 1.075000 5.660000 1.245000 ;
+ RECT 4.975000 1.425000 5.305000 1.920000 ;
+ RECT 4.980000 2.680000 5.310000 2.875000 ;
+ RECT 4.980000 2.875000 6.750000 3.000000 ;
+ RECT 5.100000 3.000000 6.750000 3.045000 ;
+ RECT 5.100000 3.045000 5.270000 3.635000 ;
+ RECT 5.450000 3.225000 6.400000 3.705000 ;
+ RECT 5.490000 1.245000 5.660000 1.475000 ;
+ RECT 5.490000 1.475000 8.110000 1.645000 ;
+ RECT 5.490000 1.645000 5.660000 2.330000 ;
+ RECT 5.490000 2.500000 5.660000 2.525000 ;
+ RECT 5.490000 2.525000 7.260000 2.695000 ;
+ RECT 5.840000 1.825000 6.170000 2.175000 ;
+ RECT 5.840000 2.175000 8.900000 2.345000 ;
+ RECT 6.580000 3.045000 6.750000 3.635000 ;
+ RECT 6.580000 3.635000 7.610000 3.805000 ;
+ RECT 6.930000 2.695000 7.260000 3.455000 ;
+ RECT 7.160000 0.365000 8.110000 0.945000 ;
+ RECT 7.440000 3.105000 9.250000 3.275000 ;
+ RECT 7.440000 3.275000 7.610000 3.635000 ;
+ RECT 7.790000 3.455000 8.740000 3.755000 ;
+ RECT 8.570000 2.345000 8.900000 2.925000 ;
+ RECT 8.640000 0.615000 8.970000 1.325000 ;
+ RECT 8.640000 1.325000 8.900000 2.175000 ;
+ RECT 9.080000 1.585000 10.250000 1.755000 ;
+ RECT 9.080000 1.755000 9.250000 3.105000 ;
+ RECT 9.430000 0.615000 10.600000 0.785000 ;
+ RECT 9.430000 0.785000 9.760000 1.325000 ;
+ RECT 9.430000 2.675000 10.305000 2.845000 ;
+ RECT 9.430000 2.845000 9.680000 3.755000 ;
+ RECT 9.625000 1.935000 9.955000 2.435000 ;
+ RECT 9.965000 1.085000 10.250000 1.585000 ;
+ RECT 10.135000 2.185000 12.495000 2.355000 ;
+ RECT 10.135000 2.355000 10.305000 2.675000 ;
+ RECT 10.430000 0.785000 10.600000 2.185000 ;
+ RECT 10.485000 2.675000 11.435000 3.705000 ;
+ RECT 10.805000 1.445000 11.135000 1.835000 ;
+ RECT 10.805000 1.835000 12.845000 2.005000 ;
+ RECT 11.130000 0.365000 12.080000 0.915000 ;
+ RECT 11.840000 2.535000 12.845000 2.705000 ;
+ RECT 11.840000 2.705000 12.090000 3.175000 ;
+ RECT 12.270000 2.885000 13.165000 3.705000 ;
+ RECT 12.620000 0.495000 12.950000 0.995000 ;
+ RECT 12.620000 0.995000 12.845000 1.835000 ;
+ RECT 12.675000 2.005000 12.845000 2.535000 ;
+ RECT 13.225000 0.995000 13.555000 1.495000 ;
+ RECT 13.345000 1.495000 13.555000 1.675000 ;
+ RECT 13.345000 1.675000 14.720000 2.005000 ;
+ RECT 13.345000 2.005000 13.595000 3.005000 ;
+ RECT 13.735000 0.365000 14.685000 1.495000 ;
+ RECT 13.775000 2.195000 14.720000 3.735000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.590000 0.395000 0.760000 0.565000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.660000 3.505000 0.830000 3.675000 ;
+ RECT 0.950000 0.395000 1.120000 0.565000 ;
+ RECT 1.020000 3.505000 1.190000 3.675000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.310000 0.395000 1.480000 0.565000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 1.950000 2.245000 2.120000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.230000 0.395000 2.400000 0.565000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.590000 0.395000 2.760000 0.565000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.050000 3.505000 3.220000 3.675000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 1.950000 4.645000 2.120000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 3.985000 5.605000 4.155000 ;
+ RECT 5.480000 3.505000 5.650000 3.675000 ;
+ RECT 5.840000 3.505000 6.010000 3.675000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 3.985000 6.085000 4.155000 ;
+ RECT 6.200000 3.505000 6.370000 3.675000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 3.985000 6.565000 4.155000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 3.985000 7.045000 4.155000 ;
+ RECT 7.190000 0.395000 7.360000 0.565000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 3.985000 7.525000 4.155000 ;
+ RECT 7.550000 0.395000 7.720000 0.565000 ;
+ RECT 7.820000 3.505000 7.990000 3.675000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 3.985000 8.005000 4.155000 ;
+ RECT 7.910000 0.395000 8.080000 0.565000 ;
+ RECT 8.180000 3.505000 8.350000 3.675000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 3.985000 8.485000 4.155000 ;
+ RECT 8.540000 3.505000 8.710000 3.675000 ;
+ RECT 8.795000 -0.085000 8.965000 0.085000 ;
+ RECT 8.795000 3.985000 8.965000 4.155000 ;
+ RECT 9.275000 -0.085000 9.445000 0.085000 ;
+ RECT 9.275000 3.985000 9.445000 4.155000 ;
+ RECT 9.755000 -0.085000 9.925000 0.085000 ;
+ RECT 9.755000 1.950000 9.925000 2.120000 ;
+ RECT 9.755000 3.985000 9.925000 4.155000 ;
+ RECT 10.235000 -0.085000 10.405000 0.085000 ;
+ RECT 10.235000 3.985000 10.405000 4.155000 ;
+ RECT 10.515000 3.505000 10.685000 3.675000 ;
+ RECT 10.715000 -0.085000 10.885000 0.085000 ;
+ RECT 10.715000 3.985000 10.885000 4.155000 ;
+ RECT 10.875000 3.505000 11.045000 3.675000 ;
+ RECT 11.160000 0.395000 11.330000 0.565000 ;
+ RECT 11.195000 -0.085000 11.365000 0.085000 ;
+ RECT 11.195000 3.985000 11.365000 4.155000 ;
+ RECT 11.235000 3.505000 11.405000 3.675000 ;
+ RECT 11.520000 0.395000 11.690000 0.565000 ;
+ RECT 11.675000 -0.085000 11.845000 0.085000 ;
+ RECT 11.675000 3.985000 11.845000 4.155000 ;
+ RECT 11.880000 0.395000 12.050000 0.565000 ;
+ RECT 12.155000 -0.085000 12.325000 0.085000 ;
+ RECT 12.155000 3.985000 12.325000 4.155000 ;
+ RECT 12.270000 3.505000 12.440000 3.675000 ;
+ RECT 12.630000 3.505000 12.800000 3.675000 ;
+ RECT 12.635000 -0.085000 12.805000 0.085000 ;
+ RECT 12.635000 3.985000 12.805000 4.155000 ;
+ RECT 12.990000 3.505000 13.160000 3.675000 ;
+ RECT 13.115000 -0.085000 13.285000 0.085000 ;
+ RECT 13.115000 3.985000 13.285000 4.155000 ;
+ RECT 13.595000 -0.085000 13.765000 0.085000 ;
+ RECT 13.595000 3.985000 13.765000 4.155000 ;
+ RECT 13.765000 0.395000 13.935000 0.565000 ;
+ RECT 13.800000 3.505000 13.970000 3.675000 ;
+ RECT 14.075000 -0.085000 14.245000 0.085000 ;
+ RECT 14.075000 3.985000 14.245000 4.155000 ;
+ RECT 14.125000 0.395000 14.295000 0.565000 ;
+ RECT 14.160000 3.505000 14.330000 3.675000 ;
+ RECT 14.485000 0.395000 14.655000 0.565000 ;
+ RECT 14.520000 3.505000 14.690000 3.675000 ;
+ RECT 14.555000 -0.085000 14.725000 0.085000 ;
+ RECT 14.555000 3.985000 14.725000 4.155000 ;
+ RECT 15.035000 -0.085000 15.205000 0.085000 ;
+ RECT 15.035000 3.985000 15.205000 4.155000 ;
+ LAYER met1 ;
+ RECT 2.015000 1.920000 2.305000 1.965000 ;
+ RECT 2.015000 1.965000 9.985000 2.105000 ;
+ RECT 2.015000 2.105000 2.305000 2.150000 ;
+ RECT 4.415000 1.920000 4.705000 1.965000 ;
+ RECT 4.415000 2.105000 4.705000 2.150000 ;
+ RECT 9.695000 1.920000 9.985000 1.965000 ;
+ RECT 9.695000 2.105000 9.985000 2.150000 ;
+ END
+END sky130_fd_sc_hvl__dfrtp_1
+MACRO sky130_fd_sc_hvl__diode_2
+ CLASS CORE ANTENNACELL ;
+ FOREIGN sky130_fd_sc_hvl__diode_2 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 0.960000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN DIODE
+ ANTENNADIFFAREA 0.607200 ;
+ ANTENNAGATEAREA 0.607200 ;
+ DIRECTION INPUT ;
+ PORT
+ LAYER li1 ;
+ RECT 0.105000 0.515000 0.855000 3.280000 ;
+ END
+ END DIODE
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 0.960000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 0.960000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 0.960000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 0.960000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 0.960000 0.085000 ;
+ RECT 0.000000 3.985000 0.960000 4.155000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__diode_2
+MACRO sky130_fd_sc_hvl__lsbufhv2lv_simple_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__lsbufhv2lv_simple_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 8.640000 BY 8.140000 ;
+ SYMMETRY X Y ;
+ SITE unithvdbl ;
+ PIN A
+ ANTENNAGATEAREA 0.585000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 4.355000 1.465000 4.685000 3.260000 ;
+ END
+ END A
+ PIN X
+ ANTENNADIFFAREA 0.626250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.995000 0.495000 3.255000 2.175000 ;
+ RECT 2.995000 2.175000 3.440000 3.755000 ;
+ END
+ END X
+ PIN LVPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.070000 3.020000 8.570000 3.305000 ;
+ END
+ END LVPWR
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 7.515000 8.640000 7.885000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 8.025000 8.640000 8.255000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 8.640000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 4.325000 8.640000 4.695000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 8.640000 0.085000 ;
+ RECT 0.000000 3.985000 0.800000 4.155000 ;
+ RECT 0.000000 8.055000 8.640000 8.225000 ;
+ RECT 3.130000 3.955000 5.095000 4.525000 ;
+ RECT 3.435000 0.365000 4.685000 0.935000 ;
+ RECT 3.565000 1.115000 5.115000 1.285000 ;
+ RECT 3.565000 1.285000 3.895000 1.745000 ;
+ RECT 3.620000 2.175000 4.175000 3.955000 ;
+ RECT 4.865000 0.495000 5.115000 1.115000 ;
+ RECT 4.865000 1.285000 5.115000 3.005000 ;
+ RECT 7.425000 3.985000 8.640000 4.155000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.155000 8.055000 0.325000 8.225000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 8.055000 0.805000 8.225000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 8.055000 1.285000 8.225000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 8.055000 1.765000 8.225000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 8.055000 2.245000 8.225000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 8.055000 2.725000 8.225000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 8.055000 3.205000 8.225000 ;
+ RECT 3.435000 0.395000 3.605000 0.565000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 8.055000 3.685000 8.225000 ;
+ RECT 3.630000 3.075000 3.800000 3.245000 ;
+ RECT 3.795000 0.395000 3.965000 0.565000 ;
+ RECT 3.990000 3.075000 4.160000 3.245000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 8.055000 4.165000 8.225000 ;
+ RECT 4.155000 0.395000 4.325000 0.565000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 8.055000 4.645000 8.225000 ;
+ RECT 4.515000 0.395000 4.685000 0.565000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 8.055000 5.125000 8.225000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 8.055000 5.605000 8.225000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 8.055000 6.085000 8.225000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 8.055000 6.565000 8.225000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 8.055000 7.045000 8.225000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 8.055000 7.525000 8.225000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 3.985000 8.005000 4.155000 ;
+ RECT 7.835000 8.055000 8.005000 8.225000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 3.985000 8.485000 4.155000 ;
+ RECT 8.315000 8.055000 8.485000 8.225000 ;
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 8.640000 0.115000 ;
+ RECT 0.000000 0.255000 8.640000 0.625000 ;
+ RECT 0.000000 3.445000 8.640000 3.815000 ;
+ END
+END sky130_fd_sc_hvl__lsbufhv2lv_simple_1
+MACRO sky130_fd_sc_hvl__nor2_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__nor2_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 2.400000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN A
+ ANTENNAGATEAREA 1.125000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.125000 1.775000 1.315000 2.120000 ;
+ END
+ END A
+ PIN B
+ ANTENNAGATEAREA 1.125000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.495000 1.775000 1.825000 2.120000 ;
+ END
+ END B
+ PIN Y
+ ANTENNADIFFAREA 0.637500 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.200000 0.495000 1.530000 1.425000 ;
+ RECT 1.200000 1.425000 2.275000 1.595000 ;
+ RECT 2.020000 1.595000 2.275000 3.755000 ;
+ END
+ END Y
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 2.400000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 2.400000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 2.400000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 2.400000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 2.400000 0.085000 ;
+ RECT 0.000000 3.985000 2.400000 4.155000 ;
+ RECT 0.090000 0.365000 1.020000 1.325000 ;
+ RECT 0.090000 2.300000 1.760000 3.755000 ;
+ RECT 1.720000 0.365000 2.310000 1.245000 ;
+ LAYER mcon ;
+ RECT 0.110000 0.395000 0.280000 0.565000 ;
+ RECT 0.120000 3.505000 0.290000 3.675000 ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.470000 0.395000 0.640000 0.565000 ;
+ RECT 0.480000 3.505000 0.650000 3.675000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.830000 0.395000 1.000000 0.565000 ;
+ RECT 0.840000 3.505000 1.010000 3.675000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.200000 3.505000 1.370000 3.675000 ;
+ RECT 1.560000 3.505000 1.730000 3.675000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 1.750000 0.395000 1.920000 0.565000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.110000 0.395000 2.280000 0.565000 ;
+ END
+END sky130_fd_sc_hvl__nor2_1
+MACRO sky130_fd_sc_hvl__conb_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__conb_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 2.400000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN HI
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.290000 0.430000 0.865000 1.070000 ;
+ RECT 0.615000 1.070000 0.865000 1.935000 ;
+ RECT 0.615000 1.935000 1.325000 2.185000 ;
+ RECT 1.075000 2.185000 1.325000 3.530000 ;
+ END
+ END HI
+ PIN LO
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.035000 0.500000 1.365000 1.500000 ;
+ RECT 1.035000 1.500000 1.795000 1.765000 ;
+ RECT 1.530000 1.765000 1.795000 3.175000 ;
+ RECT 1.530000 3.175000 2.110000 3.815000 ;
+ END
+ END LO
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 2.400000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 2.400000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 2.400000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 2.400000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 2.400000 0.085000 ;
+ RECT 0.000000 3.985000 2.400000 4.155000 ;
+ RECT 0.215000 3.175000 0.620000 3.445000 ;
+ RECT 0.215000 3.445000 0.865000 3.785000 ;
+ RECT 1.535000 0.285000 2.185000 0.625000 ;
+ RECT 1.780000 0.625000 2.185000 1.070000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.275000 3.505000 0.445000 3.675000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.505000 0.805000 3.675000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 0.395000 1.765000 0.565000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 1.955000 0.395000 2.125000 0.565000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__conb_1
+MACRO sky130_fd_sc_hvl__dfxtp_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__dfxtp_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 12.00000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN D
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.595000 1.555000 2.470000 1.750000 ;
+ END
+ END D
+ PIN Q
+ ANTENNADIFFAREA 0.596250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 11.560000 2.185000 11.890000 3.735000 ;
+ RECT 11.640000 0.685000 11.890000 2.185000 ;
+ END
+ END Q
+ PIN CLK
+ ANTENNAGATEAREA 0.585000 ;
+ DIRECTION INPUT ;
+ USE CLOCK ;
+ PORT
+ LAYER li1 ;
+ RECT 0.540000 1.905000 0.870000 2.575000 ;
+ END
+ END CLK
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 12.000000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 12.000000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 12.000000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 12.000000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 12.000000 0.085000 ;
+ RECT 0.000000 3.985000 12.000000 4.155000 ;
+ RECT 0.110000 0.595000 0.380000 1.555000 ;
+ RECT 0.110000 1.555000 1.415000 1.725000 ;
+ RECT 0.110000 1.725000 0.360000 3.565000 ;
+ RECT 0.540000 2.755000 1.490000 3.705000 ;
+ RECT 0.560000 0.365000 1.510000 1.095000 ;
+ RECT 1.165000 1.725000 1.415000 1.930000 ;
+ RECT 1.165000 1.930000 2.820000 2.225000 ;
+ RECT 1.670000 2.445000 2.820000 2.615000 ;
+ RECT 1.670000 2.615000 2.000000 3.565000 ;
+ RECT 1.690000 0.595000 2.020000 1.205000 ;
+ RECT 1.690000 1.205000 3.115000 1.375000 ;
+ RECT 2.200000 0.365000 2.765000 1.025000 ;
+ RECT 2.220000 2.795000 2.470000 3.705000 ;
+ RECT 2.650000 1.760000 3.685000 1.930000 ;
+ RECT 2.650000 2.615000 2.820000 3.305000 ;
+ RECT 2.650000 3.305000 3.680000 3.475000 ;
+ RECT 2.945000 0.265000 5.055000 0.435000 ;
+ RECT 2.945000 0.435000 3.115000 1.205000 ;
+ RECT 3.000000 2.110000 4.035000 2.280000 ;
+ RECT 3.000000 2.280000 3.330000 3.125000 ;
+ RECT 3.295000 0.615000 4.035000 1.025000 ;
+ RECT 3.430000 1.205000 3.685000 1.760000 ;
+ RECT 3.510000 2.460000 3.840000 3.135000 ;
+ RECT 3.510000 3.135000 7.655000 3.305000 ;
+ RECT 3.865000 1.025000 4.035000 2.110000 ;
+ RECT 4.055000 2.675000 4.385000 2.955000 ;
+ RECT 4.215000 0.615000 4.545000 1.525000 ;
+ RECT 4.215000 1.525000 6.345000 1.695000 ;
+ RECT 4.215000 1.695000 4.385000 2.675000 ;
+ RECT 4.565000 1.885000 4.890000 2.385000 ;
+ RECT 4.565000 2.385000 6.955000 2.555000 ;
+ RECT 4.725000 0.435000 5.055000 1.175000 ;
+ RECT 4.725000 1.175000 6.555000 1.345000 ;
+ RECT 5.070000 3.485000 6.020000 3.735000 ;
+ RECT 5.255000 0.365000 6.205000 0.995000 ;
+ RECT 5.435000 1.875000 7.305000 2.045000 ;
+ RECT 5.435000 2.045000 5.765000 2.205000 ;
+ RECT 6.385000 0.265000 7.450000 0.435000 ;
+ RECT 6.385000 0.435000 6.555000 1.175000 ;
+ RECT 6.470000 2.755000 7.305000 2.955000 ;
+ RECT 6.705000 2.225000 6.955000 2.385000 ;
+ RECT 6.735000 0.615000 7.065000 1.875000 ;
+ RECT 7.135000 2.045000 7.305000 2.755000 ;
+ RECT 7.280000 0.435000 7.450000 1.125000 ;
+ RECT 7.280000 1.125000 7.655000 1.445000 ;
+ RECT 7.485000 1.445000 7.655000 2.225000 ;
+ RECT 7.485000 2.225000 8.250000 2.515000 ;
+ RECT 7.485000 2.515000 7.655000 3.135000 ;
+ RECT 7.630000 0.525000 8.005000 0.855000 ;
+ RECT 7.630000 0.855000 8.600000 0.945000 ;
+ RECT 7.835000 0.945000 8.600000 1.025000 ;
+ RECT 7.835000 2.695000 8.600000 2.865000 ;
+ RECT 7.835000 2.865000 8.085000 3.735000 ;
+ RECT 8.430000 1.025000 8.600000 2.275000 ;
+ RECT 8.430000 2.275000 10.035000 2.445000 ;
+ RECT 8.430000 2.445000 8.600000 2.695000 ;
+ RECT 8.780000 0.365000 9.730000 1.245000 ;
+ RECT 8.815000 2.695000 9.765000 3.735000 ;
+ RECT 9.000000 1.425000 10.510000 1.595000 ;
+ RECT 9.000000 1.595000 9.330000 2.015000 ;
+ RECT 9.705000 1.775000 10.035000 2.275000 ;
+ RECT 10.180000 0.525000 10.510000 1.425000 ;
+ RECT 10.215000 1.595000 10.510000 1.675000 ;
+ RECT 10.215000 1.675000 11.460000 2.005000 ;
+ RECT 10.215000 2.005000 10.545000 3.735000 ;
+ RECT 10.690000 0.365000 11.280000 1.495000 ;
+ RECT 10.725000 2.195000 11.315000 3.735000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.570000 3.505000 0.740000 3.675000 ;
+ RECT 0.590000 0.395000 0.760000 0.565000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.930000 3.505000 1.100000 3.675000 ;
+ RECT 0.950000 0.395000 1.120000 0.565000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.290000 3.505000 1.460000 3.675000 ;
+ RECT 1.310000 0.395000 1.480000 0.565000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.215000 0.395000 2.385000 0.565000 ;
+ RECT 2.250000 3.505000 2.420000 3.675000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.575000 0.395000 2.745000 0.565000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ RECT 5.100000 3.515000 5.270000 3.685000 ;
+ RECT 5.285000 0.395000 5.455000 0.565000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 3.985000 5.605000 4.155000 ;
+ RECT 5.460000 3.515000 5.630000 3.685000 ;
+ RECT 5.645000 0.395000 5.815000 0.565000 ;
+ RECT 5.820000 3.515000 5.990000 3.685000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 3.985000 6.085000 4.155000 ;
+ RECT 6.005000 0.395000 6.175000 0.565000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 3.985000 6.565000 4.155000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 3.985000 7.045000 4.155000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 3.985000 7.525000 4.155000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 3.985000 8.005000 4.155000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 3.985000 8.485000 4.155000 ;
+ RECT 8.795000 -0.085000 8.965000 0.085000 ;
+ RECT 8.795000 3.985000 8.965000 4.155000 ;
+ RECT 8.810000 0.395000 8.980000 0.565000 ;
+ RECT 8.845000 3.505000 9.015000 3.675000 ;
+ RECT 9.170000 0.395000 9.340000 0.565000 ;
+ RECT 9.205000 3.505000 9.375000 3.675000 ;
+ RECT 9.275000 -0.085000 9.445000 0.085000 ;
+ RECT 9.275000 3.985000 9.445000 4.155000 ;
+ RECT 9.530000 0.395000 9.700000 0.565000 ;
+ RECT 9.565000 3.505000 9.735000 3.675000 ;
+ RECT 9.755000 -0.085000 9.925000 0.085000 ;
+ RECT 9.755000 3.985000 9.925000 4.155000 ;
+ RECT 10.235000 -0.085000 10.405000 0.085000 ;
+ RECT 10.235000 3.985000 10.405000 4.155000 ;
+ RECT 10.715000 -0.085000 10.885000 0.085000 ;
+ RECT 10.715000 3.985000 10.885000 4.155000 ;
+ RECT 10.720000 0.395000 10.890000 0.565000 ;
+ RECT 10.755000 3.505000 10.925000 3.675000 ;
+ RECT 11.080000 0.395000 11.250000 0.565000 ;
+ RECT 11.115000 3.505000 11.285000 3.675000 ;
+ RECT 11.195000 -0.085000 11.365000 0.085000 ;
+ RECT 11.195000 3.985000 11.365000 4.155000 ;
+ RECT 11.675000 -0.085000 11.845000 0.085000 ;
+ RECT 11.675000 3.985000 11.845000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__dfxtp_1
+MACRO sky130_fd_sc_hvl__decap_4
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__decap_4 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 1.920000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 1.920000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 1.920000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 1.920000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 1.920000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 1.920000 0.085000 ;
+ RECT 0.000000 3.985000 1.920000 4.155000 ;
+ RECT 0.170000 0.365000 1.780000 0.845000 ;
+ RECT 0.250000 2.685000 1.700000 3.755000 ;
+ RECT 0.475000 0.845000 1.780000 1.250000 ;
+ RECT 0.475000 1.250000 0.805000 2.030000 ;
+ RECT 1.015000 1.700000 1.345000 2.685000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.215000 0.395000 0.385000 0.565000 ;
+ RECT 0.495000 3.560000 0.665000 3.730000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.655000 0.395000 0.825000 0.565000 ;
+ RECT 0.860000 3.560000 1.030000 3.730000 ;
+ RECT 1.095000 0.395000 1.265000 0.565000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.300000 3.560000 1.470000 3.730000 ;
+ RECT 1.510000 0.395000 1.680000 0.565000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__decap_4
+MACRO sky130_fd_sc_hvl__decap_8
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__decap_8 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 3.840000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 3.840000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 3.840000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 3.840000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 3.840000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 3.840000 0.085000 ;
+ RECT 0.000000 3.985000 3.840000 4.155000 ;
+ RECT 0.500000 2.680000 3.240000 3.750000 ;
+ RECT 0.575000 0.360000 3.305000 1.360000 ;
+ RECT 0.735000 1.360000 1.065000 2.025000 ;
+ RECT 1.470000 1.695000 1.800000 2.680000 ;
+ RECT 2.015000 1.360000 2.345000 2.025000 ;
+ RECT 2.750000 1.695000 3.080000 2.680000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.705000 3.555000 0.875000 3.725000 ;
+ RECT 0.745000 0.390000 0.915000 0.560000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.145000 3.555000 1.315000 3.725000 ;
+ RECT 1.185000 0.390000 1.355000 0.560000 ;
+ RECT 1.560000 3.555000 1.730000 3.725000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 1.600000 0.390000 1.770000 0.560000 ;
+ RECT 1.985000 3.555000 2.155000 3.725000 ;
+ RECT 2.025000 0.390000 2.195000 0.560000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.425000 3.555000 2.595000 3.725000 ;
+ RECT 2.465000 0.390000 2.635000 0.560000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.840000 3.555000 3.010000 3.725000 ;
+ RECT 2.880000 0.390000 3.050000 0.560000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__decap_8
+MACRO sky130_fd_sc_hvl__o22a_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__o22a_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 5.280000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN A1
+ ANTENNAGATEAREA 1.125000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.420000 1.775000 2.150000 2.055000 ;
+ RECT 1.980000 1.400000 2.775000 1.570000 ;
+ RECT 1.980000 1.570000 2.150000 1.775000 ;
+ RECT 2.605000 1.230000 4.880000 1.400000 ;
+ RECT 3.035000 1.210000 3.710000 1.230000 ;
+ RECT 4.550000 1.400000 4.880000 2.015000 ;
+ END
+ END A1
+ PIN A2
+ ANTENNAGATEAREA 1.125000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 3.485000 1.580000 4.195000 1.910000 ;
+ END
+ END A2
+ PIN B1
+ ANTENNAGATEAREA 1.125000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.330000 1.750000 2.755000 2.120000 ;
+ END
+ END B1
+ PIN B2
+ ANTENNAGATEAREA 1.125000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.955000 1.580000 3.250000 2.120000 ;
+ END
+ END B2
+ PIN X
+ ANTENNADIFFAREA 0.641250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.125000 0.495000 0.380000 3.755000 ;
+ END
+ END X
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 5.280000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 5.280000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 5.280000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 5.280000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 5.280000 0.085000 ;
+ RECT 0.000000 3.985000 5.280000 4.155000 ;
+ RECT 0.560000 0.365000 1.450000 1.245000 ;
+ RECT 0.560000 2.650000 3.250000 3.755000 ;
+ RECT 0.585000 1.425000 1.800000 1.595000 ;
+ RECT 0.585000 1.595000 0.915000 2.300000 ;
+ RECT 0.585000 2.300000 3.680000 2.470000 ;
+ RECT 1.630000 1.050000 2.425000 1.220000 ;
+ RECT 1.630000 1.220000 1.800000 1.425000 ;
+ RECT 1.745000 0.265000 3.680000 0.435000 ;
+ RECT 1.745000 0.435000 2.075000 0.870000 ;
+ RECT 2.255000 0.880000 2.855000 1.050000 ;
+ RECT 2.525000 0.615000 2.855000 0.880000 ;
+ RECT 3.350000 0.435000 3.680000 1.030000 ;
+ RECT 3.430000 2.175000 3.680000 2.300000 ;
+ RECT 3.430000 2.470000 3.680000 3.755000 ;
+ RECT 3.860000 2.195000 5.170000 3.735000 ;
+ RECT 3.890000 0.365000 5.190000 1.050000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.560000 0.395000 0.730000 0.565000 ;
+ RECT 0.560000 3.505000 0.730000 3.675000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.920000 0.395000 1.090000 0.565000 ;
+ RECT 0.920000 3.505000 1.090000 3.675000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.280000 0.395000 1.450000 0.565000 ;
+ RECT 1.280000 3.505000 1.450000 3.675000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 1.640000 3.505000 1.810000 3.675000 ;
+ RECT 2.000000 3.505000 2.170000 3.675000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.360000 3.505000 2.530000 3.675000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.720000 3.505000 2.890000 3.675000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.080000 3.505000 3.250000 3.675000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.890000 3.505000 4.060000 3.675000 ;
+ RECT 3.915000 0.395000 4.085000 0.565000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.250000 3.505000 4.420000 3.675000 ;
+ RECT 4.275000 0.395000 4.445000 0.565000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.610000 3.505000 4.780000 3.675000 ;
+ RECT 4.635000 0.395000 4.805000 0.565000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ RECT 4.970000 3.505000 5.140000 3.675000 ;
+ RECT 4.995000 0.395000 5.165000 0.565000 ;
+ END
+END sky130_fd_sc_hvl__o22a_1
+MACRO sky130_fd_sc_hvl__sdfsbp_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__sdfsbp_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 20.16000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN D
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.975000 1.845000 2.305000 2.355000 ;
+ END
+ END D
+ PIN Q
+ ANTENNADIFFAREA 0.498750 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 19.700000 0.495000 20.035000 1.325000 ;
+ RECT 19.700000 2.355000 20.035000 3.435000 ;
+ RECT 19.805000 1.325000 20.035000 2.355000 ;
+ END
+ END Q
+ PIN Q_N
+ ANTENNADIFFAREA 0.611250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 17.405000 0.495000 17.785000 3.735000 ;
+ END
+ END Q_N
+ PIN SCD
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 3.485000 0.810000 3.690000 2.150000 ;
+ END
+ END SCD
+ PIN SCE
+ ANTENNAGATEAREA 0.840000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.605000 1.495000 2.955000 1.665000 ;
+ RECT 0.605000 1.665000 1.795000 2.165000 ;
+ RECT 2.680000 1.095000 2.955000 1.495000 ;
+ RECT 2.680000 1.665000 2.955000 1.765000 ;
+ END
+ END SCE
+ PIN SET_B
+ ANTENNAGATEAREA 0.840000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 10.205000 1.210000 12.355000 1.380000 ;
+ RECT 12.185000 0.265000 14.170000 0.435000 ;
+ RECT 12.185000 0.435000 12.355000 1.210000 ;
+ RECT 14.000000 0.435000 14.170000 1.425000 ;
+ RECT 14.000000 1.425000 14.845000 1.645000 ;
+ END
+ END SET_B
+ PIN CLK
+ ANTENNAGATEAREA 0.585000 ;
+ DIRECTION INPUT ;
+ USE CLOCK ;
+ PORT
+ LAYER li1 ;
+ RECT 4.380000 1.180000 4.710000 2.150000 ;
+ END
+ END CLK
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 20.160000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 20.160000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 20.160000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 20.160000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 20.160000 0.085000 ;
+ RECT 0.000000 3.985000 20.160000 4.155000 ;
+ RECT 0.130000 0.495000 0.485000 1.095000 ;
+ RECT 0.130000 1.095000 2.300000 1.315000 ;
+ RECT 0.130000 1.315000 0.300000 2.535000 ;
+ RECT 0.130000 2.535000 2.885000 2.705000 ;
+ RECT 0.130000 2.705000 0.460000 3.305000 ;
+ RECT 0.640000 2.885000 1.590000 3.705000 ;
+ RECT 0.665000 0.365000 1.615000 0.915000 ;
+ RECT 2.400000 2.885000 3.235000 3.055000 ;
+ RECT 2.400000 3.055000 2.730000 3.305000 ;
+ RECT 2.425000 0.495000 2.755000 0.745000 ;
+ RECT 2.425000 0.745000 3.305000 0.915000 ;
+ RECT 2.635000 2.015000 2.885000 2.535000 ;
+ RECT 3.065000 2.455000 4.655000 2.625000 ;
+ RECT 3.065000 2.625000 3.235000 2.885000 ;
+ RECT 3.135000 0.915000 3.305000 2.455000 ;
+ RECT 3.415000 2.805000 4.305000 3.705000 ;
+ RECT 3.870000 0.365000 4.760000 0.995000 ;
+ RECT 4.485000 2.625000 4.655000 3.635000 ;
+ RECT 4.485000 3.635000 5.515000 3.805000 ;
+ RECT 4.835000 2.805000 5.165000 3.455000 ;
+ RECT 4.940000 0.515000 5.190000 1.700000 ;
+ RECT 4.940000 1.700000 6.065000 1.870000 ;
+ RECT 4.940000 1.870000 5.165000 2.805000 ;
+ RECT 5.345000 2.050000 6.215000 2.220000 ;
+ RECT 5.345000 2.220000 5.515000 3.635000 ;
+ RECT 5.370000 0.365000 5.960000 1.020000 ;
+ RECT 5.695000 2.400000 5.865000 3.705000 ;
+ RECT 5.735000 1.200000 6.065000 1.700000 ;
+ RECT 6.045000 2.220000 6.215000 3.390000 ;
+ RECT 6.045000 3.390000 7.295000 3.560000 ;
+ RECT 6.190000 0.265000 8.220000 0.435000 ;
+ RECT 6.190000 0.435000 6.565000 1.020000 ;
+ RECT 6.395000 1.020000 6.565000 2.290000 ;
+ RECT 6.395000 2.290000 6.645000 3.210000 ;
+ RECT 6.760000 0.615000 7.010000 1.060000 ;
+ RECT 6.840000 1.060000 7.010000 2.740000 ;
+ RECT 6.840000 2.740000 7.295000 3.390000 ;
+ RECT 7.190000 0.435000 7.360000 2.290000 ;
+ RECT 7.190000 2.290000 7.520000 2.560000 ;
+ RECT 7.540000 0.640000 7.870000 1.060000 ;
+ RECT 7.700000 1.060000 7.870000 1.910000 ;
+ RECT 7.700000 1.910000 11.645000 2.080000 ;
+ RECT 7.700000 2.080000 7.995000 3.240000 ;
+ RECT 8.050000 0.435000 8.220000 1.150000 ;
+ RECT 8.050000 1.150000 8.325000 1.560000 ;
+ RECT 8.050000 1.560000 12.530000 1.730000 ;
+ RECT 8.200000 2.290000 8.530000 2.610000 ;
+ RECT 8.200000 2.610000 9.915000 2.780000 ;
+ RECT 8.410000 0.365000 9.360000 0.960000 ;
+ RECT 8.615000 2.960000 9.565000 3.705000 ;
+ RECT 8.910000 1.140000 9.910000 1.380000 ;
+ RECT 8.910000 2.260000 10.425000 2.430000 ;
+ RECT 9.580000 0.515000 9.910000 1.140000 ;
+ RECT 9.745000 2.780000 9.915000 3.170000 ;
+ RECT 9.745000 3.170000 10.775000 3.340000 ;
+ RECT 10.095000 2.430000 10.425000 2.990000 ;
+ RECT 10.545000 0.365000 11.495000 1.030000 ;
+ RECT 10.605000 3.000000 12.335000 3.170000 ;
+ RECT 10.955000 3.350000 11.905000 3.755000 ;
+ RECT 11.315000 2.080000 11.645000 2.555000 ;
+ RECT 12.025000 2.125000 13.405000 2.295000 ;
+ RECT 12.025000 2.295000 12.335000 3.000000 ;
+ RECT 12.200000 1.730000 12.530000 1.875000 ;
+ RECT 12.515000 2.525000 15.300000 2.695000 ;
+ RECT 12.515000 2.695000 12.845000 3.755000 ;
+ RECT 12.655000 0.615000 13.755000 0.785000 ;
+ RECT 12.655000 0.785000 12.985000 1.325000 ;
+ RECT 13.165000 1.415000 13.405000 2.125000 ;
+ RECT 13.500000 2.875000 14.450000 3.705000 ;
+ RECT 13.585000 0.785000 13.755000 1.825000 ;
+ RECT 13.585000 1.825000 15.545000 1.995000 ;
+ RECT 13.585000 1.995000 13.755000 2.525000 ;
+ RECT 13.935000 2.175000 16.060000 2.345000 ;
+ RECT 14.350000 0.365000 15.300000 1.245000 ;
+ RECT 14.970000 2.695000 15.300000 3.175000 ;
+ RECT 15.215000 1.425000 15.545000 1.825000 ;
+ RECT 15.685000 2.345000 16.060000 2.675000 ;
+ RECT 15.730000 0.825000 16.060000 2.175000 ;
+ RECT 16.240000 0.365000 17.190000 1.325000 ;
+ RECT 16.240000 2.195000 17.190000 3.735000 ;
+ RECT 18.025000 0.825000 18.355000 1.505000 ;
+ RECT 18.025000 1.505000 19.575000 1.675000 ;
+ RECT 18.025000 1.675000 18.355000 3.185000 ;
+ RECT 18.535000 0.365000 19.485000 1.325000 ;
+ RECT 18.535000 2.355000 19.485000 3.705000 ;
+ RECT 19.245000 1.675000 19.575000 2.175000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.670000 3.505000 0.840000 3.675000 ;
+ RECT 0.695000 0.395000 0.865000 0.565000 ;
+ RECT 1.030000 3.505000 1.200000 3.675000 ;
+ RECT 1.055000 0.395000 1.225000 0.565000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.390000 3.505000 1.560000 3.675000 ;
+ RECT 1.415000 0.395000 1.585000 0.565000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.415000 3.505000 3.585000 3.675000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.775000 3.505000 3.945000 3.675000 ;
+ RECT 3.870000 0.395000 4.040000 0.565000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.135000 3.505000 4.305000 3.675000 ;
+ RECT 4.230000 0.395000 4.400000 0.565000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.590000 0.395000 4.760000 0.565000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ RECT 5.400000 0.395000 5.570000 0.565000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 3.985000 5.605000 4.155000 ;
+ RECT 5.695000 3.505000 5.865000 3.675000 ;
+ RECT 5.760000 0.395000 5.930000 0.565000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 3.985000 6.085000 4.155000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 3.985000 6.565000 4.155000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 3.985000 7.045000 4.155000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 3.985000 7.525000 4.155000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 3.985000 8.005000 4.155000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 3.985000 8.485000 4.155000 ;
+ RECT 8.440000 0.395000 8.610000 0.565000 ;
+ RECT 8.645000 3.505000 8.815000 3.675000 ;
+ RECT 8.795000 -0.085000 8.965000 0.085000 ;
+ RECT 8.795000 3.985000 8.965000 4.155000 ;
+ RECT 8.800000 0.395000 8.970000 0.565000 ;
+ RECT 9.005000 3.505000 9.175000 3.675000 ;
+ RECT 9.160000 0.395000 9.330000 0.565000 ;
+ RECT 9.275000 -0.085000 9.445000 0.085000 ;
+ RECT 9.275000 3.985000 9.445000 4.155000 ;
+ RECT 9.365000 3.505000 9.535000 3.675000 ;
+ RECT 9.755000 -0.085000 9.925000 0.085000 ;
+ RECT 9.755000 3.985000 9.925000 4.155000 ;
+ RECT 10.235000 -0.085000 10.405000 0.085000 ;
+ RECT 10.235000 3.985000 10.405000 4.155000 ;
+ RECT 10.575000 0.395000 10.745000 0.565000 ;
+ RECT 10.715000 -0.085000 10.885000 0.085000 ;
+ RECT 10.715000 3.985000 10.885000 4.155000 ;
+ RECT 10.935000 0.395000 11.105000 0.565000 ;
+ RECT 10.985000 3.505000 11.155000 3.675000 ;
+ RECT 11.195000 -0.085000 11.365000 0.085000 ;
+ RECT 11.195000 3.985000 11.365000 4.155000 ;
+ RECT 11.295000 0.395000 11.465000 0.565000 ;
+ RECT 11.345000 3.505000 11.515000 3.675000 ;
+ RECT 11.675000 -0.085000 11.845000 0.085000 ;
+ RECT 11.675000 3.985000 11.845000 4.155000 ;
+ RECT 11.705000 3.505000 11.875000 3.675000 ;
+ RECT 12.155000 -0.085000 12.325000 0.085000 ;
+ RECT 12.155000 3.985000 12.325000 4.155000 ;
+ RECT 12.635000 -0.085000 12.805000 0.085000 ;
+ RECT 12.635000 3.985000 12.805000 4.155000 ;
+ RECT 13.115000 -0.085000 13.285000 0.085000 ;
+ RECT 13.115000 3.985000 13.285000 4.155000 ;
+ RECT 13.530000 3.505000 13.700000 3.675000 ;
+ RECT 13.595000 -0.085000 13.765000 0.085000 ;
+ RECT 13.595000 3.985000 13.765000 4.155000 ;
+ RECT 13.890000 3.505000 14.060000 3.675000 ;
+ RECT 14.075000 -0.085000 14.245000 0.085000 ;
+ RECT 14.075000 3.985000 14.245000 4.155000 ;
+ RECT 14.250000 3.505000 14.420000 3.675000 ;
+ RECT 14.380000 0.395000 14.550000 0.565000 ;
+ RECT 14.555000 -0.085000 14.725000 0.085000 ;
+ RECT 14.555000 3.985000 14.725000 4.155000 ;
+ RECT 14.740000 0.395000 14.910000 0.565000 ;
+ RECT 15.035000 -0.085000 15.205000 0.085000 ;
+ RECT 15.035000 3.985000 15.205000 4.155000 ;
+ RECT 15.100000 0.395000 15.270000 0.565000 ;
+ RECT 15.515000 -0.085000 15.685000 0.085000 ;
+ RECT 15.515000 3.985000 15.685000 4.155000 ;
+ RECT 15.995000 -0.085000 16.165000 0.085000 ;
+ RECT 15.995000 3.985000 16.165000 4.155000 ;
+ RECT 16.270000 0.395000 16.440000 0.565000 ;
+ RECT 16.270000 3.505000 16.440000 3.675000 ;
+ RECT 16.475000 -0.085000 16.645000 0.085000 ;
+ RECT 16.475000 3.985000 16.645000 4.155000 ;
+ RECT 16.630000 0.395000 16.800000 0.565000 ;
+ RECT 16.630000 3.505000 16.800000 3.675000 ;
+ RECT 16.955000 -0.085000 17.125000 0.085000 ;
+ RECT 16.955000 3.985000 17.125000 4.155000 ;
+ RECT 16.990000 0.395000 17.160000 0.565000 ;
+ RECT 16.990000 3.505000 17.160000 3.675000 ;
+ RECT 17.435000 -0.085000 17.605000 0.085000 ;
+ RECT 17.435000 3.985000 17.605000 4.155000 ;
+ RECT 17.915000 -0.085000 18.085000 0.085000 ;
+ RECT 17.915000 3.985000 18.085000 4.155000 ;
+ RECT 18.395000 -0.085000 18.565000 0.085000 ;
+ RECT 18.395000 3.985000 18.565000 4.155000 ;
+ RECT 18.565000 0.395000 18.735000 0.565000 ;
+ RECT 18.565000 3.505000 18.735000 3.675000 ;
+ RECT 18.875000 -0.085000 19.045000 0.085000 ;
+ RECT 18.875000 3.985000 19.045000 4.155000 ;
+ RECT 18.925000 0.395000 19.095000 0.565000 ;
+ RECT 18.925000 3.505000 19.095000 3.675000 ;
+ RECT 19.285000 0.395000 19.455000 0.565000 ;
+ RECT 19.285000 3.505000 19.455000 3.675000 ;
+ RECT 19.355000 -0.085000 19.525000 0.085000 ;
+ RECT 19.355000 3.985000 19.525000 4.155000 ;
+ RECT 19.835000 -0.085000 20.005000 0.085000 ;
+ RECT 19.835000 3.985000 20.005000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__sdfsbp_1
+MACRO sky130_fd_sc_hvl__dfxbp_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__dfxbp_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 13.92000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN D
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.525000 1.545000 3.350000 2.125000 ;
+ END
+ END D
+ PIN Q
+ ANTENNADIFFAREA 0.596250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 10.455000 0.675000 10.890000 1.465000 ;
+ RECT 10.455000 2.195000 10.890000 3.735000 ;
+ RECT 10.685000 1.465000 10.890000 2.195000 ;
+ END
+ END Q
+ PIN Q_N
+ ANTENNADIFFAREA 0.626250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 13.460000 2.175000 13.810000 3.755000 ;
+ RECT 13.480000 0.675000 13.810000 2.175000 ;
+ END
+ END Q_N
+ PIN CLK
+ ANTENNAGATEAREA 0.585000 ;
+ DIRECTION INPUT ;
+ USE CLOCK ;
+ PORT
+ LAYER li1 ;
+ RECT 0.560000 1.550000 0.890000 2.220000 ;
+ END
+ END CLK
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 13.920000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 13.920000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 13.920000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 13.920000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 13.920000 0.085000 ;
+ RECT 0.000000 3.985000 13.920000 4.155000 ;
+ RECT 0.110000 0.540000 0.440000 1.200000 ;
+ RECT 0.110000 1.200000 1.545000 1.370000 ;
+ RECT 0.110000 1.370000 0.380000 3.230000 ;
+ RECT 0.570000 2.400000 1.160000 3.705000 ;
+ RECT 0.620000 0.365000 1.570000 1.020000 ;
+ RECT 1.215000 1.370000 1.545000 1.870000 ;
+ RECT 1.340000 1.870000 1.510000 3.410000 ;
+ RECT 1.340000 3.410000 2.290000 3.580000 ;
+ RECT 1.690000 2.400000 1.940000 3.230000 ;
+ RECT 1.750000 0.520000 1.920000 1.195000 ;
+ RECT 1.750000 1.195000 3.340000 1.365000 ;
+ RECT 1.750000 1.365000 1.940000 2.400000 ;
+ RECT 2.100000 0.365000 2.990000 1.015000 ;
+ RECT 2.120000 2.305000 3.350000 2.475000 ;
+ RECT 2.120000 2.475000 2.290000 3.410000 ;
+ RECT 2.470000 2.655000 3.000000 3.705000 ;
+ RECT 3.170000 0.265000 4.980000 0.435000 ;
+ RECT 3.170000 0.435000 3.340000 1.195000 ;
+ RECT 3.180000 2.475000 3.350000 3.335000 ;
+ RECT 3.180000 3.335000 5.085000 3.505000 ;
+ RECT 3.520000 0.615000 3.850000 0.935000 ;
+ RECT 3.530000 0.935000 3.700000 2.655000 ;
+ RECT 3.530000 2.655000 3.770000 3.155000 ;
+ RECT 3.880000 1.115000 4.120000 1.785000 ;
+ RECT 3.950000 1.785000 4.120000 3.335000 ;
+ RECT 4.300000 0.615000 4.630000 1.015000 ;
+ RECT 4.300000 1.015000 4.470000 1.905000 ;
+ RECT 4.300000 1.905000 6.540000 2.075000 ;
+ RECT 4.300000 2.075000 4.550000 3.155000 ;
+ RECT 4.650000 1.195000 4.980000 1.245000 ;
+ RECT 4.650000 1.245000 6.485000 1.415000 ;
+ RECT 4.650000 1.415000 4.980000 1.725000 ;
+ RECT 4.755000 2.255000 5.085000 2.635000 ;
+ RECT 4.755000 2.635000 6.565000 2.805000 ;
+ RECT 4.755000 2.805000 5.085000 3.335000 ;
+ RECT 4.810000 0.435000 4.980000 1.195000 ;
+ RECT 5.185000 0.365000 6.135000 1.065000 ;
+ RECT 5.265000 2.985000 6.215000 3.715000 ;
+ RECT 5.435000 2.255000 5.765000 2.285000 ;
+ RECT 5.435000 2.285000 6.915000 2.455000 ;
+ RECT 6.210000 1.595000 6.540000 1.905000 ;
+ RECT 6.210000 2.075000 6.540000 2.105000 ;
+ RECT 6.315000 0.265000 7.345000 0.435000 ;
+ RECT 6.315000 0.435000 6.485000 1.245000 ;
+ RECT 6.395000 2.805000 6.565000 3.635000 ;
+ RECT 6.395000 3.635000 8.245000 3.805000 ;
+ RECT 6.665000 0.615000 6.995000 1.325000 ;
+ RECT 6.745000 1.325000 6.915000 2.285000 ;
+ RECT 6.745000 2.455000 6.915000 3.455000 ;
+ RECT 7.095000 2.205000 7.425000 2.495000 ;
+ RECT 7.095000 2.495000 7.265000 3.635000 ;
+ RECT 7.175000 0.435000 7.345000 1.195000 ;
+ RECT 7.175000 1.195000 7.445000 1.865000 ;
+ RECT 7.445000 2.675000 7.795000 3.455000 ;
+ RECT 7.540000 0.515000 8.595000 0.685000 ;
+ RECT 7.540000 0.685000 7.795000 1.015000 ;
+ RECT 7.625000 1.015000 7.795000 2.675000 ;
+ RECT 7.975000 1.105000 8.245000 3.635000 ;
+ RECT 8.425000 0.685000 8.595000 2.325000 ;
+ RECT 8.425000 2.325000 9.725000 2.495000 ;
+ RECT 8.505000 2.675000 9.455000 3.715000 ;
+ RECT 8.775000 0.365000 9.725000 1.325000 ;
+ RECT 8.775000 1.505000 10.235000 1.645000 ;
+ RECT 8.775000 1.645000 10.505000 1.675000 ;
+ RECT 8.775000 1.675000 9.105000 2.145000 ;
+ RECT 9.395000 1.855000 9.725000 2.325000 ;
+ RECT 9.905000 0.535000 10.235000 1.505000 ;
+ RECT 9.905000 1.675000 10.505000 1.975000 ;
+ RECT 9.905000 1.975000 10.235000 3.715000 ;
+ RECT 11.070000 0.365000 11.625000 1.485000 ;
+ RECT 11.070000 2.195000 11.605000 3.735000 ;
+ RECT 11.785000 2.195000 12.115000 2.985000 ;
+ RECT 11.805000 1.005000 12.135000 1.665000 ;
+ RECT 11.805000 1.665000 13.300000 1.995000 ;
+ RECT 11.805000 1.995000 12.115000 2.195000 ;
+ RECT 12.295000 2.175000 13.245000 3.755000 ;
+ RECT 12.315000 0.365000 13.265000 1.485000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.600000 3.505000 0.770000 3.675000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.650000 0.395000 0.820000 0.565000 ;
+ RECT 0.960000 3.505000 1.130000 3.675000 ;
+ RECT 1.010000 0.395000 1.180000 0.565000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.370000 0.395000 1.540000 0.565000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.100000 0.395000 2.270000 0.565000 ;
+ RECT 2.460000 0.395000 2.630000 0.565000 ;
+ RECT 2.470000 3.505000 2.640000 3.675000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.820000 0.395000 2.990000 0.565000 ;
+ RECT 2.830000 3.505000 3.000000 3.675000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ RECT 5.215000 0.395000 5.385000 0.565000 ;
+ RECT 5.295000 3.505000 5.465000 3.675000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 3.985000 5.605000 4.155000 ;
+ RECT 5.575000 0.395000 5.745000 0.565000 ;
+ RECT 5.655000 3.505000 5.825000 3.675000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 3.985000 6.085000 4.155000 ;
+ RECT 5.935000 0.395000 6.105000 0.565000 ;
+ RECT 6.015000 3.505000 6.185000 3.675000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 3.985000 6.565000 4.155000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 3.985000 7.045000 4.155000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 3.985000 7.525000 4.155000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 3.985000 8.005000 4.155000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 3.985000 8.485000 4.155000 ;
+ RECT 8.535000 3.515000 8.705000 3.685000 ;
+ RECT 8.795000 -0.085000 8.965000 0.085000 ;
+ RECT 8.795000 3.985000 8.965000 4.155000 ;
+ RECT 8.805000 0.395000 8.975000 0.565000 ;
+ RECT 8.895000 3.515000 9.065000 3.685000 ;
+ RECT 9.165000 0.395000 9.335000 0.565000 ;
+ RECT 9.255000 3.515000 9.425000 3.685000 ;
+ RECT 9.275000 -0.085000 9.445000 0.085000 ;
+ RECT 9.275000 3.985000 9.445000 4.155000 ;
+ RECT 9.525000 0.395000 9.695000 0.565000 ;
+ RECT 9.755000 -0.085000 9.925000 0.085000 ;
+ RECT 9.755000 3.985000 9.925000 4.155000 ;
+ RECT 10.235000 -0.085000 10.405000 0.085000 ;
+ RECT 10.235000 3.985000 10.405000 4.155000 ;
+ RECT 10.715000 -0.085000 10.885000 0.085000 ;
+ RECT 10.715000 3.985000 10.885000 4.155000 ;
+ RECT 11.070000 3.505000 11.240000 3.675000 ;
+ RECT 11.080000 0.395000 11.250000 0.565000 ;
+ RECT 11.195000 -0.085000 11.365000 0.085000 ;
+ RECT 11.195000 3.985000 11.365000 4.155000 ;
+ RECT 11.430000 3.505000 11.600000 3.675000 ;
+ RECT 11.440000 0.395000 11.610000 0.565000 ;
+ RECT 11.675000 -0.085000 11.845000 0.085000 ;
+ RECT 11.675000 3.985000 11.845000 4.155000 ;
+ RECT 12.155000 -0.085000 12.325000 0.085000 ;
+ RECT 12.155000 3.985000 12.325000 4.155000 ;
+ RECT 12.325000 3.505000 12.495000 3.675000 ;
+ RECT 12.345000 0.395000 12.515000 0.565000 ;
+ RECT 12.635000 -0.085000 12.805000 0.085000 ;
+ RECT 12.635000 3.985000 12.805000 4.155000 ;
+ RECT 12.685000 3.505000 12.855000 3.675000 ;
+ RECT 12.705000 0.395000 12.875000 0.565000 ;
+ RECT 13.045000 3.505000 13.215000 3.675000 ;
+ RECT 13.065000 0.395000 13.235000 0.565000 ;
+ RECT 13.115000 -0.085000 13.285000 0.085000 ;
+ RECT 13.115000 3.985000 13.285000 4.155000 ;
+ RECT 13.595000 -0.085000 13.765000 0.085000 ;
+ RECT 13.595000 3.985000 13.765000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__dfxbp_1
+MACRO sky130_fd_sc_hvl__dlclkp_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__dlclkp_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 10.08000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN GATE
+ ANTENNAGATEAREA 0.585000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.610000 1.385000 0.940000 2.200000 ;
+ END
+ END GATE
+ PIN GCLK
+ ANTENNADIFFAREA 0.596250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 9.630000 0.515000 9.995000 1.215000 ;
+ RECT 9.630000 1.895000 9.995000 3.735000 ;
+ RECT 9.725000 1.215000 9.995000 1.895000 ;
+ END
+ END GCLK
+ PIN CLK
+ ANTENNAGATEAREA 1.170000 ;
+ DIRECTION INPUT ;
+ USE CLOCK ;
+ PORT
+ LAYER li1 ;
+ RECT 3.360000 1.465000 3.690000 1.975000 ;
+ RECT 8.235000 3.125000 8.600000 3.445000 ;
+ RECT 8.350000 1.725000 8.680000 2.025000 ;
+ RECT 8.350000 2.025000 8.600000 3.125000 ;
+ END
+ END CLK
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 10.080000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 10.080000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 10.080000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 10.080000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 10.080000 0.085000 ;
+ RECT 0.000000 3.985000 10.080000 4.155000 ;
+ RECT 0.110000 2.200000 0.440000 3.445000 ;
+ RECT 0.110000 3.445000 1.025000 3.555000 ;
+ RECT 0.110000 3.555000 3.330000 3.815000 ;
+ RECT 0.140000 0.365000 0.765000 0.625000 ;
+ RECT 0.140000 0.625000 0.470000 1.170000 ;
+ RECT 1.155000 0.365000 2.810000 0.535000 ;
+ RECT 1.155000 0.535000 1.865000 0.670000 ;
+ RECT 1.195000 3.165000 2.495000 3.385000 ;
+ RECT 1.595000 1.555000 2.105000 1.885000 ;
+ RECT 1.670000 0.840000 2.000000 1.555000 ;
+ RECT 1.670000 1.885000 2.000000 2.995000 ;
+ RECT 2.220000 0.705000 2.470000 1.080000 ;
+ RECT 2.275000 1.080000 2.470000 2.145000 ;
+ RECT 2.275000 2.145000 3.690000 2.315000 ;
+ RECT 2.275000 2.315000 2.495000 3.165000 ;
+ RECT 2.640000 0.535000 2.810000 1.125000 ;
+ RECT 2.640000 1.125000 4.070000 1.295000 ;
+ RECT 2.640000 1.295000 2.970000 1.965000 ;
+ RECT 2.665000 3.445000 3.330000 3.555000 ;
+ RECT 2.980000 0.255000 3.925000 0.535000 ;
+ RECT 2.980000 0.535000 3.650000 0.625000 ;
+ RECT 2.980000 0.625000 3.330000 0.955000 ;
+ RECT 3.000000 2.485000 3.330000 3.445000 ;
+ RECT 3.520000 2.315000 3.690000 3.385000 ;
+ RECT 3.520000 3.385000 5.515000 3.555000 ;
+ RECT 3.820000 0.705000 4.070000 1.125000 ;
+ RECT 3.860000 1.295000 4.070000 3.005000 ;
+ RECT 3.860000 3.005000 5.175000 3.215000 ;
+ RECT 4.095000 0.255000 4.660000 0.535000 ;
+ RECT 4.375000 0.535000 4.660000 1.195000 ;
+ RECT 4.375000 1.195000 6.490000 1.365000 ;
+ RECT 4.375000 1.365000 4.545000 2.330000 ;
+ RECT 4.375000 2.330000 4.660000 2.660000 ;
+ RECT 4.715000 1.615000 5.305000 1.945000 ;
+ RECT 4.830000 0.255000 6.150000 0.625000 ;
+ RECT 5.135000 1.945000 5.305000 2.425000 ;
+ RECT 5.135000 2.425000 5.515000 2.595000 ;
+ RECT 5.345000 2.595000 5.515000 3.385000 ;
+ RECT 5.515000 1.535000 5.845000 1.875000 ;
+ RECT 5.515000 1.875000 6.930000 2.085000 ;
+ RECT 5.685000 3.445000 8.065000 3.615000 ;
+ RECT 5.685000 3.615000 9.460000 3.815000 ;
+ RECT 5.820000 0.625000 6.150000 1.025000 ;
+ RECT 5.820000 2.330000 6.150000 3.445000 ;
+ RECT 6.125000 1.365000 6.490000 1.655000 ;
+ RECT 6.320000 0.355000 6.910000 0.670000 ;
+ RECT 6.320000 0.670000 6.490000 1.195000 ;
+ RECT 6.660000 0.840000 6.930000 1.615000 ;
+ RECT 6.660000 1.615000 7.785000 1.825000 ;
+ RECT 6.660000 1.825000 6.930000 1.875000 ;
+ RECT 6.660000 2.085000 6.930000 2.660000 ;
+ RECT 7.080000 0.255000 9.460000 0.625000 ;
+ RECT 7.150000 0.885000 8.180000 1.215000 ;
+ RECT 7.150000 2.225000 7.480000 3.445000 ;
+ RECT 7.455000 1.385000 7.785000 1.615000 ;
+ RECT 7.455000 1.825000 7.785000 2.055000 ;
+ RECT 7.955000 1.215000 8.180000 1.385000 ;
+ RECT 7.955000 1.385000 9.555000 1.555000 ;
+ RECT 7.955000 1.555000 8.180000 2.955000 ;
+ RECT 8.770000 0.625000 9.100000 1.215000 ;
+ RECT 8.770000 2.195000 9.100000 3.445000 ;
+ RECT 8.770000 3.445000 9.460000 3.615000 ;
+ RECT 8.945000 1.555000 9.555000 1.725000 ;
+ LAYER mcon ;
+ RECT 0.140000 3.475000 0.310000 3.645000 ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.175000 0.425000 0.345000 0.595000 ;
+ RECT 0.500000 3.475000 0.670000 3.645000 ;
+ RECT 0.535000 0.425000 0.705000 0.595000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.860000 3.600000 1.030000 3.770000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.220000 3.600000 1.390000 3.770000 ;
+ RECT 1.580000 3.600000 1.750000 3.770000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 1.995000 3.600000 2.165000 3.770000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.355000 3.600000 2.525000 3.770000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.715000 3.475000 2.885000 3.645000 ;
+ RECT 2.995000 0.425000 3.165000 0.595000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.075000 3.475000 3.245000 3.645000 ;
+ RECT 3.355000 0.425000 3.525000 0.595000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.715000 0.355000 3.885000 0.525000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.870000 0.355000 5.040000 0.525000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ RECT 5.230000 0.355000 5.400000 0.525000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 3.985000 5.605000 4.155000 ;
+ RECT 5.590000 0.425000 5.760000 0.595000 ;
+ RECT 5.715000 3.475000 5.885000 3.645000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 3.985000 6.085000 4.155000 ;
+ RECT 5.950000 0.425000 6.120000 0.595000 ;
+ RECT 6.075000 3.475000 6.245000 3.645000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 3.985000 6.565000 4.155000 ;
+ RECT 6.435000 3.545000 6.605000 3.715000 ;
+ RECT 6.795000 3.545000 6.965000 3.715000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 3.985000 7.045000 4.155000 ;
+ RECT 7.100000 0.355000 7.270000 0.525000 ;
+ RECT 7.155000 3.475000 7.325000 3.645000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 3.985000 7.525000 4.155000 ;
+ RECT 7.460000 0.355000 7.630000 0.525000 ;
+ RECT 7.515000 3.475000 7.685000 3.645000 ;
+ RECT 7.820000 0.355000 7.990000 0.525000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 3.985000 8.005000 4.155000 ;
+ RECT 8.180000 0.355000 8.350000 0.525000 ;
+ RECT 8.195000 3.615000 8.365000 3.785000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 3.985000 8.485000 4.155000 ;
+ RECT 8.540000 0.425000 8.710000 0.595000 ;
+ RECT 8.555000 3.615000 8.725000 3.785000 ;
+ RECT 8.795000 -0.085000 8.965000 0.085000 ;
+ RECT 8.795000 3.985000 8.965000 4.155000 ;
+ RECT 8.900000 0.425000 9.070000 0.595000 ;
+ RECT 8.915000 3.475000 9.085000 3.645000 ;
+ RECT 9.260000 0.425000 9.430000 0.595000 ;
+ RECT 9.275000 -0.085000 9.445000 0.085000 ;
+ RECT 9.275000 3.475000 9.445000 3.645000 ;
+ RECT 9.275000 3.985000 9.445000 4.155000 ;
+ RECT 9.755000 -0.085000 9.925000 0.085000 ;
+ RECT 9.755000 3.985000 9.925000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__dlclkp_1
+MACRO sky130_fd_sc_hvl__lsbufhv2hv_lh_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__lsbufhv2hv_lh_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 10.56000 BY 8.140000 ;
+ SYMMETRY X Y ;
+ SITE unithvdbl ;
+ PIN A
+ ANTENNAGATEAREA 0.750000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.495000 1.530000 2.805000 2.200000 ;
+ END
+ END A
+ PIN X
+ ANTENNADIFFAREA 0.596250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 10.120000 4.405000 10.450000 7.625000 ;
+ END
+ END X
+ PIN LOWHVPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.070000 3.020000 10.490000 3.305000 ;
+ END
+ END LOWHVPWR
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 7.515000 10.560000 7.885000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 8.025000 10.560000 8.255000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 10.560000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 4.325000 10.560000 4.695000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 10.560000 0.085000 ;
+ RECT 0.000000 3.985000 0.800000 4.155000 ;
+ RECT 0.000000 8.055000 10.560000 8.225000 ;
+ RECT 3.090000 0.685000 3.420000 1.745000 ;
+ RECT 3.090000 1.745000 4.845000 1.995000 ;
+ RECT 3.090000 1.995000 3.420000 5.165000 ;
+ RECT 3.090000 5.165000 5.660000 5.495000 ;
+ RECT 3.300000 6.085000 3.890000 7.715000 ;
+ RECT 3.300000 7.715000 7.010000 7.885000 ;
+ RECT 3.590000 3.355000 4.780000 4.025000 ;
+ RECT 3.740000 0.255000 9.540000 0.425000 ;
+ RECT 3.740000 0.425000 4.330000 1.475000 ;
+ RECT 3.740000 2.325000 4.330000 3.355000 ;
+ RECT 4.210000 5.665000 7.930000 5.995000 ;
+ RECT 4.210000 5.995000 4.540000 7.545000 ;
+ RECT 4.650000 0.685000 4.980000 1.145000 ;
+ RECT 4.650000 1.145000 5.660000 1.475000 ;
+ RECT 4.650000 2.165000 6.570000 2.475000 ;
+ RECT 4.650000 2.475000 4.980000 3.115000 ;
+ RECT 4.860000 6.165000 5.450000 7.715000 ;
+ RECT 5.330000 1.475000 5.660000 2.145000 ;
+ RECT 5.330000 2.145000 6.570000 2.165000 ;
+ RECT 5.770000 5.995000 6.100000 7.545000 ;
+ RECT 5.830000 0.425000 6.420000 1.975000 ;
+ RECT 6.420000 6.165000 7.010000 7.715000 ;
+ RECT 6.740000 0.595000 7.070000 2.145000 ;
+ RECT 6.740000 2.145000 8.630000 2.475000 ;
+ RECT 7.375000 3.605000 8.045000 3.935000 ;
+ RECT 7.390000 0.425000 7.980000 1.975000 ;
+ RECT 7.600000 2.795000 8.545000 3.125000 ;
+ RECT 7.600000 3.125000 7.930000 3.435000 ;
+ RECT 7.600000 3.935000 7.930000 5.665000 ;
+ RECT 8.215000 2.475000 8.545000 2.795000 ;
+ RECT 8.215000 3.125000 8.545000 5.205000 ;
+ RECT 8.215000 5.205000 8.965000 5.535000 ;
+ RECT 8.300000 0.595000 8.630000 2.145000 ;
+ RECT 8.635000 5.535000 8.965000 6.555000 ;
+ RECT 8.715000 3.985000 10.560000 4.155000 ;
+ RECT 8.790000 4.405000 9.800000 4.800000 ;
+ RECT 8.940000 2.795000 9.530000 3.705000 ;
+ RECT 8.950000 0.425000 9.540000 1.975000 ;
+ RECT 9.210000 4.800000 9.800000 5.945000 ;
+ RECT 9.210000 6.835000 9.800000 7.745000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.155000 8.055000 0.325000 8.225000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 8.055000 0.805000 8.225000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 8.055000 1.285000 8.225000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 8.055000 1.765000 8.225000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 8.055000 2.245000 8.225000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 8.055000 2.725000 8.225000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 8.055000 3.205000 8.225000 ;
+ RECT 3.330000 7.545000 3.500000 7.715000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 8.055000 3.685000 8.225000 ;
+ RECT 3.690000 7.545000 3.860000 7.715000 ;
+ RECT 3.770000 0.425000 3.940000 0.595000 ;
+ RECT 3.770000 3.050000 3.940000 3.220000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 8.055000 4.165000 8.225000 ;
+ RECT 4.130000 0.425000 4.300000 0.595000 ;
+ RECT 4.130000 3.050000 4.300000 3.220000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 8.055000 4.645000 8.225000 ;
+ RECT 4.890000 7.545000 5.060000 7.715000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 8.055000 5.125000 8.225000 ;
+ RECT 5.250000 7.545000 5.420000 7.715000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 8.055000 5.605000 8.225000 ;
+ RECT 5.860000 0.425000 6.030000 0.595000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 8.055000 6.085000 8.225000 ;
+ RECT 6.220000 0.425000 6.390000 0.595000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 8.055000 6.565000 8.225000 ;
+ RECT 6.450000 7.545000 6.620000 7.715000 ;
+ RECT 6.810000 7.545000 6.980000 7.715000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 8.055000 7.045000 8.225000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 8.055000 7.525000 8.225000 ;
+ RECT 7.420000 0.425000 7.590000 0.595000 ;
+ RECT 7.780000 0.425000 7.950000 0.595000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 8.055000 8.005000 8.225000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 8.055000 8.485000 8.225000 ;
+ RECT 8.795000 -0.085000 8.965000 0.085000 ;
+ RECT 8.795000 3.985000 8.965000 4.155000 ;
+ RECT 8.795000 8.055000 8.965000 8.225000 ;
+ RECT 8.880000 4.495000 9.050000 4.665000 ;
+ RECT 8.970000 3.475000 9.140000 3.645000 ;
+ RECT 8.980000 0.425000 9.150000 0.595000 ;
+ RECT 9.240000 4.495000 9.410000 4.665000 ;
+ RECT 9.240000 7.545000 9.410000 7.715000 ;
+ RECT 9.275000 -0.085000 9.445000 0.085000 ;
+ RECT 9.275000 3.985000 9.445000 4.155000 ;
+ RECT 9.275000 8.055000 9.445000 8.225000 ;
+ RECT 9.330000 3.475000 9.500000 3.645000 ;
+ RECT 9.340000 0.425000 9.510000 0.595000 ;
+ RECT 9.600000 4.495000 9.770000 4.665000 ;
+ RECT 9.600000 7.545000 9.770000 7.715000 ;
+ RECT 9.755000 -0.085000 9.925000 0.085000 ;
+ RECT 9.755000 3.985000 9.925000 4.155000 ;
+ RECT 9.755000 8.055000 9.925000 8.225000 ;
+ RECT 10.235000 -0.085000 10.405000 0.085000 ;
+ RECT 10.235000 3.985000 10.405000 4.155000 ;
+ RECT 10.235000 8.055000 10.405000 8.225000 ;
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 10.560000 0.115000 ;
+ RECT 0.000000 0.255000 10.560000 0.625000 ;
+ RECT 0.000000 3.445000 10.560000 3.815000 ;
+ END
+END sky130_fd_sc_hvl__lsbufhv2hv_lh_1
+MACRO sky130_fd_sc_hvl__or2_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__or2_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 3.360000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN A
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.530000 1.175000 1.860000 1.725000 ;
+ END
+ END A
+ PIN B
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.605000 1.175000 0.935000 1.725000 ;
+ END
+ END B
+ PIN X
+ ANTENNADIFFAREA 0.641250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.980000 0.495000 3.235000 3.755000 ;
+ END
+ END X
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 3.360000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 3.360000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 3.360000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 3.360000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 3.360000 0.085000 ;
+ RECT 0.000000 3.985000 3.360000 4.155000 ;
+ RECT 0.090000 0.365000 1.000000 0.995000 ;
+ RECT 0.400000 1.905000 2.775000 2.075000 ;
+ RECT 0.400000 2.075000 0.650000 2.675000 ;
+ RECT 0.830000 2.255000 2.800000 3.755000 ;
+ RECT 1.180000 0.495000 1.510000 0.995000 ;
+ RECT 1.180000 0.995000 1.350000 1.905000 ;
+ RECT 2.040000 0.365000 2.630000 1.325000 ;
+ RECT 2.445000 1.725000 2.775000 1.905000 ;
+ LAYER mcon ;
+ RECT 0.100000 0.395000 0.270000 0.565000 ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.460000 0.395000 0.630000 0.565000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.820000 0.395000 0.990000 0.565000 ;
+ RECT 0.830000 3.505000 1.000000 3.675000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.190000 3.505000 1.360000 3.675000 ;
+ RECT 1.550000 3.505000 1.720000 3.675000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 1.910000 3.505000 2.080000 3.675000 ;
+ RECT 2.070000 0.395000 2.240000 0.565000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.270000 3.505000 2.440000 3.675000 ;
+ RECT 2.430000 0.395000 2.600000 0.565000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.630000 3.505000 2.800000 3.675000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__or2_1
+MACRO sky130_fd_sc_hvl__and2_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__and2_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 3.360000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN A
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.125000 1.175000 0.535000 1.845000 ;
+ END
+ END A
+ PIN B
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.065000 0.810000 1.455000 1.725000 ;
+ END
+ END B
+ PIN X
+ ANTENNADIFFAREA 0.626250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.980000 0.495000 3.255000 3.755000 ;
+ END
+ END X
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 3.360000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 3.360000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 3.360000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 3.360000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 3.360000 0.085000 ;
+ RECT 0.000000 3.985000 3.360000 4.155000 ;
+ RECT 0.090000 2.255000 1.020000 3.705000 ;
+ RECT 0.130000 0.495000 0.380000 0.825000 ;
+ RECT 0.130000 0.825000 0.885000 0.995000 ;
+ RECT 0.715000 0.995000 0.885000 1.905000 ;
+ RECT 0.715000 1.905000 2.775000 2.075000 ;
+ RECT 1.200000 2.075000 1.370000 2.675000 ;
+ RECT 1.550000 2.255000 2.800000 3.755000 ;
+ RECT 1.635000 0.365000 2.625000 1.325000 ;
+ RECT 2.445000 1.725000 2.775000 1.905000 ;
+ LAYER mcon ;
+ RECT 0.110000 3.505000 0.280000 3.675000 ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.470000 3.505000 0.640000 3.675000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.830000 3.505000 1.000000 3.675000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.550000 3.505000 1.720000 3.675000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 1.685000 0.395000 1.855000 0.565000 ;
+ RECT 1.910000 3.505000 2.080000 3.675000 ;
+ RECT 2.045000 0.395000 2.215000 0.565000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.270000 3.505000 2.440000 3.675000 ;
+ RECT 2.405000 0.395000 2.575000 0.565000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.630000 3.505000 2.800000 3.675000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__and2_1
+MACRO sky130_fd_sc_hvl__sdfstp_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__sdfstp_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 18.72000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN D
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.945000 1.845000 2.275000 2.355000 ;
+ END
+ END D
+ PIN Q
+ ANTENNADIFFAREA 0.478750 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 18.260000 0.495000 18.610000 3.395000 ;
+ END
+ END Q
+ PIN SCD
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 3.420000 1.175000 3.750000 2.150000 ;
+ END
+ END SCD
+ PIN SCE
+ ANTENNAGATEAREA 0.840000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.565000 1.495000 2.890000 1.665000 ;
+ RECT 0.565000 1.665000 0.895000 2.165000 ;
+ RECT 2.525000 1.095000 2.890000 1.495000 ;
+ RECT 2.525000 1.665000 2.890000 1.780000 ;
+ END
+ END SCE
+ PIN SET_B
+ ANTENNAGATEAREA 0.840000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 10.535000 1.175000 11.635000 1.345000 ;
+ RECT 11.465000 0.265000 14.215000 0.435000 ;
+ RECT 11.465000 0.435000 11.635000 1.175000 ;
+ RECT 14.045000 0.435000 14.215000 0.810000 ;
+ RECT 14.045000 0.810000 14.520000 1.760000 ;
+ END
+ END SET_B
+ PIN CLK
+ ANTENNAGATEAREA 0.585000 ;
+ DIRECTION INPUT ;
+ USE CLOCK ;
+ PORT
+ LAYER li1 ;
+ RECT 3.965000 1.175000 4.525000 2.150000 ;
+ END
+ END CLK
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 18.720000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 18.720000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 18.720000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 18.720000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 18.720000 0.085000 ;
+ RECT 0.000000 3.985000 18.720000 4.155000 ;
+ RECT 0.110000 0.515000 0.440000 1.095000 ;
+ RECT 0.110000 1.095000 2.255000 1.315000 ;
+ RECT 0.110000 1.315000 0.280000 2.535000 ;
+ RECT 0.110000 2.535000 2.890000 2.705000 ;
+ RECT 0.110000 2.705000 0.440000 3.285000 ;
+ RECT 0.620000 0.365000 1.570000 0.915000 ;
+ RECT 0.620000 2.885000 1.570000 3.705000 ;
+ RECT 2.380000 0.495000 2.710000 0.745000 ;
+ RECT 2.380000 0.745000 3.240000 0.915000 ;
+ RECT 2.380000 2.885000 3.240000 3.055000 ;
+ RECT 2.380000 3.055000 2.710000 3.305000 ;
+ RECT 2.635000 2.015000 2.890000 2.535000 ;
+ RECT 3.070000 0.915000 3.240000 2.455000 ;
+ RECT 3.070000 2.455000 4.665000 2.625000 ;
+ RECT 3.070000 2.625000 3.240000 2.885000 ;
+ RECT 3.420000 0.365000 4.370000 0.995000 ;
+ RECT 3.420000 2.805000 4.315000 3.705000 ;
+ RECT 4.495000 2.625000 4.665000 3.635000 ;
+ RECT 4.495000 3.635000 5.365000 3.805000 ;
+ RECT 4.650000 0.515000 5.015000 0.975000 ;
+ RECT 4.845000 0.975000 5.015000 1.735000 ;
+ RECT 4.845000 1.735000 5.835000 1.905000 ;
+ RECT 4.845000 1.905000 5.015000 3.455000 ;
+ RECT 5.195000 2.275000 6.075000 2.445000 ;
+ RECT 5.195000 2.445000 5.365000 3.635000 ;
+ RECT 5.200000 0.365000 5.450000 1.055000 ;
+ RECT 5.505000 1.235000 5.835000 1.735000 ;
+ RECT 5.545000 2.625000 5.725000 3.705000 ;
+ RECT 5.630000 0.265000 7.230000 0.435000 ;
+ RECT 5.630000 0.435000 5.800000 1.235000 ;
+ RECT 5.905000 2.445000 6.075000 3.635000 ;
+ RECT 5.905000 3.635000 7.095000 3.805000 ;
+ RECT 5.980000 0.675000 6.310000 1.055000 ;
+ RECT 6.140000 1.055000 6.310000 1.425000 ;
+ RECT 6.140000 1.425000 6.530000 2.095000 ;
+ RECT 6.255000 2.095000 6.530000 3.455000 ;
+ RECT 6.550000 0.615000 6.880000 1.025000 ;
+ RECT 6.710000 1.025000 6.880000 2.675000 ;
+ RECT 6.710000 2.675000 7.095000 3.635000 ;
+ RECT 7.060000 0.435000 7.230000 1.605000 ;
+ RECT 7.060000 1.605000 7.445000 1.775000 ;
+ RECT 7.275000 1.775000 7.445000 3.355000 ;
+ RECT 7.275000 3.355000 8.305000 3.525000 ;
+ RECT 7.410000 0.525000 7.795000 1.025000 ;
+ RECT 7.625000 1.025000 7.795000 1.355000 ;
+ RECT 7.625000 1.355000 8.655000 1.525000 ;
+ RECT 7.625000 1.525000 7.795000 2.675000 ;
+ RECT 7.625000 2.675000 7.955000 3.175000 ;
+ RECT 7.975000 1.705000 8.305000 1.875000 ;
+ RECT 7.975000 1.875000 12.220000 2.045000 ;
+ RECT 8.135000 2.225000 8.410000 2.575000 ;
+ RECT 8.135000 2.575000 9.795000 2.745000 ;
+ RECT 8.135000 2.745000 8.305000 3.355000 ;
+ RECT 8.200000 0.365000 9.150000 0.925000 ;
+ RECT 8.485000 1.525000 11.525000 1.695000 ;
+ RECT 8.495000 2.925000 9.445000 3.705000 ;
+ RECT 8.790000 2.225000 10.305000 2.395000 ;
+ RECT 8.835000 1.105000 9.700000 1.275000 ;
+ RECT 8.835000 1.275000 9.165000 1.345000 ;
+ RECT 9.370000 0.515000 9.700000 1.105000 ;
+ RECT 9.520000 1.455000 9.850000 1.525000 ;
+ RECT 9.625000 2.745000 9.795000 3.105000 ;
+ RECT 9.625000 3.105000 10.655000 3.275000 ;
+ RECT 9.975000 2.395000 10.305000 2.925000 ;
+ RECT 10.335000 0.365000 11.285000 0.995000 ;
+ RECT 10.485000 2.935000 12.180000 3.105000 ;
+ RECT 10.835000 3.285000 11.785000 3.755000 ;
+ RECT 11.905000 2.225000 12.570000 2.395000 ;
+ RECT 11.905000 2.395000 12.180000 2.935000 ;
+ RECT 11.970000 1.685000 12.220000 1.875000 ;
+ RECT 12.095000 0.615000 13.350000 0.785000 ;
+ RECT 12.095000 0.785000 12.265000 1.335000 ;
+ RECT 12.095000 1.335000 12.570000 1.505000 ;
+ RECT 12.360000 2.675000 12.920000 2.845000 ;
+ RECT 12.360000 2.845000 12.690000 3.755000 ;
+ RECT 12.400000 1.505000 12.570000 2.225000 ;
+ RECT 12.445000 0.965000 12.920000 1.155000 ;
+ RECT 12.750000 1.155000 12.920000 1.940000 ;
+ RECT 12.750000 1.940000 15.585000 2.110000 ;
+ RECT 12.750000 2.110000 12.920000 2.675000 ;
+ RECT 13.100000 0.785000 13.350000 1.745000 ;
+ RECT 13.265000 2.675000 14.215000 3.705000 ;
+ RECT 13.710000 2.290000 14.565000 2.495000 ;
+ RECT 14.395000 2.495000 14.565000 3.335000 ;
+ RECT 14.395000 3.335000 15.625000 3.505000 ;
+ RECT 14.700000 0.365000 15.590000 1.325000 ;
+ RECT 14.745000 2.110000 15.585000 2.175000 ;
+ RECT 14.745000 2.175000 15.075000 3.155000 ;
+ RECT 15.255000 1.505000 15.585000 1.940000 ;
+ RECT 15.295000 2.695000 16.020000 2.865000 ;
+ RECT 15.295000 2.865000 15.625000 3.335000 ;
+ RECT 15.770000 0.825000 16.020000 2.695000 ;
+ RECT 15.815000 3.045000 16.405000 3.705000 ;
+ RECT 16.585000 0.825000 16.915000 1.505000 ;
+ RECT 16.585000 1.505000 18.080000 1.675000 ;
+ RECT 16.585000 1.675000 16.915000 2.355000 ;
+ RECT 16.585000 2.355000 16.955000 3.145000 ;
+ RECT 17.095000 0.365000 18.045000 1.325000 ;
+ RECT 17.135000 2.355000 18.080000 3.705000 ;
+ RECT 17.750000 1.675000 18.080000 2.175000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.650000 0.395000 0.820000 0.565000 ;
+ RECT 0.650000 3.505000 0.820000 3.675000 ;
+ RECT 1.010000 0.395000 1.180000 0.565000 ;
+ RECT 1.010000 3.505000 1.180000 3.675000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.370000 0.395000 1.540000 0.565000 ;
+ RECT 1.370000 3.505000 1.540000 3.675000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.420000 3.505000 3.590000 3.675000 ;
+ RECT 3.450000 0.395000 3.620000 0.565000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.780000 3.505000 3.950000 3.675000 ;
+ RECT 3.810000 0.395000 3.980000 0.565000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.140000 3.505000 4.310000 3.675000 ;
+ RECT 4.170000 0.395000 4.340000 0.565000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ RECT 5.230000 0.395000 5.400000 0.565000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 3.985000 5.605000 4.155000 ;
+ RECT 5.550000 3.505000 5.720000 3.675000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 3.985000 6.085000 4.155000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 3.985000 6.565000 4.155000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 3.985000 7.045000 4.155000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 3.985000 7.525000 4.155000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 3.985000 8.005000 4.155000 ;
+ RECT 8.230000 0.395000 8.400000 0.565000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 3.985000 8.485000 4.155000 ;
+ RECT 8.525000 3.505000 8.695000 3.675000 ;
+ RECT 8.590000 0.395000 8.760000 0.565000 ;
+ RECT 8.795000 -0.085000 8.965000 0.085000 ;
+ RECT 8.795000 3.985000 8.965000 4.155000 ;
+ RECT 8.885000 3.505000 9.055000 3.675000 ;
+ RECT 8.950000 0.395000 9.120000 0.565000 ;
+ RECT 9.245000 3.505000 9.415000 3.675000 ;
+ RECT 9.275000 -0.085000 9.445000 0.085000 ;
+ RECT 9.275000 3.985000 9.445000 4.155000 ;
+ RECT 9.755000 -0.085000 9.925000 0.085000 ;
+ RECT 9.755000 3.985000 9.925000 4.155000 ;
+ RECT 10.235000 -0.085000 10.405000 0.085000 ;
+ RECT 10.235000 3.985000 10.405000 4.155000 ;
+ RECT 10.365000 0.395000 10.535000 0.565000 ;
+ RECT 10.715000 -0.085000 10.885000 0.085000 ;
+ RECT 10.715000 3.985000 10.885000 4.155000 ;
+ RECT 10.725000 0.395000 10.895000 0.565000 ;
+ RECT 10.865000 3.505000 11.035000 3.675000 ;
+ RECT 11.085000 0.395000 11.255000 0.565000 ;
+ RECT 11.195000 -0.085000 11.365000 0.085000 ;
+ RECT 11.195000 3.985000 11.365000 4.155000 ;
+ RECT 11.225000 3.505000 11.395000 3.675000 ;
+ RECT 11.585000 3.505000 11.755000 3.675000 ;
+ RECT 11.675000 -0.085000 11.845000 0.085000 ;
+ RECT 11.675000 3.985000 11.845000 4.155000 ;
+ RECT 12.155000 -0.085000 12.325000 0.085000 ;
+ RECT 12.155000 3.985000 12.325000 4.155000 ;
+ RECT 12.635000 -0.085000 12.805000 0.085000 ;
+ RECT 12.635000 3.985000 12.805000 4.155000 ;
+ RECT 13.115000 -0.085000 13.285000 0.085000 ;
+ RECT 13.115000 3.985000 13.285000 4.155000 ;
+ RECT 13.295000 3.505000 13.465000 3.675000 ;
+ RECT 13.595000 -0.085000 13.765000 0.085000 ;
+ RECT 13.595000 3.985000 13.765000 4.155000 ;
+ RECT 13.655000 3.505000 13.825000 3.675000 ;
+ RECT 14.015000 3.505000 14.185000 3.675000 ;
+ RECT 14.075000 -0.085000 14.245000 0.085000 ;
+ RECT 14.075000 3.985000 14.245000 4.155000 ;
+ RECT 14.555000 -0.085000 14.725000 0.085000 ;
+ RECT 14.555000 3.985000 14.725000 4.155000 ;
+ RECT 14.700000 0.395000 14.870000 0.565000 ;
+ RECT 15.035000 -0.085000 15.205000 0.085000 ;
+ RECT 15.035000 3.985000 15.205000 4.155000 ;
+ RECT 15.060000 0.395000 15.230000 0.565000 ;
+ RECT 15.420000 0.395000 15.590000 0.565000 ;
+ RECT 15.515000 -0.085000 15.685000 0.085000 ;
+ RECT 15.515000 3.985000 15.685000 4.155000 ;
+ RECT 15.845000 3.505000 16.015000 3.675000 ;
+ RECT 15.995000 -0.085000 16.165000 0.085000 ;
+ RECT 15.995000 3.985000 16.165000 4.155000 ;
+ RECT 16.205000 3.505000 16.375000 3.675000 ;
+ RECT 16.475000 -0.085000 16.645000 0.085000 ;
+ RECT 16.475000 3.985000 16.645000 4.155000 ;
+ RECT 16.955000 -0.085000 17.125000 0.085000 ;
+ RECT 16.955000 3.985000 17.125000 4.155000 ;
+ RECT 17.125000 0.395000 17.295000 0.565000 ;
+ RECT 17.160000 3.505000 17.330000 3.675000 ;
+ RECT 17.435000 -0.085000 17.605000 0.085000 ;
+ RECT 17.435000 3.985000 17.605000 4.155000 ;
+ RECT 17.485000 0.395000 17.655000 0.565000 ;
+ RECT 17.520000 3.505000 17.690000 3.675000 ;
+ RECT 17.845000 0.395000 18.015000 0.565000 ;
+ RECT 17.880000 3.505000 18.050000 3.675000 ;
+ RECT 17.915000 -0.085000 18.085000 0.085000 ;
+ RECT 17.915000 3.985000 18.085000 4.155000 ;
+ RECT 18.395000 -0.085000 18.565000 0.085000 ;
+ RECT 18.395000 3.985000 18.565000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__sdfstp_1
+MACRO sky130_fd_sc_hvl__dfstp_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__dfstp_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 14.88000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN D
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.505000 1.525000 2.835000 2.095000 ;
+ END
+ END D
+ PIN Q
+ ANTENNADIFFAREA 0.478750 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 14.420000 0.645000 14.770000 3.615000 ;
+ END
+ END Q
+ PIN SET_B
+ ANTENNAGATEAREA 0.840000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 7.165000 1.555000 8.100000 1.795000 ;
+ RECT 7.930000 0.840000 11.160000 1.010000 ;
+ RECT 7.930000 1.010000 8.100000 1.555000 ;
+ RECT 8.285000 0.555000 11.160000 0.840000 ;
+ RECT 10.885000 1.010000 11.160000 1.040000 ;
+ END
+ END SET_B
+ PIN CLK
+ ANTENNAGATEAREA 0.585000 ;
+ DIRECTION INPUT ;
+ USE CLOCK ;
+ PORT
+ LAYER li1 ;
+ RECT 0.545000 2.075000 0.875000 2.745000 ;
+ END
+ END CLK
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 14.880000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 14.880000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 14.880000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 14.880000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 14.880000 0.085000 ;
+ RECT 0.000000 3.985000 14.880000 4.155000 ;
+ RECT 0.115000 0.615000 0.380000 1.295000 ;
+ RECT 0.115000 1.295000 1.510000 1.465000 ;
+ RECT 0.115000 1.465000 0.365000 3.735000 ;
+ RECT 0.545000 2.925000 1.495000 3.755000 ;
+ RECT 0.570000 0.365000 1.160000 1.115000 ;
+ RECT 1.180000 1.465000 1.510000 1.895000 ;
+ RECT 1.340000 0.265000 2.290000 0.435000 ;
+ RECT 1.340000 0.435000 1.510000 1.295000 ;
+ RECT 1.675000 2.945000 2.005000 3.735000 ;
+ RECT 1.690000 0.615000 1.940000 2.275000 ;
+ RECT 1.690000 2.275000 2.835000 2.445000 ;
+ RECT 1.690000 2.445000 2.005000 2.945000 ;
+ RECT 2.120000 0.435000 2.290000 1.175000 ;
+ RECT 2.120000 1.175000 3.185000 1.345000 ;
+ RECT 2.235000 2.625000 2.485000 3.705000 ;
+ RECT 2.470000 0.365000 3.005000 0.995000 ;
+ RECT 2.665000 2.445000 2.835000 3.755000 ;
+ RECT 3.015000 1.345000 3.185000 3.285000 ;
+ RECT 3.015000 3.285000 5.005000 3.615000 ;
+ RECT 3.185000 0.495000 3.535000 0.995000 ;
+ RECT 3.365000 0.995000 3.535000 3.105000 ;
+ RECT 3.715000 1.085000 3.885000 3.285000 ;
+ RECT 4.065000 0.495000 4.315000 0.965000 ;
+ RECT 4.065000 0.965000 6.315000 1.135000 ;
+ RECT 4.065000 1.135000 4.235000 2.605000 ;
+ RECT 4.065000 2.605000 4.395000 3.105000 ;
+ RECT 4.415000 1.495000 4.655000 1.805000 ;
+ RECT 4.415000 1.805000 6.985000 1.975000 ;
+ RECT 4.415000 1.975000 4.655000 2.165000 ;
+ RECT 4.835000 2.155000 6.635000 2.325000 ;
+ RECT 4.835000 2.325000 5.005000 3.285000 ;
+ RECT 4.855000 0.365000 5.805000 0.785000 ;
+ RECT 5.135000 1.315000 5.865000 1.625000 ;
+ RECT 5.185000 2.505000 6.285000 2.675000 ;
+ RECT 5.185000 2.675000 5.425000 3.555000 ;
+ RECT 5.605000 2.855000 5.935000 3.705000 ;
+ RECT 5.985000 0.265000 6.315000 0.965000 ;
+ RECT 6.115000 2.675000 6.895000 2.845000 ;
+ RECT 6.465000 2.325000 8.960000 2.495000 ;
+ RECT 6.565000 2.845000 6.895000 3.105000 ;
+ RECT 6.800000 0.365000 7.750000 1.375000 ;
+ RECT 6.815000 1.975000 8.450000 2.145000 ;
+ RECT 7.075000 2.675000 8.025000 3.705000 ;
+ RECT 8.280000 1.545000 8.785000 1.705000 ;
+ RECT 8.280000 1.705000 9.310000 1.875000 ;
+ RECT 8.280000 1.875000 8.450000 1.975000 ;
+ RECT 8.630000 2.085000 8.960000 2.325000 ;
+ RECT 8.695000 2.675000 9.310000 2.845000 ;
+ RECT 8.695000 2.845000 8.865000 3.595000 ;
+ RECT 8.695000 3.595000 9.825000 3.805000 ;
+ RECT 9.025000 1.190000 9.660000 1.475000 ;
+ RECT 9.045000 3.025000 9.660000 3.415000 ;
+ RECT 9.140000 1.875000 9.310000 2.675000 ;
+ RECT 9.490000 1.475000 9.660000 2.315000 ;
+ RECT 9.490000 2.315000 12.210000 2.485000 ;
+ RECT 9.490000 2.485000 9.660000 3.025000 ;
+ RECT 10.010000 2.665000 10.960000 3.705000 ;
+ RECT 10.305000 1.545000 10.635000 1.655000 ;
+ RECT 10.305000 1.655000 12.560000 1.825000 ;
+ RECT 10.305000 1.825000 10.635000 2.135000 ;
+ RECT 11.300000 3.255000 11.550000 3.755000 ;
+ RECT 11.340000 0.365000 11.930000 1.475000 ;
+ RECT 11.380000 3.005000 12.560000 3.175000 ;
+ RECT 11.380000 3.175000 11.550000 3.255000 ;
+ RECT 11.410000 2.485000 12.210000 2.675000 ;
+ RECT 11.410000 2.675000 11.740000 2.825000 ;
+ RECT 11.730000 3.355000 12.680000 3.735000 ;
+ RECT 11.880000 2.005000 12.210000 2.315000 ;
+ RECT 12.120000 0.975000 12.450000 1.655000 ;
+ RECT 12.390000 1.825000 12.560000 3.005000 ;
+ RECT 12.745000 0.975000 13.075000 1.475000 ;
+ RECT 12.865000 1.475000 13.075000 2.225000 ;
+ RECT 12.865000 2.225000 14.240000 2.395000 ;
+ RECT 12.865000 2.395000 13.115000 3.365000 ;
+ RECT 13.255000 0.365000 14.205000 1.475000 ;
+ RECT 13.295000 2.575000 14.240000 3.705000 ;
+ RECT 13.910000 1.725000 14.240000 2.225000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.575000 3.505000 0.745000 3.675000 ;
+ RECT 0.600000 0.395000 0.770000 0.565000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.935000 3.505000 1.105000 3.675000 ;
+ RECT 0.960000 0.395000 1.130000 0.565000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.295000 3.505000 1.465000 3.675000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.265000 3.505000 2.435000 3.675000 ;
+ RECT 2.470000 0.395000 2.640000 0.565000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.830000 0.395000 3.000000 0.565000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.885000 0.395000 5.055000 0.565000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ RECT 5.245000 0.395000 5.415000 0.565000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 3.985000 5.605000 4.155000 ;
+ RECT 5.605000 0.395000 5.775000 0.565000 ;
+ RECT 5.635000 3.505000 5.805000 3.675000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 3.985000 6.085000 4.155000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 3.985000 6.565000 4.155000 ;
+ RECT 6.830000 0.395000 7.000000 0.565000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 3.985000 7.045000 4.155000 ;
+ RECT 7.105000 3.505000 7.275000 3.675000 ;
+ RECT 7.190000 0.395000 7.360000 0.565000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 3.985000 7.525000 4.155000 ;
+ RECT 7.465000 3.505000 7.635000 3.675000 ;
+ RECT 7.550000 0.395000 7.720000 0.565000 ;
+ RECT 7.825000 3.505000 7.995000 3.675000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 3.985000 8.005000 4.155000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 3.985000 8.485000 4.155000 ;
+ RECT 8.795000 -0.085000 8.965000 0.085000 ;
+ RECT 8.795000 3.985000 8.965000 4.155000 ;
+ RECT 9.275000 -0.085000 9.445000 0.085000 ;
+ RECT 9.275000 3.985000 9.445000 4.155000 ;
+ RECT 9.755000 -0.085000 9.925000 0.085000 ;
+ RECT 9.755000 3.985000 9.925000 4.155000 ;
+ RECT 10.040000 3.505000 10.210000 3.675000 ;
+ RECT 10.235000 -0.085000 10.405000 0.085000 ;
+ RECT 10.235000 3.985000 10.405000 4.155000 ;
+ RECT 10.400000 3.505000 10.570000 3.675000 ;
+ RECT 10.715000 -0.085000 10.885000 0.085000 ;
+ RECT 10.715000 3.985000 10.885000 4.155000 ;
+ RECT 10.760000 3.505000 10.930000 3.675000 ;
+ RECT 11.195000 -0.085000 11.365000 0.085000 ;
+ RECT 11.195000 3.985000 11.365000 4.155000 ;
+ RECT 11.370000 0.395000 11.540000 0.565000 ;
+ RECT 11.675000 -0.085000 11.845000 0.085000 ;
+ RECT 11.675000 3.985000 11.845000 4.155000 ;
+ RECT 11.730000 0.395000 11.900000 0.565000 ;
+ RECT 11.760000 3.505000 11.930000 3.675000 ;
+ RECT 12.120000 3.505000 12.290000 3.675000 ;
+ RECT 12.155000 -0.085000 12.325000 0.085000 ;
+ RECT 12.155000 3.985000 12.325000 4.155000 ;
+ RECT 12.480000 3.505000 12.650000 3.675000 ;
+ RECT 12.635000 -0.085000 12.805000 0.085000 ;
+ RECT 12.635000 3.985000 12.805000 4.155000 ;
+ RECT 13.115000 -0.085000 13.285000 0.085000 ;
+ RECT 13.115000 3.985000 13.285000 4.155000 ;
+ RECT 13.285000 0.395000 13.455000 0.565000 ;
+ RECT 13.320000 3.505000 13.490000 3.675000 ;
+ RECT 13.595000 -0.085000 13.765000 0.085000 ;
+ RECT 13.595000 3.985000 13.765000 4.155000 ;
+ RECT 13.645000 0.395000 13.815000 0.565000 ;
+ RECT 13.680000 3.505000 13.850000 3.675000 ;
+ RECT 14.005000 0.395000 14.175000 0.565000 ;
+ RECT 14.040000 3.505000 14.210000 3.675000 ;
+ RECT 14.075000 -0.085000 14.245000 0.085000 ;
+ RECT 14.075000 3.985000 14.245000 4.155000 ;
+ RECT 14.555000 -0.085000 14.725000 0.085000 ;
+ RECT 14.555000 3.985000 14.725000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__dfstp_1
+MACRO sky130_fd_sc_hvl__probec_p_8
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__probec_p_8 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 9.600000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN A
+ ANTENNAGATEAREA 3.375000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.635000 1.580000 2.245000 1.815000 ;
+ END
+ END A
+ PIN X
+ ANTENNADIFFAREA 2.520000 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met4 ;
+ RECT 2.410000 1.445000 3.590000 2.625000 ;
+ RECT 5.010000 1.445000 6.190000 2.625000 ;
+ END
+ PORT
+ LAYER met5 ;
+ RECT 2.290000 1.235000 6.310000 2.835000 ;
+ RECT 4.710000 -0.365000 6.310000 1.235000 ;
+ RECT 4.710000 2.835000 6.310000 4.435000 ;
+ END
+ END X
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met5 ;
+ RECT 7.910000 -0.365000 10.410000 1.235000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 9.600000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 9.600000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met5 ;
+ RECT 7.910000 2.835000 10.410000 4.435000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 9.600000 0.085000 ;
+ RECT 0.000000 3.985000 9.600000 4.155000 ;
+ RECT 0.245000 0.805000 0.455000 1.475000 ;
+ RECT 0.245000 1.475000 0.435000 2.095000 ;
+ RECT 0.245000 2.095000 2.595000 2.265000 ;
+ RECT 0.245000 2.265000 0.435000 3.545000 ;
+ RECT 0.615000 2.445000 1.865000 3.625000 ;
+ RECT 0.615000 3.625000 9.505000 3.795000 ;
+ RECT 0.675000 0.380000 9.505000 0.550000 ;
+ RECT 0.675000 0.550000 1.925000 1.385000 ;
+ RECT 2.045000 2.265000 2.595000 3.445000 ;
+ RECT 2.105000 0.730000 2.315000 1.230000 ;
+ RECT 2.105000 1.230000 2.595000 1.400000 ;
+ RECT 2.425000 1.400000 2.595000 1.625000 ;
+ RECT 2.425000 1.625000 3.380000 1.955000 ;
+ RECT 2.425000 1.955000 2.595000 2.095000 ;
+ RECT 2.605000 0.550000 3.495000 0.760000 ;
+ RECT 2.765000 0.760000 3.495000 1.445000 ;
+ RECT 2.765000 2.385000 3.435000 3.625000 ;
+ RECT 3.605000 1.955000 8.965000 2.205000 ;
+ RECT 3.605000 2.205000 3.935000 3.445000 ;
+ RECT 3.665000 0.805000 3.875000 1.625000 ;
+ RECT 3.665000 1.625000 8.965000 1.955000 ;
+ RECT 4.045000 0.550000 5.055000 1.445000 ;
+ RECT 4.105000 2.385000 4.995000 3.625000 ;
+ RECT 5.165000 2.205000 5.495000 3.445000 ;
+ RECT 5.225000 0.805000 5.435000 1.625000 ;
+ RECT 5.605000 0.550000 6.615000 1.445000 ;
+ RECT 5.665000 2.385000 6.555000 3.625000 ;
+ RECT 6.725000 2.205000 7.055000 3.445000 ;
+ RECT 6.785000 0.805000 6.995000 1.625000 ;
+ RECT 7.165000 0.550000 8.175000 1.445000 ;
+ RECT 7.225000 2.385000 8.115000 3.625000 ;
+ RECT 8.285000 2.205000 8.965000 3.230000 ;
+ RECT 8.285000 3.230000 8.735000 3.445000 ;
+ RECT 8.345000 0.805000 8.965000 1.625000 ;
+ RECT 8.905000 3.475000 9.505000 3.625000 ;
+ RECT 8.975000 0.550000 9.505000 0.600000 ;
+ RECT 9.135000 0.600000 9.505000 1.445000 ;
+ RECT 9.135000 2.385000 9.505000 3.475000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.615000 3.475000 0.785000 3.645000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.975000 3.475000 1.145000 3.645000 ;
+ RECT 1.035000 0.380000 1.205000 0.550000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.335000 3.475000 1.505000 3.645000 ;
+ RECT 1.395000 0.380000 1.565000 0.550000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 1.695000 3.475000 1.865000 3.645000 ;
+ RECT 1.755000 0.380000 1.925000 0.550000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.605000 0.380000 2.775000 0.550000 ;
+ RECT 2.770000 3.475000 2.940000 3.645000 ;
+ RECT 2.965000 0.380000 3.135000 0.550000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.130000 3.475000 3.300000 3.645000 ;
+ RECT 3.325000 0.380000 3.495000 0.550000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.070000 0.380000 4.240000 0.550000 ;
+ RECT 4.105000 3.475000 4.275000 3.645000 ;
+ RECT 4.430000 0.380000 4.600000 0.550000 ;
+ RECT 4.465000 3.475000 4.635000 3.645000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.790000 0.380000 4.960000 0.550000 ;
+ RECT 4.825000 3.475000 4.995000 3.645000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 3.985000 5.605000 4.155000 ;
+ RECT 5.620000 1.950000 5.790000 2.120000 ;
+ RECT 5.665000 3.475000 5.835000 3.645000 ;
+ RECT 5.670000 0.380000 5.840000 0.550000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 3.985000 6.085000 4.155000 ;
+ RECT 5.980000 1.950000 6.150000 2.120000 ;
+ RECT 6.025000 3.475000 6.195000 3.645000 ;
+ RECT 6.030000 0.380000 6.200000 0.550000 ;
+ RECT 6.385000 3.475000 6.555000 3.645000 ;
+ RECT 6.390000 0.380000 6.560000 0.550000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 3.985000 6.565000 4.155000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 3.985000 7.045000 4.155000 ;
+ RECT 7.230000 3.475000 7.400000 3.645000 ;
+ RECT 7.235000 0.380000 7.405000 0.550000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 3.985000 7.525000 4.155000 ;
+ RECT 7.595000 0.380000 7.765000 0.550000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 3.985000 8.005000 4.155000 ;
+ RECT 7.945000 3.475000 8.115000 3.645000 ;
+ RECT 7.955000 0.380000 8.125000 0.550000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 3.985000 8.485000 4.155000 ;
+ RECT 8.795000 -0.085000 8.965000 0.085000 ;
+ RECT 8.795000 3.985000 8.965000 4.155000 ;
+ RECT 8.975000 0.380000 9.145000 0.550000 ;
+ RECT 9.265000 3.475000 9.435000 3.645000 ;
+ RECT 9.275000 -0.085000 9.445000 0.085000 ;
+ RECT 9.275000 3.985000 9.445000 4.155000 ;
+ RECT 9.335000 0.380000 9.505000 0.550000 ;
+ LAYER met1 ;
+ RECT 0.000000 0.255000 9.600000 0.305000 ;
+ RECT 0.000000 0.305000 9.920000 0.565000 ;
+ RECT 0.000000 0.565000 9.600000 0.625000 ;
+ RECT 0.000000 3.445000 9.600000 3.505000 ;
+ RECT 0.000000 3.505000 9.920000 3.765000 ;
+ RECT 0.000000 3.765000 9.600000 3.815000 ;
+ RECT 5.560000 1.905000 6.210000 2.165000 ;
+ LAYER met2 ;
+ RECT 5.440000 1.895000 6.210000 2.175000 ;
+ RECT 9.215000 0.285000 9.985000 0.565000 ;
+ RECT 9.215000 3.505000 9.985000 3.785000 ;
+ LAYER met3 ;
+ RECT 2.835000 1.875000 3.615000 2.195000 ;
+ RECT 5.435000 1.870000 6.215000 2.200000 ;
+ RECT 9.210000 0.260000 9.990000 0.590000 ;
+ RECT 9.210000 3.480000 9.990000 3.810000 ;
+ LAYER met4 ;
+ RECT 9.010000 -0.155000 10.190000 1.025000 ;
+ RECT 9.010000 3.045000 10.190000 4.225000 ;
+ LAYER via ;
+ RECT 5.600000 1.905000 5.860000 2.165000 ;
+ RECT 5.920000 1.905000 6.180000 2.165000 ;
+ RECT 9.310000 0.305000 9.570000 0.565000 ;
+ RECT 9.310000 3.505000 9.570000 3.765000 ;
+ RECT 9.630000 0.305000 9.890000 0.565000 ;
+ RECT 9.630000 3.505000 9.890000 3.765000 ;
+ LAYER via2 ;
+ RECT 5.485000 1.895000 5.765000 2.175000 ;
+ RECT 5.885000 1.895000 6.165000 2.175000 ;
+ RECT 9.260000 0.285000 9.540000 0.565000 ;
+ RECT 9.260000 3.505000 9.540000 3.785000 ;
+ RECT 9.660000 0.285000 9.940000 0.565000 ;
+ RECT 9.660000 3.505000 9.940000 3.785000 ;
+ LAYER via3 ;
+ RECT 2.865000 1.875000 3.185000 2.195000 ;
+ RECT 3.265000 1.875000 3.585000 2.195000 ;
+ RECT 5.465000 1.875000 5.785000 2.195000 ;
+ RECT 5.865000 1.875000 6.185000 2.195000 ;
+ RECT 9.240000 0.265000 9.560000 0.585000 ;
+ RECT 9.240000 3.485000 9.560000 3.805000 ;
+ RECT 9.640000 0.265000 9.960000 0.585000 ;
+ RECT 9.640000 3.485000 9.960000 3.805000 ;
+ END
+END sky130_fd_sc_hvl__probec_p_8
+MACRO sky130_fd_sc_hvl__a21o_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__a21o_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 4.320000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN A1
+ ANTENNAGATEAREA 1.125000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.805000 1.505000 3.715000 1.835000 ;
+ END
+ END A1
+ PIN A2
+ ANTENNAGATEAREA 1.125000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 3.895000 1.505000 4.195000 1.835000 ;
+ END
+ END A2
+ PIN B1
+ ANTENNAGATEAREA 1.125000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.085000 1.505000 2.275000 1.750000 ;
+ END
+ END B1
+ PIN X
+ ANTENNADIFFAREA 0.611250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.110000 0.495000 0.460000 1.325000 ;
+ RECT 0.110000 1.325000 0.360000 3.735000 ;
+ END
+ END X
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 4.320000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 4.320000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 4.320000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 4.320000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 4.320000 0.085000 ;
+ RECT 0.000000 3.985000 4.320000 4.155000 ;
+ RECT 0.540000 2.280000 1.440000 3.755000 ;
+ RECT 0.565000 1.725000 0.895000 1.930000 ;
+ RECT 0.565000 1.930000 2.625000 2.100000 ;
+ RECT 0.640000 0.365000 2.250000 1.325000 ;
+ RECT 1.620000 2.100000 1.870000 3.755000 ;
+ RECT 2.320000 2.280000 4.210000 2.450000 ;
+ RECT 2.320000 2.450000 2.650000 3.755000 ;
+ RECT 2.430000 0.495000 2.680000 1.325000 ;
+ RECT 2.455000 1.325000 2.625000 1.930000 ;
+ RECT 2.830000 2.630000 3.780000 3.755000 ;
+ RECT 2.860000 0.365000 4.170000 1.325000 ;
+ RECT 3.960000 2.195000 4.210000 2.280000 ;
+ RECT 3.960000 2.450000 4.210000 3.735000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.545000 3.505000 0.715000 3.675000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.640000 0.395000 0.810000 0.565000 ;
+ RECT 0.905000 3.505000 1.075000 3.675000 ;
+ RECT 1.000000 0.395000 1.170000 0.565000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.265000 3.505000 1.435000 3.675000 ;
+ RECT 1.360000 0.395000 1.530000 0.565000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 1.720000 0.395000 1.890000 0.565000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.080000 0.395000 2.250000 0.565000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.860000 3.505000 3.030000 3.675000 ;
+ RECT 2.890000 0.395000 3.060000 0.565000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.220000 3.505000 3.390000 3.675000 ;
+ RECT 3.250000 0.395000 3.420000 0.565000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.580000 3.505000 3.750000 3.675000 ;
+ RECT 3.610000 0.395000 3.780000 0.565000 ;
+ RECT 3.970000 0.395000 4.140000 0.565000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__a21o_1
+MACRO sky130_fd_sc_hvl__xor2_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__xor2_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 5.280000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN A
+ ANTENNAGATEAREA 2.250000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.045000 1.775000 3.235000 2.150000 ;
+ END
+ END A
+ PIN B
+ ANTENNAGATEAREA 2.250000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.560000 1.775000 1.510000 2.055000 ;
+ RECT 1.340000 1.425000 3.585000 1.505000 ;
+ RECT 1.340000 1.505000 3.715000 1.595000 ;
+ RECT 1.340000 1.595000 1.510000 1.775000 ;
+ RECT 3.415000 1.595000 3.715000 1.835000 ;
+ END
+ END B
+ PIN X
+ ANTENNADIFFAREA 0.637500 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 3.850000 0.495000 4.370000 1.325000 ;
+ RECT 3.965000 1.325000 4.370000 2.425000 ;
+ END
+ END X
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 5.280000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 5.280000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 5.280000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 5.280000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 5.280000 0.085000 ;
+ RECT 0.000000 3.985000 5.280000 4.155000 ;
+ RECT 0.090000 0.365000 0.680000 1.245000 ;
+ RECT 0.130000 1.425000 1.160000 1.595000 ;
+ RECT 0.130000 1.595000 0.380000 2.435000 ;
+ RECT 0.130000 2.435000 3.230000 2.605000 ;
+ RECT 0.130000 2.605000 0.380000 3.755000 ;
+ RECT 0.560000 2.785000 2.530000 3.755000 ;
+ RECT 0.910000 0.495000 1.160000 1.425000 ;
+ RECT 1.340000 0.365000 3.670000 1.245000 ;
+ RECT 2.710000 2.785000 2.880000 2.955000 ;
+ RECT 2.710000 2.955000 5.150000 3.125000 ;
+ RECT 2.710000 3.125000 2.880000 3.755000 ;
+ RECT 3.060000 2.605000 4.720000 2.775000 ;
+ RECT 3.060000 3.305000 4.720000 3.755000 ;
+ RECT 4.550000 0.365000 5.140000 1.325000 ;
+ RECT 4.550000 1.665000 4.880000 1.995000 ;
+ RECT 4.550000 1.995000 4.720000 2.605000 ;
+ RECT 4.900000 2.175000 5.150000 2.955000 ;
+ RECT 4.900000 3.125000 5.150000 3.755000 ;
+ LAYER mcon ;
+ RECT 0.120000 0.395000 0.290000 0.565000 ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.480000 0.395000 0.650000 0.565000 ;
+ RECT 0.560000 3.505000 0.730000 3.675000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.920000 3.505000 1.090000 3.675000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.280000 3.505000 1.450000 3.675000 ;
+ RECT 1.340000 0.395000 1.510000 0.565000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 1.640000 3.505000 1.810000 3.675000 ;
+ RECT 1.700000 0.395000 1.870000 0.565000 ;
+ RECT 2.000000 3.505000 2.170000 3.675000 ;
+ RECT 2.060000 0.395000 2.230000 0.565000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.360000 3.505000 2.530000 3.675000 ;
+ RECT 2.420000 0.395000 2.590000 0.565000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.780000 0.395000 2.950000 0.565000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.085000 3.505000 3.255000 3.675000 ;
+ RECT 3.140000 0.395000 3.310000 0.565000 ;
+ RECT 3.445000 3.505000 3.615000 3.675000 ;
+ RECT 3.500000 0.395000 3.670000 0.565000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.805000 3.505000 3.975000 3.675000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.165000 3.505000 4.335000 3.675000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.525000 3.505000 4.695000 3.675000 ;
+ RECT 4.580000 0.395000 4.750000 0.565000 ;
+ RECT 4.940000 0.395000 5.110000 0.565000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__xor2_1
+MACRO sky130_fd_sc_hvl__xnor2_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__xnor2_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 5.280000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN A
+ ANTENNAGATEAREA 2.250000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.085000 1.580000 2.060000 1.750000 ;
+ END
+ END A
+ PIN B
+ ANTENNAGATEAREA 2.250000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.575000 1.725000 0.905000 1.930000 ;
+ RECT 0.575000 1.930000 3.255000 2.100000 ;
+ RECT 1.565000 2.100000 3.255000 2.120000 ;
+ RECT 2.925000 1.805000 3.255000 1.930000 ;
+ END
+ END B
+ PIN Y
+ ANTENNADIFFAREA 1.481250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 4.025000 1.905000 5.155000 2.075000 ;
+ RECT 4.025000 2.075000 4.275000 3.755000 ;
+ RECT 4.445000 1.545000 5.155000 1.905000 ;
+ RECT 4.750000 0.535000 5.155000 1.545000 ;
+ END
+ END Y
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 5.280000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 5.280000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 5.280000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 5.280000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 5.280000 0.085000 ;
+ RECT 0.000000 3.985000 5.280000 4.155000 ;
+ RECT 0.090000 2.630000 0.985000 3.755000 ;
+ RECT 0.110000 0.495000 0.440000 1.230000 ;
+ RECT 0.110000 1.230000 2.410000 1.400000 ;
+ RECT 0.110000 1.400000 0.360000 2.280000 ;
+ RECT 0.110000 2.280000 1.335000 2.450000 ;
+ RECT 0.610000 0.365000 2.410000 1.050000 ;
+ RECT 1.165000 2.450000 1.335000 3.755000 ;
+ RECT 1.515000 2.300000 3.845000 3.755000 ;
+ RECT 2.240000 1.400000 2.410000 1.455000 ;
+ RECT 2.240000 1.455000 3.980000 1.625000 ;
+ RECT 2.590000 0.495000 2.920000 1.105000 ;
+ RECT 2.590000 1.105000 4.300000 1.285000 ;
+ RECT 3.100000 0.365000 3.630000 0.925000 ;
+ RECT 3.650000 1.625000 3.980000 1.725000 ;
+ RECT 3.970000 0.535000 4.300000 1.105000 ;
+ RECT 4.465000 2.255000 5.055000 3.755000 ;
+ LAYER mcon ;
+ RECT 0.095000 3.505000 0.265000 3.675000 ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.455000 3.505000 0.625000 3.675000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.800000 0.395000 0.970000 0.565000 ;
+ RECT 0.815000 3.505000 0.985000 3.675000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.160000 0.395000 1.330000 0.565000 ;
+ RECT 1.515000 3.505000 1.685000 3.675000 ;
+ RECT 1.520000 0.395000 1.690000 0.565000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 1.875000 3.505000 2.045000 3.675000 ;
+ RECT 1.880000 0.395000 2.050000 0.565000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.235000 3.505000 2.405000 3.675000 ;
+ RECT 2.240000 0.395000 2.410000 0.565000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.595000 3.505000 2.765000 3.675000 ;
+ RECT 2.955000 3.505000 3.125000 3.675000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.100000 0.395000 3.270000 0.565000 ;
+ RECT 3.315000 3.505000 3.485000 3.675000 ;
+ RECT 3.460000 0.395000 3.630000 0.565000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.675000 3.505000 3.845000 3.675000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.495000 3.505000 4.665000 3.675000 ;
+ RECT 4.855000 3.505000 5.025000 3.675000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__xnor2_1
+MACRO sky130_fd_sc_hvl__or3_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__or3_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 3.840000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN A
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.915000 1.080000 2.450000 1.390000 ;
+ END
+ END A
+ PIN B
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.605000 1.910000 1.535000 3.260000 ;
+ END
+ END B
+ PIN C
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.530000 1.080000 1.315000 1.390000 ;
+ END
+ END C
+ PIN X
+ ANTENNADIFFAREA 0.626250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 3.460000 0.495000 3.715000 3.755000 ;
+ END
+ END X
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 3.840000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 3.840000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 3.840000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 3.840000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 3.840000 0.085000 ;
+ RECT 0.000000 3.985000 3.840000 4.155000 ;
+ RECT 0.145000 0.495000 0.360000 1.560000 ;
+ RECT 0.145000 1.560000 3.255000 1.730000 ;
+ RECT 0.145000 1.730000 0.395000 2.780000 ;
+ RECT 0.530000 0.365000 1.385000 0.910000 ;
+ RECT 1.565000 0.495000 1.965000 0.910000 ;
+ RECT 1.565000 0.910000 1.735000 1.560000 ;
+ RECT 1.620000 3.430000 3.280000 3.755000 ;
+ RECT 1.705000 2.175000 3.280000 3.430000 ;
+ RECT 2.620000 0.365000 3.290000 1.325000 ;
+ RECT 2.925000 1.730000 3.255000 1.935000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.580000 0.395000 0.750000 0.565000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.165000 0.395000 1.335000 0.565000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 1.670000 3.505000 1.840000 3.675000 ;
+ RECT 2.030000 3.505000 2.200000 3.675000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.390000 3.505000 2.560000 3.675000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.690000 0.395000 2.860000 0.565000 ;
+ RECT 2.750000 3.505000 2.920000 3.675000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.050000 0.395000 3.220000 0.565000 ;
+ RECT 3.110000 3.505000 3.280000 3.675000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__or3_1
+MACRO sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 13.92000 BY 8.140000 ;
+ SYMMETRY X Y ;
+ SITE unithvdbl ;
+ PIN A
+ ANTENNAGATEAREA 0.279000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 9.205000 1.685000 9.895000 2.015000 ;
+ END
+ END A
+ PIN SLEEP_B
+ ANTENNAGATEAREA 7.125000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 4.730000 1.830000 5.400000 2.160000 ;
+ END
+ END SLEEP_B
+ PIN X
+ ANTENNADIFFAREA 0.397500 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.755000 1.315000 1.175000 1.605000 ;
+ RECT 0.755000 1.605000 0.975000 2.405000 ;
+ RECT 0.755000 2.405000 1.175000 2.695000 ;
+ RECT 0.955000 0.895000 1.175000 1.315000 ;
+ RECT 0.955000 2.695000 1.175000 3.075000 ;
+ END
+ END X
+ PIN LVPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.070000 3.020000 13.850000 3.305000 ;
+ END
+ END LVPWR
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 7.515000 13.920000 7.885000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 8.025000 13.920000 8.255000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 13.920000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 4.325000 13.920000 4.695000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 13.920000 0.085000 ;
+ RECT 0.000000 3.985000 0.685000 4.155000 ;
+ RECT 0.000000 8.055000 13.920000 8.225000 ;
+ RECT 0.360000 4.155000 0.530000 5.280000 ;
+ RECT 0.895000 4.575000 2.780000 4.795000 ;
+ RECT 0.895000 4.795000 1.115000 6.055000 ;
+ RECT 0.895000 6.055000 1.955000 6.275000 ;
+ RECT 0.955000 6.445000 1.175000 7.625000 ;
+ RECT 0.955000 7.625000 4.900000 7.845000 ;
+ RECT 1.365000 5.555000 2.035000 5.665000 ;
+ RECT 1.365000 5.665000 5.675000 5.885000 ;
+ RECT 1.400000 0.395000 1.990000 0.625000 ;
+ RECT 1.735000 6.275000 1.955000 7.455000 ;
+ RECT 1.760000 0.625000 1.990000 1.565000 ;
+ RECT 1.760000 2.405000 1.930000 3.445000 ;
+ RECT 1.760000 3.445000 2.350000 3.735000 ;
+ RECT 2.110000 4.295000 2.780000 4.575000 ;
+ RECT 2.260000 0.645000 2.480000 2.860000 ;
+ RECT 2.260000 2.860000 2.780000 3.085000 ;
+ RECT 2.515000 6.445000 2.735000 7.625000 ;
+ RECT 2.560000 3.085000 2.780000 4.295000 ;
+ RECT 2.650000 1.830000 3.320000 1.940000 ;
+ RECT 2.650000 1.940000 4.425000 2.160000 ;
+ RECT 3.060000 3.445000 3.645000 3.735000 ;
+ RECT 3.175000 0.395000 3.765000 0.625000 ;
+ RECT 3.175000 4.410000 3.645000 4.630000 ;
+ RECT 3.175000 4.630000 3.395000 5.405000 ;
+ RECT 3.295000 5.885000 3.515000 7.455000 ;
+ RECT 3.360000 0.625000 3.590000 1.655000 ;
+ RECT 3.425000 2.405000 3.645000 3.445000 ;
+ RECT 3.425000 3.735000 3.645000 4.410000 ;
+ RECT 4.075000 6.445000 4.295000 7.625000 ;
+ RECT 4.205000 0.645000 4.425000 1.940000 ;
+ RECT 4.205000 2.160000 4.425000 3.755000 ;
+ RECT 4.680000 6.295000 8.445000 6.515000 ;
+ RECT 4.680000 6.515000 4.900000 7.625000 ;
+ RECT 5.455000 4.945000 5.675000 5.665000 ;
+ RECT 6.465000 1.305000 6.685000 6.295000 ;
+ RECT 7.155000 0.395000 7.745000 0.625000 ;
+ RECT 7.340000 0.625000 7.570000 6.055000 ;
+ RECT 7.750000 7.075000 9.535000 7.405000 ;
+ RECT 8.225000 1.305000 8.445000 6.295000 ;
+ RECT 9.100000 3.905000 10.035000 4.235000 ;
+ RECT 9.205000 4.775000 9.535000 7.075000 ;
+ RECT 9.305000 0.395000 9.895000 0.625000 ;
+ RECT 9.305000 3.020000 9.895000 3.365000 ;
+ RECT 9.565000 0.625000 9.895000 1.515000 ;
+ RECT 9.565000 2.335000 9.895000 3.020000 ;
+ RECT 9.565000 3.365000 9.895000 3.905000 ;
+ RECT 9.705000 4.235000 10.035000 5.805000 ;
+ RECT 9.705000 6.125000 10.535000 6.455000 ;
+ RECT 9.705000 6.625000 10.035000 7.520000 ;
+ RECT 9.705000 7.520000 10.295000 7.750000 ;
+ RECT 10.065000 0.735000 10.395000 3.035000 ;
+ RECT 10.065000 3.035000 10.535000 3.365000 ;
+ RECT 10.205000 3.365000 10.535000 6.125000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.155000 8.055000 0.325000 8.225000 ;
+ RECT 0.515000 3.985000 0.685000 4.155000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 8.055000 0.805000 8.225000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 8.055000 1.285000 8.225000 ;
+ RECT 1.430000 0.425000 1.600000 0.595000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 8.055000 1.765000 8.225000 ;
+ RECT 1.790000 0.425000 1.960000 0.595000 ;
+ RECT 1.790000 3.505000 1.960000 3.675000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 8.055000 2.245000 8.225000 ;
+ RECT 2.150000 3.505000 2.320000 3.675000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 8.055000 2.725000 8.225000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 8.055000 3.205000 8.225000 ;
+ RECT 3.090000 3.505000 3.260000 3.675000 ;
+ RECT 3.205000 0.425000 3.375000 0.595000 ;
+ RECT 3.450000 3.505000 3.620000 3.675000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 8.055000 3.685000 8.225000 ;
+ RECT 3.565000 0.425000 3.735000 0.595000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 8.055000 4.165000 8.225000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 8.055000 4.645000 8.225000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 8.055000 5.125000 8.225000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 8.055000 5.605000 8.225000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 8.055000 6.085000 8.225000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 8.055000 6.565000 8.225000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 8.055000 7.045000 8.225000 ;
+ RECT 7.185000 0.425000 7.355000 0.595000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 8.055000 7.525000 8.225000 ;
+ RECT 7.545000 0.425000 7.715000 0.595000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 8.055000 8.005000 8.225000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 8.055000 8.485000 8.225000 ;
+ RECT 8.795000 -0.085000 8.965000 0.085000 ;
+ RECT 8.795000 8.055000 8.965000 8.225000 ;
+ RECT 9.275000 -0.085000 9.445000 0.085000 ;
+ RECT 9.275000 8.055000 9.445000 8.225000 ;
+ RECT 9.335000 0.425000 9.505000 0.595000 ;
+ RECT 9.335000 3.080000 9.505000 3.250000 ;
+ RECT 9.695000 0.425000 9.865000 0.595000 ;
+ RECT 9.695000 3.080000 9.865000 3.250000 ;
+ RECT 9.735000 7.550000 9.905000 7.720000 ;
+ RECT 9.755000 -0.085000 9.925000 0.085000 ;
+ RECT 9.755000 8.055000 9.925000 8.225000 ;
+ RECT 10.095000 7.550000 10.265000 7.720000 ;
+ RECT 10.235000 -0.085000 10.405000 0.085000 ;
+ RECT 10.235000 8.055000 10.405000 8.225000 ;
+ RECT 10.715000 -0.085000 10.885000 0.085000 ;
+ RECT 10.715000 8.055000 10.885000 8.225000 ;
+ RECT 11.195000 -0.085000 11.365000 0.085000 ;
+ RECT 11.195000 8.055000 11.365000 8.225000 ;
+ RECT 11.675000 -0.085000 11.845000 0.085000 ;
+ RECT 11.675000 8.055000 11.845000 8.225000 ;
+ RECT 12.155000 -0.085000 12.325000 0.085000 ;
+ RECT 12.155000 8.055000 12.325000 8.225000 ;
+ RECT 12.635000 -0.085000 12.805000 0.085000 ;
+ RECT 12.635000 8.055000 12.805000 8.225000 ;
+ RECT 13.115000 -0.085000 13.285000 0.085000 ;
+ RECT 13.115000 8.055000 13.285000 8.225000 ;
+ RECT 13.595000 -0.085000 13.765000 0.085000 ;
+ RECT 13.595000 8.055000 13.765000 8.225000 ;
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 13.920000 0.115000 ;
+ RECT 0.000000 0.255000 13.920000 0.625000 ;
+ RECT 0.000000 3.445000 13.920000 3.815000 ;
+ END
+END sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1
+MACRO sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 11.04000 BY 8.140000 ;
+ SYMMETRY X Y ;
+ SITE unithvdbl ;
+ PIN A
+ ANTENNAGATEAREA 0.252000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.495000 1.530000 2.805000 2.200000 ;
+ END
+ END A
+ PIN X
+ ANTENNADIFFAREA 0.596250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 10.600000 4.405000 10.930000 6.055000 ;
+ RECT 10.600000 6.725000 10.930000 7.625000 ;
+ RECT 10.690000 6.055000 10.930000 6.725000 ;
+ END
+ END X
+ PIN LVPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.070000 3.020000 10.970000 3.305000 ;
+ END
+ END LVPWR
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 7.515000 11.040000 7.885000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 8.025000 11.040000 8.255000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 11.040000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 4.325000 11.040000 4.695000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 11.040000 0.085000 ;
+ RECT 0.000000 3.985000 0.800000 4.155000 ;
+ RECT 0.000000 8.055000 11.040000 8.225000 ;
+ RECT 2.885000 2.765000 3.265000 3.055000 ;
+ RECT 2.885000 3.055000 3.175000 5.495000 ;
+ RECT 2.975000 0.735000 3.265000 1.745000 ;
+ RECT 2.975000 1.745000 4.310000 1.995000 ;
+ RECT 2.975000 1.995000 3.265000 2.765000 ;
+ RECT 3.095000 0.335000 4.045000 0.565000 ;
+ RECT 3.145000 6.165000 3.735000 7.715000 ;
+ RECT 3.145000 7.715000 5.295000 7.885000 ;
+ RECT 3.345000 3.225000 4.115000 4.200000 ;
+ RECT 3.435000 0.565000 3.705000 1.575000 ;
+ RECT 3.435000 2.165000 3.705000 3.075000 ;
+ RECT 3.435000 3.075000 4.115000 3.225000 ;
+ RECT 3.875000 0.735000 4.185000 1.245000 ;
+ RECT 3.875000 1.245000 4.810000 1.575000 ;
+ RECT 3.875000 2.165000 5.790000 2.475000 ;
+ RECT 3.875000 2.475000 4.185000 2.905000 ;
+ RECT 4.055000 5.665000 7.025000 5.995000 ;
+ RECT 4.055000 5.995000 4.385000 7.545000 ;
+ RECT 4.480000 1.575000 4.810000 2.145000 ;
+ RECT 4.480000 2.145000 5.790000 2.165000 ;
+ RECT 4.705000 6.165000 5.295000 7.715000 ;
+ RECT 5.050000 0.255000 7.200000 0.425000 ;
+ RECT 5.050000 0.425000 5.640000 1.975000 ;
+ RECT 5.960000 0.595000 6.290000 2.145000 ;
+ RECT 5.960000 2.145000 7.850000 2.325000 ;
+ RECT 6.565000 2.795000 6.895000 4.405000 ;
+ RECT 6.565000 4.405000 7.025000 4.735000 ;
+ RECT 6.610000 0.425000 7.200000 1.975000 ;
+ RECT 6.695000 4.735000 7.025000 5.665000 ;
+ RECT 6.695000 5.995000 7.025000 6.285000 ;
+ RECT 6.695000 6.285000 8.815000 6.615000 ;
+ RECT 7.095000 2.495000 9.835000 2.705000 ;
+ RECT 7.095000 2.705000 7.765000 4.215000 ;
+ RECT 7.390000 4.405000 7.980000 5.945000 ;
+ RECT 7.520000 0.255000 9.410000 0.425000 ;
+ RECT 7.520000 0.425000 7.850000 2.145000 ;
+ RECT 7.955000 2.875000 8.545000 3.705000 ;
+ RECT 8.170000 0.595000 8.760000 2.495000 ;
+ RECT 8.235000 3.985000 11.040000 4.155000 ;
+ RECT 8.300000 4.405000 8.630000 6.285000 ;
+ RECT 8.535000 6.615000 8.815000 6.955000 ;
+ RECT 8.915000 2.705000 9.835000 3.465000 ;
+ RECT 8.995000 4.405000 9.325000 6.225000 ;
+ RECT 8.995000 6.225000 10.520000 6.555000 ;
+ RECT 8.995000 6.555000 9.325000 7.625000 ;
+ RECT 9.080000 0.425000 9.410000 2.055000 ;
+ RECT 9.690000 4.405000 10.280000 5.945000 ;
+ RECT 9.690000 6.835000 10.280000 7.745000 ;
+ RECT 10.125000 2.795000 10.715000 3.705000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.155000 8.055000 0.325000 8.225000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 8.055000 0.805000 8.225000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 8.055000 1.285000 8.225000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 8.055000 1.765000 8.225000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 8.055000 2.245000 8.225000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 8.055000 2.725000 8.225000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 8.055000 3.205000 8.225000 ;
+ RECT 3.125000 0.365000 3.295000 0.535000 ;
+ RECT 3.175000 7.545000 3.345000 7.715000 ;
+ RECT 3.485000 0.425000 3.655000 0.595000 ;
+ RECT 3.485000 3.050000 3.655000 3.220000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 8.055000 3.685000 8.225000 ;
+ RECT 3.535000 7.545000 3.705000 7.715000 ;
+ RECT 3.845000 0.365000 4.015000 0.535000 ;
+ RECT 3.845000 3.105000 4.015000 3.275000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 8.055000 4.165000 8.225000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 8.055000 4.645000 8.225000 ;
+ RECT 4.735000 7.545000 4.905000 7.715000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 8.055000 5.125000 8.225000 ;
+ RECT 5.080000 0.425000 5.250000 0.595000 ;
+ RECT 5.095000 7.545000 5.265000 7.715000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 8.055000 5.605000 8.225000 ;
+ RECT 5.440000 0.425000 5.610000 0.595000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 8.055000 6.085000 8.225000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 8.055000 6.565000 8.225000 ;
+ RECT 6.640000 0.425000 6.810000 0.595000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 8.055000 7.045000 8.225000 ;
+ RECT 7.000000 0.425000 7.170000 0.595000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 8.055000 7.525000 8.225000 ;
+ RECT 7.420000 4.495000 7.590000 4.665000 ;
+ RECT 7.780000 4.495000 7.950000 4.665000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 8.055000 8.005000 8.225000 ;
+ RECT 7.985000 3.475000 8.155000 3.645000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 3.985000 8.485000 4.155000 ;
+ RECT 8.315000 8.055000 8.485000 8.225000 ;
+ RECT 8.345000 3.475000 8.515000 3.645000 ;
+ RECT 8.795000 -0.085000 8.965000 0.085000 ;
+ RECT 8.795000 3.985000 8.965000 4.155000 ;
+ RECT 8.795000 8.055000 8.965000 8.225000 ;
+ RECT 9.275000 -0.085000 9.445000 0.085000 ;
+ RECT 9.275000 3.985000 9.445000 4.155000 ;
+ RECT 9.275000 8.055000 9.445000 8.225000 ;
+ RECT 9.720000 4.495000 9.890000 4.665000 ;
+ RECT 9.720000 7.545000 9.890000 7.715000 ;
+ RECT 9.755000 -0.085000 9.925000 0.085000 ;
+ RECT 9.755000 3.985000 9.925000 4.155000 ;
+ RECT 9.755000 8.055000 9.925000 8.225000 ;
+ RECT 10.080000 4.495000 10.250000 4.665000 ;
+ RECT 10.080000 7.545000 10.250000 7.715000 ;
+ RECT 10.155000 3.475000 10.325000 3.645000 ;
+ RECT 10.235000 -0.085000 10.405000 0.085000 ;
+ RECT 10.235000 3.985000 10.405000 4.155000 ;
+ RECT 10.235000 8.055000 10.405000 8.225000 ;
+ RECT 10.515000 3.475000 10.685000 3.645000 ;
+ RECT 10.715000 -0.085000 10.885000 0.085000 ;
+ RECT 10.715000 3.985000 10.885000 4.155000 ;
+ RECT 10.715000 8.055000 10.885000 8.225000 ;
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 11.040000 0.115000 ;
+ RECT 0.000000 0.255000 11.040000 0.625000 ;
+ RECT 0.000000 3.445000 11.040000 3.815000 ;
+ END
+END sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1
+MACRO sky130_fd_sc_hvl__and3_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__and3_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 3.840000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN A
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.605000 0.810000 0.935000 1.645000 ;
+ END
+ END A
+ PIN B
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.605000 2.175000 1.565000 2.490000 ;
+ END
+ END B
+ PIN C
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.115000 0.810000 2.255000 1.645000 ;
+ END
+ END C
+ PIN X
+ ANTENNADIFFAREA 0.626250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 3.365000 2.175000 3.715000 3.755000 ;
+ RECT 3.410000 0.495000 3.715000 2.175000 ;
+ END
+ END X
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 3.840000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 3.840000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 3.840000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 3.840000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 3.840000 0.085000 ;
+ RECT 0.000000 3.985000 3.840000 4.155000 ;
+ RECT 0.130000 0.825000 0.425000 1.825000 ;
+ RECT 0.130000 1.825000 3.240000 1.995000 ;
+ RECT 0.130000 1.995000 0.380000 3.045000 ;
+ RECT 0.560000 2.670000 1.510000 3.705000 ;
+ RECT 1.770000 1.995000 2.020000 3.045000 ;
+ RECT 2.200000 2.175000 3.150000 3.755000 ;
+ RECT 2.435000 0.365000 3.240000 1.325000 ;
+ RECT 2.910000 1.665000 3.240000 1.825000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.590000 3.505000 0.760000 3.675000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.950000 3.505000 1.120000 3.675000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.310000 3.505000 1.480000 3.675000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.230000 3.505000 2.400000 3.675000 ;
+ RECT 2.485000 0.395000 2.655000 0.565000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.590000 3.505000 2.760000 3.675000 ;
+ RECT 2.950000 3.505000 3.120000 3.675000 ;
+ RECT 3.015000 0.395000 3.185000 0.565000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__and3_1
+MACRO sky130_fd_sc_hvl__lsbufhv2lv_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__lsbufhv2lv_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 8.160000 BY 8.140000 ;
+ SYMMETRY X Y ;
+ SITE unithvdbl ;
+ PIN A
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.630000 4.870000 1.300000 5.200000 ;
+ END
+ END A
+ PIN X
+ ANTENNADIFFAREA 0.492900 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 3.485000 0.735000 3.960000 3.245000 ;
+ END
+ END X
+ PIN LVPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.070000 3.020000 8.090000 3.305000 ;
+ END
+ END LVPWR
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 7.515000 8.160000 7.885000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 8.025000 8.160000 8.255000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 8.160000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 4.325000 8.160000 4.695000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 8.160000 0.085000 ;
+ RECT 0.000000 3.985000 0.885000 4.155000 ;
+ RECT 0.000000 8.055000 8.160000 8.225000 ;
+ RECT 0.130000 2.260000 0.460000 3.445000 ;
+ RECT 0.130000 3.445000 0.720000 3.675000 ;
+ RECT 0.130000 4.465000 0.720000 4.695000 ;
+ RECT 0.130000 4.695000 0.460000 5.880000 ;
+ RECT 0.170000 1.080000 0.420000 1.565000 ;
+ RECT 0.170000 1.565000 1.750000 1.895000 ;
+ RECT 0.170000 6.220000 1.750000 6.575000 ;
+ RECT 0.170000 6.575000 0.420000 7.060000 ;
+ RECT 0.630000 2.835000 1.750000 3.085000 ;
+ RECT 0.895000 0.395000 1.485000 1.395000 ;
+ RECT 0.895000 6.745000 1.485000 7.745000 ;
+ RECT 0.950000 1.895000 1.200000 2.590000 ;
+ RECT 0.950000 5.550000 1.750000 6.220000 ;
+ RECT 1.445000 1.895000 1.750000 2.235000 ;
+ RECT 1.470000 3.085000 1.750000 5.550000 ;
+ RECT 1.920000 0.685000 2.250000 4.255000 ;
+ RECT 1.920000 4.255000 3.960000 4.595000 ;
+ RECT 1.920000 5.195000 3.540000 5.445000 ;
+ RECT 1.920000 5.445000 2.250000 7.455000 ;
+ RECT 2.530000 5.615000 3.120000 7.745000 ;
+ RECT 2.570000 0.395000 3.160000 3.910000 ;
+ RECT 3.290000 5.445000 3.540000 5.595000 ;
+ RECT 3.290000 5.595000 5.170000 5.845000 ;
+ RECT 3.480000 5.845000 3.810000 7.455000 ;
+ RECT 3.710000 4.595000 3.960000 5.415000 ;
+ RECT 3.780000 3.415000 4.750000 4.085000 ;
+ RECT 4.130000 0.395000 4.720000 1.515000 ;
+ RECT 4.130000 2.085000 4.400000 3.075000 ;
+ RECT 4.130000 3.075000 4.750000 3.415000 ;
+ RECT 4.130000 4.085000 4.400000 5.415000 ;
+ RECT 4.570000 2.085000 4.820000 2.655000 ;
+ RECT 4.570000 2.655000 5.170000 2.905000 ;
+ RECT 4.920000 2.905000 5.170000 5.595000 ;
+ RECT 7.275000 3.985000 8.160000 4.155000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.155000 8.055000 0.325000 8.225000 ;
+ RECT 0.160000 3.475000 0.330000 3.645000 ;
+ RECT 0.160000 4.495000 0.330000 4.665000 ;
+ RECT 0.520000 3.475000 0.690000 3.645000 ;
+ RECT 0.520000 4.495000 0.690000 4.665000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.635000 8.055000 0.805000 8.225000 ;
+ RECT 0.925000 0.425000 1.095000 0.595000 ;
+ RECT 0.925000 7.545000 1.095000 7.715000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 8.055000 1.285000 8.225000 ;
+ RECT 1.285000 0.425000 1.455000 0.595000 ;
+ RECT 1.285000 7.545000 1.455000 7.715000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 8.055000 1.765000 8.225000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 8.055000 2.245000 8.225000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 8.055000 2.725000 8.225000 ;
+ RECT 2.560000 7.545000 2.730000 7.715000 ;
+ RECT 2.600000 0.425000 2.770000 0.595000 ;
+ RECT 2.920000 7.545000 3.090000 7.715000 ;
+ RECT 2.960000 0.425000 3.130000 0.595000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 8.055000 3.205000 8.225000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 8.055000 3.685000 8.225000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 8.055000 4.165000 8.225000 ;
+ RECT 4.160000 0.425000 4.330000 0.595000 ;
+ RECT 4.160000 3.105000 4.330000 3.275000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 8.055000 4.645000 8.225000 ;
+ RECT 4.520000 0.425000 4.690000 0.595000 ;
+ RECT 4.520000 3.105000 4.690000 3.275000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 8.055000 5.125000 8.225000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 8.055000 5.605000 8.225000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 8.055000 6.085000 8.225000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 8.055000 6.565000 8.225000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 8.055000 7.045000 8.225000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 3.985000 7.525000 4.155000 ;
+ RECT 7.355000 8.055000 7.525000 8.225000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 3.985000 8.005000 4.155000 ;
+ RECT 7.835000 8.055000 8.005000 8.225000 ;
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 8.160000 0.115000 ;
+ RECT 0.000000 0.255000 8.160000 0.625000 ;
+ RECT 0.000000 3.445000 8.160000 3.815000 ;
+ END
+END sky130_fd_sc_hvl__lsbufhv2lv_1
+MACRO sky130_fd_sc_hvl__nand3_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__nand3_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 3.360000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN A
+ ANTENNAGATEAREA 1.125000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.455000 0.810000 2.725000 1.725000 ;
+ END
+ END A
+ PIN B
+ ANTENNAGATEAREA 1.125000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.885000 0.810000 2.275000 1.725000 ;
+ END
+ END B
+ PIN C
+ ANTENNAGATEAREA 1.125000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.125000 1.505000 0.995000 1.835000 ;
+ END
+ END C
+ PIN Y
+ ANTENNADIFFAREA 1.065000 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 1.200000 1.905000 3.235000 2.075000 ;
+ RECT 1.200000 2.075000 1.370000 3.755000 ;
+ RECT 2.905000 0.495000 3.235000 1.325000 ;
+ RECT 2.980000 1.325000 3.235000 1.905000 ;
+ RECT 2.980000 2.075000 3.235000 3.755000 ;
+ END
+ END Y
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 3.360000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 3.360000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 3.360000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 3.360000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 3.360000 0.085000 ;
+ RECT 0.000000 3.985000 3.360000 4.155000 ;
+ RECT 0.090000 0.365000 1.705000 1.325000 ;
+ RECT 0.090000 2.175000 1.020000 3.755000 ;
+ RECT 1.550000 2.255000 2.800000 3.755000 ;
+ LAYER mcon ;
+ RECT 0.095000 0.395000 0.265000 0.565000 ;
+ RECT 0.110000 3.505000 0.280000 3.675000 ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.455000 0.395000 0.625000 0.565000 ;
+ RECT 0.470000 3.505000 0.640000 3.675000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.815000 0.395000 0.985000 0.565000 ;
+ RECT 0.830000 3.505000 1.000000 3.675000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.175000 0.395000 1.345000 0.565000 ;
+ RECT 1.535000 0.395000 1.705000 0.565000 ;
+ RECT 1.550000 3.505000 1.720000 3.675000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 1.910000 3.505000 2.080000 3.675000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.270000 3.505000 2.440000 3.675000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.630000 3.505000 2.800000 3.675000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__nand3_1
+MACRO sky130_fd_sc_hvl__sdlxtp_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__sdlxtp_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 11.52000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN D
+ ANTENNAGATEAREA 0.585000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.040000 2.185000 2.370000 3.260000 ;
+ END
+ END D
+ PIN Q
+ ANTENNADIFFAREA 0.626250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 11.060000 0.515000 11.400000 3.755000 ;
+ END
+ END Q
+ PIN SCD
+ ANTENNAGATEAREA 0.585000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 3.515000 1.525000 3.860000 2.495000 ;
+ END
+ END SCD
+ PIN SCE
+ ANTENNAGATEAREA 1.005000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.585000 1.835000 2.770000 2.005000 ;
+ RECT 0.585000 2.005000 1.795000 2.775000 ;
+ RECT 2.600000 1.445000 2.985000 1.695000 ;
+ RECT 2.600000 1.695000 2.770000 1.835000 ;
+ END
+ END SCE
+ PIN GATE
+ ANTENNAGATEAREA 0.585000 ;
+ DIRECTION INPUT ;
+ USE CLOCK ;
+ PORT
+ LAYER li1 ;
+ RECT 4.370000 1.145000 4.665000 2.495000 ;
+ END
+ END GATE
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 11.520000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 11.520000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 11.520000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 11.520000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 11.520000 0.085000 ;
+ RECT 0.000000 3.985000 11.520000 4.155000 ;
+ RECT 0.130000 0.495000 0.480000 1.175000 ;
+ RECT 0.130000 1.175000 3.335000 1.265000 ;
+ RECT 0.130000 1.265000 2.295000 1.345000 ;
+ RECT 0.130000 1.345000 0.380000 3.395000 ;
+ RECT 0.560000 2.995000 1.510000 3.705000 ;
+ RECT 0.660000 0.365000 1.610000 0.995000 ;
+ RECT 1.965000 1.095000 3.335000 1.175000 ;
+ RECT 1.965000 1.345000 2.295000 1.655000 ;
+ RECT 2.420000 0.495000 2.750000 0.745000 ;
+ RECT 2.420000 0.745000 3.685000 0.915000 ;
+ RECT 2.575000 2.675000 4.665000 2.845000 ;
+ RECT 2.575000 2.845000 2.825000 3.725000 ;
+ RECT 2.950000 1.905000 3.335000 2.495000 ;
+ RECT 3.165000 1.265000 3.335000 1.905000 ;
+ RECT 3.365000 3.025000 4.315000 3.725000 ;
+ RECT 3.515000 0.915000 3.685000 1.175000 ;
+ RECT 3.515000 1.175000 4.200000 1.345000 ;
+ RECT 3.865000 0.365000 4.455000 0.975000 ;
+ RECT 4.030000 1.345000 4.200000 2.675000 ;
+ RECT 4.495000 2.845000 4.665000 3.635000 ;
+ RECT 4.495000 3.635000 5.365000 3.805000 ;
+ RECT 4.695000 0.515000 5.025000 0.975000 ;
+ RECT 4.845000 0.975000 5.015000 1.175000 ;
+ RECT 4.845000 1.175000 5.920000 1.345000 ;
+ RECT 4.845000 1.345000 5.015000 3.455000 ;
+ RECT 5.195000 2.235000 6.065000 2.405000 ;
+ RECT 5.195000 2.405000 5.365000 3.635000 ;
+ RECT 5.205000 0.365000 5.795000 0.995000 ;
+ RECT 5.545000 2.585000 5.715000 3.705000 ;
+ RECT 5.590000 1.345000 5.920000 1.845000 ;
+ RECT 5.895000 2.405000 6.065000 3.595000 ;
+ RECT 5.895000 3.595000 7.250000 3.765000 ;
+ RECT 6.045000 0.265000 7.275000 0.435000 ;
+ RECT 6.045000 0.435000 6.415000 0.975000 ;
+ RECT 6.245000 0.975000 6.415000 2.585000 ;
+ RECT 6.245000 2.585000 6.575000 3.415000 ;
+ RECT 6.595000 0.615000 6.925000 0.975000 ;
+ RECT 6.755000 0.975000 6.925000 2.925000 ;
+ RECT 6.755000 2.925000 7.250000 3.595000 ;
+ RECT 7.105000 0.435000 7.275000 1.585000 ;
+ RECT 7.105000 1.585000 8.010000 1.755000 ;
+ RECT 7.455000 0.495000 7.705000 1.075000 ;
+ RECT 7.455000 1.075000 8.360000 1.245000 ;
+ RECT 7.700000 2.925000 8.030000 3.755000 ;
+ RECT 7.840000 1.755000 8.010000 2.215000 ;
+ RECT 7.840000 2.215000 8.570000 2.475000 ;
+ RECT 7.860000 2.655000 8.920000 2.825000 ;
+ RECT 7.860000 2.825000 8.030000 2.925000 ;
+ RECT 8.190000 1.245000 8.360000 1.835000 ;
+ RECT 8.190000 1.835000 10.200000 2.005000 ;
+ RECT 8.245000 0.365000 9.195000 0.895000 ;
+ RECT 8.540000 1.075000 8.870000 1.405000 ;
+ RECT 8.540000 1.405000 10.550000 1.575000 ;
+ RECT 8.540000 1.575000 8.870000 1.655000 ;
+ RECT 8.685000 3.005000 9.635000 3.705000 ;
+ RECT 8.750000 2.005000 8.920000 2.655000 ;
+ RECT 9.385000 2.185000 10.550000 2.355000 ;
+ RECT 9.385000 2.355000 9.715000 2.675000 ;
+ RECT 9.415000 0.845000 9.745000 1.405000 ;
+ RECT 9.870000 1.755000 10.200000 1.835000 ;
+ RECT 9.895000 2.535000 10.845000 3.755000 ;
+ RECT 9.925000 0.365000 10.875000 1.225000 ;
+ RECT 10.380000 1.575000 10.550000 2.185000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.590000 3.505000 0.760000 3.675000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.690000 0.395000 0.860000 0.565000 ;
+ RECT 0.950000 3.505000 1.120000 3.675000 ;
+ RECT 1.050000 0.395000 1.220000 0.565000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.310000 3.505000 1.480000 3.675000 ;
+ RECT 1.410000 0.395000 1.580000 0.565000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.395000 3.505000 3.565000 3.675000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.755000 3.505000 3.925000 3.675000 ;
+ RECT 3.895000 0.395000 4.065000 0.565000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.115000 3.505000 4.285000 3.675000 ;
+ RECT 4.255000 0.395000 4.425000 0.565000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ RECT 5.235000 0.395000 5.405000 0.565000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 3.985000 5.605000 4.155000 ;
+ RECT 5.545000 3.505000 5.715000 3.675000 ;
+ RECT 5.595000 0.395000 5.765000 0.565000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 3.985000 6.085000 4.155000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 3.985000 6.565000 4.155000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 3.985000 7.045000 4.155000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 3.985000 7.525000 4.155000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 3.985000 8.005000 4.155000 ;
+ RECT 8.275000 0.395000 8.445000 0.565000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 3.985000 8.485000 4.155000 ;
+ RECT 8.635000 0.395000 8.805000 0.565000 ;
+ RECT 8.715000 3.505000 8.885000 3.675000 ;
+ RECT 8.795000 -0.085000 8.965000 0.085000 ;
+ RECT 8.795000 3.985000 8.965000 4.155000 ;
+ RECT 8.995000 0.395000 9.165000 0.565000 ;
+ RECT 9.075000 3.505000 9.245000 3.675000 ;
+ RECT 9.275000 -0.085000 9.445000 0.085000 ;
+ RECT 9.275000 3.985000 9.445000 4.155000 ;
+ RECT 9.435000 3.505000 9.605000 3.675000 ;
+ RECT 9.755000 -0.085000 9.925000 0.085000 ;
+ RECT 9.755000 3.985000 9.925000 4.155000 ;
+ RECT 9.925000 3.505000 10.095000 3.675000 ;
+ RECT 9.955000 0.395000 10.125000 0.565000 ;
+ RECT 10.235000 -0.085000 10.405000 0.085000 ;
+ RECT 10.235000 3.985000 10.405000 4.155000 ;
+ RECT 10.285000 3.505000 10.455000 3.675000 ;
+ RECT 10.315000 0.395000 10.485000 0.565000 ;
+ RECT 10.645000 3.505000 10.815000 3.675000 ;
+ RECT 10.675000 0.395000 10.845000 0.565000 ;
+ RECT 10.715000 -0.085000 10.885000 0.085000 ;
+ RECT 10.715000 3.985000 10.885000 4.155000 ;
+ RECT 11.195000 -0.085000 11.365000 0.085000 ;
+ RECT 11.195000 3.985000 11.365000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__sdlxtp_1
+MACRO sky130_fd_sc_hvl__dfrbp_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__dfrbp_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 16.80000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN D
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 3.850000 0.810000 4.165000 2.105000 ;
+ END
+ END D
+ PIN Q
+ ANTENNADIFFAREA 0.626250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 16.340000 0.515000 16.690000 3.755000 ;
+ END
+ END Q
+ PIN Q_N
+ ANTENNADIFFAREA 0.641250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 14.045000 0.665000 14.425000 1.495000 ;
+ RECT 14.045000 1.495000 14.380000 1.780000 ;
+ RECT 14.130000 1.780000 14.380000 3.755000 ;
+ END
+ END Q_N
+ PIN RESET_B
+ ANTENNAGATEAREA 1.260000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.980000 1.505000 3.665000 2.120000 ;
+ RECT 3.495000 0.460000 6.625000 0.630000 ;
+ RECT 3.495000 0.630000 3.665000 1.505000 ;
+ RECT 6.455000 0.630000 6.625000 1.125000 ;
+ RECT 6.455000 1.125000 8.515000 1.295000 ;
+ RECT 7.165000 1.825000 8.515000 1.995000 ;
+ RECT 8.345000 0.265000 11.075000 0.435000 ;
+ RECT 8.345000 0.435000 8.515000 1.125000 ;
+ RECT 8.345000 1.295000 8.515000 1.825000 ;
+ RECT 10.905000 0.435000 11.075000 0.960000 ;
+ RECT 10.905000 0.960000 11.840000 1.130000 ;
+ RECT 11.510000 1.130000 11.840000 1.350000 ;
+ END
+ END RESET_B
+ PIN CLK
+ ANTENNAGATEAREA 0.585000 ;
+ DIRECTION INPUT ;
+ USE CLOCK ;
+ PORT
+ LAYER li1 ;
+ RECT 0.595000 1.175000 0.925000 1.720000 ;
+ END
+ END CLK
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 16.800000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 16.800000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 16.800000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 16.800000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 16.800000 0.085000 ;
+ RECT 0.000000 3.985000 16.800000 4.155000 ;
+ RECT 0.165000 0.495000 0.495000 0.995000 ;
+ RECT 0.165000 0.995000 0.415000 2.275000 ;
+ RECT 0.165000 2.275000 1.835000 2.445000 ;
+ RECT 0.165000 2.445000 0.415000 3.455000 ;
+ RECT 0.595000 2.625000 1.485000 3.705000 ;
+ RECT 0.675000 0.365000 1.625000 0.995000 ;
+ RECT 1.505000 1.900000 1.835000 2.275000 ;
+ RECT 1.665000 2.445000 1.835000 3.635000 ;
+ RECT 1.665000 3.635000 3.205000 3.805000 ;
+ RECT 1.805000 0.495000 2.185000 0.995000 ;
+ RECT 2.015000 0.995000 2.185000 1.550000 ;
+ RECT 2.015000 1.550000 2.275000 3.455000 ;
+ RECT 2.365000 0.365000 3.315000 1.325000 ;
+ RECT 2.525000 2.300000 4.515000 2.470000 ;
+ RECT 2.525000 2.470000 2.855000 3.420000 ;
+ RECT 3.035000 2.650000 3.905000 2.820000 ;
+ RECT 3.035000 2.820000 3.205000 3.635000 ;
+ RECT 3.385000 3.000000 3.555000 3.705000 ;
+ RECT 3.735000 2.820000 3.905000 3.600000 ;
+ RECT 3.735000 3.600000 5.565000 3.770000 ;
+ RECT 4.085000 3.000000 4.515000 3.420000 ;
+ RECT 4.345000 0.825000 4.655000 1.325000 ;
+ RECT 4.345000 1.325000 4.515000 2.300000 ;
+ RECT 4.345000 2.470000 4.515000 3.000000 ;
+ RECT 4.695000 1.505000 5.925000 1.780000 ;
+ RECT 4.695000 1.780000 4.865000 2.820000 ;
+ RECT 4.865000 3.000000 5.215000 3.420000 ;
+ RECT 5.045000 2.200000 6.275000 2.370000 ;
+ RECT 5.045000 2.370000 5.215000 3.000000 ;
+ RECT 5.270000 0.825000 5.600000 1.155000 ;
+ RECT 5.270000 1.155000 6.275000 1.325000 ;
+ RECT 5.395000 2.550000 5.650000 2.875000 ;
+ RECT 5.395000 2.875000 7.035000 3.045000 ;
+ RECT 5.395000 3.045000 5.565000 3.600000 ;
+ RECT 5.595000 1.780000 5.925000 2.020000 ;
+ RECT 5.745000 3.225000 6.685000 3.705000 ;
+ RECT 6.105000 1.325000 6.275000 1.475000 ;
+ RECT 6.105000 1.475000 8.165000 1.645000 ;
+ RECT 6.105000 1.645000 6.275000 2.200000 ;
+ RECT 6.105000 2.370000 6.275000 2.525000 ;
+ RECT 6.105000 2.525000 7.385000 2.695000 ;
+ RECT 6.455000 1.825000 6.785000 2.175000 ;
+ RECT 6.455000 2.175000 9.025000 2.345000 ;
+ RECT 6.865000 3.045000 7.035000 3.635000 ;
+ RECT 6.865000 3.635000 7.735000 3.805000 ;
+ RECT 7.215000 0.365000 8.165000 0.945000 ;
+ RECT 7.215000 2.695000 7.385000 3.455000 ;
+ RECT 7.565000 2.700000 9.375000 2.870000 ;
+ RECT 7.565000 2.870000 7.735000 3.635000 ;
+ RECT 7.915000 3.050000 8.865000 3.705000 ;
+ RECT 8.695000 0.615000 9.025000 2.175000 ;
+ RECT 8.695000 2.345000 9.025000 2.520000 ;
+ RECT 9.205000 1.230000 10.375000 1.400000 ;
+ RECT 9.205000 1.400000 9.375000 2.700000 ;
+ RECT 9.555000 2.270000 10.410000 2.440000 ;
+ RECT 9.555000 2.440000 9.805000 3.350000 ;
+ RECT 9.580000 0.615000 10.725000 0.785000 ;
+ RECT 9.580000 0.785000 9.910000 0.995000 ;
+ RECT 9.725000 1.580000 10.060000 2.090000 ;
+ RECT 10.090000 1.070000 10.375000 1.230000 ;
+ RECT 10.240000 2.000000 12.530000 2.170000 ;
+ RECT 10.240000 2.170000 10.410000 2.270000 ;
+ RECT 10.555000 0.785000 10.725000 2.000000 ;
+ RECT 10.590000 2.350000 11.540000 3.705000 ;
+ RECT 10.930000 1.310000 11.260000 1.530000 ;
+ RECT 10.930000 1.530000 12.880000 1.700000 ;
+ RECT 10.930000 1.700000 11.260000 1.820000 ;
+ RECT 11.255000 0.365000 12.205000 0.780000 ;
+ RECT 11.965000 2.350000 12.880000 2.520000 ;
+ RECT 11.965000 2.520000 12.295000 2.770000 ;
+ RECT 12.200000 1.880000 12.530000 2.000000 ;
+ RECT 12.710000 0.515000 13.075000 0.975000 ;
+ RECT 12.710000 0.975000 12.880000 1.530000 ;
+ RECT 12.710000 1.700000 12.880000 2.350000 ;
+ RECT 13.060000 2.175000 13.950000 3.755000 ;
+ RECT 13.255000 0.365000 13.845000 1.495000 ;
+ RECT 14.665000 0.825000 15.015000 1.505000 ;
+ RECT 14.665000 1.505000 16.160000 1.835000 ;
+ RECT 14.665000 1.835000 14.995000 3.005000 ;
+ RECT 15.175000 2.175000 16.125000 3.755000 ;
+ RECT 15.195000 0.365000 16.145000 1.325000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.595000 3.505000 0.765000 3.675000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.705000 0.395000 0.875000 0.565000 ;
+ RECT 0.955000 3.505000 1.125000 3.675000 ;
+ RECT 1.065000 0.395000 1.235000 0.565000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.315000 3.505000 1.485000 3.675000 ;
+ RECT 1.425000 0.395000 1.595000 0.565000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 1.580000 2.245000 1.750000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.395000 0.395000 2.565000 0.565000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 2.755000 0.395000 2.925000 0.565000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.115000 0.395000 3.285000 0.565000 ;
+ RECT 3.385000 3.505000 3.555000 3.675000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ RECT 4.955000 1.580000 5.125000 1.750000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ RECT 5.435000 -0.085000 5.605000 0.085000 ;
+ RECT 5.435000 3.985000 5.605000 4.155000 ;
+ RECT 5.770000 3.505000 5.940000 3.675000 ;
+ RECT 5.915000 -0.085000 6.085000 0.085000 ;
+ RECT 5.915000 3.985000 6.085000 4.155000 ;
+ RECT 6.130000 3.505000 6.300000 3.675000 ;
+ RECT 6.395000 -0.085000 6.565000 0.085000 ;
+ RECT 6.395000 3.985000 6.565000 4.155000 ;
+ RECT 6.490000 3.505000 6.660000 3.675000 ;
+ RECT 6.875000 -0.085000 7.045000 0.085000 ;
+ RECT 6.875000 3.985000 7.045000 4.155000 ;
+ RECT 7.245000 0.395000 7.415000 0.565000 ;
+ RECT 7.355000 -0.085000 7.525000 0.085000 ;
+ RECT 7.355000 3.985000 7.525000 4.155000 ;
+ RECT 7.605000 0.395000 7.775000 0.565000 ;
+ RECT 7.835000 -0.085000 8.005000 0.085000 ;
+ RECT 7.835000 3.985000 8.005000 4.155000 ;
+ RECT 7.945000 3.505000 8.115000 3.675000 ;
+ RECT 7.965000 0.395000 8.135000 0.565000 ;
+ RECT 8.305000 3.505000 8.475000 3.675000 ;
+ RECT 8.315000 -0.085000 8.485000 0.085000 ;
+ RECT 8.315000 3.985000 8.485000 4.155000 ;
+ RECT 8.665000 3.505000 8.835000 3.675000 ;
+ RECT 8.795000 -0.085000 8.965000 0.085000 ;
+ RECT 8.795000 3.985000 8.965000 4.155000 ;
+ RECT 9.275000 -0.085000 9.445000 0.085000 ;
+ RECT 9.275000 3.985000 9.445000 4.155000 ;
+ RECT 9.755000 -0.085000 9.925000 0.085000 ;
+ RECT 9.755000 1.580000 9.925000 1.750000 ;
+ RECT 9.755000 3.985000 9.925000 4.155000 ;
+ RECT 10.235000 -0.085000 10.405000 0.085000 ;
+ RECT 10.235000 3.985000 10.405000 4.155000 ;
+ RECT 10.620000 3.505000 10.790000 3.675000 ;
+ RECT 10.715000 -0.085000 10.885000 0.085000 ;
+ RECT 10.715000 3.985000 10.885000 4.155000 ;
+ RECT 10.980000 3.505000 11.150000 3.675000 ;
+ RECT 11.195000 -0.085000 11.365000 0.085000 ;
+ RECT 11.195000 3.985000 11.365000 4.155000 ;
+ RECT 11.285000 0.395000 11.455000 0.565000 ;
+ RECT 11.340000 3.505000 11.510000 3.675000 ;
+ RECT 11.645000 0.395000 11.815000 0.565000 ;
+ RECT 11.675000 -0.085000 11.845000 0.085000 ;
+ RECT 11.675000 3.985000 11.845000 4.155000 ;
+ RECT 12.005000 0.395000 12.175000 0.565000 ;
+ RECT 12.155000 -0.085000 12.325000 0.085000 ;
+ RECT 12.155000 3.985000 12.325000 4.155000 ;
+ RECT 12.635000 -0.085000 12.805000 0.085000 ;
+ RECT 12.635000 3.985000 12.805000 4.155000 ;
+ RECT 13.060000 3.505000 13.230000 3.675000 ;
+ RECT 13.115000 -0.085000 13.285000 0.085000 ;
+ RECT 13.115000 3.985000 13.285000 4.155000 ;
+ RECT 13.285000 0.395000 13.455000 0.565000 ;
+ RECT 13.420000 3.505000 13.590000 3.675000 ;
+ RECT 13.595000 -0.085000 13.765000 0.085000 ;
+ RECT 13.595000 3.985000 13.765000 4.155000 ;
+ RECT 13.645000 0.395000 13.815000 0.565000 ;
+ RECT 13.780000 3.505000 13.950000 3.675000 ;
+ RECT 14.075000 -0.085000 14.245000 0.085000 ;
+ RECT 14.075000 3.985000 14.245000 4.155000 ;
+ RECT 14.555000 -0.085000 14.725000 0.085000 ;
+ RECT 14.555000 3.985000 14.725000 4.155000 ;
+ RECT 15.035000 -0.085000 15.205000 0.085000 ;
+ RECT 15.035000 3.985000 15.205000 4.155000 ;
+ RECT 15.205000 3.505000 15.375000 3.675000 ;
+ RECT 15.225000 0.395000 15.395000 0.565000 ;
+ RECT 15.515000 -0.085000 15.685000 0.085000 ;
+ RECT 15.515000 3.985000 15.685000 4.155000 ;
+ RECT 15.565000 3.505000 15.735000 3.675000 ;
+ RECT 15.585000 0.395000 15.755000 0.565000 ;
+ RECT 15.925000 3.505000 16.095000 3.675000 ;
+ RECT 15.945000 0.395000 16.115000 0.565000 ;
+ RECT 15.995000 -0.085000 16.165000 0.085000 ;
+ RECT 15.995000 3.985000 16.165000 4.155000 ;
+ RECT 16.475000 -0.085000 16.645000 0.085000 ;
+ RECT 16.475000 3.985000 16.645000 4.155000 ;
+ LAYER met1 ;
+ RECT 2.015000 1.550000 2.305000 1.595000 ;
+ RECT 2.015000 1.595000 9.985000 1.735000 ;
+ RECT 2.015000 1.735000 2.305000 1.780000 ;
+ RECT 4.895000 1.550000 5.185000 1.595000 ;
+ RECT 4.895000 1.735000 5.185000 1.780000 ;
+ RECT 9.695000 1.550000 9.985000 1.595000 ;
+ RECT 9.695000 1.735000 9.985000 1.780000 ;
+ END
+END sky130_fd_sc_hvl__dfrbp_1
+MACRO sky130_fd_sc_hvl__fill_1
+ CLASS CORE SPACER ;
+ FOREIGN sky130_fd_sc_hvl__fill_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 0.480000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 0.480000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 0.480000 0.085000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ END
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 0.480000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER li1 ;
+ RECT 0.000000 3.985000 0.480000 4.155000 ;
+ LAYER mcon ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ END
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 0.480000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 0.480000 3.815000 ;
+ END
+ END VPWR
+END sky130_fd_sc_hvl__fill_1
+MACRO sky130_fd_sc_hvl__fill_4
+ CLASS CORE SPACER ;
+ FOREIGN sky130_fd_sc_hvl__fill_4 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 1.920000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 1.920000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 1.920000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 1.920000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 1.920000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 1.920000 0.085000 ;
+ RECT 0.000000 3.985000 1.920000 4.155000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__fill_4
+MACRO sky130_fd_sc_hvl__fill_8
+ CLASS CORE SPACER ;
+ FOREIGN sky130_fd_sc_hvl__fill_8 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 3.840000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 3.840000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 3.840000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 3.840000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 3.840000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 3.840000 0.085000 ;
+ RECT 0.000000 3.985000 3.840000 4.155000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__fill_8
+MACRO sky130_fd_sc_hvl__fill_2
+ CLASS CORE SPACER ;
+ FOREIGN sky130_fd_sc_hvl__fill_2 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 0.960000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 0.960000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 0.960000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 0.960000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 0.960000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 0.960000 0.085000 ;
+ RECT 0.000000 3.985000 0.960000 4.155000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ END
+END sky130_fd_sc_hvl__fill_2
+MACRO sky130_fd_sc_hvl__schmittbuf_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__schmittbuf_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 5.280000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN A
+ ANTENNAGATEAREA 1.170000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 2.015000 1.855000 3.305000 2.150000 ;
+ END
+ END A
+ PIN X
+ ANTENNADIFFAREA 0.596250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 4.860000 0.515000 5.195000 3.715000 ;
+ END
+ END X
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 5.280000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 5.280000 0.085000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+ RECT 1.595000 -0.085000 1.765000 0.085000 ;
+ RECT 2.075000 -0.085000 2.245000 0.085000 ;
+ RECT 2.555000 -0.085000 2.725000 0.085000 ;
+ RECT 3.035000 -0.085000 3.205000 0.085000 ;
+ RECT 3.515000 -0.085000 3.685000 0.085000 ;
+ RECT 3.995000 -0.085000 4.165000 0.085000 ;
+ RECT 4.475000 -0.085000 4.645000 0.085000 ;
+ RECT 4.955000 -0.085000 5.125000 0.085000 ;
+ END
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 5.280000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER li1 ;
+ RECT 0.000000 3.985000 5.280000 4.155000 ;
+ LAYER mcon ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 1.115000 3.985000 1.285000 4.155000 ;
+ RECT 1.595000 3.985000 1.765000 4.155000 ;
+ RECT 2.075000 3.985000 2.245000 4.155000 ;
+ RECT 2.555000 3.985000 2.725000 4.155000 ;
+ RECT 3.035000 3.985000 3.205000 4.155000 ;
+ RECT 3.515000 3.985000 3.685000 4.155000 ;
+ RECT 3.995000 3.985000 4.165000 4.155000 ;
+ RECT 4.475000 3.985000 4.645000 4.155000 ;
+ RECT 4.955000 3.985000 5.125000 4.155000 ;
+ END
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 5.280000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 5.280000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.085000 1.805000 0.530000 1.975000 ;
+ RECT 0.085000 1.975000 0.255000 3.485000 ;
+ RECT 0.085000 3.485000 1.030000 3.655000 ;
+ RECT 0.280000 1.090000 0.530000 1.805000 ;
+ RECT 0.430000 2.165000 0.875000 2.335000 ;
+ RECT 0.430000 2.335000 0.680000 3.085000 ;
+ RECT 0.705000 0.570000 2.010000 0.795000 ;
+ RECT 0.705000 0.795000 0.875000 2.165000 ;
+ RECT 0.740000 3.405000 1.030000 3.485000 ;
+ RECT 0.740000 3.655000 1.030000 3.735000 ;
+ RECT 1.045000 1.655000 4.690000 1.685000 ;
+ RECT 1.045000 1.685000 1.835000 1.985000 ;
+ RECT 1.060000 0.975000 2.720000 1.145000 ;
+ RECT 1.060000 1.145000 1.390000 1.410000 ;
+ RECT 1.200000 2.295000 1.460000 3.235000 ;
+ RECT 1.200000 3.235000 2.790000 3.405000 ;
+ RECT 1.600000 1.315000 1.940000 1.505000 ;
+ RECT 1.600000 1.505000 4.210000 1.645000 ;
+ RECT 1.600000 1.645000 4.690000 1.655000 ;
+ RECT 1.655000 1.985000 1.835000 2.330000 ;
+ RECT 1.655000 2.330000 2.010000 3.065000 ;
+ RECT 2.390000 1.145000 2.720000 1.335000 ;
+ RECT 2.460000 2.320000 2.790000 3.235000 ;
+ RECT 3.120000 0.375000 4.630000 1.285000 ;
+ RECT 3.130000 3.405000 4.570000 3.735000 ;
+ RECT 3.235000 2.320000 4.570000 3.405000 ;
+ RECT 3.855000 1.685000 4.690000 2.055000 ;
+ LAYER mcon ;
+ RECT 3.210000 0.425000 3.380000 0.595000 ;
+ RECT 3.225000 3.475000 3.395000 3.645000 ;
+ RECT 3.570000 0.425000 3.740000 0.595000 ;
+ RECT 3.585000 3.475000 3.755000 3.645000 ;
+ RECT 3.945000 3.475000 4.115000 3.645000 ;
+ RECT 3.980000 0.425000 4.150000 0.595000 ;
+ RECT 4.305000 3.475000 4.475000 3.645000 ;
+ RECT 4.410000 0.425000 4.580000 0.595000 ;
+ END
+END sky130_fd_sc_hvl__schmittbuf_1
+MACRO sky130_fd_sc_hvl__sdfxtp_1
+ CLASS CORE ;
+ FOREIGN sky130_fd_sc_hvl__sdfxtp_1 ;
+ ORIGIN 0.000000 0.000000 ;
+ SIZE 14.88000 BY 4.070000 ;
+ SYMMETRY X Y ;
+ SITE unithv ;
+ PIN D
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.605000 2.205000 2.755000 2.520000 ;
+ END
+ END D
+ PIN Q
+ ANTENNADIFFAREA 0.596250 ;
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 13.660000 0.615000 14.020000 1.505000 ;
+ RECT 13.660000 2.195000 14.020000 3.735000 ;
+ RECT 13.850000 1.505000 14.755000 1.780000 ;
+ RECT 13.850000 1.780000 14.020000 2.195000 ;
+ END
+ END Q
+ PIN SCD
+ ANTENNAGATEAREA 0.420000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 3.600000 2.215000 4.195000 2.765000 ;
+ END
+ END SCD
+ PIN SCE
+ ANTENNAGATEAREA 0.840000 ;
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.605000 1.445000 1.795000 1.855000 ;
+ RECT 0.605000 1.855000 3.050000 2.025000 ;
+ RECT 2.720000 1.095000 3.050000 1.855000 ;
+ END
+ END SCE
+ PIN CLK
+ ANTENNAGATEAREA 0.585000 ;
+ DIRECTION INPUT ;
+ USE CLOCK ;
+ PORT
+ LAYER li1 ;
+ RECT 4.345000 1.175000 4.675000 1.685000 ;
+ END
+ END CLK
+ PIN VGND
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 0.255000 14.880000 0.625000 ;
+ END
+ END VGND
+ PIN VNB
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 -0.115000 14.880000 0.115000 ;
+ END
+ END VNB
+ PIN VPB
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.955000 14.880000 4.185000 ;
+ END
+ END VPB
+ PIN VPWR
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.000000 3.445000 14.880000 3.815000 ;
+ END
+ END VPWR
+ OBS
+ LAYER li1 ;
+ RECT 0.000000 -0.085000 14.880000 0.085000 ;
+ RECT 0.000000 3.985000 14.880000 4.155000 ;
+ RECT 0.125000 0.515000 0.455000 1.095000 ;
+ RECT 0.125000 1.095000 2.305000 1.265000 ;
+ RECT 0.125000 1.265000 0.380000 3.425000 ;
+ RECT 0.905000 0.365000 1.855000 0.915000 ;
+ RECT 0.910000 2.925000 1.860000 3.705000 ;
+ RECT 1.975000 1.265000 2.305000 1.675000 ;
+ RECT 2.395000 0.495000 2.725000 0.745000 ;
+ RECT 2.395000 0.745000 3.400000 0.915000 ;
+ RECT 2.400000 2.925000 3.400000 3.095000 ;
+ RECT 2.400000 3.095000 2.730000 3.425000 ;
+ RECT 3.230000 0.915000 3.400000 1.865000 ;
+ RECT 3.230000 1.865000 6.780000 2.035000 ;
+ RECT 3.230000 2.035000 3.400000 2.925000 ;
+ RECT 3.580000 0.365000 4.485000 0.995000 ;
+ RECT 3.635000 2.945000 4.585000 3.735000 ;
+ RECT 4.665000 0.515000 5.025000 0.975000 ;
+ RECT 4.765000 2.595000 5.605000 2.765000 ;
+ RECT 4.765000 2.765000 5.095000 3.735000 ;
+ RECT 4.855000 0.975000 5.025000 1.155000 ;
+ RECT 4.855000 1.155000 5.870000 1.325000 ;
+ RECT 5.215000 0.365000 5.805000 0.975000 ;
+ RECT 5.275000 2.215000 5.605000 2.595000 ;
+ RECT 5.315000 2.945000 5.905000 3.735000 ;
+ RECT 5.540000 1.325000 5.870000 1.685000 ;
+ RECT 5.995000 0.265000 8.210000 0.435000 ;
+ RECT 5.995000 0.435000 6.325000 0.975000 ;
+ RECT 6.095000 2.945000 6.425000 3.335000 ;
+ RECT 6.095000 3.335000 7.325000 3.505000 ;
+ RECT 6.095000 3.505000 6.425000 3.735000 ;
+ RECT 6.565000 0.615000 6.895000 0.995000 ;
+ RECT 6.565000 0.995000 6.780000 1.865000 ;
+ RECT 6.610000 2.035000 6.780000 2.695000 ;
+ RECT 6.610000 2.695000 6.975000 3.155000 ;
+ RECT 6.960000 2.225000 7.325000 2.515000 ;
+ RECT 7.075000 0.435000 7.245000 2.225000 ;
+ RECT 7.155000 2.515000 7.325000 3.335000 ;
+ RECT 7.425000 0.615000 7.755000 0.995000 ;
+ RECT 7.505000 0.995000 7.755000 1.605000 ;
+ RECT 7.505000 1.605000 9.685000 1.775000 ;
+ RECT 7.505000 1.775000 7.675000 2.675000 ;
+ RECT 7.505000 2.675000 7.755000 3.175000 ;
+ RECT 7.880000 1.955000 8.210000 2.495000 ;
+ RECT 7.935000 0.435000 8.210000 1.255000 ;
+ RECT 7.935000 1.255000 10.295000 1.425000 ;
+ RECT 8.040000 2.495000 8.210000 3.155000 ;
+ RECT 8.040000 3.155000 10.490000 3.325000 ;
+ RECT 8.620000 1.955000 10.645000 2.125000 ;
+ RECT 8.620000 2.125000 8.950000 2.555000 ;
+ RECT 8.680000 0.365000 9.630000 1.075000 ;
+ RECT 9.030000 3.505000 9.980000 3.755000 ;
+ RECT 9.810000 0.495000 10.140000 0.905000 ;
+ RECT 9.810000 0.905000 10.645000 1.075000 ;
+ RECT 9.810000 2.125000 9.980000 2.675000 ;
+ RECT 9.810000 2.675000 10.140000 2.975000 ;
+ RECT 10.045000 1.425000 10.295000 1.775000 ;
+ RECT 10.160000 2.305000 10.490000 2.495000 ;
+ RECT 10.320000 2.495000 10.490000 3.155000 ;
+ RECT 10.320000 3.325000 11.450000 3.495000 ;
+ RECT 10.475000 1.075000 10.645000 1.955000 ;
+ RECT 10.670000 2.675000 11.075000 3.145000 ;
+ RECT 10.825000 0.495000 11.800000 0.665000 ;
+ RECT 10.825000 0.665000 11.075000 2.675000 ;
+ RECT 11.255000 1.085000 11.450000 3.325000 ;
+ RECT 11.630000 0.665000 11.800000 2.345000 ;
+ RECT 11.630000 2.345000 12.930000 2.515000 ;
+ RECT 11.980000 0.365000 12.930000 1.305000 ;
+ RECT 11.980000 1.485000 13.440000 1.655000 ;
+ RECT 11.980000 1.655000 12.310000 2.155000 ;
+ RECT 11.980000 2.695000 12.930000 3.735000 ;
+ RECT 12.600000 1.845000 12.930000 2.345000 ;
+ RECT 13.110000 0.515000 13.440000 1.485000 ;
+ RECT 13.110000 1.655000 13.440000 1.685000 ;
+ RECT 13.110000 1.685000 13.670000 2.015000 ;
+ RECT 13.110000 2.015000 13.440000 3.735000 ;
+ RECT 14.200000 0.365000 14.790000 1.325000 ;
+ RECT 14.200000 2.195000 14.790000 3.735000 ;
+ LAYER mcon ;
+ RECT 0.155000 -0.085000 0.325000 0.085000 ;
+ RECT 0.155000 3.985000 0.325000 4.155000 ;
+ RECT 0.635000 -0.085000 0.805000 0.085000 ;
+ RECT 0.635000 3.985000 0.805000 4.155000 ;
+ RECT 0.935000 0.395000 1.105000 0.565000 ;
+ RECT 0.940000 3.505000 1.110000 3.675000 ;
+ RECT 1.115000 -0.085000 1.285000 0.085000 ;
+