| [OpenPhySyn] [2020-11-27 17:21:59.963] [info] Loaded 6 transforms. |
| [OpenPhySyn] [2020-11-27 17:22:00.338] [info] OpenPhySyn: 1.8.1 |
| Warning: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/opt.lib, line 36 default_operating_condition ss_150C_1v65 not found. |
| Notice 0: Reading LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef |
| Notice 0: Created 13 technology layers |
| Notice 0: Created 25 technology vias |
| Notice 0: Created 69 library cells |
| Notice 0: Finished LEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/merged_unpadded.lef |
| Notice 0: |
| Reading DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/placement/replace.def |
| Notice 0: Design: sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped |
| Notice 0: Created 2 pins. |
| Notice 0: Created 1 components and 7 component-terminals. |
| Notice 0: Created 2 nets and 2 connections. |
| Notice 0: Finished DEF file: /project/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/runs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/tmp/placement/replace.def |
| Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable |
| =============== Initial Reports ============= |
| No paths found. |
| Capacitance violations: 0 |
| Transition violations: 0 |
| wns 0.00 |
| tns 0.00 |
| Initial area: 664 um2 |
| OpenPhySyn timing repair: |
| [OpenPhySyn] [2020-11-27 17:22:00.415] [info] Invoking repair_timing transform |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Buffer library: sky130_fd_sc_hvl__buf_16, sky130_fd_sc_hvl__buf_32, sky130_fd_sc_hvl__buf_4 |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Inverter library: None |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Buffering: enabled |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Driver sizing: enabled |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Pin-swapping: enabled |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Mode: Timing-Driven |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Iteration 1 |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] No more violations or cannot find more optimal buffer |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Runtime: 0s |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Buffers: 0 |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Resize up: 0 |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Resize down: 0 |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Pin Swap: 0 |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Buffered nets: 0 |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Fanout violations: 0 |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Transition violations: 0 |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Capacitance violations: 0 |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Slack gain: 0.0 |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Initial area: 66 |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] New area: 66 |
| [OpenPhySyn] [2020-11-27 17:22:00.424] [info] Finished repair_timing transform (0) |
| Added/updated 0 cells |
| =============== Final Reports ============= |
| No paths found. |
| Capacitance violations: 0 |
| Transition violations: 0 |
| wns 0.00 |
| tns 0.00 |
| Final area: 664 um2 |
| Export optimized design |
