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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-006 / 22bcb2032493ec4f1cf9f48434e624837182a6f5^! / .
commit22bcb2032493ec4f1cf9f48434e624837182a6f5[log] [tgz]
authorNikola Petrovic <nikola.petrovic@novelic.com>Wed Dec 16 19:24:34 2020 +0100
committerNikola Petrovic <nikola.petrovic@novelic.com>Wed Dec 16 19:24:34 2020 +0100
treed8cdffba5a3479a2bd6b70689bc0eb34aa1be432
parentf48448d4736bd6d56fed4dbf7f9cc50552d8745d [diff]
Initial commit

diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..c53a448
--- /dev/null
+++ b/.gitmodules

@@ -0,0 +1,6 @@
+[submodule "cargo/spectrometer"]
+	path = cargo/spectrometer
+	url = https://github.com/milovanovic/spectrometer.git
+[submodule "cargo/wb2axip"]
+	path = cargo/wb2axip
+	url = https://github.com/milovanovic/wb2axip.git

diff --git a/cargo/Makefile b/cargo/Makefile
new file mode 100644
index 0000000..af64301
--- /dev/null
+++ b/cargo/Makefile

@@ -0,0 +1,38 @@
+SPECTROMETER_PATH = ./spectrometer
+TOP_TEST_PATH = ./top/dv/SpectrometerTest/spectrometer
+
+SIZE?=128
+export FFT_SIZE=$(SIZE)
+
+ENABLE_PLOT?=false
+
+move_user_proj_example:
+	mv ../verilog/rtl/user_proj_example.v ./user_proj_example.v
+
+move_back_user_proj_example:
+	mv ./user_proj_example.v ../verilog/rtl/user_proj_example.v 
+	
+verilog_spectrometer:
+	cd $(SPECTROMETER_PATH); sbt "runMain spectrometer.SpectrometerTestApp $(FFT_SIZE)"; cd -;
+
+test_spectrometer:
+	cd $(SPECTROMETER_PATH); SBT_OPTS="-DfftSize=$(FFT_SIZE) -DenablePlot=$(ENABLE_PLOT)" sbt "testOnly spectrometer.SpectrometerTestSpec"; cd -;
+
+.PHONY: test_top
+test_top:
+	make move_user_proj_example
+	make verilog_spectrometer
+	make test_spectrometer
+	cd $(TOP_TEST_PATH); make all; cd -;
+	make move_back_user_proj_example
+
+clean_top:
+	cd $(TOP_TEST_PATH); make clean; cd -;
+	
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifndef RISCV32
+	$(error RISCV32 is undefined, please export it before running make)
+endif

diff --git a/cargo/README.md b/cargo/README.md
new file mode 100644
index 0000000..bdafa94
--- /dev/null
+++ b/cargo/README.md

@@ -0,0 +1,3 @@
+# Spectrometer on Caravel  
+
+![Interface of the Spectrometer](./doc/Spectrometer.png)
\ No newline at end of file

diff --git a/cargo/doc/SpectrometerTest.png b/cargo/doc/SpectrometerTest.png
new file mode 100644
index 0000000..3db48c8
--- /dev/null
+++ b/cargo/doc/SpectrometerTest.png
Binary files differ

diff --git a/cargo/doc/SpectrometerTest.svg b/cargo/doc/SpectrometerTest.svg
new file mode 100644
index 0000000..66df482
--- /dev/null
+++ b/cargo/doc/SpectrometerTest.svg

@@ -0,0 +1,3 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
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Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font color="#B85450">regs</font></div></div></div></foreignObject><text x="1915" y="787" fill="#000000" font-family="Helvetica" font-size="12px" text-anchor="middle">regs</text></switch></g><path d="M 1855.2 562.33 L 1875.2 522.85 L 1954.8 522.85 L 1974.8 562.33 Z" fill="#ffffff" stroke="#000000" stroke-miterlimit="10" transform="rotate(90,1915,542.59)" pointer-events="all"/><path d="M 1900 542.5 L 1905 542.5 L 1930 517.5" fill="none" stroke="#000000" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 1912.5 512.5 Q 1932.5 532.5 1917 555.75" fill="none" stroke="#000000" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 1913.12 561.57 L 1915.06 554.45 L 1918.94 557.04 Z" fill="#000000" stroke="#000000" stroke-miterlimit="10" pointer-events="all"/><rect x="1895" y="602.5" width="40" height="20" fill="none" stroke="none" pointer-events="all"/><g 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style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe flex-end; justify-content: unsafe center; width: 38px; height: 1px; padding-top: 507px; margin-left: 1896px;"><div style="box-sizing: border-box; font-size: 0; text-align: center; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font color="#B85450">regs</font></div></div></div></foreignObject><text x="1915" y="507" fill="#000000" font-family="Helvetica" font-size="12px" text-anchor="middle">regs</text></switch></g><rect x="1995" y="642.5" width="120" height="80" fill="#ffffff" stroke="#000000" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 118px; height: 1px; padding-top: 683px; margin-left: 1996px;"><div style="box-sizing: border-box; font-size: 0; text-align: center; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 20px">ACC</font></div></div></div></foreignObject><text x="2055" y="686" fill="#000000" font-family="Helvetica" font-size="12px" text-anchor="middle">ACC</text></switch></g><rect x="2085" y="672.5" width="30" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 28px; height: 1px; padding-top: 683px; margin-left: 2085px;"><div style="box-sizing: border-box; font-size: 0; text-align: right; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font face="Helvetica">out</font></div></div></div></foreignObject><text x="2113" y="686" fill="#000000" font-family="Helvetica" font-size="12px" text-anchor="end">out</text></switch></g><rect x="1995" y="672.5" width="20" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 18px; height: 1px; padding-top: 683px; margin-left: 1997px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; ">in</div></div></div></foreignObject><text x="1997" y="686" fill="#000000" font-family="Helvetica" font-size="12px">in</text></switch></g><rect x="2035" y="643" width="40" height="14.5" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe flex-end; justify-content: unsafe center; width: 38px; height: 1px; padding-top: 655px; margin-left: 2036px;"><div style="box-sizing: border-box; font-size: 0; text-align: center; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font color="#B85450">regs</font></div></div></div></foreignObject><text x="2055" y="655" fill="#000000" font-family="Helvetica" font-size="12px" text-anchor="middle">regs</text></switch></g><rect x="2155" y="657.5" width="100" height="50" fill="#ffffff" stroke="#000000" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 98px; height: 1px; padding-top: 683px; margin-left: 2156px;"><div style="box-sizing: border-box; font-size: 0; text-align: center; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 12px">16→32</font></div></div></div></foreignObject><text x="2205" y="686" fill="#000000" font-family="Helvetica" font-size="12px" text-anchor="middle">16→32</text></switch></g><rect x="2225" y="672.5" width="30" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe 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height: 1px; padding-top: 683px; margin-left: 2157px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; ">in</div></div></div></foreignObject><text x="2157" y="686" fill="#000000" font-family="Helvetica" font-size="12px">in</text></switch></g><rect x="2185" y="707.5" width="40" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 38px; height: 1px; padding-top: 718px; margin-left: 2186px;"><div style="box-sizing: border-box; font-size: 0; text-align: center; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; ">acc_adapter</div></div></div></foreignObject><text x="2205" y="721" fill="#000000" font-family="Helvetica" font-size="12px" text-anchor="middle">acc_ada...</text></switch></g><path d="M 2395 641.48 L 2415 602 L 2534.9 602 L 2554.9 641.48 Z" fill="#ffffff" stroke="#000000" stroke-miterlimit="10" transform="rotate(90,2474.95,621.74)" pointer-events="all"/><path d="M 2462.45 622.5 L 2467.45 622.5 L 2492.45 597.5" fill="none" stroke="#000000" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 2474.95 592.5 Q 2494.95 612.5 2479.45 635.75" fill="none" stroke="#000000" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 2475.57 641.57 L 2477.51 634.45 L 2481.39 637.04 Z" fill="#000000" stroke="#000000" stroke-miterlimit="10" pointer-events="all"/><rect x="2454.95" y="554.9" width="40" height="14.5" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe flex-end; justify-content: unsafe center; width: 38px; height: 1px; padding-top: 566px; margin-left: 2456px;"><div style="box-sizing: border-box; font-size: 0; text-align: center; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font color="#B85450">regs</font></div></div></div></foreignObject><text x="2475" y="566" fill="#000000" font-family="Helvetica" font-size="12px" text-anchor="middle">regs</text></switch></g><rect x="2554.9" y="597.21" width="100" height="50" fill="#ffffff" stroke="#000000" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 98px; height: 1px; padding-top: 622px; margin-left: 2556px;"><div style="box-sizing: border-box; font-size: 0; text-align: center; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 12px">32→8</font></div></div></div></foreignObject><text x="2605" y="626" fill="#000000" font-family="Helvetica" font-size="12px" text-anchor="middle">32→8</text></switch></g><rect x="2624.9" y="612.21" width="30" height="20" fill="none" stroke="none" pointer-events="all"/><g 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requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 38px; height: 1px; padding-top: 657px; margin-left: 2586px;"><div style="box-sizing: border-box; font-size: 0; text-align: center; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; ">uTx_adapter</div></div></div></foreignObject><text x="2605" y="661" fill="#000000" font-family="Helvetica" font-size="12px" text-anchor="middle">uTx_ada...</text></switch></g><rect x="2554.9" y="756.85" width="100" height="50" fill="#ffffff" stroke="#000000" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 98px; height: 1px; padding-top: 782px; margin-left: 2556px;"><div style="box-sizing: border-box; font-size: 0; text-align: center; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 12px">32→8</font></div></div></div></foreignObject><text x="2605" y="785" fill="#000000" font-family="Helvetica" font-size="12px" text-anchor="middle">32→8</text></switch></g><rect x="2624.9" y="771.85" width="30" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" 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stroke-width="4" stroke-miterlimit="10" pointer-events="all"/><rect x="253" y="71" width="95" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 93px; height: 1px; padding-top: 81px; margin-left: 255px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><div style="font-size: 16px" align="left"><font style="font-size: 16px" color="#666666"><b>Wishbone</b></font></div></div></div></div></foreignObject><text x="255" y="85" fill="#000000" font-family="Helvetica" font-size="12px">Wishbone</text></switch></g><rect x="253" y="91" width="95" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 93px; height: 1px; padding-top: 101px; margin-left: 255px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 16px" color="#666666"><b>AXI4</b></font></div></div></div></foreignObject><text x="255" y="105" fill="#000000" font-family="Helvetica" font-size="12px">AXI4</text></switch></g><rect x="253" y="111" width="165" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 163px; height: 1px; padding-top: 121px; margin-left: 255px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 16px" color="#666666"><b>AXI4-Stream 32b<br /></b></font></div></div></div></foreignObject><text x="255" y="125" fill="#000000" font-family="Helvetica" font-size="12px">AXI4-Stream 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pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 16px" color="#666666"><b>AXI4-Stream 8b<br /></b></font></div></div></div></foreignObject><text x="255" y="165" fill="#000000" font-family="Helvetica" font-size="12px">AXI4-Stream 8b&#xa;</text></switch></g><rect x="253" y="171" width="165" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 163px; height: 1px; padding-top: 181px; margin-left: 255px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 16px" color="#666666"><b>Single line<br /></b></font></div></div></div></foreignObject><text x="255" y="185" fill="#000000" font-family="Helvetica" font-size="12px">Single line&#xa;</text></switch></g><rect x="427" y="42" width="100" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 98px; height: 1px; padding-top: 52px; margin-left: 428px;"><div style="box-sizing: border-box; font-size: 0; text-align: center; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 18px" color="#666666"><b>Blocks:</b></font></div></div></div></foreignObject><text x="477" y="56" fill="#000000" font-family="Helvetica" font-size="12px" text-anchor="middle">Blocks:</text></switch></g><rect x="442" y="71" width="343" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 341px; height: 1px; padding-top: 81px; margin-left: 444px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 16px" color="#CC6600">•<font style="font-size: 16px"><sup><span style="font-size: 7px"></span></sup></font></font><font style="font-size: 16px" color="#CC6600"><b> always_ready: ready is <font style="font-size: 16px">always</font> active</b></font></div></div></div></foreignObject><text x="444" y="85" fill="#000000" font-family="Helvetica" font-size="12px">• always_ready: ready is always active</text></switch></g><rect x="442" y="91" width="348" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 346px; height: 1px; padding-top: 101px; margin-left: 444px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 16px" color="#CC6600">•<font style="font-size: 16px"><sup><span style="font-size: 7px"></span></sup></font></font><font size="1" color="#CC6600"><sup><span style="font-size: 7px"></span></sup></font><font style="font-size: 16px" color="#CC6600"><b> all_ones: output is 0xFFFF<br /></b></font></div></div></div></foreignObject><text x="444" y="105" fill="#000000" font-family="Helvetica" font-size="12px">• all_ones: output is 0xFFFF&#xa;</text></switch></g><rect x="442" y="111" width="343" height="20" fill="none" stroke="none" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 341px; height: 1px; padding-top: 121px; margin-left: 444px;"><div style="box-sizing: border-box; font-size: 0; text-align: left; "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: #000000; line-height: 1.2; pointer-events: all; white-space: normal; word-wrap: normal; "><font style="font-size: 16px" color="#CC6600">•<font style="font-size: 16px"><sup><span style="font-size: 7px"> </span></sup></font></font><font style="font-size: 16px" color="#CC6600"><b>all_zeros: output is 0x0000<br /></b></font></div></div></div></foreignObject><text x="444" y="125" fill="#000000" font-family="Helvetica" font-size="12px">• all_zeros: output is 0x0000&#xa;</text></switch></g></g><switch><g requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"/><a transform="translate(0,-5)" xlink:href="https://desk.draw.io/support/solutions/articles/16000042487" target="_blank"><text text-anchor="middle" font-size="10px" x="50%" y="100%">Viewer does not support full SVG 1.1</text></a></switch></svg>
\ No newline at end of file

diff --git a/cargo/spectrometer b/cargo/spectrometer
new file mode 160000
index 0000000..ba0c1a0
--- /dev/null
+++ b/cargo/spectrometer

@@ -0,0 +1 @@
+Subproject commit ba0c1a00f230f2f6011c8bad4f6896c62546396c

diff --git a/cargo/top/dv/README.md b/cargo/top/dv/README.md
new file mode 100644
index 0000000..07aa660
--- /dev/null
+++ b/cargo/top/dv/README.md

@@ -0,0 +1,20 @@
+# DV Tests
+
+Organized into one subdirectories:
+  * caravel: contains tests for example user project.
+
+<pre>
+├── SpectrometerTest
+│   └── spectrometer
+│       ├── plfg_nco_fft_mag_acc_pout
+│       ├── plfg_nco_fft_mag_acc_utx
+│       ├── pin_fft_mag_acc_pout
+│       └── pin_nco_fft_mag_acc_pout
+└── SpectrometerTestWithLAoutputs
+    └── spectrometer
+        ├── plfg_nco_fft_mag_acc_pout
+        ├── plfg_nco_fft_mag_acc_utx
+        ├── pin_fft_mag_acc_pout
+        └── pin_nco_fft_mag_acc_pout
+</pre>
+

diff --git a/cargo/top/dv/SpectrometerTest/defs.h b/cargo/top/dv/SpectrometerTest/defs.h
new file mode 100644
index 0000000..5a273a0
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/defs.h

@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _STRIVE_H_
+#define _STRIVE_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+// a pointer to this is a null pointer, but the compiler does not
+// know that because "sram" is a linker symbol from sections.lds.
+extern uint32_t sram;
+
+// Pointer to firmware flash routines
+extern uint32_t flashio_worker_begin;
+extern uint32_t flashio_worker_end;
+
+// Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
+#define reg_rw_block0  (*(volatile uint32_t*)0x01000000)
+#define reg_rw_block1  (*(volatile uint32_t*)0x01100000)
+#define reg_ro_block0  (*(volatile uint32_t*)0x02000000)
+
+// UART (0x2000_0000)
+#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
+#define reg_uart_data   (*(volatile uint32_t*)0x20000004)
+#define reg_uart_enable (*(volatile uint32_t*)0x20000008)
+
+// GPIO (0x2100_0000)
+#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
+#define reg_gpio_ena  (*(volatile uint32_t*)0x21000004)
+#define reg_gpio_pu   (*(volatile uint32_t*)0x21000008)
+#define reg_gpio_pd   (*(volatile uint32_t*)0x2100000c)
+
+// Logic Analyzer (0x2200_0000)
+#define reg_la0_data (*(volatile uint32_t*)0x25000000)
+#define reg_la1_data (*(volatile uint32_t*)0x25000004)
+#define reg_la2_data (*(volatile uint32_t*)0x25000008)
+#define reg_la3_data (*(volatile uint32_t*)0x2500000c)
+
+#define reg_la0_ena (*(volatile uint32_t*)0x25000010)
+#define reg_la1_ena (*(volatile uint32_t*)0x25000014)
+#define reg_la2_ena (*(volatile uint32_t*)0x25000018)
+#define reg_la3_ena (*(volatile uint32_t*)0x2500001c)
+
+// User Project Control (0x2300_0000)
+#define reg_mprj_xfer (*(volatile uint32_t*)0x26000000)
+#define reg_mprj_pwr  (*(volatile uint32_t*)0x26000004)
+#define reg_mprj_datal (*(volatile uint32_t*)0x26000008)
+#define reg_mprj_datah (*(volatile uint32_t*)0x2600000c)
+
+#define reg_mprj_io_0 (*(volatile uint32_t*)0x26000020)
+#define reg_mprj_io_1 (*(volatile uint32_t*)0x26000024)
+#define reg_mprj_io_2 (*(volatile uint32_t*)0x26000028)
+#define reg_mprj_io_3 (*(volatile uint32_t*)0x2600002c)
+#define reg_mprj_io_4 (*(volatile uint32_t*)0x26000030)
+#define reg_mprj_io_5 (*(volatile uint32_t*)0x26000034)
+#define reg_mprj_io_6 (*(volatile uint32_t*)0x26000038)
+
+#define reg_mprj_io_7 (*(volatile uint32_t*)0x2600003c)
+#define reg_mprj_io_8 (*(volatile uint32_t*)0x26000040)
+#define reg_mprj_io_9 (*(volatile uint32_t*)0x26000044)
+#define reg_mprj_io_10 (*(volatile uint32_t*)0x26000048)
+
+#define reg_mprj_io_11 (*(volatile uint32_t*)0x2600004c)
+#define reg_mprj_io_12 (*(volatile uint32_t*)0x26000050)
+#define reg_mprj_io_13 (*(volatile uint32_t*)0x26000054)
+#define reg_mprj_io_14 (*(volatile uint32_t*)0x26000058)
+
+#define reg_mprj_io_15 (*(volatile uint32_t*)0x2600005c)
+#define reg_mprj_io_16 (*(volatile uint32_t*)0x26000060)
+#define reg_mprj_io_17 (*(volatile uint32_t*)0x26000064)
+#define reg_mprj_io_18 (*(volatile uint32_t*)0x26000068)
+
+#define reg_mprj_io_19 (*(volatile uint32_t*)0x2600006c)
+#define reg_mprj_io_20 (*(volatile uint32_t*)0x26000070)
+#define reg_mprj_io_21 (*(volatile uint32_t*)0x26000074)
+#define reg_mprj_io_22 (*(volatile uint32_t*)0x26000078)
+
+#define reg_mprj_io_23 (*(volatile uint32_t*)0x2600007c)
+#define reg_mprj_io_24 (*(volatile uint32_t*)0x26000080)
+#define reg_mprj_io_25 (*(volatile uint32_t*)0x26000084)
+#define reg_mprj_io_26 (*(volatile uint32_t*)0x26000088)
+
+#define reg_mprj_io_27 (*(volatile uint32_t*)0x2600008c)
+#define reg_mprj_io_28 (*(volatile uint32_t*)0x26000090)
+#define reg_mprj_io_29 (*(volatile uint32_t*)0x26000094)
+#define reg_mprj_io_30 (*(volatile uint32_t*)0x26000098)
+#define reg_mprj_io_31 (*(volatile uint32_t*)0x2600009c)
+
+#define reg_mprj_io_32 (*(volatile uint32_t*)0x260000a0)
+#define reg_mprj_io_33 (*(volatile uint32_t*)0x260000a4)
+#define reg_mprj_io_34 (*(volatile uint32_t*)0x260000a8)
+#define reg_mprj_io_35 (*(volatile uint32_t*)0x260000ac)
+#define reg_mprj_io_36 (*(volatile uint32_t*)0x260000b0)
+#define reg_mprj_io_37 (*(volatile uint32_t*)0x260000b4)
+
+// User Project Slaves (0x3000_0000)
+#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
+
+// Flash Control SPI Configuration (2D00_0000)
+#define reg_spictrl (*(volatile uint32_t*)0x2d000000)         
+
+// Bit fields for Flash SPI control
+#define FLASH_BITBANG_IO0	0x00000001
+#define FLASH_BITBANG_IO1	0x00000002
+#define FLASH_BITBANG_CLK	0x00000010
+#define FLASH_BITBANG_CSB	0x00000020
+#define FLASH_BITBANG_OEB0	0x00000100
+#define FLASH_BITBANG_OEB1	0x00000200
+#define FLASH_ENABLE		0x80000000
+
+// Counter-Timer 0 Configuration
+#define reg_timer0_config (*(volatile uint32_t*)0x22000000)
+#define reg_timer0_value  (*(volatile uint32_t*)0x22000004)
+#define reg_timer0_data   (*(volatile uint32_t*)0x22000008)
+
+// Counter-Timer 1 Configuration
+#define reg_timer1_config (*(volatile uint32_t*)0x23000000)
+#define reg_timer1_value  (*(volatile uint32_t*)0x23000004)
+#define reg_timer1_data   (*(volatile uint32_t*)0x23000008)
+
+// Bit fields for Counter-timer configuration
+#define TIMER_ENABLE		0x01
+#define TIMER_ONESHOT		0x02
+#define TIMER_UPCOUNT		0x04
+#define TIMER_CHAIN		0x08
+#define TIMER_IRQ_ENABLE	0x10
+
+// SPI Master Configuration
+#define reg_spimaster_config (*(volatile uint32_t*)0x24000000)
+#define reg_spimaster_data   (*(volatile uint32_t*)0x24000004)
+
+// Bit fields for SPI master configuration
+#define SPI_MASTER_DIV_MASK	0x00ff
+#define SPI_MASTER_MLB		0x0100
+#define SPI_MASTER_INV_CSB	0x0200
+#define SPI_MASTER_INV_CLK	0x0400
+#define SPI_MASTER_MODE_1	0x0800
+#define SPI_MASTER_STREAM	0x1000
+#define SPI_MASTER_ENABLE	0x2000
+#define SPI_MASTER_IRQ_ENABLE	0x4000
+#define SPI_HOUSEKEEPING_CONN	0x8000
+
+// System Area (0x2F00_0000)
+#define reg_power_good    (*(volatile uint32_t*)0x2F000000)
+#define reg_clk_out_dest  (*(volatile uint32_t*)0x2F000004)
+#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000008)
+#define reg_irq_source    (*(volatile uint32_t*)0x2F00000C)
+
+// Bit fields for reg_power_good
+#define USER1_VCCD_POWER_GOOD 0x01
+#define USER2_VCCD_POWER_GOOD 0x02
+#define USER1_VDDA_POWER_GOOD 0x04
+#define USER2_VDDA_POWER_GOOD 0x08
+
+// Bit fields for reg_clk_out_dest
+#define CLOCK1_MONITOR 0x01
+#define CLOCK2_MONITOR 0x02
+
+// Bit fields for reg_irq_source
+#define IRQ7_SOURCE 0x01
+#define IRQ8_SOURCE 0x02
+
+// Individual bit fields for the GPIO pad control
+#define MGMT_ENABLE	  0x0001
+#define OUTPUT_DISABLE	  0x0002
+#define HOLD_OVERRIDE	  0x0004
+#define INPUT_DISABLE	  0x0008
+#define MODE_SELECT	  0x0010
+#define ANALOG_ENABLE	  0x0020
+#define ANALOG_SELECT	  0x0040
+#define ANALOG_POLARITY	  0x0080
+#define SLOW_SLEW_MODE	  0x0100
+#define TRIPPOINT_SEL	  0x0200
+#define DIGITAL_MODE_MASK 0x1c00
+
+// Useful GPIO mode values
+#define GPIO_MODE_MGMT_STD_INPUT_NOPULL    0x0403
+#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN  0x0803
+#define GPIO_MODE_MGMT_STD_INPUT_PULLUP	   0x0c03
+#define GPIO_MODE_MGMT_STD_OUTPUT	   0x1809
+
+#define GPIO_MODE_USER_STD_INPUT_NOPULL	   0x0402
+#define GPIO_MODE_USER_STD_INPUT_PULLDOWN  0x0802
+#define GPIO_MODE_USER_STD_INPUT_PULLUP	   0x0c02
+#define GPIO_MODE_USER_STD_OUTPUT	   0x1808
+
+// --------------------------------------------------------
+#endif

diff --git a/cargo/top/dv/SpectrometerTest/sections.lds b/cargo/top/dv/SpectrometerTest/sections.lds
new file mode 100644
index 0000000..d785002
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/sections.lds

@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+MEMORY {
+	FLASH (rx)	: ORIGIN = 0x10000000, LENGTH = 0x400000 	/* 4MB */
+	RAM(xrw)	: ORIGIN = 0x00000000, LENGTH = 0x0400		/* 256 words (1 KB) */ 
+}
+
+SECTIONS {
+	/* The program code and other data goes into FLASH */
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)	/* .text sections (code) */
+		*(.text*)	/* .text* sections (code) */
+		*(.rodata)	/* .rodata sections (constants, strings, etc.) */
+		*(.rodata*)	/* .rodata* sections (constants, strings, etc.) */
+		*(.srodata)	/* .srodata sections (constants, strings, etc.) */
+		*(.srodata*)	/* .srodata*sections (constants, strings, etc.) */
+		. = ALIGN(4);
+		_etext = .;		/* define a global symbol at end of code */
+		_sidata = _etext;	/* This is used by the startup to initialize data */
+	} >FLASH
+
+	/* Initialized data section */
+	.data : AT ( _sidata )
+	{
+		. = ALIGN(4);
+		_sdata = .;
+		_ram_start = .;
+		. = ALIGN(4);
+		*(.data)
+		*(.data*)
+		*(.sdata)
+		*(.sdata*)
+		. = ALIGN(4);
+		_edata = .;
+	} >RAM
+
+	/* Uninitialized data section */
+	.bss :
+	{
+		. = ALIGN(4);
+		_sbss = .;
+		*(.bss)
+		*(.bss*)
+		*(.sbss)
+		*(.sbss*)
+		*(COMMON)
+
+		. = ALIGN(4);
+		_ebss = .;
+	} >RAM
+
+	/* Define the start of the heap */
+	.heap :
+	{
+		. = ALIGN(4);
+		_heap_start = .;
+	} >RAM
+}

diff --git a/cargo/top/dv/SpectrometerTest/spectrometer/Makefile b/cargo/top/dv/SpectrometerTest/spectrometer/Makefile
new file mode 100644
index 0000000..56c03ca
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spectrometer/Makefile

@@ -0,0 +1,19 @@
+# ---- Test patterns ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = plfg_nco_fft_mag_acc_pout plfg_nco_fft_mag_acc_utx pin_fft_mag_acc_pout pin_nco_fft_mag_acc_pout
+
+all:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+	done
+
+clean:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		rm -f verify.log; \
+		( cd $$i && make clean ) ; \
+	done
+
+.PHONY: clean all

diff --git a/cargo/top/dv/SpectrometerTest/spectrometer/pin_fft_mag_acc_pout/Makefile b/cargo/top/dv/SpectrometerTest/spectrometer/pin_fft_mag_acc_pout/Makefile
new file mode 100644
index 0000000..35ab772
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spectrometer/pin_fft_mag_acc_pout/Makefile

@@ -0,0 +1,54 @@
+CARAVEL_PATH = ./../../../../../..
+
+FIRMWARE_PATH = ../..
+RTL_PATH = $(CARAVEL_PATH)/verilog/rtl
+IP_PATH = $(CARAVEL_PATH)/verilog/ip
+BEHAVIOURAL_MODELS = ../../ 
+
+CARGO_PATH   = $(CARAVEL_PATH)/cargo
+WB2AXI_PATH  = $(CARAVEL_PATH)/cargo/wb2axip/rtl
+PROJECT_PATH = $(CARAVEL_PATH)/cargo/spectrometer/rtl/SpectrometerTest
+TOP_PATH     = $(CARAVEL_PATH)/cargo/top/rtl/SpectrometerTest
+
+GCC_PATH?=$(RISCV32)/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+FFT_SIZE?=64 # Pass fft size to testbench and c code
+
+.SUFFIXES:
+
+PATTERN = pin_fft_mag_acc_pout
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -DFUNCTIONAL -DSIM -DFFT_SIZE=$(FFT_SIZE) -I $(BEHAVIOURAL_MODELS) \
+	-I $(WB2AXI_PATH)  \
+	-I $(PROJECT_PATH) \
+	-I $(TOP_PATH) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -DFFT_SIZE=$(FFT_SIZE) -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.txt
+
+.PHONY: clean hex all

diff --git a/cargo/top/dv/SpectrometerTest/spectrometer/pin_fft_mag_acc_pout/pin_fft_mag_acc_pout.c b/cargo/top/dv/SpectrometerTest/spectrometer/pin_fft_mag_acc_pout/pin_fft_mag_acc_pout.c
new file mode 100644
index 0000000..932cfcf
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spectrometer/pin_fft_mag_acc_pout/pin_fft_mag_acc_pout.c

@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: Apache-2.0
+
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../../spectrometerDefs.h"
+
+/*
+	Spectrometer Test:
+		- Set spectrometer to pass data through:
+                        pin
+                        fft
+                        mag
+                        acc
+                        pout
+*/
+
+int clk = 0;
+int i;
+
+void main()
+{
+	// Configure GPIO pins
+        reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+        reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+
+        reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+
+        reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_9  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_8  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_7  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_6  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_5  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_4  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_3  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_2  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_1  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+        /* Apply configuration */
+        reg_mprj_xfer = 1;
+        while (reg_mprj_xfer == 1);
+
+        int segmentNumsArrayOffset = 6 * BEATBYTES;
+        int repeatedChirpNumsArrayOffset = segmentNumsArrayOffset + 4 * BEATBYTES;
+        int chirpOrdinalNumsArrayOffset = repeatedChirpNumsArrayOffset + 8 * BEATBYTES;
+
+        PLFG_RAM(0) = 0x24000000;
+        PLFG_REG(2*BEATBYTES) = 8;
+        PLFG_REG(4*BEATBYTES) = 1;
+        PLFG_REG(5*BEATBYTES) = 4;
+        PLFG_REG(segmentNumsArrayOffset) = 1;
+        PLFG_REG(repeatedChirpNumsArrayOffset) = 1;
+        PLFG_REG(chirpOrdinalNumsArrayOffset) = 0;
+        PLFG_REG(1*BEATBYTES) = 0;
+        PLFG_REG(0*BEATBYTES) = 1;
+
+        MAG_REG(0) = 0x2; // set jpl magnitude
+        
+        ACC_REG(0)           = FFT_SIZE;
+        ACC_REG(1*BEATBYTES) = 4;
+
+        FFT_MUX_1_REG(0)           = 0;
+        MAG_MUX_1_REG(0)           = 0;
+
+        PLFG_MUX_0_REG(1*BEATBYTES)= 1;
+        NCO_MUX_0_REG(0)           = 1;
+        FFT_MUX_0_REG(0)           = 0;
+        FFT_MUX_0_REG(1*BEATBYTES) = 1;
+        MAG_MUX_0_REG(0)           = 0;
+        MAG_MUX_0_REG(1*BEATBYTES) = 1;
+
+        OUT_MUX_REG(0)             = 0;
+        OUT_MUX_REG(2*BEATBYTES)   = 5;
+
+}
+

diff --git a/cargo/top/dv/SpectrometerTest/spectrometer/pin_fft_mag_acc_pout/pin_fft_mag_acc_pout_tb.v b/cargo/top/dv/SpectrometerTest/spectrometer/pin_fft_mag_acc_pout/pin_fft_mag_acc_pout_tb.v
new file mode 100644
index 0000000..104e343
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spectrometer/pin_fft_mag_acc_pout/pin_fft_mag_acc_pout_tb.v

@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel.v"
+`include "spiflash.v"
+
+module pin_fft_mag_acc_pout_tb;
+	// declare file for writing data
+	integer file;
+	
+	// input data to send
+	reg [7:0] inputData [0:4*`FFT_SIZE-1];
+
+	// Golden data
+	reg [15:0] goldenData [0:`FFT_SIZE-1];
+
+	// clk, rst, power signals
+	reg clock;
+    reg RSTB;
+	reg power1, power2;
+
+	// testbench signals
+    wire 		gpio;
+    wire [37:0] mprj_io;
+
+	// Output stream data wires
+	reg 	    out_ready = 0;
+	wire 	    out_valid;
+	wire  [7:0] out_data;
+	reg   [7:0] out_temp;
+
+	// Input stream data wires
+	wire 	    in_ready;
+	reg 	    in_valid = 0;
+	reg  [7:0]  in_data = 8'h04;
+	reg			in_last = 0;
+
+	reg [15:0] dataCounter = 16'b0;
+	reg [15:0] dataSentCounter = 16'b0;
+
+	// Assign wires
+	assign mprj_io[11]  = out_ready;
+	assign out_valid    = mprj_io[12];
+	assign out_data     = mprj_io[20:13];
+
+	assign in_ready 	= mprj_io[0];
+	assign mprj_io[1]   = in_valid;
+	assign mprj_io[9:2] = in_data[7:0];
+	assign mprj_io[10]  = in_last;
+
+	
+	// toggle clock
+	always #500 clock <= (clock === 1'b0);
+
+	// Read input data
+	initial $readmemh("./../../../../../../cargo/spectrometer/test_run_dir/SpectrometerTest/pin_fft_mag_acc_pout/input.txt", inputData);
+
+	// Read golden data
+	initial $readmemh("./../../../../../../cargo/spectrometer/test_run_dir/SpectrometerTest/pin_fft_mag_acc_pout/GoldenData.txt", goldenData);
+
+	// open file for writting
+	initial begin
+		$printtimescale(pin_fft_mag_acc_pout_tb);
+		file = $fopen("output.txt","w");
+		if (file) $display("File was opened successfully : %0d", file);
+    	else $display("File was NOT opened successfully : %0d", file);
+	end
+
+	initial begin
+		clock = 0;
+		#500 out_ready = 1'b1; // Set out_ready
+	end
+
+	// Check inStream.ready and inStream.valid and send data
+	always @ (posedge clock) begin
+		if (in_ready == 1'b1) begin
+			in_valid = 1'b1;
+			in_data <= inputData[dataSentCounter % (4*`FFT_SIZE)];
+			dataSentCounter <= dataSentCounter + 1'b1;
+		end
+	end
+
+	// Check outStream.ready and outStream.valid and collect data
+	always @ (posedge clock) begin
+		if (out_ready == 1'b1 && out_valid == 1'b1) begin
+			if (dataCounter % 2 == 0) out_temp <= out_data;
+			else begin
+				$fwriteh(file, "%h" ,out_data);
+				$fwriteh(file, "%h\n" ,out_temp);
+				if ({out_data,out_temp} != goldenData[dataCounter/2]) begin
+					$display("%c[1;31m",27);
+					$display ("Monitor: Test pin_fft_mag_acc_pout failed!!! Read data was %h, but should be %h.", {out_data,out_temp}, goldenData[dataCounter/2]);
+					$display("%c[0m",27);
+					$fclose(file); 
+					$finish;
+				end
+			end
+			dataCounter <= dataCounter + 1'b1;
+		end
+	end
+
+	initial begin
+		$dumpfile("pin_fft_mag_acc_pout.vcd");
+		$dumpvars(0, pin_fft_mag_acc_pout_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Test pin_fft_mag_acc_pout Failed!!! Timeout.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	// Check if enough data was send, and if so terminate test
+	initial begin
+		wait(dataCounter == 16'd 2*`FFT_SIZE);
+		$display("%c[1;32m",27);
+		$display("Monitor: Test pin_fft_mag_acc_pout passed.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#10000;
+		RSTB <= 1'b1;	    // Release reset
+		#20000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("pin_fft_mag_acc_pout.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire

diff --git a/cargo/top/dv/SpectrometerTest/spectrometer/pin_nco_fft_mag_acc_pout/Makefile b/cargo/top/dv/SpectrometerTest/spectrometer/pin_nco_fft_mag_acc_pout/Makefile
new file mode 100644
index 0000000..b3e507a
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spectrometer/pin_nco_fft_mag_acc_pout/Makefile

@@ -0,0 +1,54 @@
+CARAVEL_PATH = ./../../../../../..
+
+FIRMWARE_PATH = ../..
+RTL_PATH = $(CARAVEL_PATH)/verilog/rtl
+IP_PATH = $(CARAVEL_PATH)/verilog/ip
+BEHAVIOURAL_MODELS = ../../ 
+
+CARGO_PATH   = $(CARAVEL_PATH)/cargo
+WB2AXI_PATH  = $(CARAVEL_PATH)/cargo/wb2axip/rtl
+PROJECT_PATH = $(CARAVEL_PATH)/cargo/spectrometer/rtl/SpectrometerTest
+TOP_PATH     = $(CARAVEL_PATH)/cargo/top/rtl/SpectrometerTest
+
+GCC_PATH?=$(RISCV32)/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+FFT_SIZE?=64 # Pass fft size to testbench and c code
+
+.SUFFIXES:
+
+PATTERN = pin_nco_fft_mag_acc_pout
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -DFUNCTIONAL -DSIM -DFFT_SIZE=$(FFT_SIZE) -I $(BEHAVIOURAL_MODELS) \
+	-I $(WB2AXI_PATH)  \
+	-I $(PROJECT_PATH) \
+	-I $(TOP_PATH) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -DFFT_SIZE=$(FFT_SIZE) -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.txt
+
+.PHONY: clean hex all

diff --git a/cargo/top/dv/SpectrometerTest/spectrometer/pin_nco_fft_mag_acc_pout/pin_nco_fft_mag_acc_pout.c b/cargo/top/dv/SpectrometerTest/spectrometer/pin_nco_fft_mag_acc_pout/pin_nco_fft_mag_acc_pout.c
new file mode 100644
index 0000000..fd345b1
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spectrometer/pin_nco_fft_mag_acc_pout/pin_nco_fft_mag_acc_pout.c

@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: Apache-2.0
+
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../../spectrometerDefs.h"
+
+/*
+	Spectrometer Test:
+		- Set spectrometer to pass data through:
+                        pin
+                        nco
+                        fft
+                        mag
+                        acc
+                        pout
+*/
+
+int clk = 0;
+int i;
+
+void main()
+{
+	// Configure GPIO pins
+        reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+        reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+
+        reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+
+        reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_9  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_8  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_7  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_6  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_5  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_4  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_3  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_2  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_1  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+        /* Apply configuration */
+        reg_mprj_xfer = 1;
+        while (reg_mprj_xfer == 1);
+
+        int segmentNumsArrayOffset = 6 * BEATBYTES;
+        int repeatedChirpNumsArrayOffset = segmentNumsArrayOffset + 4 * BEATBYTES;
+        int chirpOrdinalNumsArrayOffset = repeatedChirpNumsArrayOffset + 8 * BEATBYTES;
+
+        PLFG_RAM(0) = 0x24000000;
+        PLFG_REG(2*BEATBYTES) = 8;
+        PLFG_REG(4*BEATBYTES) = 1;
+        PLFG_REG(5*BEATBYTES) = 4;
+        PLFG_REG(segmentNumsArrayOffset) = 1;
+        PLFG_REG(repeatedChirpNumsArrayOffset) = 1;
+        PLFG_REG(chirpOrdinalNumsArrayOffset) = 0;
+        PLFG_REG(1*BEATBYTES) = 0;
+        PLFG_REG(0*BEATBYTES) = 1;
+
+        MAG_REG(0) = 0x2; // set jpl magnitude
+        
+        ACC_REG(0)           = FFT_SIZE;
+        ACC_REG(1*BEATBYTES) = 4;
+
+        NCO_MUX_1_REG(0)           = 0;
+        FFT_MUX_1_REG(0)           = 0;
+        MAG_MUX_1_REG(0)           = 0;
+
+        PLFG_MUX_0_REG(0)          = 1;
+        NCO_MUX_0_REG(0)           = 0;
+        NCO_MUX_0_REG(1*BEATBYTES) = 1;
+        FFT_MUX_0_REG(0)           = 0;
+        FFT_MUX_0_REG(1*BEATBYTES) = 1;
+        MAG_MUX_0_REG(0)           = 0;
+        MAG_MUX_0_REG(1*BEATBYTES) = 1;
+
+        OUT_MUX_REG(0)             = 0;
+        OUT_MUX_REG(2*BEATBYTES)   = 5;
+
+}
+

diff --git a/cargo/top/dv/SpectrometerTest/spectrometer/pin_nco_fft_mag_acc_pout/pin_nco_fft_mag_acc_pout_tb.v b/cargo/top/dv/SpectrometerTest/spectrometer/pin_nco_fft_mag_acc_pout/pin_nco_fft_mag_acc_pout_tb.v
new file mode 100644
index 0000000..bdbd5bd
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spectrometer/pin_nco_fft_mag_acc_pout/pin_nco_fft_mag_acc_pout_tb.v

@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel.v"
+`include "spiflash.v"
+
+module pin_nco_fft_mag_acc_pout_tb;
+	// declare file for writing data
+	integer file;
+	
+	// Golden data
+	reg [15:0] goldenData [0:`FFT_SIZE-1];
+
+	// clk, rst, power signals
+	reg clock;
+    reg RSTB;
+	reg power1, power2;
+
+	// testbench signals
+    wire 		gpio;
+    wire [37:0] mprj_io;
+
+	// Output stream data wires
+	reg 	    out_ready = 0;
+	wire 	    out_valid;
+	wire  [7:0] out_data;
+	reg   [7:0] out_temp;
+
+	// Input stream data wires
+	wire 	    in_ready;
+	reg 	    in_valid = 0;
+	reg  [7:0]  in_data = 8'h04;
+	reg			in_last = 0;
+
+	reg [15:0] dataCounter = 16'b0;
+	reg [1:0] dataSentCounter = 2'b0;
+
+	// Assign wires
+	assign mprj_io[11]  = out_ready;
+	assign out_valid    = mprj_io[12];
+	assign out_data     = mprj_io[20:13];
+
+	assign in_ready 	= mprj_io[0];
+	assign mprj_io[1]   = in_valid;
+	assign mprj_io[9:2] = in_data[7:0];
+	assign mprj_io[10]  = in_last;
+
+	
+	// toggle clock
+	always #500 clock <= (clock === 1'b0);
+
+	// Read golden data
+	initial $readmemh("./../../../../../../cargo/spectrometer/test_run_dir/SpectrometerTest/pin_nco_fft_mag_acc_pout/GoldenData.txt", goldenData);
+
+	// open file for writting
+	initial begin
+		$printtimescale(pin_nco_fft_mag_acc_pout_tb);
+		file = $fopen("output.txt","w");
+		if (file) $display("File was opened successfully : %0d", file);
+    	else $display("File was NOT opened successfully : %0d", file);
+	end
+
+	initial begin
+		clock = 0;
+		#500 out_ready = 1'b1; // Set out_ready
+	end
+
+	// Check inStream.ready and inStream.valid and send data
+	always @ (posedge clock) begin
+		if (in_ready == 1'b1) begin
+			in_valid = 1'b1;
+			if (dataSentCounter % 4 == 0) in_data <= 8'h04;
+			else in_data <= 8'h00;
+			dataSentCounter <= dataSentCounter + 1'b1;
+		end
+	end
+
+	// Check outStream.ready and outStream.valid and collect data
+	always @ (posedge clock) begin
+		if (out_ready == 1'b1 && out_valid == 1'b1) begin
+			if (dataCounter % 2 == 0) out_temp <= out_data;
+			else begin
+				$fwriteh(file, "%h" ,out_data);
+				$fwriteh(file, "%h\n" ,out_temp);
+				if ({out_data,out_temp} != goldenData[dataCounter/2]) begin
+					$display("%c[1;31m",27);
+					$display ("Monitor: Test pin_nco_fft_mag_acc_pout failed!!! Read data was %h, but should be %h.", {out_data,out_temp}, goldenData[dataCounter/2]);
+					$display("%c[0m",27);
+					$fclose(file); 
+					$finish;
+				end
+			end
+			dataCounter <= dataCounter + 1'b1;
+		end
+	end
+
+	initial begin
+		$dumpfile("pin_nco_fft_mag_acc_pout.vcd");
+		$dumpvars(0, pin_nco_fft_mag_acc_pout_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Test pin_nco_fft_mag_acc_pout failed!!! Timeout.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	// Check if enough data was send, and if so terminate test
+	initial begin
+		wait(dataCounter == 16'd 2*`FFT_SIZE);
+		$display("%c[1;32m",27);
+		$display("Monitor: Test pin_nco_fft_mag_acc_pout passed.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#10000;
+		RSTB <= 1'b1;	    // Release reset
+		#20000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("pin_nco_fft_mag_acc_pout.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire

diff --git a/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_pout/Makefile b/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_pout/Makefile
new file mode 100644
index 0000000..8e6eae6
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_pout/Makefile

@@ -0,0 +1,54 @@
+CARAVEL_PATH = ./../../../../../..
+
+FIRMWARE_PATH = ../..
+RTL_PATH = $(CARAVEL_PATH)/verilog/rtl
+IP_PATH = $(CARAVEL_PATH)/verilog/ip
+BEHAVIOURAL_MODELS = ../../ 
+
+CARGO_PATH   = $(CARAVEL_PATH)/cargo
+WB2AXI_PATH  = $(CARAVEL_PATH)/cargo/wb2axip/rtl
+PROJECT_PATH = $(CARAVEL_PATH)/cargo/spectrometer/rtl/SpectrometerTest
+TOP_PATH     = $(CARAVEL_PATH)/cargo/top/rtl/SpectrometerTest
+
+GCC_PATH?=$(RISCV32)/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+FFT_SIZE?=64 # Pass fft size to testbench and c code
+
+.SUFFIXES:
+
+PATTERN = plfg_nco_fft_mag_acc_pout
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -DFUNCTIONAL -DSIM -DFFT_SIZE=$(FFT_SIZE) -I $(BEHAVIOURAL_MODELS) \
+	-I $(WB2AXI_PATH)  \
+	-I $(PROJECT_PATH) \
+	-I $(TOP_PATH) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -DFFT_SIZE=$(FFT_SIZE) -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.txt
+
+.PHONY: clean hex all

diff --git a/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_pout/plfg_nco_fft_mag_acc_pout.c b/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_pout/plfg_nco_fft_mag_acc_pout.c
new file mode 100644
index 0000000..8c5dc86
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_pout/plfg_nco_fft_mag_acc_pout.c

@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: Apache-2.0
+
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../../spectrometerDefs.h"
+
+/*
+	Spectrometer Test:
+		- Set spectrometer to pass data through:
+                        plfg
+                        nco
+                        fft
+                        mag
+                        acc
+                        pout
+*/
+
+int clk = 0;
+int i;
+
+void main()
+{
+	// Configure GPIO pins
+        reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+        reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+
+        reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+
+        reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_9  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_8  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_7  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_6  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_5  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_4  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_3  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_2  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_1  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+        reg_la0_ena  = 0xFFFFFFFB;
+        reg_la0_ena  = 0xFFFFFFFF;
+        reg_la0_ena  = 0xFFFFFFFB;
+        reg_la0_ena  = 0xFFFFFFFF;
+        reg_la0_ena  = 0xFFFFFFFB;
+        reg_la0_ena  = 0xFFFFFFFF;
+        reg_la0_ena  = 0xFFFFFFFB;
+        reg_la0_ena  = 0xFFFFFFFF;
+        reg_la0_ena  = 0xFFFFFFFB;
+        reg_la0_ena  = 0xFFFFFFFF;
+        reg_la0_ena  = 0xFFFFFFFB;
+        reg_la0_ena  = 0xFFFFFFFF;
+        reg_la0_ena  = 0xFFFFFFFB;
+        reg_la0_ena  = 0xFFFFFFFF;
+        reg_la0_data = 0xFEEDBEEF;
+
+        /* Apply configuration */
+        reg_mprj_xfer = 1;
+        while (reg_mprj_xfer == 1);
+
+        int segmentNumsArrayOffset = 6 * BEATBYTES;
+        int repeatedChirpNumsArrayOffset = segmentNumsArrayOffset + 4 * BEATBYTES;
+        int chirpOrdinalNumsArrayOffset = repeatedChirpNumsArrayOffset + 8 * BEATBYTES;
+
+        PLFG_RAM(0) = 0x24000000;
+        PLFG_REG(2*BEATBYTES) = 8;
+        PLFG_REG(4*BEATBYTES) = 1;
+        PLFG_REG(5*BEATBYTES) = 8*128/FFT_SIZE;
+        PLFG_REG(segmentNumsArrayOffset) = 1;
+        PLFG_REG(repeatedChirpNumsArrayOffset) = 1;
+        PLFG_REG(chirpOrdinalNumsArrayOffset) = 0;
+        PLFG_REG(1*BEATBYTES) = 0;
+        PLFG_REG(0*BEATBYTES) = 1;
+
+        MAG_REG(0) = 0x2; // set jpl magnitude
+        
+        ACC_REG(0)           = FFT_SIZE;
+        ACC_REG(1*BEATBYTES) = 4;
+
+        PLFG_MUX_1_REG(0) = 0;
+        NCO_MUX_1_REG(0)  = 0;
+        FFT_MUX_1_REG(0)  = 0;
+        MAG_MUX_1_REG(0)  = 0;
+
+        PLFG_MUX_0_REG(0) = 0;
+        NCO_MUX_0_REG(0)  = 0;
+        FFT_MUX_0_REG(0)  = 0;
+        MAG_MUX_0_REG(0)  = 0;
+
+        OUT_MUX_REG(0) = 0;
+
+}
+

diff --git a/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_pout/plfg_nco_fft_mag_acc_pout_tb.v b/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_pout/plfg_nco_fft_mag_acc_pout_tb.v
new file mode 100644
index 0000000..d4130e3
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_pout/plfg_nco_fft_mag_acc_pout_tb.v

@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel.v"
+`include "spiflash.v"
+
+module plfg_nco_fft_mag_acc_pout_tb;
+	// declare file for writing data
+	integer file;
+
+	// Golden data
+	reg [15:0] goldenData [0:`FFT_SIZE-1];
+	
+	// clk, rst, power signals
+	reg clock;
+    reg RSTB;
+	reg power1, power2;
+
+	// testbench signals
+    wire 		gpio;
+    wire [37:0] mprj_io;
+
+	// Output stream data wires
+	reg 	    out_ready;
+	wire 	    out_valid;
+	wire  [7:0] out_data;
+	reg   [7:0] out_temp;
+
+	reg [15:0] dataCounter = 16'b0;
+	reg [9:0] cntReg = 10'b0;
+
+
+	// Assign wires
+	assign mprj_io[11] = out_ready;
+	assign out_valid = mprj_io[12];
+	assign out_data  = mprj_io[20:13];
+
+	assign mprj_io[10:1] = cntReg[9:0];
+
+	
+	// toggle clock
+	always #500 clock <= (clock === 1'b0);
+
+	// Read golden data
+	initial $readmemh("./../../../../../../cargo/spectrometer/test_run_dir/SpectrometerTest/plfg_nco_fft_mag_acc_pout/GoldenData.txt", goldenData);
+
+	// send data to input stream
+	always @ (posedge clock) begin
+		cntReg <= cntReg + 1'b1;
+	end
+
+	// open file for writting
+	initial begin
+		$printtimescale(plfg_nco_fft_mag_acc_pout_tb);
+		file = $fopen("output.txt","w");
+		if (file) $display("File was opened successfully : %0d", file);
+    	else $display("File was NOT opened successfully : %0d", file);
+	end
+
+	initial begin
+		clock = 0;
+		#500 out_ready = 1'b1; // Set out_ready
+	end
+
+	// Chech outStream.ready and outStream.valid and collect data
+	always @ (posedge clock) begin
+		if (out_ready == 1'b1 && out_valid == 1'b1) begin
+			if (dataCounter % 2 == 0) out_temp <= out_data;
+			else begin
+				$fwriteh(file, "%h" ,out_data);
+				$fwriteh(file, "%h\n" ,out_temp);
+				if ({out_data,out_temp} != goldenData[dataCounter/2]) begin
+					$display("%c[1;31m",27);
+					$display ("Monitor: Test plfg_nco_fft_mag_acc_pout failed!!! Read data was %h, but should be %h.", {out_data,out_temp}, goldenData[dataCounter/2]);
+					$display("%c[0m",27);
+					$fclose(file); 
+					$finish;
+				end
+			end
+			dataCounter <= dataCounter + 1'b1;
+		end
+	end
+
+	initial begin
+		$dumpfile("plfg_nco_fft_mag_acc_pout.vcd");
+		$dumpvars(0, plfg_nco_fft_mag_acc_pout_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Test plfg_nco_fft_mag_acc_pout failed!!! Timeout.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	// Check if enough data was send, and if so terminate test
+	initial begin
+		wait(dataCounter == 16'd 2*`FFT_SIZE);
+		$display("%c[1;32m",27);
+		$display("Monitor: Test plfg_nco_fft_mag_acc_pout passed.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#10000;
+		RSTB <= 1'b1;	    // Release reset
+		#20000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("plfg_nco_fft_mag_acc_pout.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+endmodule
+`default_nettype wire

diff --git a/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_utx/Makefile b/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_utx/Makefile
new file mode 100644
index 0000000..bedcbdf
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_utx/Makefile

@@ -0,0 +1,54 @@
+CARAVEL_PATH = ./../../../../../..
+
+FIRMWARE_PATH = ../..
+RTL_PATH = $(CARAVEL_PATH)/verilog/rtl
+IP_PATH = $(CARAVEL_PATH)/verilog/ip
+BEHAVIOURAL_MODELS = ../../ 
+
+CARGO_PATH   = $(CARAVEL_PATH)/cargo
+WB2AXI_PATH  = $(CARAVEL_PATH)/cargo/wb2axip/rtl
+PROJECT_PATH = $(CARAVEL_PATH)/cargo/spectrometer/rtl/SpectrometerTest
+TOP_PATH     = $(CARAVEL_PATH)/cargo/top/rtl/SpectrometerTest
+
+GCC_PATH?=$(RISCV32)/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+FFT_SIZE?=64 # Pass fft size to testbench and c code
+
+.SUFFIXES:
+
+PATTERN = plfg_nco_fft_mag_acc_utx
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -DFUNCTIONAL -DSIM -DFFT_SIZE=$(FFT_SIZE) -I $(BEHAVIOURAL_MODELS) \
+	-I $(WB2AXI_PATH)  \
+	-I $(PROJECT_PATH) \
+	-I $(TOP_PATH) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -DFFT_SIZE=$(FFT_SIZE) -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.txt
+
+.PHONY: clean hex all

diff --git a/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_utx/plfg_nco_fft_mag_acc_utx.c b/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_utx/plfg_nco_fft_mag_acc_utx.c
new file mode 100644
index 0000000..9bb95c4
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_utx/plfg_nco_fft_mag_acc_utx.c

@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: Apache-2.0
+
+#include "../../defs.h"
+#include "../../stub.c"
+
+#include "../../spectrometerDefs.h"
+
+/*
+	Spectrometer Test:
+		- Set spectrometer to pass data through:
+                        plfg
+                        nco
+                        fft
+                        mag
+                        acc
+                        utx
+*/
+
+int clk = 0;
+int i;
+
+void main()
+{
+	// Configure GPIO pins
+        reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_PULLUP;
+        reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+
+        reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_11 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+
+        reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_9  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_8  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_7  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_6  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_5  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_4  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_3  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_2  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_1  = GPIO_MODE_USER_STD_INPUT_PULLDOWN;
+        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+        /* Apply configuration */
+        reg_mprj_xfer = 1;
+        while (reg_mprj_xfer == 1);
+
+        UART_REG(uart_div) = 2;
+        UART_REG(uart_txctrl) = 1;
+        UART_REG(uart_rxctrl) = 1;
+
+        MAG_REG(0) = 0x2; // set jpl magnitude
+        
+        ACC_REG(0)           = FFT_SIZE;
+        ACC_REG(1*BEATBYTES) = 4;
+
+        PLFG_MUX_1_REG(0) = 0;
+        NCO_MUX_1_REG(0)  = 0;
+        FFT_MUX_1_REG(0)  = 0;
+        MAG_MUX_1_REG(0)  = 0;
+
+        PLFG_MUX_0_REG(0) = 0;
+        NCO_MUX_0_REG(0)  = 0;
+        FFT_MUX_0_REG(0)  = 0;
+        MAG_MUX_0_REG(0)  = 0;
+
+        OUT_MUX_REG(0x4) = 0;
+
+        int segmentNumsArrayOffset = 6 * BEATBYTES;
+        int repeatedChirpNumsArrayOffset = segmentNumsArrayOffset + 4 * BEATBYTES;
+        int chirpOrdinalNumsArrayOffset = repeatedChirpNumsArrayOffset + 8 * BEATBYTES;
+
+        PLFG_RAM(0) = 0x24000000;
+        PLFG_REG(2*BEATBYTES) = 8;
+        PLFG_REG(4*BEATBYTES) = 1;
+        PLFG_REG(5*BEATBYTES) = 8*128/FFT_SIZE;;
+        PLFG_REG(segmentNumsArrayOffset) = 1;
+        PLFG_REG(repeatedChirpNumsArrayOffset) = 1;
+        PLFG_REG(chirpOrdinalNumsArrayOffset) = 0;
+        PLFG_REG(1*BEATBYTES) = 0;
+        PLFG_REG(0*BEATBYTES) = 1;
+        
+}
+

diff --git a/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_utx/plfg_nco_fft_mag_acc_utx_tb.v b/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_utx/plfg_nco_fft_mag_acc_utx_tb.v
new file mode 100644
index 0000000..82ddcfc
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spectrometer/plfg_nco_fft_mag_acc_utx/plfg_nco_fft_mag_acc_utx_tb.v

@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel.v"
+`include "spiflash.v"
+`include "uart_rx.v"
+
+module plfg_nco_fft_mag_acc_utx_tb;
+	// declare file for writing data
+	integer file;
+
+	// Golden data
+	reg [15:0] goldenData [0:`FFT_SIZE-1];
+
+	// clk, rst, power signals
+	reg clock;
+    reg RSTB;
+	reg power1, power2;
+
+	// testbench signals
+    wire 		gpio;
+    wire [37:0] mprj_io;
+
+	// Output stream data wires
+	reg 	    out_ready = 1'b0;
+	wire 	    out_valid;
+	wire  [7:0] out_data;
+
+	// uart data
+	reg  uRx = 1'b1;
+	wire uTx;
+	wire [7:0] utx_data;
+	reg  [7:0] utx_temp;
+	wire utx_valid;
+
+	reg [15:0] dataCounter = 16'b0;
+	reg [9:0] cntReg = 10'b0;
+
+
+	// Assign wires
+	assign mprj_io[11] = out_ready;
+	assign out_valid = mprj_io[12];
+	assign out_data  = mprj_io[20:13];
+
+	assign uTx = mprj_io[23];
+	assign mprj_io[24] = uRx;
+
+	assign mprj_io[10:1] = cntReg[9:0];
+
+	
+	// toggle clock
+	always #500 clock <= (clock === 1'b0);
+
+	// Read golden data
+	initial $readmemh("./../../../../../../cargo/spectrometer/test_run_dir/SpectrometerTest/plfg_nco_fft_mag_acc_utx/GoldenData.txt", goldenData);
+
+	// send data to input stream
+	always @ (posedge clock) begin
+		cntReg <= cntReg + 1'b1;
+	end
+
+	// open file for writting
+	initial begin
+		file = $fopen("output.txt","w");
+		if (file) $display("File was opened successfully : %0d", file);
+    	else $display("File was NOT opened successfully : %0d", file);
+	end
+
+	initial begin
+		clock = 0;
+	end
+
+	// Collect data from uTx
+	always @ (posedge clock) begin
+		if (utx_valid) begin
+			if (dataCounter % 2 == 0) utx_temp <= utx_data;
+			else begin
+				$fwriteh(file, "%h" ,utx_data);
+				$fwriteh(file, "%h\n" ,utx_temp);
+				if ({utx_data,utx_temp} != goldenData[dataCounter/2]) begin
+					$display("%c[1;31m",27);
+					$display ("Monitor: Test plfg_nco_fft_mag_acc_utx failed!!! Read data was %h, but should be %h.", {utx_data,utx_temp}, goldenData[dataCounter/2]);
+					$display("%c[0m",27);
+					$fclose(file); 
+					$finish;
+				end
+			end
+			dataCounter <= dataCounter + 1'b1;
+		end
+	end
+
+	initial begin
+		$dumpfile("plfg_nco_fft_mag_acc_utx.vcd");
+		$dumpvars(4, plfg_nco_fft_mag_acc_utx_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (300) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Test plfg_nco_fft_mag_acc_utx failed!!! Timeout.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	// Check if enough data was send, and if so terminate test
+	initial begin
+		wait(dataCounter == 16'd 2*`FFT_SIZE);
+		$display("%c[1;32m",27);
+		$display("Monitor: Test plfg_nco_fft_mag_acc_utx passed.");
+		$display("%c[0m",27);
+		$fclose(file); 
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#10000;
+		RSTB <= 1'b1;	    // Release reset
+		#20000;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		#200;
+		power1 <= 1'b1;
+		#200;
+		power2 <= 1'b1;
+	end
+
+    wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire VDD1V8;
+    wire VDD3V3;
+	wire VSS;
+    
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vssio	  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        .mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("plfg_nco_fft_mag_acc_utx.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),
+		.io3()
+	);
+
+	uart_rx  #(.CLKS_PER_BIT(3)
+	) urx_tb (
+   		.i_Clock(clock),
+   		.i_Rx_Serial(uTx),
+   		.o_Rx_DV(utx_valid),
+   		.o_Rx_Byte(utx_data)
+    );
+
+endmodule
+`default_nettype wire

diff --git a/cargo/top/dv/SpectrometerTest/spectrometerDefs.h b/cargo/top/dv/SpectrometerTest/spectrometerDefs.h
new file mode 100644
index 0000000..4e7f6b8
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spectrometerDefs.h

@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _SPECTROMETERDEF_H_
+#define _SPECTROMETERDEF_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+// Helper functions
+#define _AC(X,Y)        (X##Y)
+
+#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
+
+#define BEATBYTES 4
+
+#define IN_SPL_BASE     _AC(0x30000000,UL)
+
+#define PLFG_RAM_BASE   _AC(0x30001000,UL)
+#define PLFG_BASE       _AC(0x30002100,UL)
+#define PLFG_SPL_BASE   _AC(0x30002200,UL)
+#define PLFG_MUX_0_BASE _AC(0x30002210,UL)
+#define PLFG_MUX_1_BASE _AC(0x30002220,UL)
+
+#define NCO_BASE        _AC(0x30003000,UL)
+#define NCO_SPL_BASE    _AC(0x30003100,UL)
+#define NCO_MUX_0_BASE  _AC(0x30003110,UL)
+#define NCO_MUX_1_BASE  _AC(0x30003120,UL)
+
+#define FFT_BASE        _AC(0x30004000,UL)
+#define FFT_SPL_BASE    _AC(0x30004100,UL)
+#define FFT_MUX_0_BASE  _AC(0x30004110,UL)
+#define FFT_MUX_1_BASE  _AC(0x30004120,UL)
+
+#define MAG_BASE        _AC(0x30005000,UL)
+#define MAG_SPL_BASE    _AC(0x30005100,UL)
+#define MAG_MUX_0_BASE  _AC(0x30005110,UL)
+#define MAG_MUX_1_BASE  _AC(0x30005120,UL)
+
+#define ACC_QUEUE_BASE  _AC(0x30006000,UL)
+#define ACC_BASE        _AC(0x30007000,UL)
+
+#define OUT_MUX_BASE    _AC(0x30008000,UL)
+#define OUT_SPL_BASE    _AC(0x30008010,UL)
+
+#define UART_BASE       _AC(0x30009000,UL)
+#define UART_SPL_BASE   _AC(0x30009100,UL)
+
+// REGS
+#define IN_SPL_REG(offset)     _REG32(IN_SPL_BASE, offset)
+
+#define PLFG_RAM(offset)       _REG32(PLFG_RAM_BASE, offset)
+#define PLFG_REG(offset)       _REG32(PLFG_BASE, offset)
+#define PLFG_SPL_REG(offset)   _REG32(PLFG_SPL_BASE, offset)
+#define PLFG_MUX_0_REG(offset) _REG32(PLFG_MUX_0_BASE, offset)
+#define PLFG_MUX_1_REG(offset) _REG32(PLFG_MUX_1_BASE, offset)
+
+#define NCO_REG(offset)        _REG32(NCO_BASE, offset)
+#define NCO_SPL_REG(offset)    _REG32(NCO_SPL_BASE, offset)
+#define NCO_MUX_0_REG(offset)  _REG32(NCO_MUX_0_BASE, offset)
+#define NCO_MUX_1_REG(offset)  _REG32(NCO_MUX_1_BASE, offset)
+
+#define FFT_REG(offset)        _REG32(FFT_BASE, offset)
+#define FFT_SPL_REG(offset)    _REG32(FFT_SPL_BASE, offset)
+#define FFT_MUX_0_REG(offset)  _REG32(FFT_MUX_0_BASE, offset)
+#define FFT_MUX_1_REG(offset)  _REG32(FFT_MUX_1_BASE, offset)
+
+#define MAG_REG(offset)        _REG32(MAG_BASE, offset)
+#define MAG_SPL_REG(offset)    _REG32(MAG_SPL_BASE, offset)
+#define MAG_MUX_0_REG(offset)  _REG32(MAG_MUX_0_BASE, offset)
+#define MAG_MUX_1_REG(offset)  _REG32(MAG_MUX_1_BASE, offset)
+
+#define ACC_QUEUE_REG(offset)  _REG32(ACC_QUEUE_BASE, offset)
+#define ACC_REG(offset)        _REG32(ACC_BASE, offset)
+
+#define OUT_MUX_REG(offset)    _REG32(OUT_MUX_BASE, offset)
+#define OUT_SPL_REG(offset)    _REG32(OUT_SPL_BASE, offset)
+
+#define UART_REG(offset)       _REG32(UART_BASE, offset)
+#define UART_SPL_REG(offset)   _REG32(UART_SPL_BASE, offset)
+
+/* Register offsets */
+#define uart_txfifo     0x00
+#define uart_rxfifo 	0x04
+#define uart_txctrl 	0x08
+#define uart_txmark 	0x0a
+#define uart_rxctrl 	0x0c
+#define uart_rxmark		0x0e
+
+#define uart_ie     	0x10
+#define uart_ip    		0x14
+#define uart_div    	0x18
+#define uart_parity		0x1c
+#define uart_wire4		0x20
+#define uart_either8or9 0x24
+
+#define mux_output_0    0x0*BEATBYTES
+#define mux_output_1    0x1*BEATBYTES
+#define mux_output_2    0x2*BEATBYTES
+
+#define spl_ctrl        0x0*BEATBYTES
+#define spl_mask        0x1*BEATBYTES
+
+// --------------------------------------------------------
+#endif

diff --git a/cargo/top/dv/SpectrometerTest/spiflash.v b/cargo/top/dv/SpectrometerTest/spiflash.v
new file mode 100644
index 0000000..c4794c4
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/spiflash.v

@@ -0,0 +1,416 @@
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+//
+// Simple SPI flash simulation model
+//
+// This model samples io input signals 1ns before the SPI clock edge and
+// updates output signals 1ns after the SPI clock edge.
+//
+// Supported commands:
+//    AB, B9, FF, 03, BB, EB, ED
+//
+// Well written SPI flash data sheets:
+//    Cypress S25FL064L http://www.cypress.com/file/316661/download
+//    Cypress S25FL128L http://www.cypress.com/file/316171/download
+//
+
+module spiflash #(
+	parameter FILENAME = "firmware.hex"
+)(
+	input csb,
+	input clk,
+	inout io0, // MOSI
+	inout io1, // MISO
+	inout io2,
+	inout io3
+);
+	localparam verbose = 0;
+	localparam integer latency = 8;
+	
+	reg [7:0] buffer;
+	integer bitcount = 0;
+	integer bytecount = 0;
+	integer dummycount = 0;
+
+	reg [7:0] spi_cmd;
+	reg [7:0] xip_cmd = 0;
+	reg [23:0] spi_addr;
+
+	reg [7:0] spi_in;
+	reg [7:0] spi_out;
+	reg spi_io_vld;
+
+	reg powered_up = 0;
+
+	localparam [3:0] mode_spi         = 1;
+	localparam [3:0] mode_dspi_rd     = 2;
+	localparam [3:0] mode_dspi_wr     = 3;
+	localparam [3:0] mode_qspi_rd     = 4;
+	localparam [3:0] mode_qspi_wr     = 5;
+	localparam [3:0] mode_qspi_ddr_rd = 6;
+	localparam [3:0] mode_qspi_ddr_wr = 7;
+
+	reg [3:0] mode = 0;
+	reg [3:0] next_mode = 0;
+
+	reg io0_oe = 0;
+	reg io1_oe = 0;
+	reg io2_oe = 0;
+	reg io3_oe = 0;
+
+	reg io0_dout = 0;
+	reg io1_dout = 0;
+	reg io2_dout = 0;
+	reg io3_dout = 0;
+
+	assign #1 io0 = io0_oe ? io0_dout : 1'bz;
+	assign #1 io1 = io1_oe ? io1_dout : 1'bz;
+	assign #1 io2 = io2_oe ? io2_dout : 1'bz;
+	assign #1 io3 = io3_oe ? io3_dout : 1'bz;
+
+	wire io0_delayed;
+	wire io1_delayed;
+	wire io2_delayed;
+	wire io3_delayed;
+
+	assign #1 io0_delayed = io0;
+	assign #1 io1_delayed = io1;
+	assign #1 io2_delayed = io2;
+	assign #1 io3_delayed = io3;
+
+	// 16 MB (128Mb) Flash
+	reg [7:0] memory [0:16*1024*1024-1];
+
+	initial begin
+		$display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
+			memory[1048576], memory[1048577], memory[1048578],
+			memory[1048579], memory[1048580]);
+		$display("Reading %s",  FILENAME);
+		$readmemh(FILENAME, memory);
+		$display("%s loaded into memory", FILENAME);
+		$display("Memory 5 bytes = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
+			memory[1048576], memory[1048577], memory[1048578],
+			memory[1048579], memory[1048580]);
+	end
+
+	task spi_action;
+		begin
+			spi_in = buffer;
+
+			if (bytecount == 1) begin
+				spi_cmd = buffer;
+
+				if (spi_cmd == 8'h ab)
+					powered_up = 1;
+
+				if (spi_cmd == 8'h b9)
+					powered_up = 0;
+
+				if (spi_cmd == 8'h ff)
+					xip_cmd = 0;
+			end
+
+			if (powered_up && spi_cmd == 'h 03) begin
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount >= 4) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			if (powered_up && spi_cmd == 'h bb) begin
+				if (bytecount == 1)
+					mode = mode_dspi_rd;
+
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount == 5) begin
+					xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+					mode = mode_dspi_wr;
+					dummycount = latency;
+				end
+
+				if (bytecount >= 5) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			if (powered_up && spi_cmd == 'h eb) begin
+				if (bytecount == 1)
+					mode = mode_qspi_rd;
+
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount == 5) begin
+					xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+					mode = mode_qspi_wr;
+					dummycount = latency;
+				end
+
+				if (bytecount >= 5) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			if (powered_up && spi_cmd == 'h ed) begin
+				if (bytecount == 1)
+					next_mode = mode_qspi_ddr_rd;
+
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount == 5) begin
+					xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
+					mode = mode_qspi_ddr_wr;
+					dummycount = latency;
+				end
+
+				if (bytecount >= 5) begin
+					buffer = memory[spi_addr];
+					spi_addr = spi_addr + 1;
+				end
+			end
+
+			spi_out = buffer;
+			spi_io_vld = 1;
+
+			if (verbose) begin
+				if (bytecount == 1)
+					$write("<SPI-START>");
+				$write("<SPI:%02x:%02x>", spi_in, spi_out);
+			end
+
+		end
+	endtask
+
+	task ddr_rd_edge;
+		begin
+			buffer = {buffer, io3_delayed, io2_delayed, io1_delayed, io0_delayed};
+			bitcount = bitcount + 4;
+			if (bitcount == 8) begin
+				bitcount = 0;
+				bytecount = bytecount + 1;
+				spi_action;
+			end
+		end
+	endtask
+
+	task ddr_wr_edge;
+		begin
+			io0_oe = 1;
+			io1_oe = 1;
+			io2_oe = 1;
+			io3_oe = 1;
+
+			io0_dout = buffer[4];
+			io1_dout = buffer[5];
+			io2_dout = buffer[6];
+			io3_dout = buffer[7];
+
+			buffer = {buffer, 4'h 0};
+			bitcount = bitcount + 4;
+			if (bitcount == 8) begin
+				bitcount = 0;
+				bytecount = bytecount + 1;
+				spi_action;
+			end
+		end
+	endtask
+
+	always @(csb) begin
+		if (csb) begin
+			if (verbose) begin
+				$display("");
+				$fflush;
+			end
+			buffer = 0;
+			bitcount = 0;
+			bytecount = 0;
+			mode = mode_spi;
+			io0_oe = 0;
+			io1_oe = 0;
+			io2_oe = 0;
+			io3_oe = 0;
+		end else
+		if (xip_cmd) begin
+			buffer = xip_cmd;
+			bitcount = 0;
+			bytecount = 1;
+			spi_action;
+		end
+	end
+
+	always @(csb, clk) begin
+		spi_io_vld = 0;
+		if (!csb && !clk) begin
+			if (dummycount > 0) begin
+				io0_oe = 0;
+				io1_oe = 0;
+				io2_oe = 0;
+				io3_oe = 0;
+			end else
+			case (mode)
+				mode_spi: begin
+					io0_oe = 0;
+					io1_oe = 1;
+					io2_oe = 0;
+					io3_oe = 0;
+					io1_dout = buffer[7];
+				end
+				mode_dspi_rd: begin
+					io0_oe = 0;
+					io1_oe = 0;
+					io2_oe = 0;
+					io3_oe = 0;
+				end
+				mode_dspi_wr: begin
+					io0_oe = 1;
+					io1_oe = 1;
+					io2_oe = 0;
+					io3_oe = 0;
+					io0_dout = buffer[6];
+					io1_dout = buffer[7];
+				end
+				mode_qspi_rd: begin
+					io0_oe = 0;
+					io1_oe = 0;
+					io2_oe = 0;
+					io3_oe = 0;
+				end
+				mode_qspi_wr: begin
+					io0_oe = 1;
+					io1_oe = 1;
+					io2_oe = 1;
+					io3_oe = 1;
+					io0_dout = buffer[4];
+					io1_dout = buffer[5];
+					io2_dout = buffer[6];
+					io3_dout = buffer[7];
+				end
+				mode_qspi_ddr_rd: begin
+					ddr_rd_edge;
+				end
+				mode_qspi_ddr_wr: begin
+					ddr_wr_edge;
+				end
+			endcase
+			if (next_mode) begin
+				case (next_mode)
+					mode_qspi_ddr_rd: begin
+						io0_oe = 0;
+						io1_oe = 0;
+						io2_oe = 0;
+						io3_oe = 0;
+					end
+					mode_qspi_ddr_wr: begin
+						io0_oe = 1;
+						io1_oe = 1;
+						io2_oe = 1;
+						io3_oe = 1;
+						io0_dout = buffer[4];
+						io1_dout = buffer[5];
+						io2_dout = buffer[6];
+						io3_dout = buffer[7];
+					end
+				endcase
+				mode = next_mode;
+				next_mode = 0;
+			end
+		end
+	end
+
+	always @(posedge clk) begin
+		if (!csb) begin
+			if (dummycount > 0) begin
+				dummycount = dummycount - 1;
+			end else
+			case (mode)
+				mode_spi: begin
+					buffer = {buffer, io0};
+					bitcount = bitcount + 1;
+					if (bitcount == 8) begin
+						bitcount = 0;
+						bytecount = bytecount + 1;
+						spi_action;
+					end
+				end
+				mode_dspi_rd, mode_dspi_wr: begin
+					buffer = {buffer, io1, io0};
+					bitcount = bitcount + 2;
+					if (bitcount == 8) begin
+						bitcount = 0;
+						bytecount = bytecount + 1;
+						spi_action;
+					end
+				end
+				mode_qspi_rd, mode_qspi_wr: begin
+					buffer = {buffer, io3, io2, io1, io0};
+					bitcount = bitcount + 4;
+					if (bitcount == 8) begin
+						bitcount = 0;
+						bytecount = bytecount + 1;
+						spi_action;
+					end
+				end
+				mode_qspi_ddr_rd: begin
+					ddr_rd_edge;
+				end
+				mode_qspi_ddr_wr: begin
+					ddr_wr_edge;
+				end
+			endcase
+		end
+	end
+endmodule

diff --git a/cargo/top/dv/SpectrometerTest/start.s b/cargo/top/dv/SpectrometerTest/start.s
new file mode 100644
index 0000000..7dd13d8
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/start.s

@@ -0,0 +1,161 @@
+# SPDX-License-Identifier: Apache-2.0
+
+.section .text
+
+start:
+
+# zero-initialize register file
+addi x1, zero, 0
+# x2 (sp) is initialized by reset
+addi x3, zero, 0
+addi x4, zero, 0
+addi x5, zero, 0
+addi x6, zero, 0
+addi x7, zero, 0
+addi x8, zero, 0
+addi x9, zero, 0
+addi x10, zero, 0
+addi x11, zero, 0
+addi x12, zero, 0
+addi x13, zero, 0
+addi x14, zero, 0
+addi x15, zero, 0
+addi x16, zero, 0
+addi x17, zero, 0
+addi x18, zero, 0
+addi x19, zero, 0
+addi x20, zero, 0
+addi x21, zero, 0
+addi x22, zero, 0
+addi x23, zero, 0
+addi x24, zero, 0
+addi x25, zero, 0
+addi x26, zero, 0
+addi x27, zero, 0
+addi x28, zero, 0
+addi x29, zero, 0
+addi x30, zero, 0
+addi x31, zero, 0
+
+# zero initialize scratchpad memory
+# setmemloop:
+# sw zero, 0(x1)
+# addi x1, x1, 4
+# blt x1, sp, setmemloop
+
+# copy data section
+la a0, _sidata
+la a1, _sdata
+la a2, _edata
+bge a1, a2, end_init_data
+loop_init_data:
+lw a3, 0(a0)
+sw a3, 0(a1)
+addi a0, a0, 4
+addi a1, a1, 4
+blt a1, a2, loop_init_data
+end_init_data:
+
+# zero-init bss section
+la a0, _sbss
+la a1, _ebss
+bge a0, a1, end_init_bss
+loop_init_bss:
+sw zero, 0(a0)
+addi a0, a0, 4
+blt a0, a1, loop_init_bss
+end_init_bss:
+
+# call main
+call main
+loop:
+j loop
+
+.global flashio_worker_begin
+.global flashio_worker_end
+
+.balign 4
+
+flashio_worker_begin:
+# a0 ... data pointer
+# a1 ... data length
+# a2 ... optional WREN cmd (0 = disable)
+
+# address of SPI ctrl reg
+li   t0, 0x28000000
+
+# Set CS high, IO0 is output
+li   t1, 0x120
+sh   t1, 0(t0)
+
+# Enable Manual SPI Ctrl
+sb   zero, 3(t0)
+
+# Send optional WREN cmd
+beqz a2, flashio_worker_L1
+li   t5, 8
+andi t2, a2, 0xff
+flashio_worker_L4:
+srli t4, t2, 7
+sb   t4, 0(t0)
+ori  t4, t4, 0x10
+sb   t4, 0(t0)
+slli t2, t2, 1
+andi t2, t2, 0xff
+addi t5, t5, -1
+bnez t5, flashio_worker_L4
+sb   t1, 0(t0)
+
+# SPI transfer
+flashio_worker_L1:
+
+# If byte count is zero, we're done
+beqz a1, flashio_worker_L3
+
+# Set t5 to count down 32 bits
+li   t5, 32
+# Load t2 from address a0 (4 bytes)
+lw   t2, 0(a0)
+
+flashio_worker_LY:
+# Set t6 to count down 8 bits
+li   t6, 8
+
+flashio_worker_L2:
+# Clock out the bit (msb first) on IO0 and read bit in from IO1
+srli t4, t2, 31
+sb   t4, 0(t0)
+ori  t4, t4, 0x10
+sb   t4, 0(t0)
+lbu  t4, 0(t0)
+andi t4, t4, 2
+srli t4, t4, 1
+slli t2, t2, 1
+or   t2, t2, t4
+
+# Decrement 32 bit count
+addi t5, t5, -1
+bnez t5, flashio_worker_LX
+
+sw   t2, 0(a0)
+addi a0, a0, 4
+lw   t2, 0(a0)
+
+flashio_worker_LX:
+addi t6, t6, -1
+bnez t6, flashio_worker_L2
+addi a1, a1, -1
+bnez a1, flashio_worker_LY
+
+beqz t5, flashio_worker_L3
+sw   t2, 0(a0)
+
+flashio_worker_L3:
+# Back to MEMIO mode
+li   t1, 0x80
+sb   t1, 3(t0)
+
+ret
+.balign 4
+flashio_worker_end:
+

diff --git a/cargo/top/dv/SpectrometerTest/stub.c b/cargo/top/dv/SpectrometerTest/stub.c
new file mode 100644
index 0000000..b08593f
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/stub.c

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: Apache-2.0
+
+void putchar(char c)
+{
+	if (c == '\n')
+		putchar('\r');
+	reg_uart_data = c;
+}
+
+void print(const char *p)
+{
+	while (*p)
+		putchar(*(p++));
+}
\ No newline at end of file

diff --git a/cargo/top/dv/SpectrometerTest/tbuart.v b/cargo/top/dv/SpectrometerTest/tbuart.v
new file mode 100644
index 0000000..206b9eb
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/tbuart.v

@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *  PicoSoC - A simple example SoC using PicoRV32
+ *
+ *  Copyright (C) 2017  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+`timescale 1 ns / 1 ps
+
+/* tbuart --- mimic an external UART display, operating at 9600 baud	*/
+/* and accepting ASCII characters for display.				*/
+
+/* To do:  Match a known UART 3.3V 16x2 LCD display.  However, it	*/
+/* should be possible on a testing system to interface to the UART	*/
+/* pins on a Raspberry Pi, also running at 3.3V.			*/
+
+module tbuart (
+	input  ser_rx
+);
+	reg [3:0] recv_state;
+	reg [2:0] recv_divcnt;
+	reg [7:0] recv_pattern;
+	reg [8*50-1:0] recv_buf_data;	// 50 characters.  Increase as needed for tests.
+
+	reg clk;
+
+	initial begin
+		clk <= 1'b0;
+		recv_state <= 0;
+		recv_divcnt <= 0;
+		recv_pattern <= 0;
+		recv_buf_data <= 0;
+	end
+
+	// NOTE:  Running at 3.0us clock period @ 5 clocks per bit = 15.0us per
+	// bit ~= 64 kbaud. Not tuned to any particular UART.  Most run at
+	// 9600 baud default and will bounce up to higher baud rates when
+	// passed specific command words.
+
+	always #1500 clk <= (clk === 1'b0);
+
+	always @(posedge clk) begin
+		recv_divcnt <= recv_divcnt + 1;
+		case (recv_state)
+			0: begin
+				if (!ser_rx)
+					recv_state <= 1;
+				recv_divcnt <= 0;
+			end
+			1: begin
+				if (2*recv_divcnt > 3'd3) begin
+					recv_state <= 2;
+					recv_divcnt <= 0;
+				end
+			end
+			10: begin
+				if (recv_divcnt > 3'd3) begin
+					// 0x0a = '\n'
+					if (recv_pattern == 8'h0a) begin
+						$display("output: %s", recv_buf_data);
+					end else begin
+						recv_buf_data <= {recv_buf_data, recv_pattern};
+					end
+					recv_state <= 0;
+				end
+			end
+			default: begin
+				if (recv_divcnt > 3'd3) begin
+					recv_pattern <= {ser_rx, recv_pattern[7:1]};
+					recv_state <= recv_state + 1;
+					recv_divcnt <= 0;
+				end
+			end
+		endcase
+	end
+
+endmodule

diff --git a/cargo/top/dv/SpectrometerTest/uart_rx.v b/cargo/top/dv/SpectrometerTest/uart_rx.v
new file mode 100644
index 0000000..83e1a89
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/uart_rx.v

@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: Apache-2.0
+
+module uart_rx #(
+    parameter CLKS_PER_BIT = 174
+)(
+   input        i_Clock,
+   input        i_Rx_Serial,
+   output       o_Rx_DV,
+   output [7:0] o_Rx_Byte
+   );
+    
+  parameter s_IDLE         = 3'b000;
+  parameter s_RX_START_BIT = 3'b001;
+  parameter s_RX_DATA_BITS = 3'b010;
+  parameter s_RX_STOP_BIT  = 3'b011;
+  parameter s_CLEANUP      = 3'b100;
+   
+  reg           r_Rx_Data_R = 1'b1;
+  reg           r_Rx_Data   = 1'b1;
+   
+  reg [7:0]     r_Clock_Count = 0;
+  reg [2:0]     r_Bit_Index   = 0; //8 bits total
+  reg [7:0]     r_Rx_Byte     = 0;
+  reg           r_Rx_DV       = 0;
+  reg [2:0]     r_SM_Main     = 0;
+   
+  // Purpose: Double-register the incoming data.
+  // This allows it to be used in the UART RX Clock Domain.
+  // (It removes problems caused by metastability)
+  always @(posedge i_Clock)
+    begin
+      r_Rx_Data_R <= i_Rx_Serial;
+      r_Rx_Data   <= r_Rx_Data_R;
+    end
+   
+   
+  // Purpose: Control RX state machine
+  always @(posedge i_Clock)
+    begin
+       
+      case (r_SM_Main)
+        s_IDLE :
+          begin
+            r_Rx_DV       <= 1'b0;
+            r_Clock_Count <= 0;
+            r_Bit_Index   <= 0;
+             
+            if (r_Rx_Data == 1'b0)          // Start bit detected
+              r_SM_Main <= s_RX_START_BIT;
+            else
+              r_SM_Main <= s_IDLE;
+          end
+         
+        // Check middle of start bit to make sure it's still low
+        s_RX_START_BIT :
+          begin
+            if (r_Clock_Count == (CLKS_PER_BIT-1)/2)
+              begin
+                if (r_Rx_Data == 1'b0)
+                  begin
+                    r_Clock_Count <= 0;  // reset counter, found the middle
+                    r_SM_Main     <= s_RX_DATA_BITS;
+                  end
+                else
+                  r_SM_Main <= s_IDLE;
+              end
+            else
+              begin
+                r_Clock_Count <= r_Clock_Count + 1;
+                r_SM_Main     <= s_RX_START_BIT;
+              end
+          end // case: s_RX_START_BIT
+         
+         
+        // Wait CLKS_PER_BIT-1 clock cycles to sample serial data
+        s_RX_DATA_BITS :
+          begin
+            if (r_Clock_Count < CLKS_PER_BIT-1)
+              begin
+                r_Clock_Count <= r_Clock_Count + 1;
+                r_SM_Main     <= s_RX_DATA_BITS;
+              end
+            else
+              begin
+                r_Clock_Count          <= 0;
+                r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;
+                 
+                // Check if we have received all bits
+                if (r_Bit_Index < 7)
+                  begin
+                    r_Bit_Index <= r_Bit_Index + 1;
+                    r_SM_Main   <= s_RX_DATA_BITS;
+                  end
+                else
+                  begin
+                    r_Bit_Index <= 0;
+                    r_SM_Main   <= s_RX_STOP_BIT;
+                  end
+              end
+          end // case: s_RX_DATA_BITS
+     
+     
+        // Receive Stop bit.  Stop bit = 1
+        s_RX_STOP_BIT :
+          begin
+            // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
+            if (r_Clock_Count < CLKS_PER_BIT-1)
+              begin
+                r_Clock_Count <= r_Clock_Count + 1;
+                r_SM_Main     <= s_RX_STOP_BIT;
+              end
+            else
+              begin
+                r_Rx_DV       <= 1'b1;
+                r_Clock_Count <= 0;
+                r_SM_Main     <= s_CLEANUP;
+              end
+          end // case: s_RX_STOP_BIT
+     
+         
+        // Stay here 1 clock
+        s_CLEANUP :
+          begin
+            r_SM_Main <= s_IDLE;
+            r_Rx_DV   <= 1'b0;
+          end
+         
+         
+        default :
+          r_SM_Main <= s_IDLE;
+         
+      endcase
+    end   
+   
+  assign o_Rx_DV   = r_Rx_DV;
+  assign o_Rx_Byte = r_Rx_Byte;
+   
+endmodule // uart_rx
\ No newline at end of file

diff --git a/cargo/top/dv/SpectrometerTest/uart_tx.v b/cargo/top/dv/SpectrometerTest/uart_tx.v
new file mode 100644
index 0000000..d3e4472
--- /dev/null
+++ b/cargo/top/dv/SpectrometerTest/uart_tx.v

@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: Apache-2.0
+
+module uart_tx 
+  #(parameter CLKS_PER_BIT)
+  (
+   input       i_Clock,
+   input       i_Tx_DV,
+   input [7:0] i_Tx_Byte, 
+   output      o_Tx_Active,
+   output reg  o_Tx_Serial,
+   output      o_Tx_Done
+   );
+  
+  parameter s_IDLE         = 3'b000;
+  parameter s_TX_START_BIT = 3'b001;
+  parameter s_TX_DATA_BITS = 3'b010;
+  parameter s_TX_STOP_BIT  = 3'b011;
+  parameter s_CLEANUP      = 3'b100;
+   
+  reg [2:0]    r_SM_Main     = 0;
+  reg [7:0]    r_Clock_Count = 0;
+  reg [2:0]    r_Bit_Index   = 0;
+  reg [7:0]    r_Tx_Data     = 0;
+  reg          r_Tx_Done     = 0;
+  reg          r_Tx_Active   = 0;
+     
+  always @(posedge i_Clock)
+    begin
+       
+      case (r_SM_Main)
+        s_IDLE :
+          begin
+            o_Tx_Serial   <= 1'b1;         // Drive Line High for Idle
+            r_Tx_Done     <= 1'b0;
+            r_Clock_Count <= 0;
+            r_Bit_Index   <= 0;
+             
+            if (i_Tx_DV == 1'b1)
+              begin
+                r_Tx_Active <= 1'b1;
+                r_Tx_Data   <= i_Tx_Byte;
+                r_SM_Main   <= s_TX_START_BIT;
+              end
+            else
+              r_SM_Main <= s_IDLE;
+          end // case: s_IDLE
+         
+         
+        // Send out Start Bit. Start bit = 0
+        s_TX_START_BIT :
+          begin
+            o_Tx_Serial <= 1'b0;
+             
+            // Wait CLKS_PER_BIT-1 clock cycles for start bit to finish
+            if (r_Clock_Count < CLKS_PER_BIT-1)
+              begin
+                r_Clock_Count <= r_Clock_Count + 1;
+                r_SM_Main     <= s_TX_START_BIT;
+              end
+            else
+              begin
+                r_Clock_Count <= 0;
+                r_SM_Main     <= s_TX_DATA_BITS;
+              end
+          end // case: s_TX_START_BIT
+         
+         
+        // Wait CLKS_PER_BIT-1 clock cycles for data bits to finish         
+        s_TX_DATA_BITS :
+          begin
+            o_Tx_Serial <= r_Tx_Data[r_Bit_Index];
+             
+            if (r_Clock_Count < CLKS_PER_BIT-1)
+              begin
+                r_Clock_Count <= r_Clock_Count + 1;
+                r_SM_Main     <= s_TX_DATA_BITS;
+              end
+            else
+              begin
+                r_Clock_Count <= 0;
+                 
+                // Check if we have sent out all bits
+                if (r_Bit_Index < 7)
+                  begin
+                    r_Bit_Index <= r_Bit_Index + 1;
+                    r_SM_Main   <= s_TX_DATA_BITS;
+                  end
+                else
+                  begin
+                    r_Bit_Index <= 0;
+                    r_SM_Main   <= s_TX_STOP_BIT;
+                  end
+              end
+          end // case: s_TX_DATA_BITS
+         
+         
+        // Send out Stop bit.  Stop bit = 1
+        s_TX_STOP_BIT :
+          begin
+            o_Tx_Serial <= 1'b1;
+             
+            // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
+            if (r_Clock_Count < CLKS_PER_BIT-1)
+              begin
+                r_Clock_Count <= r_Clock_Count + 1;
+                r_SM_Main     <= s_TX_STOP_BIT;
+              end
+            else
+              begin
+                r_Tx_Done     <= 1'b1;
+                r_Clock_Count <= 0;
+                r_SM_Main     <= s_CLEANUP;
+                r_Tx_Active   <= 1'b0;
+              end
+          end // case: s_Tx_STOP_BIT
+         
+         
+        // Stay here 1 clock
+        s_CLEANUP :
+          begin
+            r_Tx_Done <= 1'b1;
+            r_SM_Main <= s_IDLE;
+          end
+         
+         
+        default :
+          r_SM_Main <= s_IDLE;
+         
+      endcase
+    end
+ 
+  assign o_Tx_Active = r_Tx_Active;
+  assign o_Tx_Done   = r_Tx_Done;
+   
+endmodule
\ No newline at end of file

diff --git a/cargo/top/rtl/SpectrometerTest/user_proj_example.v b/cargo/top/rtl/SpectrometerTest/user_proj_example.v
new file mode 100644
index 0000000..59623e5
--- /dev/null
+++ b/cargo/top/rtl/SpectrometerTest/user_proj_example.v

@@ -0,0 +1,290 @@
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * spectrometer
+ *
+ *-------------------------------------------------------------
+ */
+
+`ifdef SIM
+`include "wbm2axisp.v"
+`include "skidbuffer.v"
+`include "SpectrometerTest.v"
+`include "plusarg_reader.v"
+`endif
+
+module user_proj_example (
+`ifdef USE_POWER_PINS
+    inout vdda1,	// User area 1 3.3V supply
+    inout vdda2,	// User area 2 3.3V supply
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vccd2,	// User area 2 1.8v supply
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+`endif
+
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oen,
+
+    // IOs
+    input  [`MPRJ_IO_PADS-1:0] io_in,
+    output [`MPRJ_IO_PADS-1:0] io_out,
+    output [`MPRJ_IO_PADS-1:0] io_oeb
+);
+
+// Logic Analyzer Signals
+    wire [127:0] la_data_in;
+    wire [127:0] la_data_out;
+    wire [127:0] la_oen;
+
+// IOs
+    wire [`MPRJ_IO_PADS-1:0] io_in;
+    wire [`MPRJ_IO_PADS-1:0] io_out;
+    wire [`MPRJ_IO_PADS-1:0] io_oeb;
+
+// AXI write address channel signals
+	wire 		w_o_axi_awvalid;	// Write address valid
+	wire 		w_i_axi_awready; 	// Slave is ready to accept
+	wire 		w_o_axi_awid;		// Write ID
+	wire [33:0] w_o_axi_awaddr;		// Write address
+	wire [7:0]  w_o_axi_awlen;		// Write Burst Length
+	wire [2:0]  w_o_axi_awsize;		// Write Burst size
+	wire [1:0]  w_o_axi_awburst;	// Write Burst type
+	wire [0:0]  w_o_axi_awlock;		// Write lock type
+	wire [3:0]  w_o_axi_awcache;	// Write Cache type
+	wire [2:0]  w_o_axi_awprot;		// Write Protection type
+	wire [3:0]  w_o_axi_awqos;		// Write Quality of Svc
+// AXI write data channel signals
+	wire 		w_o_axi_wvalid;		// Write valid
+	wire 		w_i_axi_wready;  	// Write data ready
+	wire [31:0]	w_o_axi_wdata;		// Write data
+	wire [3:0]  w_o_axi_wstrb;		// Write strobes
+	wire 		w_o_axi_wlast;		// Last write transaction
+// AXI write response channel signals
+ 	wire 		w_i_axi_bvalid;		// Write reponse valid
+	wire 		w_o_axi_bready;  	// Response ready
+	wire 		w_i_axi_bid;		// Response ID
+	wire [1:0]  w_i_axi_bresp;		// Write response
+// AXI read address channel signals
+	wire        w_o_axi_arvalid;	// Read address valid
+	wire        w_i_axi_arready;	// Read address ready
+	wire [0:0]  w_o_axi_arid;		// Read ID
+	wire [33:0]	w_o_axi_araddr;		// Read address
+	wire [7:0]  w_o_axi_arlen;		// Read Burst Length
+	wire [2:0]  w_o_axi_arsize;		// Read Burst size
+	wire [1:0]  w_o_axi_arburst;	// Read Burst type
+	wire [0:0]  w_o_axi_arlock;		// Read lock type
+	wire [3:0]  w_o_axi_arcache;	// Read Cache type
+	wire [2:0]  w_o_axi_arprot;		// Read Protection type
+	wire [3:0]  w_o_axi_arqos;		// Read Protection type
+// AXI read data channel signals
+	wire 		w_i_axi_rvalid;  	// Read reponse valid
+	wire 		w_o_axi_rready;  	// Read Response ready
+	wire [0:0] 	w_i_axi_rid;     	// Response ID
+	wire [31:0] w_i_axi_rdata;    	// Read data
+	wire [1:0]  w_i_axi_rresp;   	// Read response
+	wire 		w_i_axi_rlast;    	// Read last
+
+// Wires for inStream and outStream
+	wire 	   w_inStream_ready;
+	wire 	   w_inStream_valid;
+	wire [7:0] w_inStream_data;
+	wire 	   w_inStream_last;
+
+	wire 	   w_outStream_ready;
+	wire 	   w_outStream_valid;
+	wire [7:0] w_outStream_data;
+	wire 	   w_outStream_last;
+
+// Wires for uart
+	wire w_uart_int;
+	wire w_uart_tx;
+	wire w_uart_rx;
+
+// Assign inStream signals
+	genvar i;
+
+	assign io_oeb[0]    = 1'b0;    //fix pin to output
+	assign io_oeb[10:1] = 10'h3ff; //fix pins to inputs
+
+	assign io_out[10:1] = 10'h333; // drive unused outputs
+
+	assign io_out[0] 			= w_inStream_ready;
+	assign w_inStream_valid  	= io_in[1];
+	assign w_inStream_data[7:0] = io_in[9:2];
+	assign w_inStream_last 		= io_in[10];
+
+// Assign outStream signals
+	assign io_oeb[11]    = 1'b1;    // fix pin to input
+	assign io_oeb[21:12] = 10'h000; // fix pins to outputs
+
+	assign io_out[11]    = 1'b1;	// drive unused outputs  
+
+	assign w_outStream_ready = io_in[11];
+	assign io_out[12]        = w_outStream_valid;
+	assign io_out[20:13] 	 = w_outStream_data[7:0];
+	assign io_out[21]    	 = w_outStream_last;
+
+// set uart pins
+	assign io_oeb[22] = 1'b0;		// uart_int is output
+	assign io_out[22] = w_uart_int;
+	assign io_oeb[23] = 1'b0;		// uart_tx is output
+	assign io_out[23] = w_uart_tx;
+	assign io_out[24] = 1'b0;
+	assign io_oeb[24] = 1'b1;		// uart_rx is input
+	assign w_uart_rx  = io_in[24];
+
+// Drive remaining io pins
+	assign io_out[`MPRJ_IO_PADS-1:25] = 13'h1666;
+	assign io_oeb[`MPRJ_IO_PADS-1:25] = 13'h0000;
+
+// Drive LA with zeroes
+	assign la_data_out = {128{1'b0}};
+
+// Wishbone to AXI4
+	wbm2axisp #(
+		.C_AXI_DATA_WIDTH(32),	// Width of the AXI R&W data
+		.C_AXI_ADDR_WIDTH(34),	// AXI Address width (log wordsize)
+		.C_AXI_ID_WIDTH(1),
+		.DW(32),				// Wishbone data width
+		.AW(32),   				// Wishbone address width (log wordsize)
+		.AXI_WRITE_ID(1'b0),
+		.AXI_READ_ID(1'b0)
+	) wb2axi (
+		.i_clk(wb_clk_i),						// System clock
+		.i_reset(wb_rst_i),					// Reset signal,drives AXI rst
+	// AXI write address channel signals
+		.o_axi_awvalid(w_o_axi_awvalid),	// Write address valid
+		.i_axi_awready(w_i_axi_awready), 	// Slave is ready to accept
+		.o_axi_awid(w_o_axi_awid),			// Write ID [C_AXI_ID_WIDTH-1:0]	
+		.o_axi_awaddr(w_o_axi_awaddr),		// Write address [C_AXI_ADDR_WIDTH-1:0]	
+		.o_axi_awlen(w_o_axi_awlen),		// Write Burst Length [7:0]		
+		.o_axi_awsize(w_o_axi_awsize),		// Write Burst size [2:0]		
+		.o_axi_awburst(w_o_axi_awburst),	// Write Burst type [1:0]		
+		.o_axi_awlock(w_o_axi_awlock),		// Write lock type [0:0]		
+		.o_axi_awcache(w_o_axi_awcache),	// Write Cache type [3:0]		
+		.o_axi_awprot(w_o_axi_awprot),		// Write Protection type [2:0]		
+		.o_axi_awqos(w_o_axi_awqos),		// Write Quality of Svc [3:0]		
+	// AXI write data channel signals
+		.o_axi_wvalid(w_o_axi_wvalid),		// Write valid
+		.i_axi_wready(w_i_axi_wready),  	// Write data ready
+		.o_axi_wdata(w_o_axi_wdata),		// Write data [C_AXI_DATA_WIDTH-1:0]	
+		.o_axi_wstrb(w_o_axi_wstrb),		// Write strobes [C_AXI_DATA_WIDTH/8-1:0] 
+		.o_axi_wlast(w_o_axi_wlast),		// Last write transaction
+	// AXI write response channel signals
+		.i_axi_bvalid(w_i_axi_bvalid),  	// Write reponse valid
+		.o_axi_bready(w_o_axi_bready),  	// Response ready
+		.i_axi_bid(w_i_axi_bid),			// Response ID [C_AXI_ID_WIDTH-1:0]	
+		.i_axi_bresp(w_i_axi_bresp),		// Write response [1:0]		
+	// AXI read address channel signals
+		.o_axi_arvalid(w_o_axi_arvalid),	// Read address valid
+		.i_axi_arready(w_i_axi_arready),	// Read address ready
+		.o_axi_arid(w_o_axi_arid),			// Read ID [C_AXI_ID_WIDTH-1:0]	
+		.o_axi_araddr(w_o_axi_araddr),		// Read address [C_AXI_ADDR_WIDTH-1:0]	
+		.o_axi_arlen(w_o_axi_arlen),		// Read Burst Length [7:0]		
+		.o_axi_arsize(w_o_axi_arsize),		// Read Burst size [2:0]		
+		.o_axi_arburst(w_o_axi_arburst),	// Read Burst type [1:0]		
+		.o_axi_arlock(w_o_axi_arlock),		// Read lock type [0:0]		
+		.o_axi_arcache(w_o_axi_arcache),	// Read Cache type [3:0]		
+		.o_axi_arprot(w_o_axi_arprot),		// Read Protection type [2:0]		
+		.o_axi_arqos(w_o_axi_arqos),		// Read Protection type [3:0]		
+	// AXI read data channel signals
+		.i_axi_rvalid(w_i_axi_rvalid),  	// Read reponse valid
+		.o_axi_rready(w_o_axi_rready),  	// Read Response ready
+		.i_axi_rid(w_i_axi_rid),     		// Response ID [C_AXI_ID_WIDTH-1:0]	
+		.i_axi_rdata(w_i_axi_rdata),   		// Read data [C_AXI_DATA_WIDTH-1:0] 
+		.i_axi_rresp(w_i_axi_rresp),   		// Read response [1:0]		
+		.i_axi_rlast(w_i_axi_rlast),   		// Read last
+	// We'll share the clock and the reset
+		.i_wb_cyc(wbs_cyc_i),
+		.i_wb_stb(wbs_stb_i),
+		.i_wb_we(wbs_we_i),
+		.i_wb_addr(wbs_adr_i),     // [(AW-1):0]
+		.i_wb_data(wbs_dat_i),     // [(DW-1):0]
+		.i_wb_sel(wbs_sel_i),      // [(DW/8-1):0]
+		.o_wb_stall(),
+		.o_wb_ack(wbs_ack_o),
+		.o_wb_data(wbs_dat_o), // [(DW-1):0]
+		.o_wb_err()
+	);
+
+// Spectrometer
+	SpectrometerTest spectrometer (
+		.clock(wb_clk_i),
+		.reset(wb_rst_i),
+	// AXI write address channel signals
+		.ioMem_0_aw_ready(w_i_axi_awready),
+		.ioMem_0_aw_valid(w_o_axi_awvalid),
+		.ioMem_0_aw_bits_id(w_o_axi_awid),
+		.ioMem_0_aw_bits_addr(w_o_axi_awaddr[33:2]),//[31:0]
+		.ioMem_0_aw_bits_len(w_o_axi_awlen), 		// [7:0]  
+		.ioMem_0_aw_bits_size(w_o_axi_awsize), 		// [2:0]  
+		.ioMem_0_aw_bits_burst(w_o_axi_awburst), 	// [1:0]  
+		.ioMem_0_aw_bits_lock(w_o_axi_awlock),
+		.ioMem_0_aw_bits_cache(w_o_axi_awcache), 	// [3:0]  
+		.ioMem_0_aw_bits_prot(w_o_axi_awprot), 		// [2:0]  
+		.ioMem_0_aw_bits_qos(w_o_axi_awqos), 		// [3:0]  
+	// AXI write data channel signals
+		.ioMem_0_w_ready(w_i_axi_wready),
+		.ioMem_0_w_valid(w_o_axi_wvalid),
+		.ioMem_0_w_bits_data(w_o_axi_wdata), 		// [31:0] 
+		.ioMem_0_w_bits_strb(w_o_axi_wstrb), 		// [3:0]  
+		.ioMem_0_w_bits_last(w_o_axi_wlast),
+	// AXI write response channel signals
+		.ioMem_0_b_ready(w_o_axi_bready),
+		.ioMem_0_b_valid(w_i_axi_bvalid),
+		.ioMem_0_b_bits_id(w_i_axi_bid),
+		.ioMem_0_b_bits_resp(w_i_axi_bresp), 		// [1:0] 
+	// AXI read address channel signals
+		.ioMem_0_ar_ready(w_i_axi_arready),
+		.ioMem_0_ar_valid(w_o_axi_arvalid),
+		.ioMem_0_ar_bits_id(w_o_axi_arid),
+		.ioMem_0_ar_bits_addr(w_o_axi_araddr[33:2]),// [31:0] 
+		.ioMem_0_ar_bits_len(w_o_axi_arlen), 		// [7:0]  
+		.ioMem_0_ar_bits_size(w_o_axi_arsize), 		// [2:0]  
+		.ioMem_0_ar_bits_burst(w_o_axi_arburst), 	// [1:0]  
+		.ioMem_0_ar_bits_lock(w_o_axi_arlock),
+		.ioMem_0_ar_bits_cache(w_o_axi_arcache), 	// [3:0]  
+		.ioMem_0_ar_bits_prot(w_o_axi_arprot), 		// [2:0]  
+		.ioMem_0_ar_bits_qos(w_o_axi_arqos), 		// [3:0]  
+	// AXI read data channel signals
+		.ioMem_0_r_ready(w_o_axi_rready),
+		.ioMem_0_r_valid(w_i_axi_rvalid),
+		.ioMem_0_r_bits_id(w_i_axi_rid),
+		.ioMem_0_r_bits_data(w_i_axi_rdata), 		// [31:0] 
+		.ioMem_0_r_bits_resp(w_i_axi_rresp), 		// [1:0]  
+		.ioMem_0_r_bits_last(w_i_axi_rlast),
+	// AXI-stream
+        .inStream_0_ready(w_inStream_ready),
+  		.inStream_0_valid(w_inStream_valid),
+  		.inStream_0_bits_data(w_inStream_data),
+  		.inStream_0_bits_last(w_inStream_last),
+		.outStream_0_ready(w_outStream_ready),
+  		.outStream_0_valid(w_outStream_valid),
+  		.outStream_0_bits_data(w_outStream_data),
+  		.outStream_0_bits_last(w_outStream_last),
+        .int_0(w_uart_int),
+        .uTx(w_uart_tx),
+        .uRx(w_uart_rx)
+	);
+endmodule
+`default_nettype wire
\ No newline at end of file

diff --git a/cargo/wb2axip b/cargo/wb2axip
new file mode 160000
index 0000000..e80d7a6
--- /dev/null
+++ b/cargo/wb2axip

@@ -0,0 +1 @@
+Subproject commit e80d7a6b5cab0a4073fd8c9037737231748bdaee