commit | fb2f115e179a5f302f8f68c7a5cf91454085d7b0 | [log] [tgz] |
---|---|---|
author | iamanintrovert <mhasan14@vols.utk.edu> | Mon Dec 14 19:01:00 2020 -0500 |
committer | GitHub <noreply@github.com> | Mon Dec 14 19:01:00 2020 -0500 |
tree | ad5639524a68cf6b41592449f4da3d843b9d5ce7 | |
parent | 7cabcdf55fc49f99c185790b7f9facad740f81a9 [diff] |
added vdda2
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v index 0bb022d..2ee3b1f 100644 --- a/verilog/gl/user_project_wrapper.v +++ b/verilog/gl/user_project_wrapper.v
@@ -6,6 +6,7 @@ input io_in[36:0]; inout vssa1; inout vdda1; + inout vdda2; inout analog_io[30:0]; 10good 10good_0();