added vdda2

verilog/gl/user_project_wrapper.v

diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 0bb022d..2ee3b1f 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -6,6 +6,7 @@
   input io_in[36:0];
   inout vssa1;
   inout vdda1;
+  inout vdda2;
   inout analog_io[30:0];
   
   10good 10good_0();