verilog/gl/user_project_wrapper.v

/* Generated by Yosys 0.9+2406 (git sha1 347dd01, gcc 8.3.1 -fPIC -Os) */

module user_project_wrapper(user_clock2, vccd1, vccd2, vdda1, vdda2, vssa1, vssa2, vssd1, vssd2, wb_clk_i, wb_rst_i, wbs_ack_o, wbs_cyc_i, wbs_stb_i, wbs_we_i, VPWR, VGND, io_in, io_oeb, io_out, la_data_in, la_data_out, la_oen, wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i);
  input VGND;
  input VPWR;
  input io_in[36:0];
  inout vssa1;
  inout vdda1;
  inout analog_io[30:0];
  
  10good 10good_0();
  
  chip-w-opamp chip-w-opamp_0();
  
endmodule
/*  
inout analog_io[26]
inout analog_io[25]
inout analog_io[24]
inout analog_io[23]
inout analog_io[22]
inout analog_io[21]
analog_io[20]
analog_io[19]
analog_io[18]
analog_io[17]
analog_io[16]
analog_io[15]
analog_io[14]
analog_io[13]
analog_io[12]
analog_io[11]
analog_io[10]
analog_io[9]
analog_io[8]
analog_io[7]
analog_io[6]
analog_io[5]
analog_io[4]
analog_io[3]
analog_io[2]
analog_io[1]
analog_io[0]

io_in[9]
io_in[8]
io_in[7]
io_in[6]
io_in[5]
io_in[4]
io_in[3]
io_in[2]
io_in[1]
io_in[0]

  output [36:0] io_oeb;
  output [36:0] io_out;
  inout  [30:0] analog_io;
  input [127:0] la_data_in;
  output [127:0] la_data_out;
  input [127:0] la_oen;
  input user_clock2;
  inout vccd1;
  inout vccd2;
  inout vdda1;
  inout vdda2;
  inout vssa1;
  inout vssa2;
  inout vssd1;
  inout vssd2;
  input wb_clk_i;
  input wb_rst_i;
  output wbs_ack_o;
  input [31:0] wbs_adr_i;
  input wbs_cyc_i;
  input [31:0] wbs_dat_i;
  output [31:0] wbs_dat_o;
  input [3:0] wbs_sel_i;
  input wbs_stb_i;
  input wbs_we_i;
  
  */