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foss-eda-tools / third_party / opencircuitdesign.com / open_pdks / 8255eadd14a92a2fa6198ff3bb190d2f4da12321 / . / sky130 / magic / sky130.tech
blob: b561940d549fccafff3a2eeaa550cd71855efb1c [file] [log] [blame]
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1###
2### Source file sky130.tech
3### Process this file with the preproc.py macro processor
4### Note that the tech name is always TECHNAME for
5### magic; this keeps compatibility between layouts
6### for all process variants.
7###
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]8#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]9# Copyright (c) 2020 R. Timothy Edwards
10# Revisions: See below
11#
12# This file is an Open Source foundry process describing
Tim Edwardsb4da28f2020-07-25 16:43:32 -0400[diff] [blame]13# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]14# process. The file may be distributed under the terms
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]15# of the Apache 2.0 license agreement.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]16#
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]17#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]18tech
19 format 35
20 TECHNAME
21end
22
23version
24 version REVISION
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]25 description "SkyWater SKY130: BETA Vendor Open Source rules and DRC"
26 requires magic-8.3.99
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]27end
28
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]29#------------------------------------------------------------------------
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]30# Status 7/10/20: Rev 1 (alpha):
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]31# First public release
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]32# Status 8/14/20: Rev 2 (alpha):
33# Started updating with new device/model naming convention
34#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]35
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]36#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]37# Supported device types
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]38#------------------------------------------------------------------------
39# device name magic ID layer description
40#------------------------------------------------------------------------
41# sky130_fd_pr__nfet_01v8 nfet standard nFET
42# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]43# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
44# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]45# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]46# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]47# sky130_fd_pr__pfet_01v8 pfet standard pFET
48# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]49# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]50# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
51# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
52# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
53# sky130_fd_pr__nfet_03v3_nvt --- native nFET
54# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
55# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
56# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]57# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]58# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode
59# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]60# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
61# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]62# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode
63# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]64# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]65# sky130_fd_pr__npn_05v0 pbase NPN in deep nwell
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]66# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]67# sky130_fd_pr__pnp_05v0 nbase PNP
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]68# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
69# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
70# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]71# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]72# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]73# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]74# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
75# sky130_fd_pr__res_generic_po npres n+ poly resistor
76# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
77# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
78# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
79# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
80# sky130_fd_pr__cap_var mvvaractor thickox varactor
81# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]82# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd ESD thickox nFET
83# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd ESD thickox pFET
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]84#
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]85# (*) Note that ppres may extract into some generic type called
86# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
87# allowed, and these are created from fixed layouts like the types below.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]88#
89# (**) nFET and pFET in standard cells are the same as devices
90# outside of the standard cell except for the DRC rule for
91# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
92#
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]93#-------------------------------------------------------------
94# The following devices are not extracted but are represented
95# only by script-generated subcells in the PDK.
96#-------------------------------------------------------------
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]97# sky130_fd_pr__esd_nfet_01v8 ESD nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]98# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]99# sky130_fd_pr__special_nfet_pass_flash flash nFET device
100# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
101# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
102# sky130_fd_pr__cap_vpp_* Vpp cap
103# sky130_fd_pr__ind_* inductor
104# sky130_fd_pr__fuse_m4 metal fuse device
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]105#--------------------------------------------------------------
106
107#-----------------------------------------------------
108# Tile planes
109#-----------------------------------------------------
110
111planes
112 dwell,dw
113 well,w
114 active,a
115 locali,li1,li
116 metal1,m1
117 metal2,m2
118 metal3,m3
119#ifdef METAL5
120#ifdef MIM
121 cap1,c1
122#endif (MIM)
123 metal4,m4
124#ifdef MIM
125 cap2,c2
126#endif (MIM)
127 metal5,m5
128#endif (METAL5)
129#ifdef REDISTRIBUTION
130 metali,mi
131#endif
132 block,b
133 comment,c
134end
135
136#-----------------------------------------------------
137# Tile types
138#-----------------------------------------------------
139
140types
141# Deep nwell
142 dwell dnwell,dnw
143
144# Wells
145 well nwell,nw
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]146 well pwell,pw
147 well rpw,rpwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]148 -well obswell
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]149 well pbase,npn
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]150 well nbase,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]151
152# Transistors
153 active nmos,ntransistor,nfet
154 -active scnmos,scntransistor,scnfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]155 -active npd,npdfet,sramnfet
156 -active npass,npassfet,srampassfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]157 active pmos,ptransistor,pfet
158 -active scpmos,scptransistor,scpfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]159 -active scpmoshvt,scpfethvt
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]160 -active ppu,ppufet,srampfet
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]161 active nnmos,nntransistor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]162 active mvnmos,mvntransistor,mvnfet
163 active mvpmos,mvptransistor,mvpfet
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]164 active mvnnmos,mvnntransistor,mvnnfet,nnfet
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]165 -active mvnmosesd,mvntransistoresd,mvnfetesd
166 -active mvpmosesd,mvptransistoresd,mvpfetesd
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]167 active varactor,varact,var
168 active mvvaractor,mvvaract,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]169
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]170 active pmoslvt,pfetlvt
171 active pmosmvt,pfetmvt
172 active pmoshvt,pfethvt
173 active nmoslvt,nfetlvt
174 active varactorhvt,varacthvt,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]175 -active nsonos,sonos
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]176 -active sramnvar,corenvar,corenvaractor
177 -active srampvar,corepvar,corepvaractor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]178
179# Diffusions
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]180 -active fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]181 active ndiff,ndiffusion,ndif
182 active pdiff,pdiffusion,pdif
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]183 active mvndiff,mvndiffusion,mvndif
184 active mvpdiff,mvpdiffusion,mvpdif
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]185 active ndiffc,ndcontact,ndc
186 active pdiffc,pdcontact,pdc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]187 active mvndiffc,mvndcontact,mvndc
188 active mvpdiffc,mvpdcontact,mvpdc
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]189 active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap
190 active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap
191 active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap
192 active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap
193 active psubdiffcont,psubstratepcontact,psc,ptapc
194 active nsubdiffcont,nsubstratencontact,nsc,ntapc
195 active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc
196 active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]197 -active obsactive
198 -active mvobsactive
199
200# Poly
201 active poly,p,polysilicon
202 active polycont,pc,pcontact,polycut,polyc
203 active xpolycontact,xpolyc,xpc
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]204 -active polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]205
206# Resistors
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]207 active npolyres,npres,mrp1
208 active ppolyres,ppres,xhrpoly
209 active xpolyres,xpres,xres,uhrpoly
210 active ndiffres,rnd,rdn,rndiff
211 active pdiffres,rpd,rdp,rpdiff
212 active mvndiffres,mvrnd,mvrdn,mvrndiff
213 active mvpdiffres,mvrpd,mvrdp,mvrpdiff
214 active rmp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]215
216# Diodes
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]217 active pdiode,pdi
218 active ndiode,ndi
219 active nndiode,nndi
220 active pdiodec,pdic
221 active ndiodec,ndic
222 active nndiodec,nndic
223 active mvpdiode,mvpdi
224 active mvndiode,mvndi
225 active mvpdiodec,mvpdic
226 active mvndiodec,mvndic
227 active pdiodelvt,pdilvt
228 active pdiodehvt,pdihvt
229 active ndiodelvt,ndilvt
230 active pdiodelvtc,pdilvtc
231 active pdiodehvtc,pdihvtc
232 active ndiodelvtc,ndilvtc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]233
234# Local Interconnect
235 locali locali,li1,li
236 -locali corelocali,coreli1,coreli
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]237 locali rlocali,rli1,rli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]238 locali viali,vial,mcon,m1c,v0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]239 -locali obsli1,obsli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]240 -locali obsli1c,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]241
242# Metal 1
243 metal1 metal1,m1,met1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]244 metal1 rmetal1,rm1,rmet1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]245 metal1 via1,m2contact,m2cut,m2c,via,v,v1
246 -metal1 obsm1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]247 metal1 padl
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]248 -metal1 m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]249
250# Metal 2
251 metal2 metal2,m2,met2
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]252 metal2 rmetal2,rm2,rmet2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]253 metal2 via2,m3contact,m3cut,m3c,v2
254 -metal2 obsm2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]255 -metal2 m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]256
257# Metal 3
258 metal3 metal3,m3,met3
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]259 metal3 rmetal3,rm3,rmet3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]260 -metal3 obsm3
261#ifdef METAL5
262 metal3 via3,v3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]263 -metal3 m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]264
265#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]266 cap1 mimcap,mim,capm
267 cap1 mimcapcontact,mimcapc,mimcc,capmc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]268#endif
269
270# Metal 4
271 metal4 metal4,m4,met4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]272 metal4 rmetal4,rm4,rmet4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]273 -metal4 obsm4
274 metal4 via4,v4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]275 -metal4 m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]276
277#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]278 cap2 mimcap2,mim2,capm2
279 cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]280#endif
281
282# Metal 5
283 metal5 metal5,m5,met5
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]284 metal5 rm5,rmetal5,rmet5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]285 -metal5 obsm5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]286 -metal5 m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]287#endif (METAL5)
288
289#ifdef REDISTRIBUTION
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]290 metal5 mrdlcontact,mrdlc
291 metali metalrdl,mrdl,metrdl
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]292 -metali obsmrdl
293#endif (REDISTRIBUTION)
294
295# Miscellaneous
296 -block glass
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]297 -block fillblock,fillblock4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]298 comment comment
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]299 -comment obscomment
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]300# fixed resistor width identifiers
301 -comment res0p35
302 -comment res0p69
303 -comment res1p41
304 -comment res2p85
305 -comment res5p73
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]306
307end
308
309#-----------------------------------------------------
310# Magic contact types
311#-----------------------------------------------------
312
313contact
314 pc poly locali
315 ndc ndiff locali
316 pdc pdiff locali
317 nsc nsd locali
318 psc psd locali
319 ndic ndiode locali
320 ndilvtc ndiodelvt locali
321 nndic nndiode locali
322 pdic pdiode locali
323 pdilvtc pdiodelvt locali
324 pdihvtc pdiodehvt locali
325 xpc xpc locali
326
327 mvndc mvndiff locali
328 mvpdc mvpdiff locali
329 mvnsc mvnsd locali
330 mvpsc mvpsd locali
331 mvndic mvndiode locali
332 mvpdic mvpdiode locali
333
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]334 mcon locali metal1
335 obsmcon obsli metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]336
337 via1 metal1 metal2
338 via2 metal2 metal3
339#ifdef METAL5
340 via3 metal3 metal4
341 via4 metal4 metal5
342#endif (METAL5)
343 stackable
344
345#ifdef METAL5
346#ifdef MIM
347 # MiM cap contacts are not stackable!
348 mimcc mimcap metal4
349 mim2cc mimcap2 metal5
350#endif (MIM)
351
352 padl m1 m2 m3 m4 m5 glass
353#else
354 padl m1 m2 m3 glass
355#endif (!METAL5)
356
357#ifdef REDISTRIBUTION
358 mrdlc metal5 mrdl
359#endif (REDISTRIBUTION)
360end
361
362#-----------------------------------------------------
363# Layer aliases
364#-----------------------------------------------------
365
366aliases
367
368 allwellplane nwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]369 allnwell nwell,obswell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]370
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]371 allnfets nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nfetlvt,nsonos
372 allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]373 allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]374 allfetsstd nfet,mvnfet,mvnfetesd,mvnnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]375 allfetsspecial scnfet,scpfet,scpfethvt
376 allfetscore npass,npd,nsonos,ppu,corenvar,corepvar
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]377 allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]378
379 allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
380 allnactive allnactivenonfet,allnfets
381 allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]382 allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]383
384 allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
385 allpactive allpactivenonfet,allpfets
386 allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]387 allpactivetap *psd,*mvpsd,corepvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]388
389 allactivenonfet allnactivenonfet,allpactivenonfet
390 allactive allactivenonfet,allfets
391
392 allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
393
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]394 allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]395 allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]396 alldifflv allndifflv,allpdifflv
397 allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
398 allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
399 alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
400
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]401 allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet
402 allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]403 alldiffmv allndiffmv,allpdiffmv
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]404 allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet
405 allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]406 alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
407 allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
408 allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
409 alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
410
411 alldiffnonfet alldifflvnonfet,alldiffmvnonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]412 alldiff alldifflv,alldiffmv,fomfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]413
414 allpolyres mrp1,xhrpoly,uhrpoly,rmp
415 allpolynonfet *poly,allpolyres,xpc
416 allpolynonres *poly,allfets,xpc
417
418 allpoly allpolynonfet,allfets
419 allpolynoncap *poly,xpc,allfets,allpolyres
420
421 allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
422 allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
423 allndiffcontmv mvndc,mvnsc,mvndic
424 allpdiffcontmv mvpdc,mvpsc,mvpdic
425 allndiffcont allndiffcontlv,allndiffcontmv
426 allpdiffcont allpdiffcontlv,allpdiffcontmv
427 alldiffcontlv allndiffcontlv,allpdiffcontlv
428 alldiffcontmv allndiffcontmv,allpdiffcontmv
429 alldiffcont alldiffcontlv,alldiffcontmv
430
431 allcont alldiffcont,pc
432
433 allres allpolyres,allactiveres
434
435 allli *locali,coreli,rli
436 allm1 *m1,rm1
437 allm2 *m2,rm2
438 allm3 *m3,rm3
439#ifdef METAL5
440 allm4 *m4,rm4
441 allm5 *m5,rm5
442#endif (METAL5)
443
444 allpad padl
445
446 psub pwell
447
448end
449
450#-----------------------------------------------------
451# Layer drawing styles
452#-----------------------------------------------------
453
454styles
455 styletype mos
456 dnwell cwell
457 nwell nwell
458 pwell pwell
459 rpwell pwell ptransistor_stripes
460 ndiff ndiffusion
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]461 fomfill ndiffusion
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]462 pdiff pdiffusion
463 nsd ndiff_in_nwell
464 psd pdiff_in_pwell
465 nfet ntransistor ntransistor_stripes
466 scnfet ntransistor ntransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]467 npass ntransistor ntransistor_stripes
468 npd ntransistor ntransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]469 pfet ptransistor ptransistor_stripes
470 scpfet ptransistor ptransistor_stripes
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]471 scpfethvt ptransistor ptransistor_stripes implant2
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]472 ppu ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]473 var polysilicon ndiff_in_nwell
474 ndc ndiffusion metal1 contact_X'es
475 pdc pdiffusion metal1 contact_X'es
476 nsc ndiff_in_nwell metal1 contact_X'es
477 psc pdiff_in_pwell metal1 contact_X'es
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]478 corenvar polysilicon ndiff_in_nwell
479 corepvar polysilicon pdiff_in_pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]480
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]481 pnp nwell ntransistor_stripes
482 npn pwell ptransistor_stripes
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]483
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]484 pfetlvt ptransistor ptransistor_stripes implant1
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]485 pfetmvt ptransistor ptransistor_stripes implant3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]486 pfethvt ptransistor ptransistor_stripes implant2
487 nfetlvt ntransistor ntransistor_stripes implant1
488 nsonos ntransistor implant3
489 varhvt polysilicon ndiff_in_nwell implant2
490
491 mvndiff ndiffusion hvndiff_mask
492 mvpdiff pdiffusion hvpdiff_mask
493 mvnsd ndiff_in_nwell hvndiff_mask
494 mvpsd pdiff_in_pwell hvpdiff_mask
495 mvnfet ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]496 mvnfetesd ntransistor ntransistor_stripes hvndiff_mask
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]497 mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
498 mvpfet ptransistor ptransistor_stripes
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]499 mvpfetesd ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]500 mvvar polysilicon ndiff_in_nwell hvndiff_mask
501 mvndc ndiffusion metal1 contact_X'es hvndiff_mask
502 mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
503 mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
504 mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
505
506 poly polysilicon
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]507 polyfill polysilicon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]508 pc polysilicon metal1 contact_X'es
509 npolyres polysilicon silicide_block nselect2
510 ppolyres polysilicon silicide_block pselect2
511 xpc polysilicon pselect2 metal1 contact_X'es
512 rmp polysilicon poly_resist_stripes
513
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]514 res0p35 implant1
515 res0p69 implant1
516 res1p41 implant1
517 res2p85 implant1
518 res5p73 implant1
519
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]520 pdiode pdiffusion pselect2
521 ndiode ndiffusion nselect2
522 pdiodec pdiffusion pselect2 metal1 contact_X'es
523 ndiodec ndiffusion nselect2 metal1 contact_X'es
524
525 nndiode ndiffusion nselect2 implant3
526 ndiodelvt ndiffusion nselect2 implant1
527 pdiodelvt pdiffusion pselect2 implant1
528 pdiodehvt pdiffusion pselect2 implant2
529 pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
530 pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
531 ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
532
533 mvpdiode pdiffusion pselect2 hvpdiff_mask
534 mvndiode ndiffusion nselect2 hvndiff_mask
535 mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
536 mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
537 nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
538
539 locali metal1
540 coreli metal1
541 rli metal1 poly_resist_stripes
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]542 mcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]543 obsli metal1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]544 obsmcon metal1 metal2 via1arrow
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]545
546 metal1 metal2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]547 m1fill metal2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]548 rm1 metal2 poly_resist_stripes
549 obsm1 metal2
550 m2c metal2 metal3 via2arrow
551 metal2 metal3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]552 m2fill metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]553 rm2 metal3 poly_resist_stripes
554 obsm2 metal3
555 m3c metal3 metal4 via3alt
556 metal3 metal4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]557 m3fill metal4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]558 rm3 metal4 poly_resist_stripes
559 obsm3 metal4
560#ifdef METAL5
561#ifdef MIM
562 mimcap metal3 mems
563 mimcc metal3 contact_X'es mems
564 mimcap2 metal4 mems
565 mim2cc metal4 contact_X'es mems
566#endif (MIM)
567 via3 metal4 metal5 via4
568 metal4 metal5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]569 m4fill metal5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]570 rm4 metal5 poly_resist_stripes
571 obsm4 metal5
572 via4 metal5 metal6 via5
573 metal5 metal6
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]574 m5fill metal6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]575 rm5 metal6 poly_resist_stripes
576 obsm5 metal6
577#endif (METAL5)
578#ifdef REDISTRIBUTION
579 mrdlc metal6 metal7 via6
580 metalrdl metal7
581 obsmrdl metal7
582#endif (REDISTRIBUTION)
583
584 glass overglass
585 mrp1 poly_resist poly_resist_stripes
586 xhrpoly poly_resist silicide_block
587 uhrpoly poly_resist
588 ndiffres ndiffusion ndop_stripes
589 pdiffres pdiffusion pdop_stripes
590 mvndiffres ndiffusion hvndiff_mask ndop_stripes
591 mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
592 comment comment
593 error_p error_waffle
594 error_s error_waffle
595 error_ps error_waffle
596 fillblock cwell
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]597 fillblock4 cwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]598
599 obswell cwell
600 obsactive implant4
601
602#ifndef METAL5
603 padl metal4 via4 overglass
604#else
605 padl metal6 via6 overglass
606#endif
607
608 magnet substrate_field_implant
609 rotate via3alt
610 fence via5
611end
612
613#-----------------------------------------------------
614# Special paint/erase rules
615#-----------------------------------------------------
616
617compose
618 compose nfet poly ndiff
619 compose pfet poly pdiff
620 compose var poly nsd
621
622 compose mvnfet poly mvndiff
623 compose mvpfet poly mvpdiff
624 compose mvvar poly mvnsd
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]625
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]626 paint obsmcon locali via1
627 paint obsmcon obsm1 obsli,obsm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]628
629 paint ndc nwell pdc
630 paint nfet nwell pfet
631 paint scnfet nwell scpfet
632 paint ndiff nwell pdiff
633 paint psd nwell nsd
634 paint psc nwell nsc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]635 paint npd nwell ppu
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]636
637 paint pdc pwell ndc
638 paint pfet pwell nfet
639 paint scpfet pwell scnfet
640 paint pdiff pwell ndiff
641 paint nsd pwell psd
642 paint nsc pwell psc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]643 paint ppu pwell npd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]644
645 paint pdc coreli pdc
646 paint ndc coreli ndc
647 paint pc coreli pc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]648 paint nsc coreli nsc
649 paint psc coreli psc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]650 paint viali coreli viali
651
652 paint coreli pdc pdc
653 paint coreli ndc ndc
654 paint coreli pc pc
655 paint coreli nsc nsc
656 paint coreli psc psc
657 paint coreli viali viali
658
659#ifdef METAL5
660 paint m4 obsm4 m4
661 paint m5 obsm5 m5
662#endif (METAL5)
663end
664
665#-----------------------------------------------------
666# Electrical connectivity
667#-----------------------------------------------------
668
669connect
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]670 *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
671 pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]672 *li,coreli *li,coreli
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]673 *m1,m1fill,obsmcon *m1,m1fill,obsmcon
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]674 *m2,m2fill *m2,m2fill
675 *m3,m3fill *m3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]676#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]677 *m4,m4fill *m4,m4fill
678 *m5,m5fill *m5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]679#ifdef MIM
680 *mimcap *mimcap
681 *mimcap2 *mimcap2
682#endif (MIM)
683#endif (METAL5)
684 allnactivenonfet allnactivenonfet
685 allpactivenonfet allpactivenonfet
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]686 *poly,xpc,allfets,polyfill *poly,xpc,allfets,polyfill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]687#ifdef REDISTRIBUTION
688 # RDL connects to m5 (i.e., padl) through glass cut
689 *mrdl *mrdl
690 glass metrdl
691#endif (REDISTRIBUTION)
692end
693
694#-----------------------------------------------------
695# CIF/GDS output layer definitions
696#-----------------------------------------------------
697# NOTE: All values in this section MUST be multiples of 25
698# or else magic will scale below the allowed layout grid size
699
700cifoutput
701
702#----------------------------------------------------------------
703style gdsii
704# NOTE: This section is used for actual GDS output
705#----------------------------------------------------------------
706 scalefactor 10 nanometers
707 options calma-permissive-labels
708 gridlimit 5
709
710#----------------------------------------------------------------
711# Create a temp layer from the cell bounding box for use in
712# generating ID layers. Note that "boundary", unlike "bbox",
713# requires the FIXED_BBOX property (abutment box) in the cell.
714#----------------------------------------------------------------
715 templayer CELLBOUND
716 boundary
717
718#----------------------------------------------------------------
719# BOUND
720#----------------------------------------------------------------
721 layer BOUND CELLBOUND
722 calma 235 4
723
724# Create a boundary outside of an abutment box, so that layers
725# can be made to stretch to the abutment box edges. First strink
726# so that any box that would be so small as to interact with
727# itself will be removed.
728
729 templayer CELLRING CELLBOUND
730 shrink 345
731 grow 545
732 and-not CELLBOUND
733
734#----------------------------------------------------------------
735# DNWELL
736#----------------------------------------------------------------
737
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]738 layer DNWELL dnwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]739 calma 64 18
740
741 layer PWRES rpw
742 and dnwell
743 calma 64 13
744
745#----------------------------------------------------------------
746# NWELL
747#----------------------------------------------------------------
748
749 layer NWELL allnwell
750 bloat-all rpw dnwell
751 and-not rpw,pwell
752 calma 64 20
753
754 layer WELLTXT
755 labels allnwell noport
756 calma 64 16
757
758 layer WELLPIN
759 labels allnwell port
760 calma 64 5
761
762#----------------------------------------------------------------
763# SUB (text/port only)
764#----------------------------------------------------------------
765
766 layer SUBTXT
767 labels pwell noport
768 calma 122 16
769
770 layer SUBPIN
771 labels pwell port
772 calma 64 59
773
774#----------------------------------------------------------------
775# DIFF
776#----------------------------------------------------------------
777
778 layer DIFF allnactivenontap,allpactivenontap,allactiveres
779 labels allnactivenontap,allpactivenontap
780 calma 65 20
781
782#----------------------------------------------------------------
783# TAP
784#----------------------------------------------------------------
785
786 layer TAP allnactivetap,allpactivetap
787 labels allnactivetap,allpactivetap
788 calma 65 44
789
790#----------------------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]791# FOM
792#----------------------------------------------------------------
793
794 layer FOMFILL fomfill
795 labels fomfill
796 calma 65 28
797
798#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]799# PSDM, NSDM (PPLUS, NPLUS implants)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]800#----------------------------------------------------------------
801
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]802 templayer basePSDM pdiffres,mvpdiffres
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]803 grow 15
804 or xhrpoly,uhrpoly,xpc
805 grow 110
806 bloat-or allpactivetap * 125 allnactivenontap 0
807 bloat-or allpactivenontap * 125 allnactivetap 0
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]808
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]809 templayer baseNSDM ndiffres,mvndiffres
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]810 grow 125
811 bloat-or allnactivetap * 125 allpactivenontap 0
812 bloat-or allnactivenontap * 125 allpactivetap 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]813
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]814 templayer extendPSDM basePSDM,CELLRING
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]815 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]816 and-not baseNSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]817 and-not CELLRING
818
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]819 layer PSDM basePSDM,extendPSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]820 grow 185
821 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]822 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]823 mask-hints PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]824 calma 94 20
825
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]826 templayer extendNSDM baseNSDM,CELLRING
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]827 bridge 380 380
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]828 and-not basePSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]829 and-not CELLRING
830
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]831 layer NSDM baseNSDM,extendNSDM
Tim Edwardsb894d922020-11-29 19:04:15 -0500[diff] [blame]832 grow 185
833 shrink 185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]834 close 265000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]835 mask-hints NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]836 calma 93 44
837
838#----------------------------------------------------------------
839# LVTN
840#----------------------------------------------------------------
841
842 layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
843 grow 180
844 bridge 380 380
845 grow 185
846 shrink 185
847 close 265000
848 calma 125 44
849
850#----------------------------------------------------------------
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]851# HVTR
852#----------------------------------------------------------------
853
854 layer HVTR pfetmvt
855 grow 180
856 bridge 380 380
857 grow 185
858 shrink 185
859 close 265000
860 calma 18 20
861
862#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]863# HVTP
864#----------------------------------------------------------------
865
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]866 layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]867 grow 180
868 bridge 380 380
869 grow 185
870 shrink 185
871 close 265000
872 calma 78 44
873
874#----------------------------------------------------------------
875# SONOS
876#----------------------------------------------------------------
877
878 layer SONOS nsonos
879 grow 100
880 grow-min 410
881 bridge 500 410
882 grow 250
883 shrink 250
884 calma 80 20
885
886#----------------------------------------------------------------
887# SONOS requires COREID around area (areaid.ce). Also, the
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]888# coreli layer indicates a cell needing COREID. Also, devices
889# npd, npass, and ppu indicate a COREID cell.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]890#----------------------------------------------------------------
891
892 layer COREID
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]893 bloat-all nsonos,coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]894 mask-hints COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]895 calma 81 2
896
897#----------------------------------------------------------------
898# STDCELL applies to all cells containing scnfet or scpfet.
899#----------------------------------------------------------------
900
901 layer STDCELL scnfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]902 bloat-all scpfet,scpfethvt,scnfet CELLBOUND
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]903 mask-hints STDCELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]904 calma 81 4
905
906#----------------------------------------------------------------
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]907# ESDID is a marker layer for ESD devices in the padframe I/O.
908#----------------------------------------------------------------
909
910 layer ESDID
911 bloat-all mvnfetesd *mvndiff,*poly
912 bloat-all mvpfetesd *mvpdiff,*poly
913 grow 100
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]914 mask-hints ESDID
Tim Edwardsbba9bd12020-12-22 17:16:09 -0500[diff] [blame]915 calma 81 19
916
917#----------------------------------------------------------------
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]918# NPNID and PNPID apply to bipolar transistors
919#----------------------------------------------------------------
920
921 layer NPNID
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]922 bloat-all npn dnwell
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]923 mask-hints NPNID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]924 calma 82 20
925
926 templayer pnparea pnp
927 grow 400
928
929 layer PNPID
930 bloat-all pnparea *psd
931 or pnparea
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]932 mask-hints PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]933 calma 82 44
934
935#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]936# RPM
937#----------------------------------------------------------------
938
939 layer RPM
940 bloat-all xhrpoly xpc
941 grow 200
942 grow-min 1270
943 grow 420
944 shrink 420
945 calma 86 20
946
947#----------------------------------------------------------------
948# URPM (2kOhms/sq. poly implant)
949#----------------------------------------------------------------
950
951 layer URPM
952 bloat-all uhrpoly xpc
953 grow 200
954 grow-min 1270
955 grow 420
956 shrink 420
957 calma 79 20
958
959#----------------------------------------------------------------
960# LDNTM (Tip implant for SONOS FETs)
961#----------------------------------------------------------------
962
963 layer LDNTM
964 bloat-all nsonos *ndiff
965 grow 185
966 grow 345
967 shrink 345
968 calma 11 44
969
970#----------------------------------------------------------------
971# HVNTM (Tip implant for MV ndiff devices)
972#----------------------------------------------------------------
973
974 templayer hvntm_block *mvpsd
975 grow 185
976
977 layer HVNTM
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]978 bloat-all mvnfet,mvnfetesd,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]979 bloat-all mvvaractor *mvnsd
980 and-not hvntm_block
981 grow 185
982 grow 345
983 shrink 345
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]984 and-not hvntm_block
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]985 calma 125 20
986
987#----------------------------------------------------------------
988# POLY
989#----------------------------------------------------------------
990
991 layer POLY allpoly
992 calma 66 20
993
994 layer POLYTXT
995 labels allpoly noport
996 calma 66 16
997
998 layer POLYPIN
999 labels allpoly port
1000 calma 66 5
1001
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1002 layer POLYFILL polyfill
1003 labels polyfill
1004 calma 66 28
1005
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1006#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1007# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1008#----------------------------------------------------------------
1009
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1010 templayer thkox_area alldiffmv,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1011 grow 185
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]1012 bloat-all alldiffmv nwell
1013 grow 345
1014 shrink 345
1015
1016 templayer large_ptap_mv thkox_area
1017 shrink 420
1018 grow 420
1019
1020 templayer small_ptap_mv thkox_area
1021 and-not large_ptap_mv
1022 # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
1023 grow-min 840
1024
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1025 templayer baseHVI thkox_area,small_ptap_mv
Tim Edwardseacb0a62020-11-17 20:20:13 -0500[diff] [blame]1026 bridge 700 600
1027 grow 345
1028 shrink 345
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1029
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1030 templayer extendHVI baseHVI,CELLRING
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1031 grow 345
1032 shrink 345
1033 and-not CELLRING
1034
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1035 layer HVI baseHVI,extendHVI
1036 mask-hints HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1037 calma 75 20
1038
1039#----------------------------------------------------------------
1040# CONT (LICON)
1041#----------------------------------------------------------------
1042
1043 layer CONT allcont
1044 squares-grid 0 170 170
1045 calma 66 44
1046
1047 # Contact for pres is different than other LICON contacts
1048 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
1049 templayer xpc_horiz xpc
1050 shrink 1007
1051 grow 1007
1052
1053 layer CONT xpc
1054 and-not xpc_horiz
1055 # Force long edge vertical for contacts narrower than 2um
1056 # Minimum space is 350 but 520 satisfies no. of contacts rule
1057 slots 80 190 520 80 2000 350
1058 calma 66 44
1059
1060 layer CONT xpc
1061 and xpc_horiz
1062 # Force long edge vertical for contacts wider than 2um
1063 # Minimum space is 350 but 520 satisfies no. of contacts rule
1064 slots 80 2000 350 80 190 520
1065 calma 66 44
1066
1067#----------------------------------------------------------------
1068# NPC (Nitride poly cut)
1069# surrounds CONT (LICON) on poly only (i.e., pc)
1070#----------------------------------------------------------------
1071
1072 layer NPC pc
1073 squares-grid 0 170 170
1074 grow 100
1075 bridge 270 270
1076 grow 130
1077 shrink 130
Tim Edwards5bd81e42020-12-16 11:53:16 -0500[diff] [blame]1078 mask-hints NPC
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1079 calma 95 20
1080
1081 # NPC is also generated on xhrpoly and uhrpoly resistors
1082
1083 layer NPC xpc,xhrpoly,uhrpoly
1084 # xpc surrounds precision_resistor by 0.095um
1085 grow 95
1086 grow 130
1087 shrink 130
1088 calma 95 20
1089
1090#----------------------------------------------------------------
1091# Device markers
1092#----------------------------------------------------------------
1093
1094 layer DIFFRES rdn,mvrdn,rdp,mvrdp
1095 calma 65 13
1096
1097 layer POLYRES mrp1
1098 calma 66 13
1099
1100 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
1101 layer POLYSHORT rmp
1102 calma 66 15
1103
1104 # POLYRES extends to edge of contact cut
1105 layer POLYRES xhrpoly,uhrpoly
1106 grow 60
1107 and xpc
1108 or xhrpoly,uhrpoly
1109 calma 66 13
1110
1111 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
1112 # To be done: Expand to include anode, cathode, and guard ring
1113 calma 81 23
1114
1115#----------------------------------------------------------------
1116# LI
1117#----------------------------------------------------------------
1118 layer LI allli
1119 calma 67 20
1120
1121 layer LITXT
1122 labels *locali,coreli noport
1123 calma 67 16
1124
1125 layer LIPIN
1126 labels *locali,coreli port
1127 calma 67 5
1128
1129 layer LIRES rli
1130 labels rli
1131 calma 67 13
1132
1133#----------------------------------------------------------------
1134# MCON
1135#----------------------------------------------------------------
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1136 layer MCON mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1137 squares-grid 0 170 190
1138 calma 67 44
1139
1140#----------------------------------------------------------------
1141# MET1
1142#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1143 layer MET1 allm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1144 calma 68 20
1145
1146 layer MET1TXT
1147 labels allm1 noport
1148 calma 68 16
1149
1150 layer MET1PIN
1151 labels allm1 port
1152 calma 68 5
1153
1154 layer MET1RES rm1
1155 labels rm1
1156 calma 68 13
1157
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1158 layer MET1FILL m1fill
1159 labels m1fill
1160 calma 68 28
1161
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1162#----------------------------------------------------------------
1163# VIA1
1164#----------------------------------------------------------------
1165 layer VIA1 via1
1166 squares-grid 55 150 170
1167 calma 68 44
1168
1169#----------------------------------------------------------------
1170# MET2
1171#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1172 layer MET2 allm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1173 calma 69 20
1174
1175 layer MET2TXT
1176 labels allm2 noport
1177 calma 69 16
1178
1179 layer MET2PIN
1180 labels allm2 port
1181 calma 69 5
1182
1183 layer MET2RES rm2
1184 labels rm2
1185 calma 69 13
1186
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1187 layer MET2FILL m2fill
1188 labels m2fill
1189 calma 69 28
1190
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1191#----------------------------------------------------------------
1192# VIA2
1193#----------------------------------------------------------------
1194 layer VIA2 via2
1195 squares-grid 40 200 200
1196 calma 69 44
1197
1198#----------------------------------------------------------------
1199# MET3
1200#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1201 layer MET3 allm3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1202 calma 70 20
1203
1204 layer MET3TXT
1205 labels allm3 noport
1206 calma 70 16
1207
1208 layer MET3PIN
1209 labels allm3 port
1210 calma 70 5
1211
1212 layer MET3RES rm3
1213 labels rm3
1214 calma 70 13
1215
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1216 layer MET3FILL m3fill
1217 labels m3fill
1218 calma 70 28
1219
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1220#ifdef METAL5
1221#----------------------------------------------------------------
1222# VIA3
1223#----------------------------------------------------------------
1224 layer VIA3 via3
1225#ifdef MIM
1226 or mimcc
1227#endif (MIM)
1228 squares-grid 60 200 200
1229 calma 70 44
1230
1231#----------------------------------------------------------------
1232# MET4
1233#----------------------------------------------------------------
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1234 layer MET4 allm4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1235 calma 71 20
1236
1237 layer MET4TXT
1238 labels allm4 noport
1239 calma 71 16
1240
1241 layer MET4PIN
1242 labels allm4 port
1243 calma 71 5
1244
1245 layer MET4RES rm4
1246 labels rm4
1247 calma 71 13
1248
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1249 layer MET4FILL m4fill
1250 labels m4fill
1251 calma 71 28
1252
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1253#----------------------------------------------------------------
1254# VIA4
1255#----------------------------------------------------------------
1256 layer VIA4 via4
1257#ifdef MIM
1258 or mim2cc
1259#endif (MIM)
1260 squares-grid 190 800 800
1261 calma 71 44
1262
1263#----------------------------------------------------------------
1264# MET5
1265#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1266 layer MET5 allm5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1267 calma 72 20
1268
1269 layer MET5TXT
1270 labels allm5 noport
1271 calma 72 16
1272
1273 layer MET5PIN
1274 labels allm5 port
1275 calma 72 5
1276
1277 layer MET5RES rm5
1278 labels rm5
1279 calma 72 13
1280
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1281 layer MET5FILL m5fill
1282 labels m5fill
1283 calma 72 28
1284
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1285#endif (METAL5)
1286
1287#ifdef REDISTRIBUTION
1288#----------------------------------------------------------------
1289# RDL
1290#----------------------------------------------------------------
1291 layer RDL *metrdl
1292 calma 74 20
1293
1294 layer RDLTXT
1295 labels *metrdl noport
1296 calma 74 16
1297
1298 layer RDLPIN
1299 labels *metrdl port
1300 calma 74 5
1301
Tim Edwardsfa35ae22020-10-21 10:59:05 -0400[diff] [blame]1302 layer PI1 *metrdl
1303 and padl,glass
1304 # Test only---needs GDS layer number
1305
1306 layer UBM *metrdl
1307 shrink 50000
1308 grow 40000
1309 # Test only---needs GDS layer number
1310
1311 layer PI2 *metrdl
1312 shrink 50000
1313 grow 25000
1314 # Test only---needs GDS layer number
1315
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1316#endif REDISTRIBUTION
1317
1318#----------------------------------------------------------------
1319# GLASS
1320#----------------------------------------------------------------
1321 layer GLASS glass
1322 calma 76 20
1323
1324#ifdef MIM
1325#----------------------------------------------------------------
1326# CAPM
1327#----------------------------------------------------------------
1328 layer CAPM *mimcap
1329 labels mimcap
1330 calma 89 44
1331
1332 layer CAPM2 *mimcap2
1333 labels mimcap2
1334 calma 97 44
1335#endif (MIM)
1336
1337#----------------------------------------------------------------
1338# Chip top level marker for DRC latchup rules to check 15um
1339# distance to taps (otherwise 6um is used)
1340#----------------------------------------------------------------
1341
1342 layer LOWTAPDENSITY
1343 bbox top
1344 # Clear 200um for pads + 50um for required high tap density
1345 # in critical area.
1346 shrink 250000
1347 calma 81 14
1348
1349#----------------------------------------------------------------
1350# FILLBLOCK
1351#----------------------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1352 layer FILLOBSFOM obsactive
1353 calma 22 24
1354
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1355 layer FILLOBSM1 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1356 calma 62 24
1357
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1358 layer FILLOBSM2 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1359 calma 105 52
1360
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1361 layer FILLOBSM3 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1362 calma 107 24
1363
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1364 layer FILLOBSM4 fillblock,fillblock4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1365 calma 112 4
1366
1367 render DNWELL cwell -0.1 0.1
1368 render NWELL nwell 0.0 0.2062
1369 render DIFF ndiffusion 0.2062 0.12
1370 render TAP pdiffusion 0.2062 0.12
1371 render POLY polysilicon 0.3262 0.18
1372 render CONT via 0.5062 0.43
1373 render LI metal1 0.9361 0.10
1374 render MCON via 1.0361 0.34
1375 render MET1 metal2 1.3761 0.36
1376 render VIA1 via 1.7361 0.27
1377 render MET2 metal3 2.0061 0.36
1378 render VIA2 via 2.3661 0.42
1379 render MET3 metal4 2.7861 0.845
1380#ifdef METAL5
1381 render VIA3 via 3.6311 0.39
1382 render MET4 metal5 4.0211 0.845
1383 render VIA4 via 4.8661 0.505
1384 render MET5 metal6 5.3711 1.26
1385 render CAPM metal8 2.4661 0.2
1386 render CAPM2 metal9 3.7311 0.2
1387#ifdef REDISTRIBUTION
1388 render RDL metal7 11.8834 4.0
1389#endif (!REDISTRIBUTION)
1390#endif (!METAL5)
1391
1392#----------------------------------------------------------------
1393style drc
1394#----------------------------------------------------------------
1395# NOTE: This style is used for DRC only, not for GDS output
1396#----------------------------------------------------------------
1397 scalefactor 10 nanometers
1398 options calma-permissive-labels
1399
1400 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
1401 templayer dnwell_shrink dnwell
1402 shrink 1030
1403
1404 templayer nwell_missing dnwell
1405 grow 400
1406 and-not dnwell_shrink
1407 and-not nwell
1408
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1409 templayer pwell_in_dnwell dnwell
1410 and-not nwell
1411
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1412 # SONOS nFET devices must be in deep nwell
1413 templayer dnwell_missing nsonos
1414 and-not dnwell
1415
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1416 # SONOS nFET devices must be in cell with abutment box
1417 templayer abutment_box
1418 boundary
1419
1420 templayer bbox_missing nsonos
1421 and-not abutment_box
1422
1423 # Make sure nwell covers varactor poly
1424 templayer var_poly_no_nwell
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]1425 bloat-all varactor,mvvaractor *poly
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1426 grow 150
1427 and-not nwell
1428
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1429 # Define MiM cap bottom plate for spacing rule
1430 templayer mim_bottom
1431 bloat-all *mimcap *metal3
1432
1433 # Define MiM2 cap bottom plate for spacing rule
1434 templayer mim2_bottom
1435 bloat-all *mimcap2 *metal4
1436
1437 # Note that metal fill is performed by the foundry and so is not
1438 # an option for a cifoutput style.
1439
1440 # Check latchup rule (15um minimum from tap LICON center to any
1441 # non-tap diffusion. Note that to count as a tap, the diffusion
1442 # must be contacted to LI
1443
1444 templayer ptap_reach psc,mvpsc
1445 and-not dnwell
1446 # grow total is 15um. grow in 0.84um increments to ensure that
1447 # no nwell ring is crossed
1448 grow 840
1449 and-not nwell,dnwell
1450 grow 840
1451 and-not nwell,dnwell
1452 grow 840
1453 and-not nwell,dnwell
1454 grow 840
1455 and-not nwell,dnwell
1456 grow 840
1457 and-not nwell,dnwell
1458 grow 840
1459 and-not nwell,dnwell
1460 grow 840
1461 and-not nwell,dnwell
1462 grow 840
1463 and-not nwell,dnwell
1464 grow 840
1465 and-not nwell,dnwell
1466 grow 840
1467 and-not nwell,dnwell
1468 grow 840
1469 and-not nwell,dnwell
1470 grow 840
1471 and-not nwell,dnwell
1472 grow 840
1473 and-not nwell,dnwell
1474 grow 840
1475 and-not nwell,dnwell
1476 grow 840
1477 and-not nwell,dnwell
1478 grow 840
1479 and-not nwell,dnwell
1480 grow 840
1481 and-not nwell,dnwell
1482 grow 635
1483 and-not nwell,dnwell
1484
1485 templayer ptap_missing *ndiff,*mvndiff
1486 and-not dnwell
1487 and-not ptap_reach
1488
1489 templayer ntap_reach nsc,mvnsc
1490 # grow total is 15um. grow in 1.27um increments to ensure that
1491 # no nwell ring is crossed. There is no difference between
1492 # ntaps in and out of deep nwell.
1493 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1494 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1495 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1496 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1497 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1498 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1499 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1500 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1501 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1502 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1503 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1504 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1505 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1506 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1507 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1508 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1509 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1510 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1511 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1512 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1513 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1514 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1515 grow 945
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1516 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1517
1518 templayer ntap_missing *pdiff,*mvpdiff
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1519 and-not pwell_in_dnwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1520 and-not ntap_reach
1521
1522 templayer dptap_reach psc,mvpsc
1523 and dnwell
1524 grow 840
1525 and-not nwell
1526 and dnwell
1527 grow 840
1528 and-not nwell
1529 and dnwell
1530 grow 840
1531 and-not nwell
1532 and dnwell
1533 grow 840
1534 and-not nwell
1535 and dnwell
1536 grow 840
1537 and-not nwell
1538 and dnwell
1539 grow 840
1540 and-not nwell
1541 and dnwell
1542 grow 840
1543 and-not nwell
1544 and dnwell
1545 grow 840
1546 and-not nwell
1547 and dnwell
1548 grow 840
1549 and-not nwell
1550 and dnwell
1551 grow 840
1552 and-not nwell
1553 and dnwell
1554 grow 840
1555 and-not nwell
1556 and dnwell
1557 grow 840
1558 and-not nwell
1559 and dnwell
1560 grow 840
1561 and-not nwell
1562 and dnwell
1563 grow 840
1564 and-not nwell
1565 and dnwell
1566 grow 840
1567 and-not nwell
1568 and dnwell
1569 grow 840
1570 and-not nwell
1571 and dnwell
1572 grow 840
1573 and-not nwell
1574 and dnwell
1575 grow 635
1576 and-not nwell
1577 and dnwell
1578
1579 templayer dptap_missing *ndiff,*mvndiff
1580 and dnwell
1581 and-not dptap_reach
1582
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1583 templayer pdiff_crosses_dnwell dnwell
1584 grow 20
1585 and-not dnwell
1586 and allpdifflv,allpdiffmv
1587
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1588 # MV nwell must be 2um from any other nwell
1589 templayer mvnwell
1590 bloat-all alldiffmv nwell
1591 grow-min 840
1592 bridge 700 600
1593
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1594 # Simple spacing checks to lvnwell must use CIF-DRC rule
1595 templayer allmvdiffnowell *mvndiff,*mvpsd
1596
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1597 templayer lvnwell nwell
1598 and-not mvnwell
1599
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1600 templayer nwell_with_tap
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1601 bloat-all nsc,mvnsc nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1602
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1603 templayer nwell_missing_tap nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1604 and-not nwell_with_tap
1605
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1606 templayer tap_with_licon
1607 bloat-all psc,mvpsc psd,mvpsd
1608 bloat-all nsc,mvnsc nsd,mvnsd
1609
1610 templayer tap_missing_licon psd,nsd,mvpsd,mvnsd
1611 and-not tap_with_licon
1612
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1613 # Make sure varactor nwell contains no P diffusion
1614 templayer pdiff_in_varactor_well
1615 bloat-all varactor,mvvaractor nwell
1616 and allpactive
1617
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1618 # HVNTM spacing requires recreating HVNTM
1619 templayer hvntm_block *mvpsd
1620 grow 185
1621
1622 templayer hvntm_generate
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]1623 bloat-all mvnfet,mvnfetesd,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1624 bloat-all mvvaractor *mvnsd
1625 and-not hvntm_block
1626 grow 185
1627 grow 345
1628 shrink 345
1629 and-not hvntm_block
1630
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1631 templayer m1_small_hole allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1632 close 140000
1633
1634 templayer m1_hole_empty m1_small_hole
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1635 and-not allm1,obsm1,obsmcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1636
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1637 templayer m2_small_hole allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1638 close 140000
1639
1640 templayer m2_hole_empty m2_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1641 and-not allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1642
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1643 templayer m1_huge allm1
1644 shrink 1500
1645 grow 1500
1646
1647 templayer m1_large_halo m1_huge
1648 grow 280
1649 and-not m1_huge
1650 and allm1
1651
1652 templayer m2_huge allm2
1653 shrink 1500
1654 grow 1500
1655
1656 templayer m2_large_halo m2_huge
1657 grow 280
1658 and-not m2_huge
1659 and allm2
1660
1661 templayer m3_huge allm3
1662 shrink 1500
1663 grow 1500
1664
1665 templayer m3_large_halo m3_huge
1666 grow 400
1667 and-not m3_huge
1668 and allm3
1669
1670 templayer m4_huge allm4
1671 shrink 1500
1672 grow 1500
1673
1674 templayer m4_large_halo m4_huge
1675 grow 400
1676 and-not m4_huge
1677 and allm4
1678
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1679#ifdef EXPERIMENTAL
1680#----------------------------------------------------------------
1681style paint
1682#----------------------------------------------------------------
1683# NOTE: This style is used for database manipulations only via
1684# the "cif paint" command.
1685#----------------------------------------------------------------
1686
1687 scalefactor 10 nanometers
1688
1689 templayer m1grow *m1
1690 grow 290
1691
1692 # layer listrap: Use the following set of commands to strap local
1693 # interconnect wires with metal1 (inside the cursor box) to satisfy
1694 # the maximum aspect ratio rule for local interconnect:
1695 #
1696 # tech unlock *
1697 # cif ostyle paint
1698 # cif paint m1strap comment
1699 # cif paint m1strap m1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]1700 # cif paint listrap viali
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1701 # erase comment
1702
1703 templayer m1strap *li
1704 and-not m1grow
1705 grow 30
1706
1707 templayer listrap comment
1708 slots 30 170 170 60
1709
1710#endif (EXPERIMENTAL)
1711
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1712#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1713style wafflefill variants (),(tiled)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1714#----------------------------------------------------------------
1715# Style used by scripts for automatically generating fill layers
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1716# NOTE: Be sure to generate output on flattened layout.
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1717#----------------------------------------------------------------
1718 scalefactor 10 nanometers
1719 options calma-permissive-labels
1720 gridlimit 5
1721
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1722#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1723# Generate and retain a layer representing the bounding box.
1724#
1725# For variant ():
1726# The bounding box is the full extent of geometry on the top level
1727# cell.
1728#
1729# For variant (tiled):
1730# Use with a script that breaks layout into flattened tiles and runs
1731# fill individually on each. The tiles should be larger than the
1732# step size, and each should draw a layer "comment" the size of the
1733# step box.
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1734#----------------------------------------------------------------
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1735
1736 variants ()
1737 templayer topbox
1738 bbox top
1739
1740 variants (tiled)
1741 templayer topbox comment
1742 # Each tile imposes the full keepout distance rule of
1743 # 3um on all sides.
1744 shrink 1500
1745
1746 variants *
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1747
1748#----------------------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1749# Generate guard-band around nwells to keep FOM from crossing
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1750# Spacing from LV nwell = Diff/Tap 9 = 0.34um
1751# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1752# Enclosure by nwell = Diff/Tap 8 = 0.18um
1753#----------------------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1754
1755 templayer mvnwell
1756 bloat-all alldiffmv nwell
1757
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1758 templayer lvnwell allnwell
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1759 and-not mvnwell
1760
1761 templayer well_shrink mvnwell
1762 shrink 250
1763 or lvnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1764 shrink 180
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1765 templayer well_guardband allnwell
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1766 grow 340
1767 and-not well_shrink
1768
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1769#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1770# Diffusion and poly keep-out areas
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1771#---------------------------------------------------
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1772 templayer obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1773 or rpw,pnp,npn
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1774 grow 500
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1775 or well_guardband
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1776
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]1777 templayer obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]1778 or rpw,pnp,npn
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1779 grow 1000
1780
1781#---------------------------------------------------
1782# FOM and POLY fill
1783#---------------------------------------------------
1784 templayer fomfill_pass1 topbox
1785 slots 0 4080 1320 0 4080 1320 1360 0
1786 and-not obstruct_fom
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1787 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1788 shrink 2035
1789 grow 2035
1790
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1791#---------------------------------------------------
1792
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1793 templayer obstruct_poly_pass1 fomfill_pass1
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1794 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1795 or obstruct_poly
1796 templayer polyfill_pass1 topbox
1797 slots 0 720 360 0 720 360 240 0
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1798 and-not obstruct_poly_pass1
1799 and topbox
1800 shrink 355
1801 grow 355
1802
1803#---------------------------------------------------
1804
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1805 templayer obstruct_fom_pass2 fomfill_pass1
1806 grow 1290
1807 or polyfill_pass1
1808 grow 300
1809 or obstruct_fom
1810 templayer fomfill_pass2 topbox
1811 slots 0 2500 1320 0 2500 1320 1360 0
1812 and-not obstruct_fom_pass2
1813 and topbox
1814 shrink 1245
1815 grow 1245
1816
1817#---------------------------------------------------
1818
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1819 templayer obstruct_poly_coarse polyfill_pass1
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1820 grow 60
1821 or fomfill_pass1,fomfill_pass2
1822 grow 300
1823 or obstruct_poly
1824 templayer polyfill_coarse topbox
1825 slots 0 720 360 0 720 360 240 120
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1826 and-not obstruct_poly_coarse
1827 and topbox
1828 shrink 355
1829 grow 355
1830
1831#---------------------------------------------------
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1832 templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1833 grow 60
1834 or fomfill_pass1,fomfill_pass2
1835 grow 300
1836 or obstruct_poly
1837 templayer polyfill_medium topbox
1838 slots 0 540 360 0 540 360 240 100
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1839 and-not obstruct_poly_medium
1840 and topbox
1841 shrink 265
1842 grow 265
1843
1844#---------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1845 templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1846 grow 60
1847 or fomfill_pass1,fomfill_pass2
1848 grow 300
1849 or obstruct_poly
1850 templayer polyfill_fine topbox
1851 slots 0 480 360 0 480 360 240 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1852 and-not obstruct_poly_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1853 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1854 shrink 235
1855 grow 235
1856
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1857#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1858
1859 templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
1860 grow 1290
1861 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1862 grow 300
1863 or obstruct_fom
1864 templayer fomfill_coarse topbox
1865 slots 0 1500 1320 0 1500 1320 1360 0
1866 and-not obstruct_fom_coarse
1867 and topbox
1868 shrink 745
1869 grow 745
1870
1871#---------------------------------------------------
1872
1873 templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
1874 grow 1290
1875 or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
1876 grow 300
1877 or obstruct_fom
1878 templayer fomfill_fine topbox
1879 slots 0 500 400 0 500 400 160 0
1880 and-not obstruct_fom_fine
1881 and topbox
1882 shrink 245
1883 grow 245
1884
1885#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1886 layer FOMFILL fomfill_pass1
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1887 or fomfill_pass2
1888 or fomfill_coarse
1889 or fomfill_fine
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1890 calma 65 28
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1891
1892 layer POLYFILL polyfill_pass1
1893 or polyfill_coarse
1894 or polyfill_medium
1895 or polyfill_fine
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1896 calma 66 28
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1897
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1898#---------------------------------------------------
1899# MET1 fill
1900#---------------------------------------------------
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1901
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1902 templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1903 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1904 templayer met1fill_coarse topbox
1905 slots 0 2000 200 0 2000 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1906 and-not obstruct_m1_coarse
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1907 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1908 shrink 995
1909 grow 995
1910
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1911 templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1912 grow 2800
1913 or met1fill_coarse
1914 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1915 templayer met1fill_medium topbox
1916 slots 0 1000 200 0 1000 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1917 and-not obstruct_m1_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1918 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1919 shrink 495
1920 grow 495
1921
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1922 templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1923 grow 300
1924 or met1fill_coarse,met1fill_medium
1925 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1926 templayer met1fill_fine topbox
1927 slots 0 580 200 0 580 200 700 0
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1928 and-not obstruct_m1_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1929 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1930 shrink 285
1931 grow 285
1932
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1933 templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1934 grow 100
1935 or met1fill_coarse,met1fill_medium,met1fill_fine
1936 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1937 templayer met1fill_veryfine topbox
1938 slots 0 300 200 0 300 200 100 50
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1939 and-not obstruct_m1_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1940 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1941 shrink 145
1942 grow 145
1943
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1944 layer MET1FILL met1fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1945 or met1fill_medium
1946 or met1fill_fine
1947 or met1fill_veryfine
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1948 calma 68 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1949
1950#---------------------------------------------------
1951# MET2 fill
1952#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1953 templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1954 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1955 templayer met2fill_coarse topbox
1956 slots 0 2000 200 0 2000 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1957 and-not obstruct_m2
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1958 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1959 shrink 995
1960 grow 995
1961
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1962 templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1963 grow 2800
1964 or met2fill_coarse
1965 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1966 templayer met2fill_medium topbox
1967 slots 0 1000 200 0 1000 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1968 and-not obstruct_m2_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1969 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1970 shrink 495
1971 grow 495
1972
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1973 templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1974 grow 300
1975 or met2fill_coarse,met2fill_medium
1976 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1977 templayer met2fill_fine topbox
1978 slots 0 580 200 0 580 200 700 350
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1979 and-not obstruct_m2_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1980 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1981 shrink 285
1982 grow 285
1983
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]1984 templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1985 grow 100
1986 or met2fill_coarse,met2fill_medium,met2fill_fine
1987 grow 200
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]1988 templayer met2fill_veryfine topbox
1989 slots 0 300 200 0 300 200 100 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1990 and-not obstruct_m2_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]1991 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1992 shrink 145
1993 grow 145
1994
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1995 layer MET2FILL met2fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1996 or met2fill_medium
1997 or met2fill_fine
1998 or met2fill_veryfine
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]1999 calma 69 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2000
2001#---------------------------------------------------
2002# MET3 fill
2003#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2004 templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2005 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2006 templayer met3fill_coarse topbox
2007 slots 0 2000 300 0 2000 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2008 and-not obstruct_m3
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2009 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2010 shrink 995
2011 grow 995
2012
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2013 templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2014 grow 2700
2015 or met3fill_coarse
2016 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2017 templayer met3fill_medium topbox
2018 slots 0 1000 300 0 1000 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2019 and-not obstruct_m3_medium
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2020 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2021 shrink 495
2022 grow 495
2023
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2024 templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2025 grow 200
2026 or met3fill_coarse,met3fill_medium
2027 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2028 templayer met3fill_fine topbox
2029 slots 0 580 300 0 580 300 700 700
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2030 and-not obstruct_m3_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2031 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2032 shrink 285
2033 grow 285
2034
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2035 templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2036 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2037 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2038 or met3fill_coarse,met3fill_medium,met3fill_fine
2039 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2040 templayer met3fill_veryfine topbox
2041 slots 0 400 300 0 400 300 150 200
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2042 and-not obstruct_m3_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2043 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2044 shrink 195
2045 grow 195
2046
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2047 layer MET3FILL met3fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2048 or met3fill_medium
2049 or met3fill_fine
2050 or met3fill_veryfine
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2051 calma 70 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2052
2053#ifdef METAL5
2054#---------------------------------------------------
2055# MET4 fill
2056#---------------------------------------------------
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2057 templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2058 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2059 templayer met4fill_coarse topbox
2060 slots 0 2000 300 0 2000 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2061 and-not obstruct_m4
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2062 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2063 shrink 995
2064 grow 995
2065
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2066 templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2067 grow 2700
2068 or met4fill_coarse
2069 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2070 templayer met4fill_medium topbox
2071 slots 0 1000 300 0 1000 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2072 and-not obstruct_m4_medium
Tim Edwardsb71e5f82020-12-29 16:15:26 -0500[diff] [blame]2073 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2074 shrink 495
2075 grow 495
2076
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2077 templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2078 grow 200
2079 or met4fill_coarse,met4fill_medium
2080 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2081 templayer met4fill_fine topbox
2082 slots 0 580 300 0 580 300 700 1050
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2083 and-not obstruct_m4_fine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2084 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2085 shrink 285
2086 grow 285
2087
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]2088 templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2089 # Note: Adding 0.1 to waffle rule to clear wide spacing rule
2090 grow 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2091 or met4fill_coarse,met4fill_medium,met4fill_fine
2092 grow 300
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2093 templayer met4fill_veryfine topbox
2094 slots 0 400 300 0 400 300 150 300
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2095 and-not obstruct_m4_veryfine
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2096 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2097 shrink 195
2098 grow 195
2099
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2100 layer MET4FILL met4fill_coarse
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2101 or met4fill_medium
2102 or met4fill_fine
2103 or met4fill_veryfine
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2104 calma 71 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2105
2106#---------------------------------------------------
2107# MET5 fill
2108#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2109 templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
2110 grow 3000
Tim Edwardsdddb6fa2020-12-08 11:56:35 -0500[diff] [blame]2111 templayer met5fill_gen topbox
2112 slots 0 3000 1600 0 3000 1600 1000 100
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2113 and-not obstruct_m5
Tim Edwards9ad30452020-12-07 17:03:03 -0500[diff] [blame]2114 and topbox
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2115 shrink 1495
2116 grow 1495
2117
Tim Edwards045bf8e2020-12-16 17:35:57 -0500[diff] [blame]2118 layer MET5FILL met5fill_gen
2119 calma 72 28
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]2120#endif (METAL5)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2121
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2122end
2123
2124#-----------------------------------------------------------------------
2125cifinput
2126#-----------------------------------------------------------------------
2127# NOTE: All values in this section MUST be multiples of 25
2128# or else magic will scale below the allowed layout grid size
2129#-----------------------------------------------------------------------
2130
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2131style sky130 variants (),(vendor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2132 scalefactor 10 nanometers
2133 gridlimit 5
2134
2135 options ignore-unknown-layer-labels no-reconnect-labels
2136
2137#ifndef MIM
2138 ignore CAPM
2139 ignore CAPM2
2140#endif (!MIM)
2141#ifndef METAL5
2142 ignore MET4,VIA3
2143 ignore MET5,VIA4
2144#endif
2145 ignore NPC
2146 ignore SEALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2147 ignore CAPID
2148 ignore LDNTM
2149 ignore HVNTM
2150 ignore POLYMOD
2151 ignore LOWTAPDENSITY
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]2152 ignore FILLOBSPOLY
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2153
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2154 layer pnp NWELL,WELLTXT,WELLPIN
2155 and PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2156 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2157 variants (vendor)
2158 labels WELLTXT port
2159 variants ()
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2160 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2161 variants *
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2162 labels WELLPIN port
2163
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2164 layer nwell NWELL,WELLTXT,WELLPIN
2165 and-not PNPID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2166 labels NWELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2167 variants (vendor)
2168 labels WELLTXT port
2169 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2170 labels WELLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2171 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2172 labels WELLPIN port
2173
2174 layer pwell SUBTXT,SUBPIN
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2175 variants (vendor)
2176 labels SUBTXT port
2177 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2178 labels SUBTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2179 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2180 labels SUBPIN port
2181
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]2182 # Always draw pwell under p-tap
2183 layer pwell TAP
2184 and-not NWELL
2185
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2186 layer dnwell DNWELL
2187 labels DNWELL
2188
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2189 layer npn DNWELL
2190 and-not NWELL
2191 and NPNID
2192
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2193 layer rpw PWRES
2194 and DNWELL
2195 labels PWRES
2196
2197 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
2198 and-not POLY
2199 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2200 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2201 and-not DIODE
2202 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2203 and-not HVI
2204 and NSDM
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2205 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2206 copyup ndifcheck
2207 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2208 variants (vendor)
2209 labels DIFFTXT port
2210 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2211 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2212 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2213 labels DIFFPIN port
2214 labels TAPPIN port
2215
2216 layer ndiff ndiffarea
2217
2218 # Copy ndiff areas up for contact checks
2219 templayer xndifcheck ndifcheck
2220 copyup ndifcheck
2221
2222 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
2223 and-not POLY
2224 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2225 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2226 and-not DIODE
2227 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2228 and HVI
2229 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2230 copyup ndifcheck
2231 labels DIFF
2232 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2233 variants (vendor)
2234 labels DIFFTXT port
2235 variants ()
2236 labels DIFFTXT text
2237 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2238 labels DIFFPIN port
2239
2240 layer mvndiff mvndiffarea
2241
2242 # Copy ndiff areas up for contact checks
2243 templayer mvxndifcheck mvndifcheck
2244 copyup mvndifcheck
2245
2246 layer ndiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2247 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2248 and DIODE
2249 and-not NWELL
2250 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2251 and-not PSDM
2252 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2253 and-not LVTN
2254 labels DIFF
2255
2256 layer ndiodelvt DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2257 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2258 and DIODE
2259 and-not NWELL
2260 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2261 and-not PSDM
2262 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2263 and LVTN
2264 labels DIFF
2265
2266 templayer ndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2267 and NSDM
2268 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2269 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2270 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2271
2272 layer ndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2273 and NSDM
2274 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2275 labels DIFF
2276
2277 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
2278 and-not POLY
2279 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2280 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2281 and-not DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2282 and-not HVI
2283 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2284 copyup pdifcheck
2285 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2286 variants (vendor)
2287 labels DIFFTXT port
2288 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2289 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2290 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2291 labels DIFFPIN port
2292
2293 layer pdiff pdiffarea
2294
2295 layer mvndiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2296 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2297 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2298 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2299 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2300 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2301 and-not LVTN
2302 labels DIFF
2303
2304 layer nndiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2305 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2306 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2307 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2308 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2309 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2310 and LVTN
2311 labels DIFF
2312
2313 templayer mvndiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2314 and NSDM
2315 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2316 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2317 copyup DIODE,NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2318
2319 layer mvndiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2320 and NSDM
2321 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2322 labels DIFF
2323
2324 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
2325 and-not POLY
2326 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2327 and-not NSDM
2328 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2329 and-not DIODE
2330 and-not DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2331 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2332 copyup mvpdifcheck
2333 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2334 variants (vendor)
2335 labels DIFFTXT port
2336 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2337 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2338 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2339 labels DIFFPIN port
2340
2341 layer mvpdiff mvpdiffarea
2342
2343 # Copy pdiff areas up for contact checks
2344 templayer xpdifcheck pdifcheck
2345 copyup pdifcheck
2346
2347 layer pdiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2348 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2349 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2350 and-not NSDM
2351 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2352 and-not LVTN
2353 and-not HVTP
2354 and DIODE
2355 labels DIFF
2356
2357 layer pdiodelvt DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2358 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2359 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2360 and-not NSDM
2361 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2362 and LVTN
2363 and-not HVTP
2364 and DIODE
2365 labels DIFF
2366
2367 layer pdiodehvt DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2368 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2369 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2370 and-not NSDM
2371 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2372 and-not LVTN
2373 and HVTP
2374 and DIODE
2375 labels DIFF
2376
2377 templayer pdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2378 and PSDM
2379 and-not HVI
2380 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2381
2382 # Define pfet areas as known pdiff, regardless of the presence of a well.
2383
2384 templayer pfetarea DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2385 and-not NSDM
2386 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2387 and POLY
2388
2389 layer pfet pfetarea
2390 and-not LVTN
2391 and-not HVTP
2392 and-not STDCELL
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2393 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2394 labels DIFF
2395
2396 layer scpfet pfetarea
2397 and-not LVTN
2398 and-not HVTP
2399 and STDCELL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2400 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2401 labels DIFF
2402
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2403 layer scpfethvt pfetarea
2404 and-not LVTN
2405 and HVTP
2406 and STDCELL
2407 labels DIFF
2408
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2409 layer ppu pfetarea
2410 and-not LVTN
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2411 and HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2412 and COREID
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2413 # Shrink-grow operation eliminates the smaller ppass device
2414 shrink 70
2415 grow 70
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2416 labels DIFF
2417
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2418 layer pfetlvt pfetarea
2419 and LVTN
2420 labels DIFF
2421
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]2422 layer pfetmvt pfetarea
2423 and HVTR
2424 labels DIFF
2425
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2426 layer pfethvt pfetarea
2427 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2428 and-not STDCELL
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2429 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2430 labels DIFF
2431
2432 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
2433 layer nwell pfetarea
2434 grow 180
2435
2436 # Copy mvpdiff areas up for contact checks
2437 templayer mvxpdifcheck mvpdifcheck
2438 copyup mvpdifcheck
2439
2440 layer mvpdiode DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2441 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2442 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2443 and-not NSDM
2444 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2445 and DIODE
2446 labels DIFF
2447
2448 templayer mvpdiodearea DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2449 and PSDM
2450 and HVI
2451 copyup DIODE,PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2452
2453 # Define pfet areas as known pdiff,
2454 # regardless of the presence of a
2455 # well.
2456
2457 templayer mvpfetarea DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2458 and-not NSDM
2459 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2460 and POLY
2461
2462 layer mvpfet mvpfetarea
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2463 and-not ESDID
2464 labels DIFF
2465
2466 layer mvpfetesd mvpfetarea
2467 and ESDID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2468 labels DIFF
2469
2470 layer pdiff DIFF,DIFFTXT,DIFFPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2471 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2472 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2473 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2474 and-not DIODE
2475 and-not DIFFRES
2476 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2477 variants (vendor)
2478 labels DIFFTXT port
2479 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2480 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2481 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2482 labels DIFFPIN port
2483
2484 layer pdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2485 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2486 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2487 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2488 labels DIFF
2489
2490 layer nfet DIFF
2491 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2492 and-not PSDM
2493 and NSDM
2494 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2495 and-not LVTN
2496 and-not SONOS
2497 and-not STDCELL
Tim Edwardsdf812912020-12-11 21:40:14 -0500[diff] [blame]2498 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2499 labels DIFF
2500
2501 layer scnfet DIFF
2502 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2503 and-not PSDM
2504 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2505 and-not NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2506 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2507 and-not LVTN
2508 and-not SONOS
2509 and STDCELL
2510 labels DIFF
2511
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2512 layer npass DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2513 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2514 and-not PSDM
2515 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2516 and-not NWELL
2517 and COREID
Tim Edwardsdf812912020-12-11 21:40:14 -0500[diff] [blame]2518 # Shrink-grow operation eliminates the smaller npass device
2519 shrink 70
2520 grow 70
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2521 labels DIFF
2522
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2523 layer npd DIFF
2524 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2525 and-not PSDM
2526 and NSDM
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2527 and-not NWELL
2528 and COREID
2529 # Shrink-grow operation eliminates the smaller npass device
2530 shrink 70
2531 grow 70
2532 labels DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2533
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2534 layer nfetlvt DIFF
2535 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2536 and-not PSDM
2537 and NSDM
2538 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2539 and LVTN
2540 and-not SONOS
2541 labels DIFF
2542
2543 layer nsonos DIFF
2544 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2545 and-not PSDM
2546 and NSDM
2547 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2548 and LVTN
2549 and SONOS
2550 labels DIFF
2551
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2552 templayer nsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2553 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2554 and NWELL
2555 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2556 and-not PSDM
2557 and-not HVI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2558 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2559 copyup nsubcheck
2560
2561 layer nsd nsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2562 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2563
2564 layer nsd TAP,TAPPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2565 and NSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2566 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2567 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2568 labels TAP
2569 labels TAPPIN port
2570
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2571 layer corenvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2572 and NSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2573 and POLY
2574 and COREID
2575 labels TAP
2576
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2577 templayer nsdexpand nsdarea
2578 grow 500
2579
2580 # Copy nsub areas up for contact checks
2581 templayer xnsubcheck nsubcheck
2582 copyup nsubcheck
2583
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2584 templayer psdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2585 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2586 and-not NWELL
2587 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2588 and-not NSDM
2589 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2590 and-not pfetexpand
2591 copyup psubcheck
2592
2593 layer psd psdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2594 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2595
2596 layer psd TAP,TAPPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2597 and PSDM
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2598 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2599 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2600 labels TAP
2601 labels TAPPIN port
2602
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2603 layer corepvar TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2604 and PSDM
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2605 and POLY
2606 and COREID
2607 labels TAP
2608
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2609 templayer psdexpand psdarea
2610 grow 500
2611
2612 layer mvpdiff DIFF,DIFFTXT,DIFFPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2613 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2614 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2615 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2616 and mvpfetexpand
2617 labels DIFF
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2618 variants (vendor)
2619 labels DIFFTXT port
2620 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2621 labels DIFFTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2622 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2623 labels DIFFPIN port
2624
2625 layer mvpdiffres DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2626 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2627 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2628 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2629 and-not mvrdpioedge
2630 labels DIFF
2631
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2632 templayer mvnfetarea DIFF
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2633 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2634 and-not PSDM
2635 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2636 and-not LVTN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2637 and HVI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2638 grow 350
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2639
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2640 templayer mvnnfetarea DIFF,TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2641 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2642 and-not PSDM
2643 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2644 and LVTN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2645 and HVI
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2646 and-not mvnfetarea
2647
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2648 layer mvnfetesd DIFF
2649 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2650 and-not PSDM
2651 and NSDM
2652 and HVI
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2653 and ESDID
2654 and-not mvnnfetarea
2655 labels DIFF
2656
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2657 layer mvnfet DIFF
2658 and POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2659 and-not PSDM
2660 and NSDM
2661 and HVI
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]2662 and-not ESDID
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2663 and-not mvnnfetarea
2664 labels DIFF
2665
2666 layer mvnnfet mvnnfetarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2667 labels DIFF
2668
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2669 templayer mvnsdarea TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2670 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2671 and NWELL
2672 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2673 and-not PSDM
2674 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2675 copyup mvnsubcheck
2676
2677 layer mvnsd mvnsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2678 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2679
2680 layer mvnsd TAP,TAPPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2681 and NSDM
2682 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2683 labels TAP
2684 labels TAPPIN port
2685
2686 templayer mvnsdexpand mvnsdarea
2687 grow 500
2688
2689 # Copy nsub areas up for contact checks
2690 templayer mvxnsubcheck mvnsubcheck
2691 copyup mvnsubcheck
2692
2693 templayer mvpsdarea DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2694 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2695 and-not NWELL
2696 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2697 and-not NSDM
2698 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2699 and-not mvpfetexpand
2700 copyup mvpsubcheck
2701
2702 layer mvpsd mvpsdarea
2703 labels DIFF
2704
2705 layer mvpsd TAP,TAPPIN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2706 and PSDM
2707 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2708 labels TAP
2709 labels TAPPIN port
2710
2711 templayer mvpsdexpand mvpsdarea
2712 grow 500
2713
2714 # Copy psub areas up for contact checks
2715 templayer xpsubcheck psubcheck
2716 copyup psubcheck
2717
2718 templayer mvxpsubcheck mvpsubcheck
2719 copyup mvpsubcheck
2720
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2721 layer psd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2722 and-not PSDM
2723 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2724 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2725 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2726 and-not pfetexpand
2727 and psdexpand
2728
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2729 layer nsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2730 and-not PSDM
2731 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2732 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2733 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2734 and nsdexpand
2735
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2736 layer mvpsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2737 and-not PSDM
2738 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2739 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2740 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2741 and-not mvpfetexpand
2742 and mvpsdexpand
2743
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2744 layer mvnsd TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2745 and-not PSDM
2746 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2747 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2748 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2749 and mvnsdexpand
2750
2751 templayer hresarea POLY
2752 and RPM
2753 grow 3000
2754
2755 templayer uresarea POLY
2756 and URPM
2757 grow 3000
2758
2759 templayer diffresarea DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2760 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2761 grow 3000
2762
2763 templayer mvdiffresarea DIFFRES
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2764 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2765 grow 3000
2766
2767 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
2768
2769 layer pfet POLY
2770 and DIFF
2771 and diffresarea
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2772 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2773 and-not STDCELL
2774
2775 layer scpfet POLY
2776 and DIFF
2777 and diffresarea
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2778 and-not HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2779 and-not NSDM
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2780 and STDCELL
2781
2782 layer scpfethvt POLY
2783 and DIFF
2784 and diffresarea
2785 and HVTP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2786 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2787 and STDCELL
2788
2789 templayer xpolyterm RPM,URPM
2790 and POLY
2791 and-not POLYRES
2792 # add back the 0.06um contact surround in the direction of the resistor
2793 grow 60
2794 and POLY
2795
2796 layer xpc xpolyterm
2797
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]2798 templayer polyarea POLY,POLYTXT,POLYPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2799 and-not POLYRES
2800 and-not POLYSHORT
2801 and-not DIFF
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]2802 and-not TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2803 and-not RPM
2804 and-not URPM
2805 copyup polycheck
2806
Tim Edwardscc521e82020-12-11 13:02:41 -0500[diff] [blame]2807 layer poly polyarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2808 labels POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2809 variants (vendor)
2810 labels POLYTXT port
2811 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2812 labels POLYTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]2813 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2814 labels POLYPIN port
2815
2816 # Copy (non-resistor) poly areas up for contact checks
2817 templayer xpolycheck polycheck
2818 copyup polycheck
2819
2820 layer mrp1 POLY
2821 and POLYRES
2822 and-not RPM
2823 and-not URPM
2824 labels POLY
2825
2826 layer rmp POLY
2827 and POLYSHORT
2828 labels POLY
2829
2830 layer xhrpoly POLY
2831 and POLYRES
2832 and RPM
2833 and-not URPM
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2834 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2835 and NPC
2836 and-not xpolyterm
2837 labels POLY
2838
2839 layer uhrpoly POLY
2840 and POLYRES
2841 and URPM
2842 and-not RPM
2843 and NPC
2844 and-not xpolyterm
2845 labels POLY
2846
2847 templayer ndcbase CONT
2848 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2849 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2850 and-not NWELL
2851 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2852 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2853
2854 layer ndc ndcbase
2855 grow 85
2856 shrink 85
2857 shrink 85
2858 grow 85
2859 or ndcbase
2860 labels CONT
2861
2862 templayer nscbase CONT
2863 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2864 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2865 and NWELL
2866 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2867 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2868
2869 layer nsc nscbase
2870 grow 85
2871 shrink 85
2872 shrink 85
2873 grow 85
2874 or nscbase
2875 labels CONT
2876
2877 templayer pdcbase CONT
2878 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2879 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2880 and NWELL
2881 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2882 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2883
2884 layer pdc pdcbase
2885 grow 85
2886 shrink 85
2887 shrink 85
2888 grow 85
2889 or pdcbase
2890 labels CONT
2891
2892 templayer pdcnowell CONT
2893 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2894 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2895 and pfetexpand
2896 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2897 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2898
2899 layer pdc pdcnowell
2900 grow 85
2901 shrink 85
2902 shrink 85
2903 grow 85
2904 or pdcnowell
2905 labels CONT
2906
2907 templayer pscbase CONT
2908 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2909 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2910 and-not NWELL
2911 and-not pfetexpand
2912 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2913 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2914
2915 layer psc pscbase
2916 grow 85
2917 shrink 85
2918 shrink 85
2919 grow 85
2920 or pscbase
2921 labels CONT
2922
2923 templayer pcbase CONT
2924 and POLY
2925 and-not DIFF
2926 and-not RPM,URPM
2927 and LI
2928
2929 layer pc pcbase
2930 grow 85
2931 shrink 85
2932 shrink 85
2933 grow 85
2934 or pcbase
2935 labels CONT
2936
2937 templayer ndicbase CONT
2938 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2939 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2940 and DIODE
2941 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2942 and-not PSDM
2943 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2944 and-not LVTN
2945
2946 layer ndic ndicbase
2947 grow 85
2948 shrink 85
2949 shrink 85
2950 grow 85
2951 or ndicbase
2952 labels CONT
2953
2954 templayer ndilvtcbase CONT
2955 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2956 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2957 and DIODE
2958 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2959 and-not PSDM
2960 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2961 and LVTN
2962
2963 layer ndilvtc ndilvtcbase
2964 grow 85
2965 shrink 85
2966 shrink 85
2967 grow 85
2968 or ndilvtcbase
2969 labels CONT
2970
2971 templayer pdicbase CONT
2972 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2973 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2974 and DIODE
2975 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2976 and-not NSDM
2977 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2978 and-not LVTN
2979 and-not HVTP
2980
2981 layer pdic pdicbase
2982 grow 85
2983 shrink 85
2984 shrink 85
2985 grow 85
2986 or pdicbase
2987 labels CONT
2988
2989 templayer pdilvtcbase CONT
2990 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2991 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2992 and DIODE
2993 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]2994 and-not NSDM
2995 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2996 and LVTN
2997 and-not HVTP
2998
2999 layer pdilvtc pdilvtcbase
3000 grow 85
3001 shrink 85
3002 shrink 85
3003 grow 85
3004 or pdilvtcbase
3005 labels CONT
3006
3007 templayer pdihvtcbase CONT
3008 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3009 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3010 and DIODE
3011 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3012 and-not NSDM
3013 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3014 and-not LVTN
3015 and HVTP
3016
3017 layer pdihvtc pdihvtcbase
3018 grow 85
3019 shrink 85
3020 shrink 85
3021 grow 85
3022 or pdihvtcbase
3023 labels CONT
3024
3025 templayer mvndcbase CONT
3026 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3027 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3028 and-not NWELL
3029 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3030 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3031
3032 layer mvndc mvndcbase
3033 grow 85
3034 shrink 85
3035 shrink 85
3036 grow 85
3037 or mvndcbase
3038 labels CONT
3039
3040 templayer mvnscbase CONT
3041 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3042 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3043 and NWELL
3044 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3045 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3046
3047 layer mvnsc mvnscbase
3048 grow 85
3049 shrink 85
3050 shrink 85
3051 grow 85
3052 or mvnscbase
3053 labels CONT
3054
3055 templayer mvpdcbase CONT
3056 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3057 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3058 and NWELL
3059 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3060 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3061
3062 layer mvpdc mvpdcbase
3063 grow 85
3064 shrink 85
3065 shrink 85
3066 grow 85
3067 or mvpdcbase
3068 labels CONT
3069
3070 templayer mvpdcnowell CONT
3071 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3072 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3073 and mvpfetexpand
3074 and MET1
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3075 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3076
3077 layer mvpdc mvpdcnowell
3078 grow 85
3079 shrink 85
3080 shrink 85
3081 grow 85
3082 or mvpdcnowell
3083 labels CONT
3084
3085 templayer mvpscbase CONT
3086 and DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3087 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3088 and-not NWELL
3089 and-not mvpfetexpand
3090 and LI
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3091 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3092
3093 layer mvpsc mvpscbase
3094 grow 85
3095 shrink 85
3096 shrink 85
3097 grow 85
3098 or mvpscbase
3099 labels CONT
3100
3101 templayer mvndicbase CONT
3102 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3103 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3104 and DIODE
3105 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3106 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3107 and-not LVTN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3108 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3109
3110 layer mvndic mvndicbase
3111 grow 85
3112 shrink 85
3113 shrink 85
3114 grow 85
3115 or mvndicbase
3116 labels CONT
3117
3118 templayer nndicbase CONT
3119 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3120 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3121 and DIODE
3122 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3123 and-not PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3124 and LVTN
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3125 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3126
3127 layer nndic nndicbase
3128 grow 85
3129 shrink 85
3130 shrink 85
3131 grow 85
3132 or nndicbase
3133 labels CONT
3134
3135 templayer mvpdicbase CONT
3136 and DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3137 and PSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3138 and DIODE
3139 and-not POLY
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3140 and-not NSDM
3141 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3142
3143 layer mvpdic mvpdicbase
3144 grow 85
3145 shrink 85
3146 shrink 85
3147 grow 85
3148 or mvpdicbase
3149 labels CONT
3150
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3151 layer fomfill FOMFILL
3152 labels FOMFILL
3153
3154 layer polyfill POLYFILL
3155 labels POLYFILL
3156
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3157 layer coreli LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3158 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3159 and COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3160 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3161 variants (vendor)
3162 labels LITXT port
3163 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3164 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3165 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3166 labels LIPIN port
3167
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3168 layer locali LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3169 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3170 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3171 labels LI
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3172 variants (vendor)
3173 labels LITXT port
3174 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3175 labels LITXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3176 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3177 labels LIPIN port
3178
3179 layer rli LI
3180 and LIRES,LISHORT
3181 labels LIRES,LISHORT
3182
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3183 layer mcon MCON
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3184 grow 95
3185 shrink 95
3186 shrink 85
3187 grow 85
3188 or MCON
3189 labels MCON
3190
3191 layer m1 MET1,MET1TXT,MET1PIN
3192 and-not MET1RES,MET1SHORT
3193 labels MET1
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3194 variants (vendor)
3195 labels MET1TXT port
3196 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3197 labels MET1TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3198 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3199 labels MET1PIN port
3200
3201 layer rm1 MET1
3202 and MET1RES,MET1SHORT
3203 labels MET1RES,MET1SHORT
3204
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3205 layer m1fill MET1FILL
3206 labels MET1FILL
3207
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3208#ifdef MIM
3209 layer mimcap MET3
3210 and CAPM
3211 labels CAPM
3212
3213 layer mimcc VIA3
3214 and CAPM
3215 grow 60
3216 grow 40
3217 shrink 40
3218 labels CAPM
3219
3220 layer mimcap2 MET4
3221 and CAPM2
3222 labels CAPM2
3223
3224 layer mim2cc VIA4
3225 and CAPM2
3226 grow 190
3227 grow 210
3228 shrink 210
3229 labels CAPM2
3230
3231#endif (MIM)
3232
3233 templayer m2cbase VIA1
3234 grow 55
3235
3236 layer m2c m2cbase
3237 grow 30
3238 shrink 30
3239 shrink 130
3240 grow 130
3241 or m2cbase
3242
3243 layer m2 MET2,MET2TXT,MET2PIN
3244 and-not MET2RES,MET2SHORT
3245 labels MET2
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3246 variants (vendor)
3247 labels MET2TXT port
3248 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3249 labels MET2TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3250 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3251 labels MET2PIN port
3252
3253 layer rm2 MET2
3254 and MET2RES,MET2SHORT
3255 labels MET2RES,MET2SHORT
3256
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3257 layer m2fill MET2FILL
3258 labels MET2FILL
3259
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3260 templayer m3cbase VIA2
3261 grow 40
3262
3263 layer m3c m3cbase
3264 grow 60
3265 shrink 60
3266 shrink 140
3267 grow 140
3268 or m3cbase
3269
3270 layer m3 MET3,MET3TXT,MET3PIN
3271 and-not MET3RES,MET3SHORT
3272#ifdef MIM
3273 and-not CAPM
3274#endif (MIM)
3275 labels MET3
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3276 variants (vendor)
3277 labels MET3TXT port
3278 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3279 labels MET3TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3280 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3281 labels MET3PIN port
3282
3283 layer rm3 MET3
3284 and MET3RES,MET3SHORT
3285 labels MET3RES,MET3SHORT
3286
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3287 layer m3fill MET3FILL
3288 labels MET3FILL
3289
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3290#ifdef (METAL5)
3291
3292 templayer via3base VIA3
3293#ifdef MIM
3294 and-not CAPM
3295#endif (MIM)
3296 grow 60
3297
3298 layer via3 via3base
3299 grow 40
3300 shrink 40
3301 shrink 160
3302 grow 160
3303 or via3base
3304
3305 layer m4 MET4,MET4TXT,MET4PIN
3306 and-not MET4RES,MET4SHORT
3307#ifdef MIM
3308 and-not CAPM2
3309#endif (MIM)
3310 labels MET4
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3311 variants (vendor)
3312 labels MET4TXT port
3313 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3314 labels MET4TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3315 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3316 labels MET4PIN port
3317
3318 layer rm4 MET4
3319 and MET4RES,MET4SHORT
3320 labels MET4RES,MET4SHORT
3321
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3322 layer m4fill MET4FILL
3323 labels MET4FILL
3324
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3325 layer m5 MET5,MET5TXT,MET5PIN
3326 and-not MET5RES,MET5SHORT
3327 labels MET5
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3328 variants (vendor)
3329 labels MET5TXT port
3330 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3331 labels MET5TXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3332 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3333 labels MET5PIN port
3334
3335 layer rm5 MET5
3336 and MET5RES,MET5SHORT
3337 labels MET5RES,MET5SHORT
3338
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3339 layer m5fill MET5FILL
3340 labels MET5FILL
3341
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3342 templayer via4base VIA4
3343#ifdef MIM
3344 and-not CAPM2
3345#endif (MIM)
3346 grow 190
3347
3348 layer via4 via4base
3349 grow 210
3350 shrink 210
3351 shrink 590
3352 grow 590
3353 or via4base
3354#endif (METAL5)
3355
3356#ifdef REDISTRIBUTION
3357 layer metrdl RDL,RDLTXT,RDLPIN
3358 labels RDL
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3359 variants (vendor)
3360 labels RDLTXT port
3361 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3362 labels RDLTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3363 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3364 labels RDLPIN port
3365#endif
3366
3367 # Find diffusion not covered in
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3368 # NSDM or PSDM and pull it into
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3369 # the next layer up
3370
3371 templayer gentrans DIFF
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3372 and-not PSDM
3373 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3374 and POLY
3375 copyup DIFF,POLY
3376
3377 templayer gendiff DIFF,TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3378 and-not PSDM
3379 and-not NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3380 and-not POLY
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3381 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3382 copyup DIFF
3383
3384 # Handle contacts found by copyup
3385
3386 templayer ndiccopy CONT
3387 and LI
3388 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3389 and NSDM
3390 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3391
3392 layer ndic ndiccopy
3393 grow 85
3394 shrink 85
3395 shrink 85
3396 grow 85
3397 or ndiccopy
3398 labels CONT
3399
3400 templayer mvndiccopy CONT
3401 and LI
3402 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3403 and NSDM
3404 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3405
3406 layer mvndic mvndiccopy
3407 grow 85
3408 shrink 85
3409 shrink 85
3410 grow 85
3411 or mvndiccopy
3412 labels CONT
3413
3414 templayer pdiccopy CONT
3415 and LI
3416 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3417 and PSDM
3418 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3419
3420 layer pdic pdiccopy
3421 grow 85
3422 shrink 85
3423 shrink 85
3424 grow 85
3425 or pdiccopy
3426 labels CONT
3427
3428 templayer mvpdiccopy CONT
3429 and LI
3430 and DIODE
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3431 and PSDM
3432 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3433
3434 layer mvpdic mvpdiccopy
3435 grow 85
3436 shrink 85
3437 shrink 85
3438 grow 85
3439 or mvpdiccopy
3440 labels CONT
3441
3442 templayer ndccopy CONT
3443 and ndifcheck
3444
3445 layer ndc ndccopy
3446 grow 85
3447 shrink 85
3448 shrink 85
3449 grow 85
3450 or ndccopy
3451 labels CONT
3452
3453 templayer mvndccopy CONT
3454 and mvndifcheck
3455
3456 layer mvndc mvndccopy
3457 grow 85
3458 shrink 85
3459 shrink 85
3460 grow 85
3461 or mvndccopy
3462 labels CONT
3463
3464 templayer pdccopy CONT
3465 and pdifcheck
3466
3467 layer pdc pdccopy
3468 grow 85
3469 shrink 85
3470 shrink 85
3471 grow 85
3472 or pdccopy
3473 labels CONT
3474
3475 templayer mvpdccopy CONT
3476 and mvpdifcheck
3477
3478 layer mvpdc mvpdccopy
3479 grow 85
3480 shrink 85
3481 shrink 85
3482 grow 85
3483 or mvpdccopy
3484 labels CONT
3485
3486 templayer pccopy CONT
3487 and polycheck
3488
3489 layer pc pccopy
3490 grow 85
3491 shrink 85
3492 shrink 85
3493 grow 85
3494 or pccopy
3495 labels CONT
3496
3497 templayer nsccopy CONT
3498 and nsubcheck
3499
3500 layer nsc nsccopy
3501 grow 85
3502 shrink 85
3503 shrink 85
3504 grow 85
3505 or nsccopy
3506 labels CONT
3507
3508 templayer mvnsccopy CONT
3509 and mvnsubcheck
3510
3511 layer mvnsc mvnsccopy
3512 grow 85
3513 shrink 85
3514 shrink 85
3515 grow 85
3516 or mvnsccopy
3517 labels CONT
3518
3519 templayer psccopy CONT
3520 and psubcheck
3521
3522 layer psc psccopy
3523 grow 85
3524 shrink 85
3525 shrink 85
3526 grow 85
3527 or psccopy
3528 labels CONT
3529
3530 templayer mvpsccopy CONT
3531 and mvpsubcheck
3532
3533 layer mvpsc mvpsccopy
3534 grow 85
3535 shrink 85
3536 shrink 85
3537 grow 85
3538 or mvpsccopy
3539 labels CONT
3540
3541 # Find contacts not covered in
3542 # metal and pull them into the
3543 # next layer up
3544
3545 templayer gencont CONT
3546 and LI
3547 and-not DIFF,TAP
3548 and-not POLY
3549 and-not DIODE
3550 and-not nsubcheck
3551 and-not psubcheck
3552 and-not mvnsubcheck
3553 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3554 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3555 copyup CONT,LI
3556
3557 templayer barecont CONT
3558 and-not LI
3559 and-not nsubcheck
3560 and-not psubcheck
3561 and-not mvnsubcheck
3562 and-not mvpsubcheck
Tim Edwardsea386762020-12-14 17:27:06 -0500[diff] [blame]3563 and-not CORELI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3564 copyup CONT
3565
3566 layer glass GLASS,PADTXT,PADPIN
3567 labels GLASS
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3568 variants (vendor)
3569 labels PADTXT port
3570 variants ()
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3571 labels PADTXT text
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3572 variants *
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3573 labels PADPIN port
3574
3575 templayer boundary BOUND,STDCELL,PADCELL
3576 boundary
3577
3578 layer comment LVSTEXT
3579 labels LVSTEXT text
3580
3581 layer comment TTEXT
3582 labels TTEXT text
3583
3584 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3585 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3586
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]3587 layer obsactive FILLOBSFOM
3588
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3589# MOS Varactor
3590
3591 layer var POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3592 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3593 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3594 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3595 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3596 and-not HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3597 # NOTE: Else forms a varactor that is not in the vendor netlist.
3598 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3599 labels POLY
3600
3601 layer varhvt POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3602 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3603 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3604 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3605 and-not HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3606 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3607 labels POLY
3608
3609 layer mvvar POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3610 and TAP
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3611 and NSDM
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3612 and NWELL
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3613 and HVI
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3614 labels POLY
3615
3616 calma NWELL 64 20
3617 calma DIFF 65 20
3618 calma DNWELL 64 18
3619 calma PWRES 64 13
3620 calma TAP 65 44
3621 # LVTN
3622 calma LVTN 125 44
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]3623 # HVTR
3624 calma HVTR 18 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3625 # HVTP
3626 calma HVTP 78 44
3627 # SONOS (TUNM)
3628 calma SONOS 80 20
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]3629 # NSDM (NPLUS)
3630 calma NSDM 93 44
3631 # PSDM (PPLUS)
3632 calma PSDM 94 20
3633 # HVI (THKOX)
3634 calma HVI 75 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3635 # NPC
3636 calma NPC 95 20
3637 # P+ POLY MASK
3638 calma RPM 86 20
3639 calma URPM 79 20
3640 calma LDNTM 11 44
3641 calma HVNTM 125 20
Tim Edwards3af6a1e2020-09-16 11:48:17 -0400[diff] [blame]3642 # Poly resistor ID mark
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3643 calma POLYRES 66 13
3644 # Diffusion resistor ID mark
3645 calma DIFFRES 65 13
3646 calma POLY 66 20
3647 calma POLYMOD 66 83
3648 # Diode ID mark
3649 calma DIODE 81 23
3650 # Bipolar NPN mark
3651 calma NPNID 82 20
3652 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3653 calma PNPID 82 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3654 # Capacitor ID
3655 calma CAPID 82 64
3656 # Core area ID mark
3657 calma COREID 81 2
3658 # Standard cell ID mark
3659 calma STDCELL 81 4
3660 # Padframe cell ID mark
3661 calma PADCELL 81 3
3662 # Seal ring ID mark
3663 calma SEALID 81 1
3664 # Low tap density ID mark
3665 calma LOWTAPDENSITY 81 14
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3666 # ESD area ID
3667 calma ESDID 81 19
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3668
3669 # LICON
3670 calma CONT 66 44
3671 calma LI 67 20
3672 calma MCON 67 44
3673
3674 calma MET1 68 20
3675 calma VIA1 68 44
3676 calma MET2 69 20
3677 calma VIA2 69 44
3678 calma MET3 70 20
3679#ifdef METAL5
3680 calma VIA3 70 44
3681 calma MET4 71 20
3682 calma VIA4 71 44
3683 calma MET5 72 20
3684#endif
3685#ifdef REDISTRIBUTION
3686 calma RDL 74 20
3687#endif
3688 calma GLASS 76 20
3689
3690 calma SUBPIN 64 59
3691 calma PADPIN 76 5
3692 calma DIFFPIN 65 6
3693 calma TAPPIN 65 5
3694 calma WELLPIN 64 5
3695 calma LIPIN 67 5
3696 calma POLYPIN 66 5
3697 calma MET1PIN 68 5
3698 calma MET2PIN 69 5
3699 calma MET3PIN 70 5
3700#ifdef METAL5
3701 calma MET4PIN 71 5
3702 calma MET5PIN 72 5
3703#endif
3704#ifdef REDISTRIBUTION
3705 calma RDLPIN 74 5
3706#endif
3707
3708 calma LIRES 67 13
3709 calma MET1RES 68 13
3710 calma MET2RES 69 13
3711 calma MET3RES 70 13
3712#ifdef METAL5
3713 calma MET4RES 71 13
3714 calma MET5RES 72 13
3715#endif
3716
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3717 calma MET1FILL 68 28
3718 calma MET2FILL 69 28
3719 calma MET3FILL 70 28
3720#ifdef METAL5
3721 calma MET4FILL 71 28
3722 calma MET5FILL 72 28
3723#endif
3724
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3725 calma POLYSHORT 66 15
3726 calma LISHORT 67 15
3727 calma MET1SHORT 68 15
3728 calma MET2SHORT 69 15
3729 calma MET3SHORT 70 15
3730#ifdef METAL5
3731 calma MET4SHORT 71 15
3732 calma MET5SHORT 72 15
3733#endif
3734
3735 calma SUBTXT 122 16
3736 calma PADTXT 76 16
3737 calma DIFFTXT 65 16
3738 calma POLYTXT 66 16
3739 calma WELLTXT 64 16
3740 calma LITXT 67 16
3741 calma MET1TXT 68 16
3742 calma MET2TXT 69 16
3743 calma MET3TXT 70 16
3744#ifdef METAL5
3745 calma MET4TXT 71 16
3746 calma MET5TXT 72 16
3747#endif
3748#ifdef REDISTRIBUTION
3749 calma RDLPIN 74 16
3750#endif
3751
3752 calma BOUND 235 4
3753
3754 calma LVSTEXT 83 44
3755
3756#ifdef (MIM)
3757 calma CAPM 89 44
3758 calma CAPM2 97 44
3759#endif (MIM)
3760
3761 calma FILLOBSM1 62 24
3762 calma FILLOBSM2 105 52
3763 calma FILLOBSM3 107 24
Tim Edwards14db3482020-12-30 13:28:09 -0500[diff] [blame]3764 calma FILLOBSM4 112 4
3765 calma FILLOBSFOM 22 24
3766 calma FILLOBSPOLY 33 24
3767
Tim Edwards916492d2020-12-27 10:29:28 -0500[diff] [blame]3768 calma FOMFILL 65 28
3769 calma POLYFILL 66 28
3770 calma MET1FILL 68 28
3771 calma MET2FILL 69 28
3772 calma MET3FILL 70 28
3773 calma MET4FILL 71 28
3774 calma MET5FILL 72 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3775
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3776#-----------------------------------------------------------------------
3777
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]3778style rdlimport
3779 # This style is for reading shapes generated with the RDL layers
3780
3781 scalefactor 10 nanometers
3782 gridlimit 5
3783
3784 options ignore-unknown-layer-labels no-reconnect-labels
3785
3786 layer mrdl RDL
3787 layer mrdlc RDLC
3788
3789 calma RDL 10 0
3790 calma RDLC 20 0
3791
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3792end
3793
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3794#-----------------------------------------------------
3795# Digital flow maze router cost parameters
3796#-----------------------------------------------------
3797
3798mzrouter
3799end
3800
3801#-----------------------------------------------------
3802# Vendor DRC rules
3803#-----------------------------------------------------
3804
3805drc
3806
3807 style drc variants (fast),(full),(routing)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3808 scalefactor 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3809 cifstyle drc
3810
3811 variants (fast),(full)
3812
3813#-----------------------------
3814# DNWELL
3815#-----------------------------
3816
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3817 width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
3818 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3819 spacing dnwell allnwell 4500 surround_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3820 "Deep N-well spacing to N-well < %d (nwell.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3821
3822 variants (full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3823 cifmaxwidth nwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3824 "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3825 cifmaxwidth dnwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3826 "SONOS nFET must be in Deep N-well (tunm.6a)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3827
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3828 cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
3829 "P+ diff cannot straddle Deep N-well (dnwell.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3830 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3831
3832#-----------------------------
3833# NWELL
3834#-----------------------------
3835
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3836 width allnwell 840 "N-well width < %d (nwell.1)"
3837 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3838
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3839 variants (full)
3840 cifmaxwidth nwell_missing_tap 0 bend_illegal \
3841 "All nwells must contain metal-connected N+ taps (nwell.4)"
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]3842
3843 cifspacing mvnwell lvnwell 2000 touching_illegal \
3844 "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
3845 cifspacing mvnwell mvnwell 2000 touching_ok \
3846 "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3847 variants (fast),(full)
3848
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3849#-----------------------------
3850# DIFF
3851#-----------------------------
3852
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3853 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3854 150 "Diffusion width < %d (diff/tap.1)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3855 width *mvndiff,mvnfet,mvnfetesd,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3856 "MV Diffusion width < %d (diff/tap.14)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3857
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3858 width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
3859 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
3860 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
3861 extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
3862 extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
3863 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3864 spacing alldifflv,var,varhvt,fomfill alldifflv,var,varhvt,fomfill 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3865 "Diffusion spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3866 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3867 "MV Diffusion spacing < %d (diff/tap.15a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3868 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3869 "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3870 spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3871 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3872 spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3873 "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3874 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3875 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3876 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3877 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3878 spacing *psd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3879 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3880 spacing *mvpsd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3881 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3882 surround *nsd allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3883 "N-well overlap of N-tap < %d (diff/tap.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3884 surround *mvnsd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3885 "N-well overlap of MV N-tap < %d (diff/tap.19)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3886 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3887 "N-well overlap of P-Diffusion < %d (diff/tap.8)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3888 surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3889 "N-well overlap of P-Diffusion < %d (diff/tap.17)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3890 surround mvvar allnwell 560 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3891 "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3892 spacing *mvndiode *mvndiode 1070 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3893 "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]3894
3895variants (full)
3896 cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
3897 "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
3898variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3899
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3900 spacing allnfets allpactivenonfet 270 touching_illegal \
3901 "nFET cannot abut P-diffusion (diff/tap.3)"
3902 spacing allpfets allnactivenonfet 270 touching_illegal \
3903 "pFET cannot abut N-diffusion (diff/tap.3)"
3904
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3905 # Butting junction rules
3906 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3907 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3908 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3909 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3910 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3911 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3912 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3913 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3914
3915 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3916 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3917 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3918 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3919 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3920 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3921 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3922 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
3923
3924 # Sandwiched butting junction restrictions
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]3925 edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
3926 edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
3927
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]3928 area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
3929 area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
3930
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]3931 angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3932
3933 variants (full)
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]3934 cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3935
3936 # Latchup rules
3937 cifmaxwidth ptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3938 "N-diff distance to P-tap must be < 15.0um (LU.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3939 cifmaxwidth dptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3940 "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3941 cifmaxwidth ntap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3942 "P-diff distance to N-tap must be < 15.0um (LU.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3943
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3944 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3945
3946#-----------------------------
3947# POLY
3948#-----------------------------
3949
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3950 width allpoly,polyfill 150 "poly width < %d (poly.1a)"
3951 spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3952
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3953 spacing allpolynonfet,polyfill \
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]3954 *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3955 75 corner_ok allfets \
3956 "poly spacing to Diffusion < %d (poly.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3957 spacing npres *nsd 480 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3958 "poly resistor spacing to N-tap < %d (poly.9)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3959 overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3960 overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3961 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3962 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3963 overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]3964 overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
3965 overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3966 rect_only allfets "No bends in transistors (poly.11)"
3967 rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3968 extend xpc/a xhrpoly,uhrpoly 2160 \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3969 "poly contact extends poly resistor by < %d (licon.1c + li.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3970 spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]3971 "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3972
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3973 spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 780 touching_illegal \
3974 "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
3975 spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
3976 "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
3977 spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 830 touching_illegal \
3978 "Distance from precision resistor to MV N+ diffusion < %d (rpm.3 + rpm.9)"
3979
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]3980 angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]3981
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3982#--------------------------------------------------------------------
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3983# HVTP
3984#--------------------------------------------------------------------
3985
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]3986 spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3987 360 touching_illegal \
3988 "Min. spacing between pFET and HVTP < %d (hvtp.4)"
3989
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3990 spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]3991 "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
3992
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]3993#--------------------------------------------------------------------
3994# LVTN
3995#--------------------------------------------------------------------
3996
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3997 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
3998 allfetsnolvt 360 touching_illegal \
3999 "Min. spacing between FET and LVTN < %d (lvtn.3a)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4000
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4001 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4002 740 touching_illegal \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4003 "Min. spacing between LVTN and HVTP < %d (lvtn.9)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4004
4005 # Spacing across S/D direction requires edge rule
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4006 edge4way allfetsnolvt allactivenonfet 415 \
4007 ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
4008 "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4009
4010#--------------------------------------------------------------------
4011# NPC (Nitride poly Cut)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4012#--------------------------------------------------------------------
4013
4014# Layer NPC is defined automatically around poly contacts (grow 0.1um)
4015
4016#--------------------------------------------------------------------
4017# CONT (LICON, contact between poly/diff and LI)
4018#--------------------------------------------------------------------
4019
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4020 width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
4021 width nsc/li 170 "N-tap contact width < %d (licon.1)"
4022 width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
4023 width psc/li 170 "P-tap contact width < %d (licon.1)"
4024 width ndic/li 170 "N-diode contact width < %d (licon.1)"
4025 width pdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4026 width pc/li 170 "poly contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4027
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4028 width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
4029 area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)"
4030 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4031
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4032 width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
4033 width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
4034 width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
4035 width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
4036 width mvndic/li 170 "N-diode contact width < %d (licon.1)"
4037 width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4038
4039 spacing allpdiffcont allndiffcont 170 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4040 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4041 spacing allndiffcont allndiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4042 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4043 spacing allpdiffcont allpdiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4044 "Diffusion contact spacing < %d (licon.2)"
4045 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4046
4047 spacing pc alldiff 190 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4048 "poly contact spacing to diffusion < %d (licon.14)"
4049 spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
4050 "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4051
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4052 spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4053 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4054 spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4055 "Diffusion contact to standard cell gate < %d (licon.11)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4056 spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
4057 "Diffusion contact to SRAM gate < %d (licon.11)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4058 spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,mvpfet,mvpfetesd 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4059 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4060 spacing nsc varactor,varhvt 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4061 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4062 spacing mvnsc mvvar 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4063 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4064
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4065 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4066 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4067 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4068 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4069 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4070 surround ndic/a *ndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4071 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4072 surround pdic/a *pdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4073 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4074
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4075 spacing psc/a allnactivenontap 60 touching_illegal \
4076 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4077 spacing nsc/a allpactivenontap 60 touching_illegal \
4078 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4079
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4080 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4081 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards374485b2020-11-27 11:24:13 -0500[diff] [blame]4082 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
4083 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4084 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4085 surround ndic/a *ndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4086 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4087 surround pdic/a *pdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4088 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4089
4090 surround nsc/a *nsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4091 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4092 surround psc/a *psd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4093 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4094
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4095 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4096 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4097 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4098 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4099 surround mvndic/a *mvndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4100 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4101 surround mvpdic/a *mvpdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4102 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4103
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4104 spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
4105 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
4106 spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
4107 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
4108
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4109 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4110 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4111 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4112 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4113 surround mvndic/a *mvndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4114 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4115 surround mvpdic/a *mvpdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4116 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4117
4118 surround mvnsc/a *mvnsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4119 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4120 surround mvpsc/a *mvpsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4121 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4122
4123 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4124 "poly overlap of poly contact < %d (licon.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4125 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4126 "poly overlap of poly contact < %d in one direction (licon.8a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4127
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4128 exact_overlap (allcont)/a
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4129
4130#-------------------------------------------------------------
4131# LI - Local interconnect layer
4132#-------------------------------------------------------------
4133
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4134variants *
4135
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]4136 width *li 170 "Local interconnect width < %d (li.1)"
4137 width rli 290 "Local interconnect width < %d (li.7)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4138
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4139 spacing *locali,rli *locali,rli,*obsli 170 touching_ok \
4140 "Local interconnect spacing < %d (li.3)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4141
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4142 # Local interconnect in core (SRAM) cells has more relaxed rules. There are
4143 # no special layers for the contacts in core cells, so they must be included
4144 # in the rule.
Tim Edwards8c4d8ac2020-12-09 22:51:37 -0500[diff] [blame]4145 width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
4146 "Core local interconnect width < %d (li.c1)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4147
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4148 spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \
Tim Edwards3717c4a2020-12-08 17:11:56 -0500[diff] [blame]4149 "Core local interconnect spacing < %d (li.c2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4150
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4151 surround pc/li *li,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4152 "Local interconnect overlap of poly contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4153
4154 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4155 *li,rli,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4156 "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4157
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]4158 area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4159
Tim Edwardsb04723d2020-11-13 19:48:27 -0500[diff] [blame]4160 angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
4161 angles coreli 45 \
4162 "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4163
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4164#-------------------------------------------------------------
4165# MCON - Contact between local interconnect and metal1
4166#-------------------------------------------------------------
4167
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4168 width mcon/m1 170 "mcon.width < %d (mcon.1)"
4169 spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4170
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4171 exact_overlap mcon/li
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4172
4173#-------------------------------------------------------------
4174# METAL1 -
4175#-------------------------------------------------------------
4176
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4177 width *m1,rm1 140 "Metal1 width < %d (met1.1)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4178 spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4179 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4180
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4181 surround mcon/m1 *met1 30 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4182 "Metal1 overlap of local interconnect contact < %d (met1.4)"
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4183 surround mcon/m1 *met1 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4184 "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4185
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4186 angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4187
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4188variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4189 widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4190 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4191 widespacing *obsm1 3005 allm1 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4192 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4193
4194variants (full)
4195 cifmaxwidth m1_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4196 "Min area of metal1 holes > 0.14um^2 (met1.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4197
4198 cifspacing m1_large_halo m1_large_halo 280 touching_ok \
4199 "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4200variants *
4201
4202#--------------------------------------------------
4203# VIA1
4204#--------------------------------------------------
4205
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4206 width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
4207 spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4208 surround v1/m1 *m1 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4209 "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4210 surround v1/m2 *m2 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4211 "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4212
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4213 exact_overlap v1/m1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4214
4215#--------------------------------------------------
4216# METAL2 -
4217#--------------------------------------------------
4218
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4219 width allm2,m2fill 140 "Metal2 width < %d (met2.1)"
4220 spacing allm2 allm2,obsm2,m2fill 140 touching_ok "Metal2 spacing < %d (met2.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4221 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4222
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4223 angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
4224
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4225variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4226 widespacing allm2 3005 allm2,obsm2,m2fill 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4227 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4228 widespacing obsm2 3005 allm2 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4229 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4230
4231variants (full)
4232 cifmaxwidth m2_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4233 "Min area of metal2 holes > 0.14um^2 (met2.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4234
4235 cifspacing m2_large_halo m2_large_halo 280 touching_ok \
4236 "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4237variants *
4238
4239#--------------------------------------------------
4240# VIA2
4241#--------------------------------------------------
4242
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4243 width v2/m2 280 "via2.width < %d (via2.1a + 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4244
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4245 spacing v2 v2 120 touching_ok "via2.spacing < 0.24um (via2.2 - 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4246
4247 surround v2/m2 *m2 45 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4248 "Metal2 overlap of via2.< %d in one direction (via2.4a - via2.4)"
4249 surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of via2.< %d (met3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4250
4251 exact_overlap v2/m2
4252
4253#--------------------------------------------------
4254# METAL3 -
4255#--------------------------------------------------
4256
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4257 width allm3,m3fill 300 "Metal3 width < %d (met3.1)"
4258 spacing allm3 allm3,obsm3,m3fill 300 touching_ok "Metal3 spacing < %d (met3.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4259 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4260
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4261 angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
4262
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4263variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4264 widespacing allm3,m3fill 3005 allm3,obsm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4265 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4266 widespacing obsm3 3005 allm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4267 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4268variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4269 cifspacing m3_large_halo m3_large_halo 400 touching_ok \
4270 "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4271variants *
4272
4273
4274#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4275#undef METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4276#--------------------------------------------------
4277# VIA3 - Requires METAL5 Module
4278#--------------------------------------------------
4279
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4280 width v3/m3 320 "via3.width < %d (via3.1 + 2 * via3.4)"
4281 spacing v3 v3 80 touching_ok "via3.spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4282 surround v3/m3 *m3 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4283 "Metal3 overlap of via3.in one direction < %d (via3.5 - via3.4)"
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]4284 surround v3/m4 *m4 5 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4285 "Metal4 overlap of via3.< %d (met4.3 - via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4286
4287 exact_overlap v3/m3
4288
4289#-----------------------------
4290# METAL4 - METAL4 Module
4291#-----------------------------
4292
4293variants *
4294
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4295 width allm4,m4fill 300 "Metal4 width < %d (met4.1)"
4296 spacing allm4 allm4,obsm4,m4fill 300 touching_ok "Metal4 spacing < %d (met4.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4297 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4298
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4299 angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
4300
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4301variants (fast),(full)
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4302 widespacing allm4,m4fill 3005 allm4,obsm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4303 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardsebc20a22020-12-18 10:32:46 -0500[diff] [blame]4304 widespacing obsm4 3005 allm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4305 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]4306variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4307 cifspacing m4_large_halo m4_large_halo 400 touching_ok \
4308 "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4309variants *
4310
4311#--------------------------------------------------
4312# VIA4 - Requires METAL5 Module
4313#--------------------------------------------------
4314
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4315 width v4/m4 1180 "via4.width < %d (via4.1 + 2 * via4.4)"
4316 spacing v4 v4 420 touching_ok "via4.spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4317 surround v4/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4318 "Metal5 overlap of via4.< %d (met5.3 - via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4319
4320 exact_overlap v4/m4
4321
4322#-----------------------------
4323# METAL5 - METAL5 Module
4324#-----------------------------
4325
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4326 width allm5,m5fill 1600 "Metal5 width < %d (met5.1)"
4327 spacing allm5 allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4328 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4329
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]4330 angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
4331
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]4332#define METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4333#endif (METAL5)
4334
4335#ifdef REDISTRIBUTION
4336
4337variants (full)
4338
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4339 width metrdl 10000 "RDL width < %d (rdl.1)"
4340 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
4341 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
4342 spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4343
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4344variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4345
4346#endif (REDISTRIBUTION)
4347
4348#--------------------------------------------------
4349# NMOS, PMOS
4350#--------------------------------------------------
4351
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4352 edge4way *poly allfetsstd 420 allfets 0 0 \
4353 "Transistor width < %d (diff/tap.2)"
4354 edge4way *poly allfetsspecial 360 allfets 0 0 \
4355 "Transistor in standard cell width < %d (diff/tap.2)"
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]4356 edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
4357 "N-Transistor in SRAM core width < %d (diff/tap.2)"
4358 edge4way *poly ppu 140 allfets 0 0 \
4359 "P-Transistor in SRAM core width < %d (diff/tap.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4360
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4361 # Except: Note that standard cells allow transistor width minimum 0.36um
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4362 width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4363
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4364 spacing allpolynonfet,polyfill *nsd 55 corner_ok varactor \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4365 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4366 spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvaractor \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4367 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4368
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]4369 edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4370 "Butting P-tap spacing to NMOS gate < %d (poly.6)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4371 edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4372 "Butting N-tap spacing to PMOS gate < %d (poly.6)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4373 edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet)/a *mvpsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4374 "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4375 edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4376 "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4377
4378 # No LV FETs in HV diff
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4379 spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4380 "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4381
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]4382 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4383 "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4384
4385 # No HV FETs in LV diff
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4386 spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4387 "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4388
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4389 spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4390 "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4391
4392 # Minimum length of MV FETs. Note that this is larger than the minimum
4393 # width (0.29um), so an edge rule is required
4394
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4395 edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4396 "MV NMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4397
4398 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4399 "MV Varactor minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4400
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]4401 edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4402 "MV PMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4403
4404#--------------------------------------------------
4405# mrp1 (N+ poly resistor)
4406#--------------------------------------------------
4407
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4408 width mrp1 330 "mrp1 resistor width < %d (poly.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4409
4410#--------------------------------------------------
4411# xhrpoly (P+ poly resistor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4412# uhrpoly (P+ poly resistor, 2kOhm/sq)
4413#--------------------------------------------------
4414
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4415 # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
4416 width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
4417 width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
4418
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4419 spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4420 "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4421
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4422 spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
Tim Edwardse162c052020-11-11 11:01:06 -0500[diff] [blame]4423 "Poly resistor spacing to poly < %d (poly.9)"
4424
4425 spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
4426 "Poly resistor spacing to poly < %d (poly.9)"
4427
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4428 spacing mrp1 *poly 480 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4429 "Poly resistor spacing to poly < %d (poly.9)"
4430
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]4431 spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4432 "Poly resistor spacing to diffusion < %d (poly.9)"
4433
4434#------------------------------------
4435# nsonos
4436#------------------------------------
4437
4438variants (full)
4439 cifmaxwidth bbox_missing 0 bend_illegal \
4440 "SONOS transistor must be in cell with abutment box (tunm.8)"
4441variants (fast),(full)
4442
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4443#------------------------------------
4444# MOS Varactor device rules
4445#------------------------------------
4446
4447 overhang *nsd var,varhvt 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4448 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4449
4450 overhang *mvnsd mvvar 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4451 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4452
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4453 width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
4454 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4455
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4456variants (full)
4457 cifmaxwidth var_poly_no_nwell 0 bend_illegal \
4458 "N-well overlap of varactor poly < 0.15um (varac.5)"
4459
4460 cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
4461 "Varactor N-well must not contain P+ diffusion (varac.7)"
4462variants (fast),(full)
4463
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4464#ifdef MIM
4465#-----------------------------------------------------------
4466# MiM CAP (CAPM) -
4467#-----------------------------------------------------------
4468
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4469 width *mimcap 1000 "MiM cap width < %d (capm.1)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4470 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4471 spacing *mimcap via3/m3 80 touching_illegal \
4472 "MiM cap spacing to via3 < %d (capm.5 - via3.4)"
4473 surround *mimcc *mimcap 80 absence_illegal \
4474 "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4475 rect_only *mimcap "MiM cap must be rectangular (capm.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4476
4477 surround *mimcap *metal3/m3 140 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4478 "Metal3 must surround MiM cap by %d (capm.3)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4479 spacing via2 *mimcap 100 touching_illegal \
4480 "MiM cap spacing to via2 < %d (capm.8 - via2.4)"
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4481 spacing *mimcap *metal3/m3 500 surround_ok \
4482 "MiM cap spacing to unrelated metal3 < %d (capm.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4483
4484variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4485 cifspacing mim_bottom mim_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4486 "MiM cap bottom plate spacing < %d (capm.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4487variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4488
4489 # MiM cap contact rules (VIA3)
4490
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4491 width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4492 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4493 surround mimcc/m4 *m4 5 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4494 "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4495 exact_overlap mimcc/c1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4496
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4497 width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
4498 spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4499 spacing *mimcap2 via4/m4 10 touching_illegal \
4500 "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
4501 surround *mim2cc *mimcap2 10 absence_illegal \
4502 "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4503 rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4504
4505 surround *mimcap2 *metal4/m4 140 absence_illegal \
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4506 "Metal4 must surround MiM2 cap by %d (cap2m.3)"
Tim Edwards5ad4eb42020-11-27 10:58:22 -0500[diff] [blame]4507 spacing via3,mimcc *mimcap2 80 touching_illegal \
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]4508 "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]4509 spacing *mimcap2 *metal4/m4 500 surround_ok \
4510 "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4511
4512variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]4513 cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]4514 "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]4515variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4516
4517 # MiM cap contact rules (VIA4)
4518
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4519 width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4520 spacing mim2cc mim2cc 420 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4521 "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4522 surround mim2cc/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]4523 "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]4524 exact_overlap mim2cc/c2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4525
4526#endif (MIM)
4527
4528#----------------------------
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]4529# HVNTM
4530#----------------------------
4531variants (full)
4532 cifspacing hvntm_generate hvntm_generate 700 touching_ok \
4533 "HVNTM spacing < %d (hvntm.2)"
4534variants (fast),(full)
4535
4536#----------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4537# End DRC style
4538#----------------------------
4539
4540end
4541
4542#----------------------------
4543# LEF format definitions
4544#----------------------------
4545
4546lef
4547
Tim Edwards282d9542020-07-15 17:52:08 -0400[diff] [blame]4548 masterslice pwell pwell PWELL substrate
4549 masterslice nwell nwell NWELL
Tim Edwardsd9fe0002020-07-14 21:53:24 -0400[diff] [blame]4550
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4551 routing li li1 LI1 LI li
4552
4553 routing m1 met1 MET1 m1
4554 routing m2 met2 MET2 m2
4555 routing m3 met3 MET3 m3
4556#ifdef METAL5
4557 routing m4 met4 MET4 m4
4558 routing m5 met5 MET5 m5
4559#endif (METAL5)
4560#ifdef REDISTRIBUTION
4561 routing mrdl met6 MET6 m6 MRDL METRDL
4562#endif
4563
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4564 cut mcon mcon MCON Mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4565 cut m2c via via1 VIA VIA1 cont2 via12
4566 cut m3c via2 VIA2 cont3 via23
4567#ifdef METAL5
4568 cut via3 via3 VIA3 cont4 via34
4569 cut via4 via4 VIA4 cont5 via45
4570#endif (METAL5)
4571
4572 obs obsli li1
4573 obs obsm1 met1
4574 obs obsm2 met2
4575 obs obsm3 met3
4576
4577#ifdef METAL5
4578 obs obsm4 met4
4579 obs obsm5 met5
4580#endif (METAL5)
4581#ifdef REDISTRIBUTION
4582 obs obsmrdl met6
4583#endif
4584
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4585 # NOTE: obsmcon only used with li1, not obsli.
4586 obs obsmcon mcon
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4587
Tim Edwards3959de82020-12-01 10:36:13 -0500[diff] [blame]4588 # Vias on obstruction layers should be ignored, so cast to obstruction metal.
4589 obs obsm1 via
4590 obs obsm2 via2
4591#ifdef METAL5
4592 obs obsm3 via3
4593 obs obsm4 via4
4594#endif (METAL5)
4595
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4596end
4597
4598#-----------------------------------------------------
4599# Device and Parasitic extraction
4600#-----------------------------------------------------
4601
4602
4603extract
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4604 style ngspice variants (),(orig),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4605 cscale 1
4606 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
4607 # dimensions must be in units of microns in the extract file.
4608 # Use extract style "ngspice(si)" to override this and produce
4609 # a file with SI units for length/area.
4610
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4611 variants (),(orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4612 lambda 1E6
4613 variants (si)
4614 lambda 1.0
4615 variants *
4616
4617 units microns
4618 step 7
4619 sidehalo 2
4620
4621 # NOTE: MiM cap layers have been purposely put out of order,
4622 # may want to reconsider.
4623
4624 planeorder dwell 0
4625 planeorder well 1
4626 planeorder active 2
4627 planeorder locali 3
4628 planeorder metal1 4
4629 planeorder metal2 5
4630 planeorder metal3 6
4631#ifdef METAL5
4632 planeorder metal4 7
4633 planeorder metal5 8
4634#ifdef REDISTRIBUTION
4635 planeorder metali 9
4636 planeorder block 10
4637 planeorder comment 11
4638 planeorder cap1 12
4639 planeorder cap2 13
4640#else (!REDISTRIBUTION)
4641 planeorder block 9
4642 planeorder comment 10
4643 planeorder cap1 11
4644 planeorder cap2 12
4645#endif (!REDISTRIBUTION)
4646#else (!METAL5)
4647#ifdef REDISTRIBUTION
4648 planeorder metali 7
4649 planeorder block 8
4650 planeorder comment 9
4651 planeorder cap1 10
4652 planeorder cap2 11
4653#else (!REDISTRIBUTION)
4654 planeorder block 7
4655 planeorder comment 8
4656 planeorder cap1 9
4657 planeorder cap2 10
4658#endif (!REDISTRIBUTION)
4659#endif (!METAL5)
4660
4661 height dnwell -0.1 0.1
4662 height nwell,pwell 0.0 0.2062
4663 height alldiff 0.2062 0.12
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4664 height fomfill 0.2062 0.12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4665 height allpoly 0.3262 0.18
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4666 height polyfill 0.3262 0.18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4667 height alldiffcont 0.3262 0.61
4668 height pc 0.5062 0.43
4669 height allli 0.9361 0.10
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4670 height mcon 1.0361 0.34
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4671 height allm1 1.3761 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4672 height m1fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4673 height v1 1.7361 0.27
4674 height allm2 2.0061 0.36
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4675 height m2fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4676 height v2 2.3661 0.42
4677 height allm3 2.7861 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4678 height m3fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4679#ifdef METAL5
4680 height v3 3.6311 0.39
4681 height allm4 4.0211 0.845
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4682 height m4fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4683 height v4 4.8661 0.505
4684 height allm5 5.3711 1.26
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]4685 height m5fill 1.3761 0.36
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4686 height mimcap 2.4661 0.2
4687 height mimcap2 3.7311 0.2
4688 height mimcc 2.6661 0.12
4689 height mim2cc 3.9311 0.09
4690#ifdef REDISTRIBUTION
4691 height mrdlc 6.6311 5.2523
4692 height mrdl 11.8834 4.0
4693#endif (!REDISTRIBUTION)
4694#endif (!METAL5)
4695
4696 # Antenna check parameters
4697 # Note that checks w/diode diffusion are not modeled
4698 model partial
4699 antenna poly sidewall 50 none
4700 antenna allcont surface 3 none
4701 antenna li sidewall 75 0 450
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4702 antenna mcon surface 3 0 18
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4703 antenna m1,m2,m3 sidewall 400 2600 400
4704 antenna v1 surface 3 0 18
4705 antenna v2 surface 6 0 36
4706#ifdef METAL5
4707 antenna m4,m5 sidewall 400 2600 400
4708 antenna v3,v4 surface 6 0 36
4709#endif (METAL5)
4710
4711 tiedown alldiffnonfet
4712
4713 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell
4714
4715# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
4716
4717# Resistances are in milliohms per square
4718# Optional 3rd argument is the corner adjustment fraction
4719# Device values come from trtc.cor (typical corner)
4720 resist (dnwell)/dwell 2200000
4721 resist (pwell)/well 3050000
4722 resist (nwell)/well 1700000
4723 resist (rpw)/well 3050000 0.5
4724 resist (*ndiff,nsd)/active 120000
4725 resist (*pdiff,*psd)/active 197000
4726 resist (*mvndiff,mvnsd)/active 114000
4727 resist (*mvpdiff,*mvpsd)/active 191000
4728
4729 resist ndiffres/active 120000 0.5
4730 resist pdiffres/active 197000 0.5
4731 resist mvndiffres/active 114000 0.5
4732 resist mvpdiffres/active 191000 0.5
4733 resist mrp1/active 48200 0.5
4734 resist xhrpoly/active 319800 0.5
4735 resist uhrpoly/active 2000000 0.5
4736
4737 resist (allpolynonres)/active 48200
4738 resist rmp/active 48200
4739
4740 resist (allli)/locali 12200
4741 resist (allm1)/metal1 125
4742 resist (allm2)/metal2 125
4743 resist (allm3)/metal3 47
4744#ifdef METAL5
4745 resist (allm4)/metal4 47
4746 resist (allm5)/metal5 29
4747#endif (METAL5)
4748#ifdef REDISTRIBUTION
4749 resist mrdl/metali 5
4750#endif (REDISTRIBUTION)
4751
4752 contact ndc,nsc 15000
4753 contact pdc,psc 15000
4754 contact mvndc,mvnsc 15000
4755 contact mvpdc,mvpsc 15000
4756 contact pc 15000
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]4757 contact mcon 152000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4758 contact m2c 4500
4759 contact m3c 3410
4760#ifdef METAL5
4761#ifdef MIM
4762 contact mimcc 4500
4763 contact mim2cc 3410
4764#endif (MIM)
4765 contact via3 3410
4766 contact via4 380
4767#endif (METAL5)
4768#ifdef REDISTRIBUTION
4769 contact mrdlc 6
4770#endif (REDISTRIBUTION)
4771
4772#-------------------------------------------------------------------------
4773# Parasitic capacitance values: Use document (...)
4774#-------------------------------------------------------------------------
4775# This uses the new "default" definitions that determine the intervening
4776# planes from the planeorder stack, take care of the reflexive sideoverlap
4777# definitions, and generally clean up the section and make it more readable.
4778#
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4779# Also uses "units microns" statement. All values are taken from the
4780# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
4781# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4782#-------------------------------------------------------------------------
4783# Remember that device capacitances to substrate are taken care of by the
4784# models. Thus, active and poly definitions ignore all "fet" types.
4785# fet types are excluded when computing parasitic capacitance to
4786# active from layers above them because poly is a shield; fet types are
4787# included for parasitics from layers above to poly. Resistor types
4788# should be removed from all parasitic capacitance calculations, or else
4789# they just create floating caps. Technically, the capacitance probably
4790# should be split between the two terminals. Unsure of the correct model.
4791#-------------------------------------------------------------------------
4792
4793#n-well
4794# NOTE: This value not found in PEX files
4795defaultareacap nwell well 120
4796
4797#n-active
4798# Rely on device models to capture *ndiff area cap
4799# Do not extract parasitics from resistors
4800# defaultareacap allnactivenonfet active 790
4801# defaultperimeter allnactivenonfet active 280
4802
4803#p-active
4804# Rely on device models to capture *pdiff area cap
4805# Do not extract parasitics from resistors
4806# defaultareacap allpactivenonfet active 810
4807# defaultperimeter allpactivenonfet active 300
4808
4809#poly
4810# Do not extract parasitics from resistors
4811# defaultsidewall allpolynonfet active 22
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4812# defaultareacap allpolynonfet active 106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4813# defaultperimeter allpolynonfet active 57
4814
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4815 defaultsidewall *poly active 23
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4816 defaultareacap *poly active nwell,obswell,pwell well 106
4817 defaultperimeter *poly active nwell,obswell,pwell well 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4818
4819#locali
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4820 defaultsidewall allli locali 33
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4821 defaultareacap allli locali nwell,obswell,pwell well 37
4822 defaultperimeter allli locali nwell,obswell,pwell well 55
4823 defaultoverlap allli locali nwell well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4824
4825#locali->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4826 defaultoverlap allli locali allactivenonfet active 37
4827 defaultsideoverlap allli locali allactivenonfet active 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4828
4829#locali->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4830 defaultoverlap allli locali allpolynonres active 94
4831 defaultsideoverlap allli locali allpolynonres active 52
4832 defaultsideoverlap *poly active allli locali 25
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4833
4834#metal1
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4835 defaultsidewall allm1 metal1 45
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4836 defaultareacap allm1 metal1 nwell,obswell,pwell well 26
4837 defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4838 defaultoverlap allm1 metal1 nwell well 26
4839
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4840#metal1->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4841 defaultoverlap allm1 metal1 allactivenonfet active 26
4842 defaultsideoverlap allm1 metal1 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4843
4844#metal1->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4845 defaultoverlap allm1 metal1 allpolynonres active 45
4846 defaultsideoverlap allm1 metal1 allpolynonres active 47
4847 defaultsideoverlap *poly active allm1 metal1 17
4848
4849#metal1->locali
4850 defaultoverlap allm1 metal1 allli locali 114
4851 defaultsideoverlap allm1 metal1 allli locali 59
4852 defaultsideoverlap allli locali allm1 metal1 35
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4853
4854#metal2
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]4855 defaultsidewall allm2 metal2 50
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4856 defaultareacap allm2 metal2 nwell,obswell,pwell well 17
4857 defaultperimeter allm2 metal2 nwell,obswell,pwell well 41
4858 defaultoverlap allm2 metal2 nwell well 38
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4859
4860#metal2->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4861 defaultoverlap allm2 metal2 allactivenonfet active 17
4862 defaultsideoverlap allm2 metal2 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4863
4864#metal2->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4865 defaultoverlap allm2 metal2 allpolynonres active 24
4866 defaultsideoverlap allm2 metal2 allpolynonres active 41
4867 defaultsideoverlap *poly active allm2 metal2 11
4868
4869#metal2->locali
4870 defaultoverlap allm2 metal2 allli locali 38
4871 defaultsideoverlap allm2 metal2 allli locali 46
4872 defaultsideoverlap allli locali allm2 metal2 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4873
4874#metal2->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4875 defaultoverlap allm2 metal2 allm1 metal1 134
4876 defaultsideoverlap allm2 metal2 allm1 metal1 67
4877 defaultsideoverlap allm1 metal1 allm2 metal2 48
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4878
4879#metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4880 defaultsidewall allm3 metal3 63
4881 defaultoverlap allm3 metal3 nwell well 12
4882 defaultareacap allm3 metal3 nwell,obswell,pwell well 12
4883 defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4884
4885#metal3->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4886 defaultoverlap allm3 metal3 allactive active 12
4887 defaultsideoverlap allm3 metal3 allactive active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4888
4889#metal3->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4890 defaultoverlap allm3 metal3 allpolynonres active 16
4891 defaultsideoverlap allm3 metal3 allpolynonres active 44
4892 defaultsideoverlap *poly active allm3 metal3 9
4893
4894#metal3->locali
4895 defaultoverlap allm3 metal3 allli locali 21
4896 defaultsideoverlap allm3 metal3 allli locali 47
4897 defaultsideoverlap allli locali allm3 metal3 15
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4898
4899#metal3->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4900 defaultoverlap allm3 metal3 allm1 metal1 35
4901 defaultsideoverlap allm3 metal3 allm1 metal1 55
4902 defaultsideoverlap allm1 metal1 allm3 metal3 27
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4903
4904#metal3->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4905 defaultoverlap allm3 metal3 allm2 metal2 86
4906 defaultsideoverlap allm3 metal3 allm2 metal2 70
4907 defaultsideoverlap allm2 metal2 allm3 metal3 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4908
4909#ifdef METAL5
4910#metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4911 defaultsidewall allm4 metal4 67
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4912# defaultareacap alltopm metal4 well 6
4913 areacap allm4/m4 8
4914 defaultoverlap allm4 metal4 nwell well 8
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4915 defaultperimeter allm4 metal4 well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4916
4917#metal4->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4918 defaultoverlap allm4 metal4 allactivenonfet active 8
4919 defaultsideoverlap allm4 metal4 allactivenonfet active 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4920
4921#metal4->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4922 defaultoverlap allm4 metal4 allpolynonres active 10
4923 defaultsideoverlap allm4 metal4 allpolynonres active 38
4924 defaultsideoverlap *poly active allm4 metal4 6
4925
4926#metal4->locali
4927 defaultoverlap allm4 metal4 allli locali 12
4928 defaultsideoverlap allm4 metal4 allli locali 40
4929 defaultsideoverlap allli locali allm4 metal4 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4930
4931#metal4->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4932 defaultoverlap allm4 metal4 allm1 metal1 15
4933 defaultsideoverlap allm4 metal4 allm1 metal1 43
4934 defaultsideoverlap allm1 metal1 allm4 metal4 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4935
4936#metal4->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4937 defaultoverlap allm4 metal4 allm2 metal2 20
4938 defaultsideoverlap allm4 metal4 allm2 metal2 46
4939 defaultsideoverlap allm2 metal2 allm4 metal4 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4940
4941#metal4->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4942 defaultoverlap allm4 metal4 allm3 metal3 84
4943 defaultsideoverlap allm4 metal4 allm3 metal3 71
4944 defaultsideoverlap allm3 metal3 allm4 metal4 43
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4945
4946#metal5
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4947 defaultsidewall allm5 metal5 127
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4948# defaultareacap allm5 metal5 well 6
4949 areacap allm5/m5 6
4950 defaultoverlap allm5 metal5 nwell well 6
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4951 defaultperimeter allm5 metal5 well 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4952
4953#metal5->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4954 defaultoverlap allm5 metal5 allactivenonfet active 6
4955 defaultsideoverlap allm5 metal5 allactivenonfet active 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4956
4957#metal5->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4958 defaultoverlap allm5 metal5 allpolynonres active 7
4959 defaultsideoverlap allm5 metal5 allpolynonres active 40
4960 defaultsideoverlap *poly active allm5 metal5 6
4961
4962#metal5->locali
4963 defaultoverlap allm5 metal5 allli locali 8
4964 defaultsideoverlap allm5 metal5 allli locali 41
4965 defaultsideoverlap allli locali allm5 metal5 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4966
4967#metal5->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4968 defaultoverlap allm5 metal5 allm1 metal1 9
4969 defaultsideoverlap allm5 metal5 allm1 metal1 43
4970 defaultsideoverlap allm1 metal1 allm5 metal5 12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4971
4972#metal5->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4973 defaultoverlap allm5 metal5 allm2 metal2 11
4974 defaultsideoverlap allm5 metal5 allm2 metal2 46
4975 defaultsideoverlap allm2 metal2 allm5 metal5 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4976
4977#metal5->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4978 defaultoverlap allm5 metal5 allm3 metal3 20
4979 defaultsideoverlap allm5 metal5 allm3 metal3 54
4980 defaultsideoverlap allm3 metal3 allm5 metal5 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4981
4982#metal5->metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]4983 defaultoverlap allm5 metal5 allm4 metal4 68
4984 defaultsideoverlap allm5 metal5 allm4 metal4 83
4985 defaultsideoverlap allm4 metal4 allm5 metal5 47
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4986#endif (METAL5)
4987
Tim Edwards0a0272b2020-07-28 14:40:10 -0400[diff] [blame]4988#ifdef REDISTRIBUTION
4989#endif (REDISTRIBUTION)
4990
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4991# Devices: Base models (not subcircuit wrappers)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4992
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4993variants (),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]4994
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4995 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
4996 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]4997 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]4998 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
4999 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
5000 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
5001 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
5002 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5003 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5004 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5005
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5006 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5007 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5008 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5009 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5010 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
5011 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5012 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
5013 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5014 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5015 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5016 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5017 *nndiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5018 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5019 *nndiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5020 device subcircuit sky130_fd_pr__cap_var mvvaractor \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5021 *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5022
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5023 # Bipolars
5024 device msubcircuit sky130_fd_pr__npn_05v0 npn dnwell *ndiff space/w error a2=area
5025 device msubcircuit sky130_fd_pr__pnp_05v0 pnp pwell,space/w *pdiff a2=area
5026 device msubcircuit sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
5027
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5028 # Ignore the extended-drain FET geometry that forms part of the high-voltage
5029 # bipolar devices.
Tim Edwardsc40fe0f2020-10-26 13:11:45 -0400[diff] [blame]5030 device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
5031 device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]5032
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5033 # Extended drain devices (must appear before the regular devices)
5034 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
5035 dnwell pwell,space/w error l=l w=w
5036 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
5037 dnwell pwell,space/w error l=l w=w
5038 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
5039 pwell,space/w nwell error l=l w=w
5040
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5041 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
5042 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w
5043 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
5044 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
5045 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
5046 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5047 device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \
5048 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
5049 device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \
5050 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5051
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5052 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5053 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5054 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5055 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5056#ifdef METAL5
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5057 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5058 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5059#endif (METAL5)
5060
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5061 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5062 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5063 device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5064 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5065 device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5066 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5067 device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5068 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5069 device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5070 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5071 device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5072 xpc pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5073 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5074 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5075 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5076 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5077 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5078 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5079 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5080 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5081 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]5082 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5083 device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5084 xpc pwell,space/w error l=l w=w
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5085
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5086 device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5087 *ndiff pwell,space/w error l=l w=w
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5088 device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5089 *pdiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5090 device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5091 pwell dnwell error l=l w=w
Tim Edwards3c1dd9a2020-11-27 13:49:58 -0500[diff] [blame]5092 device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \
5093 *mvndiff pwell,space/w error l=l w=w
5094 device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \
5095 *mvpdiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5096
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5097 device resistor sky130_fd_pr__res_generic_po rmp *poly
5098 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5099
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5100 device subcircuit sky130_fd_pr__diode_pd2nw_05v5 *pdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5101 nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5102 device subcircuit sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt \
5103 nwell a=area
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]5104 device subcircuit sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt \
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5105 nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5106 device subcircuit sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5107 nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5108
5109 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5 *ndiode \
5110 pwell,space/w a=area
5111 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt \
5112 pwell,space/w a=area
5113 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode \
5114 pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5115 device msubcircuit sky130_fd_pr__diode_pw2nd_11v0 *mvndiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]5116 pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5117
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5118
5119#ifdef MIM
Tim Edwardsb1a18422020-10-02 08:51:29 -0400[diff] [blame]5120 device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
5121 device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5122#endif (MIM)
5123
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5124 variants (orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5125
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5126 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
5127 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
5128 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
5129 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5130 device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5131 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
5132 device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
5133 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5134 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
5135 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
5136 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
5137 pwell,space/w
5138
Tim Edwards40ea8a32020-12-09 13:33:40 -0500[diff] [blame]5139 # Note that corenvar, corepvar are not considered devices, and extract as
5140 # parasitic capacitance instead (but cap values need to be added).
5141
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5142 # Extended drain devices (must appear before the regular devices)
5143 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
5144 dnwell pwell,space/w error
5145 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
5146 dnwell pwell,space/w error
5147 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
5148 pwell,space/w nwell error
5149
5150 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5151 device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5152 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwards48e7c842020-12-22 17:11:51 -0500[diff] [blame]5153 device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5154 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5155
5156 # These devices always extract as subcircuits
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5157 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
5158 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
5159 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5160
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5161 device resistor sky130_fd_pr__res_generic_po rmp *poly
5162 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
5163 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
5164 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
5165 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5166#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5167 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
5168 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5169#endif (METAL5)
5170
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5171 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
5172 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
5173 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
5174 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
5175 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
5176 device resistor sky130_fd_pr__res_high_po xhrpoly xpc
5177 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
5178 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
5179 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
5180 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
5181 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
5182 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
5183 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
5184 device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
5185 device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5186 device resistor mrdn_hv mvndiffres *mvndiff
5187 device resistor mrdp_hv mvpdiffres *mvpdiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5188 device resistor sky130_fd_pr__res_iso_pw rpw pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5189
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5190 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5191 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
5192 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5193 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5194
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5195 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5196 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
5197 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]5198 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5199
Tim Edwards1021f552020-09-11 17:37:51 -0400[diff] [blame]5200 device bjt sky130_fd_pr__npn_05v5 npn dnwell *ndiff space/w error a2=area
5201 device bjt sky130_fd_pr__pnp_05v5 pnp pwell,space/w *pdiff a2=area
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]5202 device bjt sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5203
5204#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]5205 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
5206 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5207#endif (MIM)
5208
5209end
5210
5211#-----------------------------------------------------
5212# Wiring tool definitions
5213#-----------------------------------------------------
5214
5215wiring
5216 # All wiring values are in nanometers
5217 scalefactor 10
5218
Tim Edwardsc9b68fa2020-12-30 14:45:27 -0500[diff] [blame]5219 contact mcon 170 li 0 0 m1 30 60
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5220 contact v1 260 m1 0 30 m2 0 30
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5221 contact v2 280 m2 0 45 m3 25 0
5222#ifdef METAL5
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]5223 contact v3 320 m3 0 30 m4 5 5
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]5224 contact v4 1180 m4 0 m5 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5225#endif (METAL5)
5226
5227 contact pc 170 poly 50 80 li 0 80
5228 contact pdc 170 pdiff 40 60 li 0 80
5229 contact ndc 170 ndiff 40 60 li 0 80
5230 contact psc 170 psd 40 60 li 0 80
5231 contact nsc 170 nsd 40 60 li 0 80
5232
5233end
5234
5235#-----------------------------------------------------
5236# Plain old router. . .
5237#-----------------------------------------------------
5238
5239router
5240end
5241
5242#------------------------------------------------------------
5243# Plowing (restored in magic 8.2, need to fill this section)
5244#------------------------------------------------------------
5245
5246plowing
5247end
5248
5249#-----------------------------------------------------------------
5250# No special plot layers defined (use default PNM color choices)
5251#-----------------------------------------------------------------
5252
5253plot
5254 style pnm
5255 default
5256 draw fillblock no_color_at_all
Tim Edwards0e6036e2020-12-24 12:33:13 -0500[diff] [blame]5257 draw fillblock4 no_color_at_all
5258 draw fomfill no_color_at_all
5259 draw polyfill no_color_at_all
5260 draw m1fill no_color_at_all
5261 draw m2fill no_color_at_all
5262 draw m3fill no_color_at_all
5263 draw m4fill no_color_at_all
5264 draw m5fill no_color_at_all
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5265 draw nwell cwell
5266end
5267