Updated definition.json files
diff --git a/cells/ADDFX1/definition.json b/cells/ADDFX1/definition.json
index 76038db..a5f50e9 100644
--- a/cells/ADDFX1/definition.json
+++ b/cells/ADDFX1/definition.json
@@ -1,7 +1,7 @@
{
"description": "3-2 counter (full-adder) cell.",
"equation": "",
- "file_prefix": "sky130_osu_sc_ADDFX1",
+ "file_prefix": "sky130_osu_sc__ADDFX1",
"library": "sky130_osu_sc",
"name": "ADDFX1",
"parameters": [],
@@ -20,7 +20,7 @@
],
[
"signal",
- "C",
+ "CI",
"input",
""
],
@@ -47,8 +47,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_ADDFX1"
+ "verilog_name": "sky130_osu_sc__ADDFX1"
}
diff --git a/cells/ADDFXL/definition.json b/cells/ADDFXL/definition.json
index 962eb56..1219267 100644
--- a/cells/ADDFXL/definition.json
+++ b/cells/ADDFXL/definition.json
@@ -1,7 +1,7 @@
{
"description": "3-2 counter (full-adder) cell.",
"equation": "",
- "file_prefix": "sky130_osu_sc_ADDFXL",
+ "file_prefix": "sky130_osu_sc__ADDFXL",
"library": "sky130_osu_sc",
"name": "ADDFXL",
"parameters": [],
@@ -20,7 +20,7 @@
],
[
"signal",
- "C",
+ "CI",
"input",
""
],
@@ -47,8 +47,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_ADDFXL"
+ "verilog_name": "sky130_osu_sc__ADDFXL"
}
diff --git a/cells/ADDHX1/definition.json b/cells/ADDHX1/definition.json
index 3803d7a..a86f1e6 100644
--- a/cells/ADDHX1/definition.json
+++ b/cells/ADDHX1/definition.json
@@ -1,9 +1,9 @@
{
"description": "2-2 counter (half-adder) cell.",
"equation": "",
- "file_prefix": "sky130_osu_sc_ADDFXL",
+ "file_prefix": "sky130_osu_sc__ADDHX1",
"library": "sky130_osu_sc",
- "name": "ADDFXL",
+ "name": "ADDHX1",
"parameters": [],
"ports": [
[
@@ -41,8 +41,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_ADDFXL"
+ "verilog_name": "sky130_osu_sc__ADDHX1"
}
diff --git a/cells/ADDHXL/definition.json b/cells/ADDHXL/definition.json
index 506bbcc..05bd034 100644
--- a/cells/ADDHXL/definition.json
+++ b/cells/ADDHXL/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-2 counter (half-adder) cell.",
"equation": "",
- "file_prefix": "sky130_osu_sc_ADDHXL",
+ "file_prefix": "sky130_osu_sc__ADDHXL",
"library": "sky130_osu_sc",
"name": "ADDHXL",
"parameters": [],
@@ -41,8 +41,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_ADDHXL"
+ "verilog_name": "sky130_osu_sc__ADDHXL"
}
diff --git a/cells/AND2X1/definition.json b/cells/AND2X1/definition.json
index ad324df..35b8335 100644
--- a/cells/AND2X1/definition.json
+++ b/cells/AND2X1/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-input AND gate.",
"equation": "Y = A & B",
- "file_prefix": "sky130_osu_sc_AND2X1",
+ "file_prefix": "sky130_osu_sc__AND2X1",
"library": "sky130_osu_sc",
"name": "AND2X1",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_AND2X1"
+ "verilog_name": "sky130_osu_sc__AND2X1"
}
diff --git a/cells/AND2X2/definition.json b/cells/AND2X2/definition.json
index 6f3ea82..8a762dc 100644
--- a/cells/AND2X2/definition.json
+++ b/cells/AND2X2/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-input AND gate.",
"equation": "Y = A & B",
- "file_prefix": "sky130_osu_sc_AND2X2",
+ "file_prefix": "sky130_osu_sc__AND2X2",
"library": "sky130_osu_sc",
"name": "AND2X2",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_AND2X2"
+ "verilog_name": "sky130_osu_sc__AND2X2"
}
diff --git a/cells/AND2X4/definition.json b/cells/AND2X4/definition.json
index 75ab1b1..70c40f3 100644
--- a/cells/AND2X4/definition.json
+++ b/cells/AND2X4/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-input AND gate.",
"equation": "Y = A & B",
- "file_prefix": "sky130_osu_sc_AND2X4",
+ "file_prefix": "sky130_osu_sc__AND2X4",
"library": "sky130_osu_sc",
"name": "AND2X4",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_AND2X4"
+ "verilog_name": "sky130_osu_sc__AND2X4"
}
diff --git a/cells/AND2X8/definition.json b/cells/AND2X8/definition.json
index 085c39f..b664308 100644
--- a/cells/AND2X8/definition.json
+++ b/cells/AND2X8/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-input AND gate.",
"equation": "Y = A & B",
- "file_prefix": "sky130_osu_sc_AND2X8",
+ "file_prefix": "sky130_osu_sc__AND2X8",
"library": "sky130_osu_sc",
"name": "AND2X8",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_AND2X8"
+ "verilog_name": "sky130_osu_sc__AND2X8"
}
diff --git a/cells/AND2XL/definition.json b/cells/AND2XL/definition.json
index 6f36654..29c9bcc 100644
--- a/cells/AND2XL/definition.json
+++ b/cells/AND2XL/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-input AND gate.",
"equation": "Y = A & B",
- "file_prefix": "sky130_osu_sc_AND2XL",
+ "file_prefix": "sky130_osu_sc__AND2XL",
"library": "sky130_osu_sc",
"name": "AND2XL",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_AND2XL"
+ "verilog_name": "sky130_osu_sc__AND2XL"
}
diff --git a/cells/AND3XL/definition.json b/cells/AND3XL/definition.json
index af10367..5e567f2 100644
--- a/cells/AND3XL/definition.json
+++ b/cells/AND3XL/definition.json
@@ -1,7 +1,7 @@
{
"description": "3-input AND gate.",
"equation": "Y = A & B & C",
- "file_prefix": "sky130_osu_sc_AND3XL",
+ "file_prefix": "sky130_osu_sc__AND3XL",
"library": "sky130_osu_sc",
"name": "AND3XL",
"parameters": [],
@@ -41,8 +41,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_AND3XL"
+ "verilog_name": "sky130_osu_sc__AND3XL"
}
diff --git a/cells/ANT/definition.json b/cells/ANT/definition.json
index 13c7d25..d266f4e 100644
--- a/cells/ANT/definition.json
+++ b/cells/ANT/definition.json
@@ -1,7 +1,7 @@
{
"description": "Antenna-fixing diode cell.",
"equation": "",
- "file_prefix": "sky130_osu_sc_ANT",
+ "file_prefix": "sky130_osu_sc__ANT",
"library": "sky130_osu_sc",
"name": "ANT",
"parameters": [],
@@ -23,8 +23,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_ANT"
+ "verilog_name": "sky130_osu_sc__ANT"
}
diff --git a/cells/ANTFILL/definition.json b/cells/ANTFILL/definition.json
index cdeb5b7..ae4c2f3 100644
--- a/cells/ANTFILL/definition.json
+++ b/cells/ANTFILL/definition.json
@@ -1,7 +1,7 @@
{
"description": "Filler gate with same footprint as ANT.",
"equation": "",
- "file_prefix": "sky130_osu_sc_ANTFILL",
+ "file_prefix": "sky130_osu_sc__ANTFILL",
"library": "sky130_osu_sc",
"name": "ANTFILL",
"parameters": [],
@@ -17,8 +17,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_ANTFILL"
+ "verilog_name": "sky130_osu_sc__ANTFILL"
}
diff --git a/cells/AOI21XL/definition.json b/cells/AOI21XL/definition.json
index c918b1e..a31940e 100644
--- a/cells/AOI21XL/definition.json
+++ b/cells/AOI21XL/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-1 and-or-invert",
"equation": "(!A0 + !A1) * (!B0)",
- "file_prefix": "sky130_osu_sc_AOI21XL",
+ "file_prefix": "sky130_osu_sc__AOI21XL",
"library": "sky130_osu_sc",
"name": "AOI21XL",
"parameters": [],
@@ -41,8 +41,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_AOI21XL"
+ "verilog_name": "sky130_osu_sc__AOI21XL"
}
diff --git a/cells/BUFX1/definition.json b/cells/BUFX1/definition.json
index f0d2397..f70d86e 100644
--- a/cells/BUFX1/definition.json
+++ b/cells/BUFX1/definition.json
@@ -1,7 +1,7 @@
{
- "description": "Buffer.",
+ "description": "Buffer",
"equation": "Y = A",
- "file_prefix": "sky130_osu_sc_BUFX1",
+ "file_prefix": "sky130_osu_sc__BUFX1",
"library": "sky130_osu_sc",
"name": "BUFX1",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_BUFX1"
+ "verilog_name": "sky130_osu_sc__BUFX1"
}
diff --git a/cells/BUFX2/definition.json b/cells/BUFX2/definition.json
index 54c3737..f8b8ff7 100644
--- a/cells/BUFX2/definition.json
+++ b/cells/BUFX2/definition.json
@@ -1,7 +1,7 @@
{
- "description": "Buffer.",
+ "description": "Buffer",
"equation": "Y = A",
- "file_prefix": "sky130_osu_sc_BUFX2",
+ "file_prefix": "sky130_osu_sc__BUFX2",
"library": "sky130_osu_sc",
"name": "BUFX2",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_BUFX2"
+ "verilog_name": "sky130_osu_sc__BUFX2"
}
diff --git a/cells/BUFX4/definition.json b/cells/BUFX4/definition.json
index 79a75ae..a4d46cb 100644
--- a/cells/BUFX4/definition.json
+++ b/cells/BUFX4/definition.json
@@ -1,7 +1,7 @@
{
- "description": "Buffer.",
+ "description": "Buffer",
"equation": "Y = A",
- "file_prefix": "sky130_osu_sc_BUFX4",
+ "file_prefix": "sky130_osu_sc__BUFX4",
"library": "sky130_osu_sc",
"name": "BUFX4",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_BUFX4"
+ "verilog_name": "sky130_osu_sc__BUFX4"
}
diff --git a/cells/BUFX6/definition.json b/cells/BUFX6/definition.json
index 99da318..b60fa20 100644
--- a/cells/BUFX6/definition.json
+++ b/cells/BUFX6/definition.json
@@ -1,7 +1,7 @@
{
- "description": "Buffer.",
+ "description": "Buffer",
"equation": "Y = A",
- "file_prefix": "sky130_osu_sc_BUFX6",
+ "file_prefix": "sky130_osu_sc__BUFX6",
"library": "sky130_osu_sc",
"name": "BUFX6",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_BUFX6"
+ "verilog_name": "sky130_osu_sc__BUFX6"
}
diff --git a/cells/BUFX8/definition.json b/cells/BUFX8/definition.json
index da3155b..cbfa0ce 100644
--- a/cells/BUFX8/definition.json
+++ b/cells/BUFX8/definition.json
@@ -1,7 +1,7 @@
{
- "description": "Buffer.",
+ "description": "Buffer",
"equation": "Y = A",
- "file_prefix": "sky130_osu_sc_BUFX8",
+ "file_prefix": "sky130_osu_sc__BUFX8",
"library": "sky130_osu_sc",
"name": "BUFX8",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_BUFX8"
+ "verilog_name": "sky130_osu_sc__BUFX8"
}
diff --git a/cells/BUFXL/definition.json b/cells/BUFXL/definition.json
index 1dd7051..8bcdc59 100644
--- a/cells/BUFXL/definition.json
+++ b/cells/BUFXL/definition.json
@@ -1,7 +1,7 @@
{
- "description": "Buffer.",
+ "description": "Buffer",
"equation": "Y = A",
- "file_prefix": "sky130_osu_sc_BUFXL",
+ "file_prefix": "sky130_osu_sc__BUFXL",
"library": "sky130_osu_sc",
"name": "BUFXL",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_BUFXL"
+ "verilog_name": "sky130_osu_sc__BUFXL"
}
diff --git a/cells/CLKBUFX1/definition.json b/cells/CLKBUFX1/definition.json
index 2b80e0a..fde7bfb 100644
--- a/cells/CLKBUFX1/definition.json
+++ b/cells/CLKBUFX1/definition.json
@@ -1,7 +1,7 @@
{
"description": "Clock buffer.",
"equation": "Y = A",
- "file_prefix": "sky130_osu_sc_CLKBUFX1",
+ "file_prefix": "sky130_osu_sc__CLKBUFX1",
"library": "sky130_osu_sc",
"name": "CLKBUFX1",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_CLKBUFX1"
+ "verilog_name": "sky130_osu_sc__CLKBUFX1"
}
diff --git a/cells/CLKINVX1/definition.json b/cells/CLKINVX1/definition.json
new file mode 100644
index 0000000..7672d74
--- /dev/null
+++ b/cells/CLKINVX1/definition.json
@@ -0,0 +1,37 @@
+ {
+ "description": "clock inverter.",
+ "equation": "Y = ~A",
+ "file_prefix": "sky130_osu_sc__CLKINVX1",
+ "library": "sky130_osu_sc",
+ "name": "CLKINVX1",
+ "parameters": [],
+ "ports": [
+ [
+ "signal",
+ "Y",
+ "output",
+ ""
+ ],
+ [
+ "signal",
+ "A",
+ "input",
+ ""
+ ],
+ [
+ "power",
+ "VDD",
+ "input",
+ "supply1"
+ ],
+ [
+ "power",
+ "GND",
+ "input",
+ "supply0"
+ ]
+ ],
+ "type": "cell",
+ "verilog_name": "sky130_osu_sc__CLKINVX1"
+ }
+
diff --git a/cells/CLKINVX2/definition.json b/cells/CLKINVX2/definition.json
new file mode 100644
index 0000000..4c4d7d2
--- /dev/null
+++ b/cells/CLKINVX2/definition.json
@@ -0,0 +1,37 @@
+{
+ "description": "clock inverter.",
+ "equation": "Y = ~A",
+ "file_prefix": "sky130_osu_sc__CLKINVX2",
+ "library": "sky130_osu_sc",
+ "name": "CLKINVX2",
+ "parameters": [],
+ "ports": [
+ [
+ "signal",
+ "Y",
+ "output",
+ ""
+ ],
+ [
+ "signal",
+ "A",
+ "input",
+ ""
+ ],
+ [
+ "power",
+ "VDD",
+ "input",
+ "supply1"
+ ],
+ [
+ "power",
+ "GND",
+ "input",
+ "supply0"
+ ]
+ ],
+ "type": "cell",
+ "verilog_name": "sky130_osu_sc__CLKINVX2"
+ }
+
diff --git a/cells/CLKINVX4/definition.json b/cells/CLKINVX4/definition.json
new file mode 100644
index 0000000..5a4e04d
--- /dev/null
+++ b/cells/CLKINVX4/definition.json
@@ -0,0 +1,37 @@
+{
+ "description": "clock inverter.",
+ "equation": "Y = ~A",
+ "file_prefix": "sky130_osu_sc__CLKINVX4",
+ "library": "sky130_osu_sc",
+ "name": "CLKINVX4",
+ "parameters": [],
+ "ports": [
+ [
+ "signal",
+ "Y",
+ "output",
+ ""
+ ],
+ [
+ "signal",
+ "A",
+ "input",
+ ""
+ ],
+ [
+ "power",
+ "VDD",
+ "input",
+ "supply1"
+ ],
+ [
+ "power",
+ "GND",
+ "input",
+ "supply0"
+ ]
+ ],
+ "type": "cell",
+ "verilog_name": "sky130_osu_sc__CLKINVX4"
+ }
+
diff --git a/cells/DECAPX1/definition.json b/cells/DECAPX1/definition.json
index 76b3836..57d942a 100644
--- a/cells/DECAPX1/definition.json
+++ b/cells/DECAPX1/definition.json
@@ -1,7 +1,7 @@
{
"description": "Decoupling capacitor.",
"equation": "",
- "file_prefix": "sky130_osu_sc_DECAPX1",
+ "file_prefix": "sky130_osu_sc__DECAPX1",
"library": "sky130_osu_sc",
"name": "DECAPX1",
"parameters": [],
@@ -17,8 +17,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_DECAPX1"
+ "verilog_name": "sky130_osu_sc__DECAPX1"
}
diff --git a/cells/DECAPXL/definition.json b/cells/DECAPXL/definition.json
index 6132ce9..6868a19 100644
--- a/cells/DECAPXL/definition.json
+++ b/cells/DECAPXL/definition.json
@@ -1,7 +1,7 @@
{
"description": "Decoupling capacitor.",
"equation": "",
- "file_prefix": "sky130_osu_sc_DECAPXL",
+ "file_prefix": "sky130_osu_sc__DECAPXL",
"library": "sky130_osu_sc",
"name": "DECAPXL",
"parameters": [],
@@ -17,8 +17,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_DECAPXL"
+ "verilog_name": "sky130_osu_sc__DECAPXL"
}
diff --git a/cells/DFFNX1/definition.json b/cells/DFFNX1/definition.json
index 912e772..3ff0c80 100644
--- a/cells/DFFNX1/definition.json
+++ b/cells/DFFNX1/definition.json
@@ -1,7 +1,7 @@
{
"description": "D flip-flop, negative-edge triggered.",
"equation": "",
- "file_prefix": "sky130_osu_sc_DFFNX1",
+ "file_prefix": "sky130_osu_sc__DFFNX1",
"library": "sky130_osu_sc",
"name": "DFFNX1",
"parameters": [],
@@ -14,7 +14,7 @@
],
[
"signal",
- "CK",
+ "CLK",
"input",
""
],
@@ -41,8 +41,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_DFFNX1"
+ "verilog_name": "sky130_osu_sc__DFFNX1"
}
diff --git a/cells/DFFNXL/definition.json b/cells/DFFNXL/definition.json
index 3638ffc..ad726ec 100644
--- a/cells/DFFNXL/definition.json
+++ b/cells/DFFNXL/definition.json
@@ -1,7 +1,7 @@
{
"description": "D flip-flop, negative-edge triggered.",
"equation": "",
- "file_prefix": "sky130_osu_sc_DFFNXL",
+ "file_prefix": "sky130_osu_sc__DFFNXL",
"library": "sky130_osu_sc",
"name": "DFFNXL",
"parameters": [],
@@ -14,7 +14,7 @@
],
[
"signal",
- "CK",
+ "CLK",
"input",
""
],
@@ -41,8 +41,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_DFFNXL"
+ "verilog_name": "sky130_osu_sc__DFFNXL"
}
diff --git a/cells/DFFRX1/definition.json b/cells/DFFRX1/definition.json
index 7c59c86..62e83b9 100644
--- a/cells/DFFRX1/definition.json
+++ b/cells/DFFRX1/definition.json
@@ -1,9 +1,9 @@
{
"description": "D flip-flop, negative-edge triggered, active-low async reset.",
"equation": "",
- "file_prefix": "sky130_osu_sc_DFFRXL",
+ "file_prefix": "sky130_osu_sc__DFFRX1",
"library": "sky130_osu_sc",
- "name": "DFFRXL",
+ "name": "DFFRX1",
"parameters": [],
"ports": [
[
@@ -47,8 +47,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_DFFRXL"
+ "verilog_name": "sky130_osu_sc__DFFRX1"
}
diff --git a/cells/DFFRXL/definition.json b/cells/DFFRXL/definition.json
index 7c59c86..d3b75b5 100644
--- a/cells/DFFRXL/definition.json
+++ b/cells/DFFRXL/definition.json
@@ -1,7 +1,7 @@
{
"description": "D flip-flop, negative-edge triggered, active-low async reset.",
"equation": "",
- "file_prefix": "sky130_osu_sc_DFFRXL",
+ "file_prefix": "sky130_osu_sc__DFFRXL",
"library": "sky130_osu_sc",
"name": "DFFRXL",
"parameters": [],
@@ -47,8 +47,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_DFFRXL"
+ "verilog_name": "sky130_osu_sc__DFFRXL"
}
diff --git a/cells/DFFSX1/definition.json b/cells/DFFSX1/definition.json
index eecf846..5d49bc4 100644
--- a/cells/DFFSX1/definition.json
+++ b/cells/DFFSX1/definition.json
@@ -1,7 +1,7 @@
{
"description": "D flip-flop, negative-edge triggered, active-low async set.",
"equation": "",
- "file_prefix": "sky130_osu_sc_DFFSX1",
+ "file_prefix": "sky130_osu_sc__DFFSX1",
"library": "sky130_osu_sc",
"name": "DFFSX1",
"parameters": [],
@@ -14,7 +14,7 @@
],
[
"signal",
- "S",
+ "SN",
"input",
""
],
@@ -47,8 +47,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_DFFSX1"
+ "verilog_name": "sky130_osu_sc__DFFSX1"
}
diff --git a/cells/DFFSXL/definition.json b/cells/DFFSXL/definition.json
index 9b884d0..a669006 100644
--- a/cells/DFFSXL/definition.json
+++ b/cells/DFFSXL/definition.json
@@ -1,7 +1,7 @@
{
"description": "D flip-flop, negative-edge triggered, active-low async set.",
"equation": "",
- "file_prefix": "sky130_osu_sc_DFFSXL",
+ "file_prefix": "sky130_osu_sc__DFFSXL",
"library": "sky130_osu_sc",
"name": "DFFSXL",
"parameters": [],
@@ -14,7 +14,7 @@
],
[
"signal",
- "S",
+ "SN",
"input",
""
],
@@ -47,8 +47,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_DFFSXL"
+ "verilog_name": "sky130_osu_sc__DFFSXL"
}
diff --git a/cells/DFFX1/definition.json b/cells/DFFX1/definition.json
index bca68cd..d0624db 100644
--- a/cells/DFFX1/definition.json
+++ b/cells/DFFX1/definition.json
@@ -1,7 +1,7 @@
{
"description": "D flip-flop, positive edge triggered.",
"equation": "",
- "file_prefix": "sky130_osu_sc_DFFX1",
+ "file_prefix": "sky130_osu_sc__DFFX1",
"library": "sky130_osu_sc",
"name": "DFFX1",
"parameters": [],
@@ -41,8 +41,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_DFFX1"
+ "verilog_name": "sky130_osu_sc__DFFX1"
}
diff --git a/cells/DFFXL/definition.json b/cells/DFFXL/definition.json
index c1f7356..99bd0a3 100644
--- a/cells/DFFXL/definition.json
+++ b/cells/DFFXL/definition.json
@@ -1,7 +1,7 @@
{
"description": "D flip-flop, positive edge triggered.",
"equation": "",
- "file_prefix": "sky130_osu_sc_DFFXL",
+ "file_prefix": "sky130_osu_sc__DFFXL",
"library": "sky130_osu_sc",
"name": "DFFXL",
"parameters": [],
@@ -41,8 +41,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_DFFXL"
+ "verilog_name": "sky130_osu_sc__DFFXL"
}
diff --git a/cells/DLY1/definition.json b/cells/DLY1/definition.json
index 44d27b9..e3e3c3f 100644
--- a/cells/DLY1/definition.json
+++ b/cells/DLY1/definition.json
@@ -1,7 +1,7 @@
{
"description": "Delay cell.",
"equation": "Y = A",
- "file_prefix": "sky130_osu_sc_DLY1",
+ "file_prefix": "sky130_osu_sc__DLY1",
"library": "sky130_osu_sc",
"name": "DLY1",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_DLY1"
+ "verilog_name": "sky130_osu_sc__DLY1"
}
diff --git a/cells/DLY2/definition.json b/cells/DLY2/definition.json
index d34cabc..6819d04 100644
--- a/cells/DLY2/definition.json
+++ b/cells/DLY2/definition.json
@@ -1,7 +1,7 @@
{
"description": "Delay cell.",
"equation": "Y = A",
- "file_prefix": "sky130_osu_sc_DLY2",
+ "file_prefix": "sky130_osu_sc__DLY2",
"library": "sky130_osu_sc",
"name": "DLY2",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_DLY2"
+ "verilog_name": "sky130_osu_sc__DLY2"
}
diff --git a/cells/DLY3/definition.json b/cells/DLY3/definition.json
index e0e175d..bd209fe 100644
--- a/cells/DLY3/definition.json
+++ b/cells/DLY3/definition.json
@@ -1,7 +1,7 @@
{
"description": "Delay cell.",
"equation": "Y = A",
- "file_prefix": "sky130_osu_sc_DLY3",
+ "file_prefix": "sky130_osu_sc__DLY3",
"library": "sky130_osu_sc",
"name": "DLY3",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_DLY3"
+ "verilog_name": "sky130_osu_sc__DLY3"
}
diff --git a/cells/DLY4/definition.json b/cells/DLY4/definition.json
index 4f48527..ab583dc 100644
--- a/cells/DLY4/definition.json
+++ b/cells/DLY4/definition.json
@@ -1,7 +1,7 @@
{
"description": "Delay cell.",
"equation": "Y = A",
- "file_prefix": "sky130_osu_sc_DLY4",
+ "file_prefix": "sky130_osu_sc__DLY4",
"library": "sky130_osu_sc",
"name": "DLY4",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_DLY4"
+ "verilog_name": "sky130_osu_sc__DLY4"
}
diff --git a/cells/FILLX1/definition.json b/cells/FILLX1/definition.json
index e5e4095..521da92 100644
--- a/cells/FILLX1/definition.json
+++ b/cells/FILLX1/definition.json
@@ -1,7 +1,7 @@
{
"description": "Filler cell.",
"equation": "",
- "file_prefix": "sky130_osu_sc_FILLX1",
+ "file_prefix": "sky130_osu_sc__FILLX1",
"library": "sky130_osu_sc",
"name": "FILLX1",
"parameters": [],
@@ -17,8 +17,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_FILLX1"
+ "verilog_name": "sky130_osu_sc__FILLX1"
}
diff --git a/cells/FILLX16/definition.json b/cells/FILLX16/definition.json
index 90d8cd2..7e66a83 100644
--- a/cells/FILLX16/definition.json
+++ b/cells/FILLX16/definition.json
@@ -1,7 +1,7 @@
{
"description": "Filler cell.",
"equation": "",
- "file_prefix": "sky130_osu_sc_FILLX16",
+ "file_prefix": "sky130_osu_sc__FILLX16",
"library": "sky130_osu_sc",
"name": "FILLX16",
"parameters": [],
@@ -17,8 +17,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_FILLX16"
+ "verilog_name": "sky130_osu_sc__FILLX16"
}
diff --git a/cells/FILLX2/definition.json b/cells/FILLX2/definition.json
index d419c56..0d542f6 100644
--- a/cells/FILLX2/definition.json
+++ b/cells/FILLX2/definition.json
@@ -1,7 +1,7 @@
{
"description": "Filler cell.",
"equation": "",
- "file_prefix": "sky130_osu_sc_FILLX2",
+ "file_prefix": "sky130_osu_sc__FILLX2",
"library": "sky130_osu_sc",
"name": "FILLX2",
"parameters": [],
@@ -17,8 +17,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_FILLX2"
+ "verilog_name": "sky130_osu_sc__FILLX2"
}
diff --git a/cells/FILLX32/definition.json b/cells/FILLX32/definition.json
index 84506de..9bdb284 100644
--- a/cells/FILLX32/definition.json
+++ b/cells/FILLX32/definition.json
@@ -1,7 +1,7 @@
{
"description": "Filler cell.",
"equation": "",
- "file_prefix": "sky130_osu_sc_FILLX32",
+ "file_prefix": "sky130_osu_sc__FILLX32",
"library": "sky130_osu_sc",
"name": "FILLX32",
"parameters": [],
@@ -17,8 +17,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_FILLX32"
+ "verilog_name": "sky130_osu_sc__FILLX32"
}
diff --git a/cells/FILLX4/definition.json b/cells/FILLX4/definition.json
index b0c9d80..6aaa9e3 100644
--- a/cells/FILLX4/definition.json
+++ b/cells/FILLX4/definition.json
@@ -1,7 +1,7 @@
{
"description": "Filler cell.",
"equation": "",
- "file_prefix": "sky130_osu_sc_FILLX4",
+ "file_prefix": "sky130_osu_sc__FILLX4",
"library": "sky130_osu_sc",
"name": "FILLX4",
"parameters": [],
@@ -17,8 +17,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_FILLX4"
+ "verilog_name": "sky130_osu_sc__FILLX4"
}
diff --git a/cells/FILLX8/definition.json b/cells/FILLX8/definition.json
index b5d4ceb..190f269 100644
--- a/cells/FILLX8/definition.json
+++ b/cells/FILLX8/definition.json
@@ -1,7 +1,7 @@
{
"description": "Filler cell.",
"equation": "",
- "file_prefix": "sky130_osu_sc_FILLX8",
+ "file_prefix": "sky130_osu_sc__FILLX8",
"library": "sky130_osu_sc",
"name": "FILLX8",
"parameters": [],
@@ -17,8 +17,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_FILLX8"
+ "verilog_name": "sky130_osu_sc__FILLX8"
}
diff --git a/cells/INVX1/definition.json b/cells/INVX1/definition.json
index bd44e54..2010adb 100644
--- a/cells/INVX1/definition.json
+++ b/cells/INVX1/definition.json
@@ -1,7 +1,7 @@
{
"description": "Inverter.",
"equation": "Y = ~A",
- "file_prefix": "sky130_osu_sc_INVX1",
+ "file_prefix": "sky130_osu_sc__INVX1",
"library": "sky130_osu_sc",
"name": "INVX1",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_INVX1"
+ "verilog_name": "sky130_osu_sc__INVX1"
}
diff --git a/cells/INVX10/definition.json b/cells/INVX10/definition.json
index 7a69ee1..341a076 100644
--- a/cells/INVX10/definition.json
+++ b/cells/INVX10/definition.json
@@ -1,7 +1,7 @@
{
"description": "Inverter.",
"equation": "Y = ~A",
- "file_prefix": "sky130_osu_sc_INVX10",
+ "file_prefix": "sky130_osu_sc__INVX10",
"library": "sky130_osu_sc",
"name": "INVX10",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_INVX10"
+ "verilog_name": "sky130_osu_sc__INVX10"
}
diff --git a/cells/INVX2/definition.json b/cells/INVX2/definition.json
index 2004541..29ef5f1 100644
--- a/cells/INVX2/definition.json
+++ b/cells/INVX2/definition.json
@@ -1,7 +1,7 @@
{
"description": "Inverter.",
"equation": "Y = ~A",
- "file_prefix": "sky130_osu_sc_INVX2",
+ "file_prefix": "sky130_osu_sc__INVX2",
"library": "sky130_osu_sc",
"name": "INVX2",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_INVX2"
+ "verilog_name": "sky130_osu_sc__INVX2"
}
diff --git a/cells/INVX3/definition.json b/cells/INVX3/definition.json
index e6ce223..b0d4209 100644
--- a/cells/INVX3/definition.json
+++ b/cells/INVX3/definition.json
@@ -1,7 +1,7 @@
{
"description": "Inverter.",
"equation": "Y = ~A",
- "file_prefix": "sky130_osu_sc_INVX3",
+ "file_prefix": "sky130_osu_sc__INVX3",
"library": "sky130_osu_sc",
"name": "INVX3",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_INVX3"
+ "verilog_name": "sky130_osu_sc__INVX3"
}
diff --git a/cells/INVX4/definition.json b/cells/INVX4/definition.json
index e6ce223..4fd4523 100644
--- a/cells/INVX4/definition.json
+++ b/cells/INVX4/definition.json
@@ -1,9 +1,9 @@
{
"description": "Inverter.",
"equation": "Y = ~A",
- "file_prefix": "sky130_osu_sc_INVX3",
+ "file_prefix": "sky130_osu_sc__INVX4",
"library": "sky130_osu_sc",
- "name": "INVX3",
+ "name": "INVX4",
"parameters": [],
"ports": [
[
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_INVX3"
+ "verilog_name": "sky130_osu_sc__INVX4"
}
diff --git a/cells/INVX6/definition.json b/cells/INVX6/definition.json
index 625f46a..4671903 100644
--- a/cells/INVX6/definition.json
+++ b/cells/INVX6/definition.json
@@ -1,7 +1,7 @@
{
"description": "Inverter.",
"equation": "Y = ~A",
- "file_prefix": "sky130_osu_sc_INVX6",
+ "file_prefix": "sky130_osu_sc__INVX6",
"library": "sky130_osu_sc",
"name": "INVX6",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_INVX6"
+ "verilog_name": "sky130_osu_sc__INVX6"
}
diff --git a/cells/INVX8/definition.json b/cells/INVX8/definition.json
index 33de586..3ed6618 100644
--- a/cells/INVX8/definition.json
+++ b/cells/INVX8/definition.json
@@ -1,7 +1,7 @@
{
"description": "Inverter.",
"equation": "Y = ~A",
- "file_prefix": "sky130_osu_sc_INVX8",
+ "file_prefix": "sky130_osu_sc__INVX8",
"library": "sky130_osu_sc",
"name": "INVX8",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_INVX8"
+ "verilog_name": "sky130_osu_sc__INVX8"
}
diff --git a/cells/INVXL/definition.json b/cells/INVXL/definition.json
index 3ffdb07..813c4e8 100644
--- a/cells/INVXL/definition.json
+++ b/cells/INVXL/definition.json
@@ -1,7 +1,7 @@
{
"description": "Inverter.",
"equation": "Y = ~A",
- "file_prefix": "sky130_osu_sc_INVXL",
+ "file_prefix": "sky130_osu_sc__INVXL",
"library": "sky130_osu_sc",
"name": "INVXL",
"parameters": [],
@@ -29,8 +29,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_INVXL"
+ "verilog_name": "sky130_osu_sc__INVXL"
}
diff --git a/cells/NAND2X1/definition.json b/cells/NAND2X1/definition.json
index db53af2..54618ee 100644
--- a/cells/NAND2X1/definition.json
+++ b/cells/NAND2X1/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-input NAND gate.",
"equation": "Y = !(A & B)",
- "file_prefix": "sky130_osu_sc_NAND2X1",
+ "file_prefix": "sky130_osu_sc__NAND2X1",
"library": "sky130_osu_sc",
"name": "NAND2X1",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_NAND2X1"
+ "verilog_name": "sky130_osu_sc__NAND2X1"
}
diff --git a/cells/NAND2XL/definition.json b/cells/NAND2XL/definition.json
index 18a8886..fca5a1b 100644
--- a/cells/NAND2XL/definition.json
+++ b/cells/NAND2XL/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-input NAND gate.",
"equation": "Y = !(A & B)",
- "file_prefix": "sky130_osu_sc_NAND2XL",
+ "file_prefix": "sky130_osu_sc__NAND2XL",
"library": "sky130_osu_sc",
"name": "NAND2XL",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_NAND2XL"
+ "verilog_name": "sky130_osu_sc__NAND2XL"
}
diff --git a/cells/NAND3X1/definition.json b/cells/NAND3X1/definition.json
index 3b04eb9..e67d97c 100644
--- a/cells/NAND3X1/definition.json
+++ b/cells/NAND3X1/definition.json
@@ -1,7 +1,7 @@
{
"description": "3-input NAND gate.",
"equation": "Y = !(A & B & C)",
- "file_prefix": "sky130_osu_sc_NAND3X1",
+ "file_prefix": "sky130_osu_sc__NAND3X1",
"library": "sky130_osu_sc",
"name": "NAND3X1",
"parameters": [],
@@ -41,8 +41,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_NAND3X1"
+ "verilog_name": "sky130_osu_sc__NAND3X1"
}
diff --git a/cells/NAND3XL/definition.json b/cells/NAND3XL/definition.json
index 993af21..2e57614 100644
--- a/cells/NAND3XL/definition.json
+++ b/cells/NAND3XL/definition.json
@@ -1,7 +1,7 @@
{
"description": "3-input NAND gate.",
"equation": "Y = !(A & B & C)",
- "file_prefix": "sky130_osu_sc_NAND3XL",
+ "file_prefix": "sky130_osu_sc__NAND3XL",
"library": "sky130_osu_sc",
"name": "NAND3XL",
"parameters": [],
@@ -41,8 +41,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_NAND3XL"
+ "verilog_name": "sky130_osu_sc__NAND3XL"
}
diff --git a/cells/NAND4XL/definition.json b/cells/NAND4XL/definition.json
index 255a0eb..762a7ee 100644
--- a/cells/NAND4XL/definition.json
+++ b/cells/NAND4XL/definition.json
@@ -1,7 +1,7 @@
{
- "description": "2-input NAND gate.",
+ "description": "4-input NAND gate.",
"equation": "Y = A & B & C & D",
- "file_prefix": "sky130_osu_sc_NAND4XL",
+ "file_prefix": "sky130_osu_sc__NAND4XL",
"library": "sky130_osu_sc",
"name": "NAND4XL",
"parameters": [],
@@ -47,8 +47,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_NAND4XL"
+ "verilog_name": "sky130_osu_sc__NAND4XL"
}
diff --git a/cells/NOR2X1/definition.json b/cells/NOR2X1/definition.json
index 78b5c67..b5d6f4a 100644
--- a/cells/NOR2X1/definition.json
+++ b/cells/NOR2X1/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-input NOR gate.",
"equation": "Y = !(A | B)",
- "file_prefix": "sky130_osu_sc_NOR2X1",
+ "file_prefix": "sky130_osu_sc__NOR2X1",
"library": "sky130_osu_sc",
"name": "NOR2X1",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_NOR2X1"
+ "verilog_name": "sky130_osu_sc__NOR2X1"
}
diff --git a/cells/NOR2XL/definition.json b/cells/NOR2XL/definition.json
index b7a1ed7..4061ab4 100644
--- a/cells/NOR2XL/definition.json
+++ b/cells/NOR2XL/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-input NOR gate.",
"equation": "Y = !(A | B)",
- "file_prefix": "sky130_osu_sc_NOR2XL",
+ "file_prefix": "sky130_osu_sc__NOR2XL",
"library": "sky130_osu_sc",
"name": "NOR2XL",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_NOR2XL"
+ "verilog_name": "sky130_osu_sc__NOR2XL"
}
diff --git a/cells/OAI21XL/definition.json b/cells/OAI21XL/definition.json
index 90c28e6..7e5dac6 100644
--- a/cells/OAI21XL/definition.json
+++ b/cells/OAI21XL/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-1 and-or-invert",
"equation": "(!A0 * !A1) + (!B0)",
- "file_prefix": "sky130_osu_sc_OAI21XL",
+ "file_prefix": "sky130_osu_sc__OAI21XL",
"library": "sky130_osu_sc",
"name": "OAI21XL",
"parameters": [],
@@ -14,13 +14,13 @@
],
[
"signal",
- "B1",
+ "A1",
"input",
""
],
[
"signal",
- "B0",
+ "B1",
"input",
""
],
@@ -41,8 +41,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_OAI21XL"
+ "verilog_name": "sky130_osu_sc__OAI21XL"
}
diff --git a/cells/OR2X1/definition.json b/cells/OR2X1/definition.json
index 8d1f389..caf6595 100644
--- a/cells/OR2X1/definition.json
+++ b/cells/OR2X1/definition.json
@@ -1,9 +1,9 @@
{
"description": "2-input OR gate.",
"equation": "Y = A | B",
- "file_prefix": "sky130_osu_sc_OR2XL",
+ "file_prefix": "sky130_osu_sc__OR2X1",
"library": "sky130_osu_sc",
- "name": "OR2XL",
+ "name": "OR2X1",
"parameters": [],
"ports": [
[
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_OR2XL"
+ "verilog_name": "sky130_osu_sc__OR2X1"
}
diff --git a/cells/OR2X2/definition.json b/cells/OR2X2/definition.json
index e3c6237..e6b5b39 100644
--- a/cells/OR2X2/definition.json
+++ b/cells/OR2X2/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-input OR gate.",
"equation": "Y = A | B",
- "file_prefix": "sky130_osu_sc_OR2X2",
+ "file_prefix": "sky130_osu_sc__OR2X2",
"library": "sky130_osu_sc",
"name": "OR2X2",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_OR2X2"
+ "verilog_name": "sky130_osu_sc__OR2X2"
}
diff --git a/cells/OR2X4/definition.json b/cells/OR2X4/definition.json
index 4552f79..5e49023 100644
--- a/cells/OR2X4/definition.json
+++ b/cells/OR2X4/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-input OR gate.",
"equation": "Y = A | B",
- "file_prefix": "sky130_osu_sc_OR2X4",
+ "file_prefix": "sky130_osu_sc__OR2X4",
"library": "sky130_osu_sc",
"name": "OR2X4",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_OR2X4"
+ "verilog_name": "sky130_osu_sc__OR2X4"
}
diff --git a/cells/OR2XL/definition.json b/cells/OR2XL/definition.json
index 8d1f389..12fe0ed 100644
--- a/cells/OR2XL/definition.json
+++ b/cells/OR2XL/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-input OR gate.",
"equation": "Y = A | B",
- "file_prefix": "sky130_osu_sc_OR2XL",
+ "file_prefix": "sky130_osu_sc__OR2XL",
"library": "sky130_osu_sc",
"name": "OR2XL",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_OR2XL"
+ "verilog_name": "sky130_osu_sc__OR2XL"
}
diff --git a/cells/TBUFXL/definition.json b/cells/TBUFXL/definition.json
index 0b9c1ea..d71e017 100644
--- a/cells/TBUFXL/definition.json
+++ b/cells/TBUFXL/definition.json
@@ -1,7 +1,7 @@
{
"description": "Active high tri-state buffer.",
"equation": "Y = A",
- "file_prefix": "sky130_osu_sc_TBUFXL",
+ "file_prefix": "sky130_osu_sc__TBUFXL",
"library": "sky130_osu_sc",
"name": "TBUFXL",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_TBUFXL"
+ "verilog_name": "sky130_osu_sc__TBUFXL"
}
diff --git a/cells/TIEHI/definition.json b/cells/TIEHI/definition.json
index 3a4c99a..d8d750f 100644
--- a/cells/TIEHI/definition.json
+++ b/cells/TIEHI/definition.json
@@ -1,7 +1,7 @@
{
"description": "TIEHI gate.",
"equation": "Y = 1",
- "file_prefix": "sky130_osu_sc_TIEHI",
+ "file_prefix": "sky130_osu_sc__TIEHI",
"library": "sky130_osu_sc",
"name": "TIEHI",
"parameters": [],
@@ -23,8 +23,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_TIEHI"
+ "verilog_name": "sky130_osu_sc__TIEHI"
}
diff --git a/cells/TIELO/definition.json b/cells/TIELO/definition.json
index 6a92cf7..de1b477 100644
--- a/cells/TIELO/definition.json
+++ b/cells/TIELO/definition.json
@@ -1,7 +1,7 @@
{
"description": "TIELO gate.",
"equation": "Y = 0",
- "file_prefix": "sky130_osu_sc_TIELO",
+ "file_prefix": "sky130_osu_sc__TIELO",
"library": "sky130_osu_sc",
"name": "TIELO",
"parameters": [],
@@ -23,8 +23,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_TIELO"
+ "verilog_name": "sky130_osu_sc__TIELO"
}
diff --git a/cells/TNBUFXL/definition.json b/cells/TNBUFXL/definition.json
index f21bd09..54f6aad 100644
--- a/cells/TNBUFXL/definition.json
+++ b/cells/TNBUFXL/definition.json
@@ -1,7 +1,7 @@
{
"description": "Active high tri-state inverting buffer.",
"equation": "Y = !A",
- "file_prefix": "sky130_osu_sc_TNBUFXL",
+ "file_prefix": "sky130_osu_sc__TNBUFXL",
"library": "sky130_osu_sc",
"name": "TNBUFXL",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_TNBUFXL"
+ "verilog_name": "sky130_osu_sc__TNBUFXL"
}
diff --git a/cells/XNOR2XL/definition.json b/cells/XNOR2XL/definition.json
index cae1eb5..10155eb 100644
--- a/cells/XNOR2XL/definition.json
+++ b/cells/XNOR2XL/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-input inverting XOR gate.",
"equation": "Y = !(A ^ B)",
- "file_prefix": "sky130_osu_sc_XNOR2XL",
+ "file_prefix": "sky130_osu_sc__XNOR2XL",
"library": "sky130_osu_sc",
"name": "XNOR2XL",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_XNOR2XL"
+ "verilog_name": "sky130_osu_sc__XNOR2XL"
}
diff --git a/cells/XOR2XL/definition.json b/cells/XOR2XL/definition.json
index a116fb2..2010b37 100644
--- a/cells/XOR2XL/definition.json
+++ b/cells/XOR2XL/definition.json
@@ -1,7 +1,7 @@
{
"description": "2-input XOR gate.",
"equation": "Y = A ^ B",
- "file_prefix": "sky130_osu_sc_XOR2XL",
+ "file_prefix": "sky130_osu_sc__XOR2XL",
"library": "sky130_osu_sc",
"name": "XOR2XL",
"parameters": [],
@@ -35,8 +35,8 @@
"GND",
"input",
"supply0"
- ],
+ ]
],
"type": "cell",
- "verilog_name": "sky130_osu_sc_XOR2XL"
+ "verilog_name": "sky130_osu_sc__XOR2XL"
}
