cells/AND3XL/definition.json

{
 "description": "3-input AND gate.",
 "equation": "Y = A & B & C",
 "file_prefix": "sky130_osu_sc__AND3XL",
 "library": "sky130_osu_sc",
 "name": "AND3XL",
 "parameters": [],
 "ports": [
  [
   "signal",
   "Y",
   "output",
   ""
  ],
  [
   "signal",
   "A",
   "input",
   ""
  ],
  [
   "signal",
   "B",
   "input",
   ""
  ],
  [
   "signal",
   "C",
   "input",
   ""
  ],
  [
   "power",
   "VDD",
   "input",
   "supply1"
  ],
  [
   "power",
   "GND",
   "input",
   "supply0"
  ]
 ],
 "type": "cell",
 "verilog_name": "sky130_osu_sc__AND3XL"
}