cells/CLKINVX2/definition.json

{
    "description": "clock inverter.",
    "equation": "Y = ~A",
    "file_prefix": "sky130_osu_sc__CLKINVX2",
    "library": "sky130_osu_sc",
    "name": "CLKINVX2",
    "parameters": [],
    "ports": [
     [
      "signal",
      "Y",
      "output",
      ""
     ],
     [
      "signal",
      "A",
      "input",
      ""
     ],
     [
      "power",
      "VDD",
      "input",
      "supply1"
     ],
     [
      "power",
      "GND",
      "input",
      "supply0"
     ]
    ],
    "type": "cell",
    "verilog_name": "sky130_osu_sc__CLKINVX2"
   }