Updates to spice, PEX and PXI files as well as the addition of lvs reports
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_1.lvs.report b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.lvs.report
new file mode 100644
index 0000000..a007600
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.lvs.report
@@ -0,0 +1,485 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a2111o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a2111o_1.sp ('sky130_fd_sc_ms__a2111o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice ('sky130_fd_sc_ms__a2111o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:49:18 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a2111o_1     sky130_fd_sc_ms__a2111o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a2111o_1
+SOURCE CELL NAME:         sky130_fd_sc_ms__a2111o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1 C1 D1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pex.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pex.spice
index a274fce..63b7c62 100644
--- a/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111o_1.pex.spice
-* Created: Fri Aug 28 16:55:21 2020
+* Created: Wed Sep  2 11:49:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pxi.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pxi.spice
index b10a8c1..93d5867 100644
--- a/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111o_1.pxi.spice
-* Created: Fri Aug 28 16:55:21 2020
+* Created: Wed Sep  2 11:49:21 2020
 * 
 x_PM_SKY130_FD_SC_MS__A2111O_1%A1 N_A1_c_73_n N_A1_M1010_g N_A1_M1002_g A1 A1
 + N_A1_c_76_n N_A1_c_77_n N_A1_c_78_n PM_SKY130_FD_SC_MS__A2111O_1%A1
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice
index 924608a..34d7342 100644
--- a/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice
+++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111o_1.spice
-* Created: Fri Aug 28 16:55:21 2020
+* Created: Wed Sep  2 11:49:21 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_2.lvs.report b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.lvs.report
new file mode 100644
index 0000000..027179c
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.lvs.report
@@ -0,0 +1,492 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a2111o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a2111o_2.sp ('sky130_fd_sc_ms__a2111o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice ('sky130_fd_sc_ms__a2111o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:49:24 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a2111o_2     sky130_fd_sc_ms__a2111o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a2111o_2
+SOURCE CELL NAME:         sky130_fd_sc_ms__a2111o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pex.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pex.spice
index dd1155d..42ce939 100644
--- a/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111o_2.pex.spice
-* Created: Fri Aug 28 16:55:31 2020
+* Created: Wed Sep  2 11:49:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pxi.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pxi.spice
index 03b8f26..2566fb7 100644
--- a/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111o_2.pxi.spice
-* Created: Fri Aug 28 16:55:31 2020
+* Created: Wed Sep  2 11:49:27 2020
 * 
 x_PM_SKY130_FD_SC_MS__A2111O_2%A_91_244# N_A_91_244#_M1013_s N_A_91_244#_M1003_d
 + N_A_91_244#_M1011_d N_A_91_244#_M1001_s N_A_91_244#_M1004_g N_A_91_244#_c_87_n
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice
index 6c8fd3b..d7433a0 100644
--- a/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice
+++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111o_2.spice
-* Created: Fri Aug 28 16:55:31 2020
+* Created: Wed Sep  2 11:49:27 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_4.lvs.report b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.lvs.report
new file mode 100644
index 0000000..543234b
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.lvs.report
@@ -0,0 +1,506 @@
+
+LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice"
+
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a2111o_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a2111o_4.sp ('sky130_fd_sc_ms__a2111o_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice ('sky130_fd_sc_ms__a2111o_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:49:31 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a2111o_4     sky130_fd_sc_ms__a2111o_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a2111o_4
+SOURCE CELL NAME:         sky130_fd_sc_ms__a2111o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:         14        14         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           4          4            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 12.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pex.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pex.spice
index e0f58af..5375763 100644
--- a/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111o_4.pex.spice
-* Created: Fri Aug 28 16:55:40 2020
+* Created: Wed Sep  2 11:49:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pxi.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pxi.spice
index a9dc724..388b420 100644
--- a/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111o_4.pxi.spice
-* Created: Fri Aug 28 16:55:40 2020
+* Created: Wed Sep  2 11:49:33 2020
 * 
 x_PM_SKY130_FD_SC_MS__A2111O_4%A_137_260# N_A_137_260#_M1011_d
 + N_A_137_260#_M1004_s N_A_137_260#_M1009_s N_A_137_260#_M1001_d
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice
index ca19369..414b5f3 100644
--- a/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice
+++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111o_4.spice
-* Created: Fri Aug 28 16:55:40 2020
+* Created: Wed Sep  2 11:49:33 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.lvs.report b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.lvs.report
new file mode 100644
index 0000000..cf79ad7
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a2111oi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a2111oi_1.sp ('sky130_fd_sc_ms__a2111oi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.spice ('sky130_fd_sc_ms__a2111oi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:49:37 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a2111oi_1    sky130_fd_sc_ms__a2111oi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a2111oi_1
+SOURCE CELL NAME:         sky130_fd_sc_ms__a2111oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pex.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pex.spice
index 76f4def..3ad186a 100644
--- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111oi_1.pex.spice
-* Created: Fri Aug 28 16:55:49 2020
+* Created: Wed Sep  2 11:49:40 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pxi.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pxi.spice
index 7803545..bc02651 100644
--- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111oi_1.pxi.spice
-* Created: Fri Aug 28 16:55:49 2020
+* Created: Wed Sep  2 11:49:40 2020
 * 
 x_PM_SKY130_FD_SC_MS__A2111OI_1%D1 N_D1_M1007_g N_D1_M1003_g D1 N_D1_c_60_n
 + N_D1_c_61_n PM_SKY130_FD_SC_MS__A2111OI_1%D1
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.spice
index 52d4c62..52d4e5d 100644
--- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.spice
+++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111oi_1.spice
-* Created: Fri Aug 28 16:55:49 2020
+* Created: Wed Sep  2 11:49:40 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.lvs.report b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.lvs.report
new file mode 100644
index 0000000..67b9a65
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a2111oi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a2111oi_2.sp ('sky130_fd_sc_ms__a2111oi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.spice ('sky130_fd_sc_ms__a2111oi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:49:43 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a2111oi_2    sky130_fd_sc_ms__a2111oi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a2111oi_2
+SOURCE CELL NAME:         sky130_fd_sc_ms__a2111oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:          7         7         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        18        17
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   14 layout mos transistors were reduced to 7.
+     7 mos transistors were deleted by parallel reduction.
+   14 source mos transistors were reduced to 7.
+     7 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pex.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pex.spice
index e55fbeb..c3a980d 100644
--- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111oi_2.pex.spice
-* Created: Fri Aug 28 16:55:58 2020
+* Created: Wed Sep  2 11:49:46 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pxi.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pxi.spice
index 02fe4d6..1fb1acc 100644
--- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111oi_2.pxi.spice
-* Created: Fri Aug 28 16:55:58 2020
+* Created: Wed Sep  2 11:49:46 2020
 * 
 x_PM_SKY130_FD_SC_MS__A2111OI_2%D1 N_D1_M1003_g N_D1_M1007_g N_D1_M1004_g D1 D1
 + N_D1_c_92_n PM_SKY130_FD_SC_MS__A2111OI_2%D1
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.spice
index cbe0cbf..f943d46 100644
--- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.spice
+++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111oi_2.spice
-* Created: Fri Aug 28 16:55:58 2020
+* Created: Wed Sep  2 11:49:46 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.lvs.report b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.lvs.report
new file mode 100644
index 0000000..49f72e9
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a2111oi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a2111oi_4.sp ('sky130_fd_sc_ms__a2111oi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.spice ('sky130_fd_sc_ms__a2111oi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:49:50 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a2111oi_4    sky130_fd_sc_ms__a2111oi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a2111oi_4
+SOURCE CELL NAME:         sky130_fd_sc_ms__a2111oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              14        14
+
+ Instances:         14        14         MN (4 pins)
+                    20        20         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        35        34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1_1 (7 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   34 layout mos transistors were reduced to 10.
+     24 mos transistors were deleted by parallel reduction.
+   34 source mos transistors were reduced to 10.
+     24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pex.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pex.spice
index e196fb8..4f56a07 100644
--- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111oi_4.pex.spice
-* Created: Fri Aug 28 16:56:28 2020
+* Created: Wed Sep  2 11:49:52 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pxi.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pxi.spice
index 54a53e1..89a8d3a 100644
--- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111oi_4.pxi.spice
-* Created: Fri Aug 28 16:56:28 2020
+* Created: Wed Sep  2 11:49:52 2020
 * 
 x_PM_SKY130_FD_SC_MS__A2111OI_4%D1 N_D1_M1021_g N_D1_M1022_g N_D1_M1026_g
 + N_D1_c_142_n N_D1_M1017_g N_D1_c_143_n N_D1_M1029_g N_D1_M1031_g D1 D1 D1
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.spice
index 9625235..c74d289 100644
--- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.spice
+++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a2111oi_4.spice
-* Created: Fri Aug 28 16:56:28 2020
+* Created: Wed Sep  2 11:49:52 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_1.lvs.report b/cells/a211o/sky130_fd_sc_ms__a211o_1.lvs.report
new file mode 100644
index 0000000..ab2a5e4
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_ms__a211o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a211o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a211o_1.sp ('sky130_fd_sc_ms__a211o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a211o/sky130_fd_sc_ms__a211o_1.spice ('sky130_fd_sc_ms__a211o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:49:56 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a211o_1      sky130_fd_sc_ms__a211o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a211o_1
+SOURCE CELL NAME:         sky130_fd_sc_ms__a211o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_1.pex.spice b/cells/a211o/sky130_fd_sc_ms__a211o_1.pex.spice
index e2d7ed6..b5e9de8 100644
--- a/cells/a211o/sky130_fd_sc_ms__a211o_1.pex.spice
+++ b/cells/a211o/sky130_fd_sc_ms__a211o_1.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211o_1.pex.spice
-* Created: Fri Aug 28 16:56:38 2020
+* Created: Wed Sep  2 11:49:59 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_1.pxi.spice b/cells/a211o/sky130_fd_sc_ms__a211o_1.pxi.spice
index bce9c50..8981bee 100644
--- a/cells/a211o/sky130_fd_sc_ms__a211o_1.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_ms__a211o_1.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211o_1.pxi.spice
-* Created: Fri Aug 28 16:56:38 2020
+* Created: Wed Sep  2 11:49:59 2020
 * 
 x_PM_SKY130_FD_SC_MS__A211O_1%A_81_264# N_A_81_264#_M1008_d N_A_81_264#_M1004_d
 + N_A_81_264#_M1001_d N_A_81_264#_M1007_g N_A_81_264#_M1000_g N_A_81_264#_c_66_n
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_1.spice b/cells/a211o/sky130_fd_sc_ms__a211o_1.spice
index 207d1cd..2176f70 100644
--- a/cells/a211o/sky130_fd_sc_ms__a211o_1.spice
+++ b/cells/a211o/sky130_fd_sc_ms__a211o_1.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211o_1.spice
-* Created: Fri Aug 28 16:56:38 2020
+* Created: Wed Sep  2 11:49:59 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_2.lvs.report b/cells/a211o/sky130_fd_sc_ms__a211o_2.lvs.report
new file mode 100644
index 0000000..f256c73
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_ms__a211o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a211o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a211o_2.sp ('sky130_fd_sc_ms__a211o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a211o/sky130_fd_sc_ms__a211o_2.spice ('sky130_fd_sc_ms__a211o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:50:03 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a211o_2      sky130_fd_sc_ms__a211o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a211o_2
+SOURCE CELL NAME:         sky130_fd_sc_ms__a211o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 C1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_2.pex.spice b/cells/a211o/sky130_fd_sc_ms__a211o_2.pex.spice
index b7983ea..624e1fe 100644
--- a/cells/a211o/sky130_fd_sc_ms__a211o_2.pex.spice
+++ b/cells/a211o/sky130_fd_sc_ms__a211o_2.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211o_2.pex.spice
-* Created: Fri Aug 28 16:56:47 2020
+* Created: Wed Sep  2 11:50:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_2.pxi.spice b/cells/a211o/sky130_fd_sc_ms__a211o_2.pxi.spice
index e6f4da8..3aeabea 100644
--- a/cells/a211o/sky130_fd_sc_ms__a211o_2.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_ms__a211o_2.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211o_2.pxi.spice
-* Created: Fri Aug 28 16:56:47 2020
+* Created: Wed Sep  2 11:50:05 2020
 * 
 x_PM_SKY130_FD_SC_MS__A211O_2%A_85_270# N_A_85_270#_M1001_d N_A_85_270#_M1009_d
 + N_A_85_270#_M1006_d N_A_85_270#_M1010_g N_A_85_270#_M1004_g
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_2.spice b/cells/a211o/sky130_fd_sc_ms__a211o_2.spice
index 06fe3a9..53f6554 100644
--- a/cells/a211o/sky130_fd_sc_ms__a211o_2.spice
+++ b/cells/a211o/sky130_fd_sc_ms__a211o_2.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211o_2.spice
-* Created: Fri Aug 28 16:56:47 2020
+* Created: Wed Sep  2 11:50:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_4.lvs.report b/cells/a211o/sky130_fd_sc_ms__a211o_4.lvs.report
new file mode 100644
index 0000000..3587cc8
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_ms__a211o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a211o_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a211o_4.sp ('sky130_fd_sc_ms__a211o_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a211o/sky130_fd_sc_ms__a211o_4.spice ('sky130_fd_sc_ms__a211o_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:50:09 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a211o_4      sky130_fd_sc_ms__a211o_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a211o_4
+SOURCE CELL NAME:         sky130_fd_sc_ms__a211o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              13        13
+
+ Instances:         12        12         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        25        24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   24 layout mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+   24 source mos transistors were reduced to 10.
+     14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 C1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_4.pex.spice b/cells/a211o/sky130_fd_sc_ms__a211o_4.pex.spice
index 6abfd2b..86ddd67 100644
--- a/cells/a211o/sky130_fd_sc_ms__a211o_4.pex.spice
+++ b/cells/a211o/sky130_fd_sc_ms__a211o_4.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211o_4.pex.spice
-* Created: Fri Aug 28 16:56:56 2020
+* Created: Wed Sep  2 11:50:12 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_4.pxi.spice b/cells/a211o/sky130_fd_sc_ms__a211o_4.pxi.spice
index 6815851..be24969 100644
--- a/cells/a211o/sky130_fd_sc_ms__a211o_4.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_ms__a211o_4.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211o_4.pxi.spice
-* Created: Fri Aug 28 16:56:56 2020
+* Created: Wed Sep  2 11:50:12 2020
 * 
 x_PM_SKY130_FD_SC_MS__A211O_4%A_105_280# N_A_105_280#_M1005_d
 + N_A_105_280#_M1021_d N_A_105_280#_M1002_d N_A_105_280#_M1009_d
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_4.spice b/cells/a211o/sky130_fd_sc_ms__a211o_4.spice
index b90b325..d5ced42 100644
--- a/cells/a211o/sky130_fd_sc_ms__a211o_4.spice
+++ b/cells/a211o/sky130_fd_sc_ms__a211o_4.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211o_4.spice
-* Created: Fri Aug 28 16:56:56 2020
+* Created: Wed Sep  2 11:50:12 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_1.lvs.report b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.lvs.report
new file mode 100644
index 0000000..79800ac
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a211oi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a211oi_1.sp ('sky130_fd_sc_ms__a211oi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a211oi/sky130_fd_sc_ms__a211oi_1.spice ('sky130_fd_sc_ms__a211oi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:50:16 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a211oi_1     sky130_fd_sc_ms__a211oi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a211oi_1
+SOURCE CELL NAME:         sky130_fd_sc_ms__a211oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pex.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pex.spice
index 0d3ddb8..bdb35c7 100644
--- a/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211oi_1.pex.spice
-* Created: Fri Aug 28 16:57:05 2020
+* Created: Wed Sep  2 11:50:18 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pxi.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pxi.spice
index a377506..c9d199a 100644
--- a/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211oi_1.pxi.spice
-* Created: Fri Aug 28 16:57:05 2020
+* Created: Wed Sep  2 11:50:18 2020
 * 
 x_PM_SKY130_FD_SC_MS__A211OI_1%A2 N_A2_M1005_g N_A2_M1003_g A2 N_A2_c_52_n
 + N_A2_c_53_n PM_SKY130_FD_SC_MS__A211OI_1%A2
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_1.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.spice
index e2ddb4e..77e5418 100644
--- a/cells/a211oi/sky130_fd_sc_ms__a211oi_1.spice
+++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211oi_1.spice
-* Created: Fri Aug 28 16:57:05 2020
+* Created: Wed Sep  2 11:50:18 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_2.lvs.report b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.lvs.report
new file mode 100644
index 0000000..71cbbb4
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a211oi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a211oi_2.sp ('sky130_fd_sc_ms__a211oi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a211oi/sky130_fd_sc_ms__a211oi_2.spice ('sky130_fd_sc_ms__a211oi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:50:22 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a211oi_2     sky130_fd_sc_ms__a211oi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a211oi_2
+SOURCE CELL NAME:         sky130_fd_sc_ms__a211oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:          6         6         MN (4 pins)
+                     8         8         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pex.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pex.spice
index c9eceea..24acffc 100644
--- a/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211oi_2.pex.spice
-* Created: Fri Aug 28 16:57:34 2020
+* Created: Wed Sep  2 11:50:25 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pxi.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pxi.spice
index b7a8569..bdc1c27 100644
--- a/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211oi_2.pxi.spice
-* Created: Fri Aug 28 16:57:34 2020
+* Created: Wed Sep  2 11:50:25 2020
 * 
 x_PM_SKY130_FD_SC_MS__A211OI_2%A1 N_A1_M1010_g N_A1_c_79_n N_A1_M1007_g
 + N_A1_M1011_g N_A1_c_81_n N_A1_M1009_g A1 N_A1_c_83_n
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_2.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.spice
index f266de1..0e415d3 100644
--- a/cells/a211oi/sky130_fd_sc_ms__a211oi_2.spice
+++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211oi_2.spice
-* Created: Fri Aug 28 16:57:34 2020
+* Created: Wed Sep  2 11:50:25 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_4.lvs.report b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.lvs.report
new file mode 100644
index 0000000..557e18a
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a211oi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a211oi_4.sp ('sky130_fd_sc_ms__a211oi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a211oi/sky130_fd_sc_ms__a211oi_4.spice ('sky130_fd_sc_ms__a211oi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:50:28 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a211oi_4     sky130_fd_sc_ms__a211oi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a211oi_4
+SOURCE CELL NAME:         sky130_fd_sc_ms__a211oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:              12        12
+
+ Instances:         12        12         MN (4 pins)
+                    16        16         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        29        28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              9         9
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1_1 (6 pins)
+                ------    ------
+ Total Inst:         4         4
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               9          9            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1_1
+                  -------    -------    ---------    ---------
+   Total Inst:          4          4            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   28 layout mos transistors were reduced to 8.
+     20 mos transistors were deleted by parallel reduction.
+   28 source mos transistors were reduced to 8.
+     20 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pex.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pex.spice
index e64db34..3e312de 100644
--- a/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211oi_4.pex.spice
-* Created: Fri Aug 28 16:57:43 2020
+* Created: Wed Sep  2 11:50:31 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pxi.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pxi.spice
index 604315f..0692723 100644
--- a/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211oi_4.pxi.spice
-* Created: Fri Aug 28 16:57:43 2020
+* Created: Wed Sep  2 11:50:31 2020
 * 
 x_PM_SKY130_FD_SC_MS__A211OI_4%A2 N_A2_M1006_g N_A2_M1003_g N_A2_M1009_g
 + N_A2_M1005_g N_A2_M1011_g N_A2_M1010_g N_A2_M1016_g N_A2_M1012_g A2 A2 A2 A2
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_4.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.spice
index d721eac..7cab312 100644
--- a/cells/a211oi/sky130_fd_sc_ms__a211oi_4.spice
+++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a211oi_4.spice
-* Created: Fri Aug 28 16:57:43 2020
+* Created: Wed Sep  2 11:50:31 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_1.lvs.report b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.lvs.report
new file mode 100644
index 0000000..8664121
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a21bo_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a21bo_1.sp ('sky130_fd_sc_ms__a21bo_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21bo/sky130_fd_sc_ms__a21bo_1.spice ('sky130_fd_sc_ms__a21bo_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:50:35 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a21bo_1      sky130_fd_sc_ms__a21bo_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a21bo_1
+SOURCE CELL NAME:         sky130_fd_sc_ms__a21bo_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1_N VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pex.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pex.spice
index b15499e..d047161 100644
--- a/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21bo_1.pex.spice
-* Created: Fri Aug 28 16:57:52 2020
+* Created: Wed Sep  2 11:50:38 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pxi.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pxi.spice
index 828bf31..2ba28f8 100644
--- a/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21bo_1.pxi.spice
-* Created: Fri Aug 28 16:57:52 2020
+* Created: Wed Sep  2 11:50:38 2020
 * 
 x_PM_SKY130_FD_SC_MS__A21BO_1%A2 N_A2_c_75_n N_A2_M1006_g N_A2_M1002_g
 + N_A2_c_78_n A2 N_A2_c_79_n PM_SKY130_FD_SC_MS__A21BO_1%A2
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_1.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.spice
index e8f64a6..4535001 100644
--- a/cells/a21bo/sky130_fd_sc_ms__a21bo_1.spice
+++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21bo_1.spice
-* Created: Fri Aug 28 16:57:52 2020
+* Created: Wed Sep  2 11:50:38 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_2.lvs.report b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.lvs.report
new file mode 100644
index 0000000..d051597
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a21bo_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a21bo_2.sp ('sky130_fd_sc_ms__a21bo_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21bo/sky130_fd_sc_ms__a21bo_2.spice ('sky130_fd_sc_ms__a21bo_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:50:41 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a21bo_2      sky130_fd_sc_ms__a21bo_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a21bo_2
+SOURCE CELL NAME:         sky130_fd_sc_ms__a21bo_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1_N A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pex.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pex.spice
index 1f80591..d6d7c0e 100644
--- a/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21bo_2.pex.spice
-* Created: Fri Aug 28 16:58:00 2020
+* Created: Wed Sep  2 11:50:44 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pxi.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pxi.spice
index 37a627a..06bfdbb 100644
--- a/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21bo_2.pxi.spice
-* Created: Fri Aug 28 16:58:00 2020
+* Created: Wed Sep  2 11:50:44 2020
 * 
 x_PM_SKY130_FD_SC_MS__A21BO_2%B1_N N_B1_N_M1001_g N_B1_N_c_74_n N_B1_N_M1010_g
 + B1_N N_B1_N_c_75_n N_B1_N_c_76_n PM_SKY130_FD_SC_MS__A21BO_2%B1_N
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_2.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.spice
index d5a85d5..ad19a6c 100644
--- a/cells/a21bo/sky130_fd_sc_ms__a21bo_2.spice
+++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21bo_2.spice
-* Created: Fri Aug 28 16:58:00 2020
+* Created: Wed Sep  2 11:50:44 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_4.lvs.report b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.lvs.report
new file mode 100644
index 0000000..b8298d9
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a21bo_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a21bo_4.sp ('sky130_fd_sc_ms__a21bo_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21bo/sky130_fd_sc_ms__a21bo_4.spice ('sky130_fd_sc_ms__a21bo_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:50:48 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a21bo_4      sky130_fd_sc_ms__a21bo_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a21bo_4
+SOURCE CELL NAME:         sky130_fd_sc_ms__a21bo_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              12        12
+
+ Instances:         11        11         MN (4 pins)
+                    11        11         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     2         2         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         7         7
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:               10         10            0            0
+
+   Instances:           3          3            0            0    MN(NLOWVT)
+                        2          2            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          7          7            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1_N A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pex.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pex.spice
index 04e4aeb..456750f 100644
--- a/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21bo_4.pex.spice
-* Created: Fri Aug 28 16:58:09 2020
+* Created: Wed Sep  2 11:50:50 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pxi.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pxi.spice
index 37d4dbe..c799c42 100644
--- a/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21bo_4.pxi.spice
-* Created: Fri Aug 28 16:58:09 2020
+* Created: Wed Sep  2 11:50:50 2020
 * 
 x_PM_SKY130_FD_SC_MS__A21BO_4%B1_N N_B1_N_M1016_g N_B1_N_M1009_g N_B1_N_c_115_n
 + B1_N N_B1_N_c_117_n PM_SKY130_FD_SC_MS__A21BO_4%B1_N
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_4.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.spice
index e65c355..2eafcf2 100644
--- a/cells/a21bo/sky130_fd_sc_ms__a21bo_4.spice
+++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21bo_4.spice
-* Created: Fri Aug 28 16:58:09 2020
+* Created: Wed Sep  2 11:50:50 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_1.lvs.report b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.lvs.report
new file mode 100644
index 0000000..b67edb7
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a21boi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a21boi_1.sp ('sky130_fd_sc_ms__a21boi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21boi/sky130_fd_sc_ms__a21boi_1.spice ('sky130_fd_sc_ms__a21boi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:50:54 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a21boi_1     sky130_fd_sc_ms__a21boi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a21boi_1
+SOURCE CELL NAME:         sky130_fd_sc_ms__a21boi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1_N A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pex.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pex.spice
index 4c747fa..3fb6593 100644
--- a/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21boi_1.pex.spice
-* Created: Fri Aug 28 16:58:38 2020
+* Created: Wed Sep  2 11:50:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pxi.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pxi.spice
index ca0a5db..b3c399a 100644
--- a/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21boi_1.pxi.spice
-* Created: Fri Aug 28 16:58:38 2020
+* Created: Wed Sep  2 11:50:57 2020
 * 
 x_PM_SKY130_FD_SC_MS__A21BOI_1%B1_N N_B1_N_c_60_n N_B1_N_M1007_g N_B1_N_c_61_n
 + N_B1_N_c_62_n N_B1_N_M1001_g B1_N B1_N B1_N N_B1_N_c_63_n N_B1_N_c_64_n
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_1.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.spice
index 3ba2ab0..20da2f6 100644
--- a/cells/a21boi/sky130_fd_sc_ms__a21boi_1.spice
+++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21boi_1.spice
-* Created: Fri Aug 28 16:58:38 2020
+* Created: Wed Sep  2 11:50:57 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_2.lvs.report b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.lvs.report
new file mode 100644
index 0000000..0ece6b3
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a21boi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a21boi_2.sp ('sky130_fd_sc_ms__a21boi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21boi/sky130_fd_sc_ms__a21boi_2.spice ('sky130_fd_sc_ms__a21boi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:51:00 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a21boi_2     sky130_fd_sc_ms__a21boi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a21boi_2
+SOURCE CELL NAME:         sky130_fd_sc_ms__a21boi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   12 layout mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+   12 source mos transistors were reduced to 6.
+     6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1_N A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pex.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pex.spice
index 22a6a52..098014c 100644
--- a/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21boi_2.pex.spice
-* Created: Fri Aug 28 16:58:47 2020
+* Created: Wed Sep  2 11:51:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pxi.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pxi.spice
index e0e12d4..e389ef4 100644
--- a/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21boi_2.pxi.spice
-* Created: Fri Aug 28 16:58:47 2020
+* Created: Wed Sep  2 11:51:03 2020
 * 
 x_PM_SKY130_FD_SC_MS__A21BOI_2%B1_N N_B1_N_M1010_g N_B1_N_M1003_g N_B1_N_c_84_n
 + N_B1_N_c_85_n B1_N PM_SKY130_FD_SC_MS__A21BOI_2%B1_N
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_2.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.spice
index 68f5091..6963a30 100644
--- a/cells/a21boi/sky130_fd_sc_ms__a21boi_2.spice
+++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21boi_2.spice
-* Created: Fri Aug 28 16:58:47 2020
+* Created: Wed Sep  2 11:51:03 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_4.lvs.report b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.lvs.report
new file mode 100644
index 0000000..3c3c507
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a21boi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a21boi_4.sp ('sky130_fd_sc_ms__a21boi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21boi/sky130_fd_sc_ms__a21boi_4.spice ('sky130_fd_sc_ms__a21boi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:51:07 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a21boi_4     sky130_fd_sc_ms__a21boi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a21boi_4
+SOURCE CELL NAME:         sky130_fd_sc_ms__a21boi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:         13        13         MN (4 pins)
+                    14        14         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        28        27
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   26 layout mos transistors were reduced to 7.
+     19 mos transistors were deleted by parallel reduction.
+   26 source mos transistors were reduced to 7.
+     19 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A1 A2 B1_N VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pex.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pex.spice
index ac82c44..b8be4d3 100644
--- a/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21boi_4.pex.spice
-* Created: Fri Aug 28 16:58:57 2020
+* Created: Wed Sep  2 11:51:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pxi.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pxi.spice
index 5f3c5f4..ec7b7c5 100644
--- a/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21boi_4.pxi.spice
-* Created: Fri Aug 28 16:58:57 2020
+* Created: Wed Sep  2 11:51:10 2020
 * 
 x_PM_SKY130_FD_SC_MS__A21BOI_4%A1 N_A1_M1008_g N_A1_M1003_g N_A1_M1009_g
 + N_A1_M1005_g N_A1_M1010_g N_A1_M1006_g N_A1_M1014_g N_A1_M1015_g A1 A1 A1 A1
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_4.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.spice
index 5ff5554..2cc175f 100644
--- a/cells/a21boi/sky130_fd_sc_ms__a21boi_4.spice
+++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21boi_4.spice
-* Created: Fri Aug 28 16:58:57 2020
+* Created: Wed Sep  2 11:51:10 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_1.lvs.report b/cells/a21o/sky130_fd_sc_ms__a21o_1.lvs.report
new file mode 100644
index 0000000..e7f11b7
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_ms__a21o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a21o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a21o_1.sp ('sky130_fd_sc_ms__a21o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21o/sky130_fd_sc_ms__a21o_1.spice ('sky130_fd_sc_ms__a21o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:51:14 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a21o_1       sky130_fd_sc_ms__a21o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a21o_1
+SOURCE CELL NAME:         sky130_fd_sc_ms__a21o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          4         4         MN (4 pins)
+                     4         4         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         9         8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_1.pex.spice b/cells/a21o/sky130_fd_sc_ms__a21o_1.pex.spice
index ea1e74e..23bddaa 100644
--- a/cells/a21o/sky130_fd_sc_ms__a21o_1.pex.spice
+++ b/cells/a21o/sky130_fd_sc_ms__a21o_1.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21o_1.pex.spice
-* Created: Fri Aug 28 16:59:05 2020
+* Created: Wed Sep  2 11:51:16 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_1.pxi.spice b/cells/a21o/sky130_fd_sc_ms__a21o_1.pxi.spice
index 229c4d2..4d328be 100644
--- a/cells/a21o/sky130_fd_sc_ms__a21o_1.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_ms__a21o_1.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21o_1.pxi.spice
-* Created: Fri Aug 28 16:59:05 2020
+* Created: Wed Sep  2 11:51:16 2020
 * 
 x_PM_SKY130_FD_SC_MS__A21O_1%A_81_264# N_A_81_264#_M1003_d N_A_81_264#_M1006_s
 + N_A_81_264#_M1005_g N_A_81_264#_c_63_n N_A_81_264#_c_64_n N_A_81_264#_M1000_g
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_1.spice b/cells/a21o/sky130_fd_sc_ms__a21o_1.spice
index ab1e19e..36b208b 100644
--- a/cells/a21o/sky130_fd_sc_ms__a21o_1.spice
+++ b/cells/a21o/sky130_fd_sc_ms__a21o_1.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21o_1.spice
-* Created: Fri Aug 28 16:59:05 2020
+* Created: Wed Sep  2 11:51:16 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_2.lvs.report b/cells/a21o/sky130_fd_sc_ms__a21o_2.lvs.report
new file mode 100644
index 0000000..272e692
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_ms__a21o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a21o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a21o_2.sp ('sky130_fd_sc_ms__a21o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21o/sky130_fd_sc_ms__a21o_2.spice ('sky130_fd_sc_ms__a21o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:51:20 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a21o_2       sky130_fd_sc_ms__a21o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a21o_2
+SOURCE CELL NAME:         sky130_fd_sc_ms__a21o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:          5         5         MN (4 pins)
+                     5         5         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        11        10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_2.pex.spice b/cells/a21o/sky130_fd_sc_ms__a21o_2.pex.spice
index ecc2512..6b4700d 100644
--- a/cells/a21o/sky130_fd_sc_ms__a21o_2.pex.spice
+++ b/cells/a21o/sky130_fd_sc_ms__a21o_2.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21o_2.pex.spice
-* Created: Fri Aug 28 16:59:14 2020
+* Created: Wed Sep  2 11:51:23 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_2.pxi.spice b/cells/a21o/sky130_fd_sc_ms__a21o_2.pxi.spice
index dcafd8e..9101271 100644
--- a/cells/a21o/sky130_fd_sc_ms__a21o_2.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_ms__a21o_2.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21o_2.pxi.spice
-* Created: Fri Aug 28 16:59:14 2020
+* Created: Wed Sep  2 11:51:23 2020
 * 
 x_PM_SKY130_FD_SC_MS__A21O_2%A_84_244# N_A_84_244#_M1004_d N_A_84_244#_M1007_s
 + N_A_84_244#_M1001_g N_A_84_244#_c_61_n N_A_84_244#_M1003_g N_A_84_244#_M1002_g
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_2.spice b/cells/a21o/sky130_fd_sc_ms__a21o_2.spice
index e55aad2..bfe8441 100644
--- a/cells/a21o/sky130_fd_sc_ms__a21o_2.spice
+++ b/cells/a21o/sky130_fd_sc_ms__a21o_2.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21o_2.spice
-* Created: Fri Aug 28 16:59:14 2020
+* Created: Wed Sep  2 11:51:23 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_4.lvs.report b/cells/a21o/sky130_fd_sc_ms__a21o_4.lvs.report
new file mode 100644
index 0000000..db01b4e
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_ms__a21o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a21o_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a21o_4.sp ('sky130_fd_sc_ms__a21o_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21o/sky130_fd_sc_ms__a21o_4.spice ('sky130_fd_sc_ms__a21o_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:51:26 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a21o_4       sky130_fd_sc_ms__a21o_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a21o_4
+SOURCE CELL NAME:         sky130_fd_sc_ms__a21o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              11        11
+
+ Instances:         10        10         MN (4 pins)
+                    10        10         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        21        20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               9         9
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         5         5
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                9          9            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          5          5            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   20 layout mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+   20 source mos transistors were reduced to 8.
+     12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_4.pex.spice b/cells/a21o/sky130_fd_sc_ms__a21o_4.pex.spice
index ce1bc76..8c8db2c 100644
--- a/cells/a21o/sky130_fd_sc_ms__a21o_4.pex.spice
+++ b/cells/a21o/sky130_fd_sc_ms__a21o_4.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21o_4.pex.spice
-* Created: Fri Aug 28 16:59:43 2020
+* Created: Wed Sep  2 11:51:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_4.pxi.spice b/cells/a21o/sky130_fd_sc_ms__a21o_4.pxi.spice
index dc8dde6..182a3a7 100644
--- a/cells/a21o/sky130_fd_sc_ms__a21o_4.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_ms__a21o_4.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21o_4.pxi.spice
-* Created: Fri Aug 28 16:59:43 2020
+* Created: Wed Sep  2 11:51:29 2020
 * 
 x_PM_SKY130_FD_SC_MS__A21O_4%A_91_48# N_A_91_48#_M1005_d N_A_91_48#_M1003_s
 + N_A_91_48#_M1006_d N_A_91_48#_M1001_g N_A_91_48#_M1007_g N_A_91_48#_M1004_g
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_4.spice b/cells/a21o/sky130_fd_sc_ms__a21o_4.spice
index a5fa17e..e374455 100644
--- a/cells/a21o/sky130_fd_sc_ms__a21o_4.spice
+++ b/cells/a21o/sky130_fd_sc_ms__a21o_4.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21o_4.spice
-* Created: Fri Aug 28 16:59:43 2020
+* Created: Wed Sep  2 11:51:29 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_1.lvs.report b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.lvs.report
new file mode 100644
index 0000000..a7f060b
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a21oi_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a21oi_1.sp ('sky130_fd_sc_ms__a21oi_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21oi/sky130_fd_sc_ms__a21oi_1.spice ('sky130_fd_sc_ms__a21oi_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:51:32 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a21oi_1      sky130_fd_sc_ms__a21oi_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a21oi_1
+SOURCE CELL NAME:         sky130_fd_sc_ms__a21oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          3         3         MN (4 pins)
+                     3         3         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:         7         6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pex.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pex.spice
index dfe616d..bec2dab 100644
--- a/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21oi_1.pex.spice
-* Created: Fri Aug 28 16:59:52 2020
+* Created: Wed Sep  2 11:51:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pxi.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pxi.spice
index 1d573d4..39cd5a8 100644
--- a/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21oi_1.pxi.spice
-* Created: Fri Aug 28 16:59:52 2020
+* Created: Wed Sep  2 11:51:35 2020
 * 
 x_PM_SKY130_FD_SC_MS__A21OI_1%A2 N_A2_M1003_g N_A2_c_40_n N_A2_M1005_g A2
 + N_A2_c_42_n PM_SKY130_FD_SC_MS__A21OI_1%A2
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_1.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.spice
index 753d8c7..f4994c5 100644
--- a/cells/a21oi/sky130_fd_sc_ms__a21oi_1.spice
+++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21oi_1.spice
-* Created: Fri Aug 28 16:59:52 2020
+* Created: Wed Sep  2 11:51:35 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_2.lvs.report b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.lvs.report
new file mode 100644
index 0000000..29aa6d3
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a21oi_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a21oi_2.sp ('sky130_fd_sc_ms__a21oi_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21oi/sky130_fd_sc_ms__a21oi_2.spice ('sky130_fd_sc_ms__a21oi_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:51:39 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a21oi_2      sky130_fd_sc_ms__a21oi_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a21oi_2
+SOURCE CELL NAME:         sky130_fd_sc_ms__a21oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:          5         5         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        12        11
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   10 layout mos transistors were reduced to 5.
+     5 mos transistors were deleted by parallel reduction.
+   10 source mos transistors were reduced to 5.
+     5 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB B1 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pex.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pex.spice
index d628d53..c0f6903 100644
--- a/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21oi_2.pex.spice
-* Created: Fri Aug 28 17:00:01 2020
+* Created: Wed Sep  2 11:51:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pxi.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pxi.spice
index e16db12..ca0c3a5 100644
--- a/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21oi_2.pxi.spice
-* Created: Fri Aug 28 17:00:01 2020
+* Created: Wed Sep  2 11:51:41 2020
 * 
 x_PM_SKY130_FD_SC_MS__A21OI_2%B1 N_B1_M1007_g N_B1_c_70_n N_B1_c_76_n
 + N_B1_M1003_g N_B1_c_71_n N_B1_c_78_n N_B1_M1004_g N_B1_c_72_n B1 N_B1_c_74_n
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_2.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.spice
index 4bc5ffc..ea3b633 100644
--- a/cells/a21oi/sky130_fd_sc_ms__a21oi_2.spice
+++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21oi_2.spice
-* Created: Fri Aug 28 17:00:01 2020
+* Created: Wed Sep  2 11:51:41 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_4.lvs.report b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.lvs.report
new file mode 100644
index 0000000..d009a6b
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a21oi_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a21oi_4.sp ('sky130_fd_sc_ms__a21oi_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21oi/sky130_fd_sc_ms__a21oi_4.spice ('sky130_fd_sc_ms__a21oi_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:51:48 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a21oi_4      sky130_fd_sc_ms__a21oi_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a21oi_4
+SOURCE CELL NAME:         sky130_fd_sc_ms__a21oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:              10        10
+
+ Instances:         10        10         MN (4 pins)
+                    12        12         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        23        22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:              8         8
+
+ Nets:               8         8
+
+ Instances:          1         1         MN (4 pins)
+                     1         1         SMN2 (4 pins)
+                     1         1         SPMP_2_1 (5 pins)
+                ------    ------
+ Total Inst:         3         3
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:               8          8            0            0
+
+   Nets:                8          8            0            0
+
+   Instances:           1          1            0            0    MN(NLOWVT)
+                        1          1            0            0    SMN2
+                        1          1            0            0    SPMP_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          3          3            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   22 layout mos transistors were reduced to 6.
+     16 mos transistors were deleted by parallel reduction.
+   22 source mos transistors were reduced to 6.
+     16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pex.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pex.spice
index 098cd8f..83d264b 100644
--- a/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21oi_4.pex.spice
-* Created: Fri Aug 28 17:00:10 2020
+* Created: Wed Sep  2 11:51:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pxi.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pxi.spice
index 3fec3d1..936e6d0 100644
--- a/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21oi_4.pxi.spice
-* Created: Fri Aug 28 17:00:10 2020
+* Created: Wed Sep  2 11:51:51 2020
 * 
 x_PM_SKY130_FD_SC_MS__A21OI_4%A2 N_A2_M1003_g N_A2_M1002_g N_A2_M1005_g
 + N_A2_M1014_g N_A2_M1007_g N_A2_M1015_g N_A2_M1008_g N_A2_M1017_g A2 A2 A2
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_4.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.spice
index fd40fe8..9c652ea 100644
--- a/cells/a21oi/sky130_fd_sc_ms__a21oi_4.spice
+++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a21oi_4.spice
-* Created: Fri Aug 28 17:00:10 2020
+* Created: Wed Sep  2 11:51:51 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_1.lvs.report b/cells/a221o/sky130_fd_sc_ms__a221o_1.lvs.report
new file mode 100644
index 0000000..2f2a8c0
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_ms__a221o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a221o_1.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a221o_1.sp ('sky130_fd_sc_ms__a221o_1')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a221o/sky130_fd_sc_ms__a221o_1.spice ('sky130_fd_sc_ms__a221o_1')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:51:55 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a221o_1      sky130_fd_sc_ms__a221o_1
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a221o_1
+SOURCE CELL NAME:         sky130_fd_sc_ms__a221o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          6         6         MN (4 pins)
+                     6         6         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        13        12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SPMP_2_2_1 (7 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SPMP_2_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 B2 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_1.pex.spice b/cells/a221o/sky130_fd_sc_ms__a221o_1.pex.spice
index 1d9a268..3c97388 100644
--- a/cells/a221o/sky130_fd_sc_ms__a221o_1.pex.spice
+++ b/cells/a221o/sky130_fd_sc_ms__a221o_1.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a221o_1.pex.spice
-* Created: Fri Aug 28 17:00:19 2020
+* Created: Wed Sep  2 11:51:58 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_1.pxi.spice b/cells/a221o/sky130_fd_sc_ms__a221o_1.pxi.spice
index 56eccdd..5d115d1 100644
--- a/cells/a221o/sky130_fd_sc_ms__a221o_1.pxi.spice
+++ b/cells/a221o/sky130_fd_sc_ms__a221o_1.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a221o_1.pxi.spice
-* Created: Fri Aug 28 17:00:19 2020
+* Created: Wed Sep  2 11:51:58 2020
 * 
 x_PM_SKY130_FD_SC_MS__A221O_1%A_148_260# N_A_148_260#_M1005_d
 + N_A_148_260#_M1003_d N_A_148_260#_M1006_d N_A_148_260#_M1000_g
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_1.spice b/cells/a221o/sky130_fd_sc_ms__a221o_1.spice
index 8f50bd9..9e5c1cc 100644
--- a/cells/a221o/sky130_fd_sc_ms__a221o_1.spice
+++ b/cells/a221o/sky130_fd_sc_ms__a221o_1.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a221o_1.spice
-* Created: Fri Aug 28 17:00:19 2020
+* Created: Wed Sep  2 11:51:58 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_2.lvs.report b/cells/a221o/sky130_fd_sc_ms__a221o_2.lvs.report
new file mode 100644
index 0000000..5e85d43
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_ms__a221o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a221o_2.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a221o_2.sp ('sky130_fd_sc_ms__a221o_2')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a221o/sky130_fd_sc_ms__a221o_2.spice ('sky130_fd_sc_ms__a221o_2')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:52:02 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a221o_2      sky130_fd_sc_ms__a221o_2
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+   LVS DEVICE TYPE                        RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+   // Reduction
+
+   LVS REDUCE SERIES MOS                  NO
+   LVS REDUCE PARALLEL MOS                NO
+   LVS REDUCE SEMI SERIES MOS             NO
+   LVS REDUCE SPLIT GATES                 YES [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE PARALLEL BIPOLAR            NO
+   LVS REDUCE SERIES CAPACITORS           NO
+   LVS REDUCE PARALLEL CAPACITORS         NO
+   LVS REDUCE SERIES RESISTORS            NO
+   LVS REDUCE PARALLEL RESISTORS          NO
+   LVS REDUCE PARALLEL DIODES             NO
+
+   LVS REDUCE  condiode  PARALLEL
+   LVS REDUCE  condiodeHvPsub  PARALLEL
+   LVS REDUCE  p20vhv1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  n20vhviso1  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  nvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  pvhv  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MP  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  M  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  MN  PARALLEL [ TOLERANCE l 1 w 1 ]
+   LVS REDUCE  Q(npnpar1x1)  PARALLEL
+   LVS REDUCE  Q(npnpar1x2)  PARALLEL
+   LVS REDUCE  Q(npn_1x1_2p0_hv)  PARALLEL
+   LVS REDUCE  Q(pnppar)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  Q(pnppar5x)  PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+   LVS REDUCE  D  PARALLEL [ TOLERANCE a 1 p 1 ]
+   LVS REDUCE  D  SERIES POS NEG NO
+   LVS REDUCE  C(xcmimc1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  C(xcmimc2)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R(mrp1)  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  PARALLEL [ TOLERANCE w 1 l 1 ]
+   LVS REDUCE  R  SERIES POS NEG NO
+   LVS REDUCE  R(short)  PARALLEL
+   LVS REDUCE  R(short)  SERIES POS NEG NO
+   LVS REDUCE  R(fuse)  PARALLEL NO
+   LVS REDUCE  R(fuse)  SERIES POS NEG NO
+   LVS REDUCE  R(metop)  PARALLEL [ TOLERANCE metopNumber 0 ]
+   LVS REDUCE  R(metop)  SERIES POS NEG NO
+   LVS REDUCTION PRIORITY                 PARALLEL
+   
+   LVS SHORT EQUIVALENT NODES             NO
+
+   // Filter
+
+   LVS FILTER  R(cds_thru)  SHORT SOURCE
+   LVS FILTER  R(cds_thru)  SHORT LAYOUT
+   LVS FILTER  Dpar  OPEN SOURCE
+   LVS FILTER  Dpar  OPEN LAYOUT
+   LVS FILTER  Probe  OPEN SOURCE
+   LVS FILTER  Probe  OPEN LAYOUT
+   LVS FILTER  icecap  OPEN SOURCE
+   LVS FILTER  s8fmlt_iref_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_neg_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_termx  OPEN SOURCE
+   LVS FILTER  s8fmlt_vdac_termx  OPEN SOURCE
+   LVS FILTER  D  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN SOURCE
+   LVS FILTER  diff_dev  OPEN LAYOUT
+   LVS FILTER  tap_dev  OPEN SOURCE
+   LVS FILTER  tap_dev  OPEN LAYOUT
+   LVS FILTER  cad_dummy_open_device  OPEN SOURCE
+   LVS FILTER  cad_dummy_open_device  OPEN LAYOUT
+
+   // Trace Property
+
+   TRACE PROPERTY  xcnwvc  m m 0
+   TRACE PROPERTY  xcnwvc  w w 0
+   TRACE PROPERTY  xcnwvc  l l 0
+   TRACE PROPERTY  xcnwvc2  m m 0
+   TRACE PROPERTY  xcnwvc2  w w 0
+   TRACE PROPERTY  xcnwvc2  l l 0
+   TRACE PROPERTY  xchvnwc  m m 0
+   TRACE PROPERTY  q(npnpar1x1)  m m 0
+   TRACE PROPERTY  q(npnpar1x2)  m m 0
+   TRACE PROPERTY  q(npn_1x1_2p0_hv)  m m 0
+   TRACE PROPERTY  q(pnppar)  barea barea 0
+   TRACE PROPERTY  q(pnppar)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar)  earea earea 0
+   TRACE PROPERTY  q(pnppar)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar)  m m 0
+   TRACE PROPERTY  q(pnppar5x)  barea barea 0
+   TRACE PROPERTY  q(pnppar5x)  bperi bperi 0
+   TRACE PROPERTY  q(pnppar5x)  earea earea 0
+   TRACE PROPERTY  q(pnppar5x)  eperi eperi 0
+   TRACE PROPERTY  q(pnppar5x)  m m 0
+   TRACE PROPERTY  d(ndiode)  a a 1
+   TRACE PROPERTY  d(ndiode)  p p 1
+   TRACE PROPERTY  d(ndiode)  m m 0
+   TRACE PROPERTY  d(ndiode_h)  a a 1
+   TRACE PROPERTY  d(ndiode_h)  p p 1
+   TRACE PROPERTY  d(ndiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_300)  m m 0
+   TRACE PROPERTY  d(pdiode)  a a 1
+   TRACE PROPERTY  d(pdiode)  p p 1
+   TRACE PROPERTY  d(pdiode)  m m 0
+   TRACE PROPERTY  d(pdiode_h)  a a 1
+   TRACE PROPERTY  d(pdiode_h)  p p 1
+   TRACE PROPERTY  d(pdiode_h)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_100)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_200)  m m 0
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  a a 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  p p 1
+   TRACE PROPERTY  d(xesd_pdiode_h_300)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub)  a a 1
+   TRACE PROPERTY  d(dnwdiode_psub)  p p 1
+   TRACE PROPERTY  d(dnwdiode_psub)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_100)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_200)  m m 0
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  a a 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  p p 1
+   TRACE PROPERTY  d(xesd_ndiode_h_dnwl_300)  m m 0
+   TRACE PROPERTY  xcmvpp  m m 0
+   TRACE PROPERTY  xcmvpp_2  m m 0
+   TRACE PROPERTY  xcmvpp2_nhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp2_phv5x4  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap2_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_wafflecap1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l40  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l20  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l10  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_atlas_fingercap_l5  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1_met5pullin  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_5x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_4x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_3x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_2x1  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x2  m m 0
+   TRACE PROPERTY  xcmvpp_hd5_1x1  m m 0
+   TRACE PROPERTY  xcmvppx4_2xnhvnative10x4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym50p4shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_lim5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m5shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_lim4shield  m m 0
+   TRACE PROPERTY  xcmvpp6p8x6p1_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_polym4shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m4shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3_lishield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp8p6x7p9_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp1p8x1p8_m3shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4m5shield  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m4  m m 0
+   TRACE PROPERTY  xcmvpp11p5x11p7_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp4p4x4p6_m1m2  m m 0
+   TRACE PROPERTY  xcmvpp5  m m 0
+   TRACE PROPERTY  xcmvpp4  m m 0
+   TRACE PROPERTY  xcmvpp3  m m 0
+   TRACE PROPERTY  r(mrdn)  w w 1
+   TRACE PROPERTY  r(mrdn)  l l 1
+   TRACE PROPERTY  r(mrdn)  m m 0
+   TRACE PROPERTY  r(mrdn_hv)  w w 1
+   TRACE PROPERTY  r(mrdn_hv)  l l 1
+   TRACE PROPERTY  r(mrdn_hv)  m m 0
+   TRACE PROPERTY  r(mrdp)  w w 1
+   TRACE PROPERTY  r(mrdp)  l l 1
+   TRACE PROPERTY  r(mrdp)  m m 0
+   TRACE PROPERTY  r(mrdp_hv)  w w 1
+   TRACE PROPERTY  r(mrdp_hv)  l l 1
+   TRACE PROPERTY  r(mrdp_hv)  m m 0
+   TRACE PROPERTY  r(mrl1)  w w 1
+   TRACE PROPERTY  r(mrl1)  l l 1
+   TRACE PROPERTY  r(mrl1)  m m 0
+   TRACE PROPERTY  r(xpwres)  w w 1
+   TRACE PROPERTY  r(xpwres)  l l 1
+   TRACE PROPERTY  r(xpwres)  m m 0
+   TRACE PROPERTY  r(short)  m m 0
+   TRACE PROPERTY  r(fuse)  w w 1
+   TRACE PROPERTY  r(fuse)  l l 1
+   TRACE PROPERTY  r(fuse)  m m 0
+   TRACE PROPERTY  r(metop)  metopnumber metopnumber 0
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_victim)  m m 0
+   TRACE PROPERTY  d(nwdiode_victim)  a a 10
+   TRACE PROPERTY  d(nwdiode_victim)  p p 10
+   TRACE PROPERTY  d(nwdiode_victim)  m m 0
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  a a 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  p p 10
+   TRACE PROPERTY  d(dnwdiode_psub_aggressor)  m m 0
+   TRACE PROPERTY  d(nwdiode_aggressor)  a a 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  p p 10
+   TRACE PROPERTY  d(nwdiode_aggressor)  m m 0
+
+   // User Trace Property
+
+   TRACE PROPERTY  mn(nshort)  m mult w l
+   TRACE PROPERTY  mn(npass)  m mult w l
+   TRACE PROPERTY  mn(nlowvt)  m mult w l
+   TRACE PROPERTY  m(sonos_e)  m mult w l
+   TRACE PROPERTY  m  m mult w l
+   TRACE PROPERTY  m(fnpass)  m mult w l
+   TRACE PROPERTY  mn(nhv)  m mult w l
+   TRACE PROPERTY  mn(nhvnative)  m mult w l
+   TRACE PROPERTY  mn(ntvnative)  m mult w l
+   TRACE PROPERTY  mp(pshort)  m mult w l
+   TRACE PROPERTY  mp  m mult w l
+   TRACE PROPERTY  mp(phighvt)  m mult w l
+   TRACE PROPERTY  mp(plowvt)  m mult w l
+   TRACE PROPERTY  mp(phv)  m mult w l
+   TRACE PROPERTY  mn(nshortesd)  m mult w l
+   TRACE PROPERTY  mn(nhvesd)  m mult w l
+   TRACE PROPERTY  mn(nhvnativeesd)  m mult w l
+   TRACE PROPERTY  mp(phvesd)  m mult w l
+   TRACE PROPERTY  nvhv  m mult w l
+   TRACE PROPERTY  n20vhv1  m mult w l
+   TRACE PROPERTY  n20nativevhv1  m mult w l
+   TRACE PROPERTY  n20vhviso1  m mult w l
+   TRACE PROPERTY  n20nativevhviso1  m mult w l
+   TRACE PROPERTY  pvhv  m mult w l
+   TRACE PROPERTY  p20vhv1  m mult w l
+   TRACE PROPERTY  c(xcmimc1)  w l m
+   TRACE PROPERTY  c(xcmimc2)  w l m
+   TRACE PROPERTY  r(mrp1)  m w l
+   TRACE PROPERTY  xhrpoly_0p35  m w l
+   TRACE PROPERTY  xuhrpoly_0p35  m w l
+   TRACE PROPERTY  xhrpoly_0p69  m w l
+   TRACE PROPERTY  xuhrpoly_0p69  m w l
+   TRACE PROPERTY  xhrpoly_1p41  m w l
+   TRACE PROPERTY  xuhrpoly_1p41  m w l
+   TRACE PROPERTY  xhrpoly_2p85  m w l
+   TRACE PROPERTY  xuhrpoly_2p85  m w l
+
+
+
+                   CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+LAYOUT CELL NAME:         sky130_fd_sc_ms__a221o_2
+SOURCE CELL NAME:         sky130_fd_sc_ms__a221o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              15        15
+
+ Instances:          7         7         MN (4 pins)
+                     7         7         MP (4 pins)
+                     1         0    *    Dpar (2 pins)
+                ------    ------
+ Total Inst:        15        14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+                Layout    Source         Component Type
+                ------    ------         --------------
+ Ports:             10        10
+
+ Nets:              11        11
+
+ Instances:          2         2         MN (4 pins)
+                     1         1         MP (4 pins)
+                     2         2         SMN2 (4 pins)
+                     1         1         SPMP_2_2_1 (7 pins)
+                ------    ------
+ Total Inst:         6         6
+
+
+       * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+                               INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+                  Matched    Matched    Unmatched    Unmatched    Component
+                   Layout     Source       Layout       Source    Type
+                  -------    -------    ---------    ---------    ---------
+   Ports:              10         10            0            0
+
+   Nets:               11         11            0            0
+
+   Instances:           2          2            0            0    MN(NLOWVT)
+                        1          1            0            0    MP(PSHORT)
+                        2          2            0            0    SMN2
+                        1          1            0            0    SPMP_2_2_1
+                  -------    -------    ---------    ---------
+   Total Inst:          6          6            0            0
+
+
+o Statistics:
+
+   1 layout instance was filtered and its pins removed from adjoining nets.
+
+   4 layout mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+   4 source mos transistors were reduced to 2.
+     2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+   Ports:        VNB VPB A2 A1 B1 B2 C1 VPWR X VGND
+
+
+**************************************************************************************************************
+                                         SUMMARY
+**************************************************************************************************************
+
+Total CPU Time:      0 sec
+Total Elapsed Time:  0 sec
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_2.pex.spice b/cells/a221o/sky130_fd_sc_ms__a221o_2.pex.spice
index 7483897..ed2fd09 100644
--- a/cells/a221o/sky130_fd_sc_ms__a221o_2.pex.spice
+++ b/cells/a221o/sky130_fd_sc_ms__a221o_2.pex.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a221o_2.pex.spice
-* Created: Fri Aug 28 17:00:49 2020
+* Created: Wed Sep  2 11:52:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_2.pxi.spice b/cells/a221o/sky130_fd_sc_ms__a221o_2.pxi.spice
index 7830601..93587f1 100644
--- a/cells/a221o/sky130_fd_sc_ms__a221o_2.pxi.spice
+++ b/cells/a221o/sky130_fd_sc_ms__a221o_2.pxi.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a221o_2.pxi.spice
-* Created: Fri Aug 28 17:00:49 2020
+* Created: Wed Sep  2 11:52:05 2020
 * 
 x_PM_SKY130_FD_SC_MS__A221O_2%A_89_260# N_A_89_260#_M1001_d N_A_89_260#_M1010_d
 + N_A_89_260#_M1006_d N_A_89_260#_M1011_g N_A_89_260#_M1002_g
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_2.spice b/cells/a221o/sky130_fd_sc_ms__a221o_2.spice
index 48fb8b1..7151669 100644
--- a/cells/a221o/sky130_fd_sc_ms__a221o_2.spice
+++ b/cells/a221o/sky130_fd_sc_ms__a221o_2.spice
@@ -1,5 +1,5 @@
 * File: sky130_fd_sc_ms__a221o_2.spice
-* Created: Fri Aug 28 17:00:49 2020
+* Created: Wed Sep  2 11:52:05 2020
 * Program "Calibre xRC"
 * Version "v2018.4_34.26"
 * 
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_4.lvs.report b/cells/a221o/sky130_fd_sc_ms__a221o_4.lvs.report
new file mode 100644
index 0000000..cbcf357
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_ms__a221o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+                  ##################################################
+                  ##                                              ##
+                  ##         C A L I B R E    S Y S T E M         ##
+                  ##                                              ##
+                  ##             L V S   R E P O R T              ##
+                  ##                                              ##
+                  ##################################################
+
+
+
+REPORT FILE NAME:         sky130_fd_sc_ms__a221o_4.lvs.report
+LAYOUT NAME:              svdb/sky130_fd_sc_ms__a221o_4.sp ('sky130_fd_sc_ms__a221o_4')
+SOURCE NAME:              /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a221o/sky130_fd_sc_ms__a221o_4.spice ('sky130_fd_sc_ms__a221o_4')
+RULE FILE:                /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME:            Wed Sep  2 11:52:08 2020
+CURRENT DIRECTORY:        /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME:                hlusk
+CALIBRE VERSION:          v2018.4_34.26    Mon Dec 3 14:40:54 PST 2018
+
+
+
+                               OVERALL COMPARISON RESULTS
+
+
+
+                         #       ###################       _   _   
+                        #        #                 #       *   *   
+                   #   #         #     CORRECT     #         |     
+                    # #          #                 #       \___/  
+                     #           ###################               
+
+
+
+
+**************************************************************************************************************
+                                      CELL  SUMMARY
+**************************************************************************************************************
+
+  Result         Layout                        Source
+  -----------    -----------                   --------------
+  CORRECT        sky130_fd_sc_ms__a221o_4      sky130_fd_sc_ms__a221o_4
+
+
+
+**************************************************************************************************************
+                                      LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+   // LVS COMPONENT TYPE PROPERTY
+   // LVS COMPONENT SUBTYPE PROPERTY
+   // LVS PIN NAME PROPERTY
+   // LVS POWER NAME
+   // LVS GROUND NAME
+   LVS CELL SUPPLY                        NO
+   LVS RECOGNIZE GATES                    ALL
+   LVS IGNORE PORTS                       NO
+   LVS CHECK PORT NAMES                   YES
+   LVS IGNORE TRIVIAL NAMED PORTS         NO
+   LVS BUILTIN DEVICE PIN SWAP            YES
+   LVS ALL CAPACITOR PINS SWAPPABLE       NO
+   LVS DISCARD PINS BY DEVICE             YES
+   LVS SOFT SUBSTRATE PINS                NO
+   LVS INJECT LOGIC                       NO
+   LVS EXPAND UNBALANCED CELLS            YES
+   LVS FLATTEN INSIDE CELL                NO
+   LVS EXPAND SEED PROMOTIONS             NO
+   LVS PRESERVE PARAMETERIZED CELLS       NO
+   LVS GLOBALS ARE PORTS                  YES
+   LVS REVERSE WL                         NO
+   LVS SPICE PREFER PINS                  YES
+   LVS SPICE SLASH IS SPACE               NO
+   LVS SPICE ALLOW FLOATING PINS          YES
+   LVS SPICE ALLOW INLINE PARAMETERS      NO
+   LVS SPICE ALLOW UNQUOTED STRINGS       YES
+   LVS SPICE CONDITIONAL LDD              NO
+   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO
+   // LVS SPICE EXCLUDE CELL SOURCE
+   // LVS SPICE EXCLUDE CELL LAYOUT
+   LVS SPICE IMPLIED MOS AREA             NO
+   // LVS SPICE MULTIPLIER NAME
+   LVS SPICE OVERRIDE GLOBALS             YES
+   LVS SPICE REDEFINE PARAM               YES
+   LVS SPICE REPLICATE DEVICES            YES
+   LVS SPICE SCALE X PARAMETERS           NO
+   LVS SPICE STRICT WL                    YES
+   // LVS SPICE OPTION
+   LVS STRICT SUBTYPES                    YES
+   LVS EXACT SUBTYPES                     NO
+   LAYOUT CASE                            NO
+   SOURCE CASE                            NO
+   LVS COMPARE CASE                       NO
+   LVS DOWNCASE DEVICE                    NO
+   LVS REPORT MAXIMUM                     50
+   LVS PROPERTY RESOLUTION MAXIMUM        ALL
+   LVS SIGNATURE MAXIMUM                  ALL
+   // LVS FILTER UNUSED OPTION
+   // LVS REPORT OPTION
+   LVS REPORT UNITS                       YES
+   // LVS NON USER NAME PORT
+   LVS NON USER NAME NET                  "^n[0-9]*$" "^net[0-9]*$"
+   // LVS NON USER NAME INSTANCE
+   // LVS IGNORE DEVICE PIN
+   // LVS PREFER NETS FILTER SOURCE
+   // LVS PREFER NETS FILTER LAYOUT
+
+   // Device Type Map
+
+   LVS DEVICE TYPE                        RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+   LVS DEVICE TYPE