Updates to spice, PEX and PXI files as well as the addition of lvs reports
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_1.lvs.report b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.lvs.report new file mode 100644 index 0000000..a007600 --- /dev/null +++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.lvs.report
@@ -0,0 +1,485 @@ + +LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice" +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice" +Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice" +Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice" +Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice" +Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice" +Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice" +Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice" +Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice" +Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice" +Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice" +Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice" +Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice" + + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a2111o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a2111o_1.sp ('sky130_fd_sc_ms__a2111o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice ('sky130_fd_sc_ms__a2111o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:49:18 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a2111o_1 sky130_fd_sc_ms__a2111o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a2111o_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a2111o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1 C1 D1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pex.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pex.spice index a274fce..63b7c62 100644 --- a/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pex.spice +++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111o_1.pex.spice -* Created: Fri Aug 28 16:55:21 2020 +* Created: Wed Sep 2 11:49:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pxi.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pxi.spice index b10a8c1..93d5867 100644 --- a/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pxi.spice +++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111o_1.pxi.spice -* Created: Fri Aug 28 16:55:21 2020 +* Created: Wed Sep 2 11:49:21 2020 * x_PM_SKY130_FD_SC_MS__A2111O_1%A1 N_A1_c_73_n N_A1_M1010_g N_A1_M1002_g A1 A1 + N_A1_c_76_n N_A1_c_77_n N_A1_c_78_n PM_SKY130_FD_SC_MS__A2111O_1%A1
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice index 924608a..34d7342 100644 --- a/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice +++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111o_1.spice -* Created: Fri Aug 28 16:55:21 2020 +* Created: Wed Sep 2 11:49:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_2.lvs.report b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.lvs.report new file mode 100644 index 0000000..027179c --- /dev/null +++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.lvs.report
@@ -0,0 +1,492 @@ + +LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" +Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" +Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" +Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" +Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" +Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" +Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" +Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" +Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" +Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" +Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" +Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" +Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" +Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice" + + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a2111o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a2111o_2.sp ('sky130_fd_sc_ms__a2111o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice ('sky130_fd_sc_ms__a2111o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:49:24 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a2111o_2 sky130_fd_sc_ms__a2111o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a2111o_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a2111o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pex.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pex.spice index dd1155d..42ce939 100644 --- a/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pex.spice +++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111o_2.pex.spice -* Created: Fri Aug 28 16:55:31 2020 +* Created: Wed Sep 2 11:49:27 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pxi.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pxi.spice index 03b8f26..2566fb7 100644 --- a/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pxi.spice +++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111o_2.pxi.spice -* Created: Fri Aug 28 16:55:31 2020 +* Created: Wed Sep 2 11:49:27 2020 * x_PM_SKY130_FD_SC_MS__A2111O_2%A_91_244# N_A_91_244#_M1013_s N_A_91_244#_M1003_d + N_A_91_244#_M1011_d N_A_91_244#_M1001_s N_A_91_244#_M1004_g N_A_91_244#_c_87_n
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice index 6c8fd3b..d7433a0 100644 --- a/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice +++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111o_2.spice -* Created: Fri Aug 28 16:55:31 2020 +* Created: Wed Sep 2 11:49:27 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_4.lvs.report b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.lvs.report new file mode 100644 index 0000000..543234b --- /dev/null +++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.lvs.report
@@ -0,0 +1,506 @@ + +LVS Netlist Compiler - Errors and Warnings for "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Warning: Duplicate parameter definition "MULT" at line 19 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 21 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 23 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 25 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 27 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 29 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 31 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 33 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 35 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 37 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 39 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 41 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 43 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 45 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 47 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 49 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 51 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 53 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 55 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 57 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 59 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 61 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 63 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 65 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 67 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 69 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 71 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" +Warning: Duplicate parameter definition "MULT" at line 73 in file "/home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice" + + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a2111o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a2111o_4.sp ('sky130_fd_sc_ms__a2111o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice ('sky130_fd_sc_ms__a2111o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:49:31 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a2111o_4 sky130_fd_sc_ms__a2111o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a2111o_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a2111o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pex.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pex.spice index e0f58af..5375763 100644 --- a/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pex.spice +++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111o_4.pex.spice -* Created: Fri Aug 28 16:55:40 2020 +* Created: Wed Sep 2 11:49:33 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pxi.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pxi.spice index a9dc724..388b420 100644 --- a/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pxi.spice +++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111o_4.pxi.spice -* Created: Fri Aug 28 16:55:40 2020 +* Created: Wed Sep 2 11:49:33 2020 * x_PM_SKY130_FD_SC_MS__A2111O_4%A_137_260# N_A_137_260#_M1011_d + N_A_137_260#_M1004_s N_A_137_260#_M1009_s N_A_137_260#_M1001_d
diff --git a/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice index ca19369..414b5f3 100644 --- a/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice +++ b/cells/a2111o/sky130_fd_sc_ms__a2111o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111o_4.spice -* Created: Fri Aug 28 16:55:40 2020 +* Created: Wed Sep 2 11:49:33 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.lvs.report b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.lvs.report new file mode 100644 index 0000000..cf79ad7 --- /dev/null +++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a2111oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a2111oi_1.sp ('sky130_fd_sc_ms__a2111oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.spice ('sky130_fd_sc_ms__a2111oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:49:37 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a2111oi_1 sky130_fd_sc_ms__a2111oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a2111oi_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a2111oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pex.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pex.spice index 76f4def..3ad186a 100644 --- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pex.spice +++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111oi_1.pex.spice -* Created: Fri Aug 28 16:55:49 2020 +* Created: Wed Sep 2 11:49:40 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pxi.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pxi.spice index 7803545..bc02651 100644 --- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pxi.spice +++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111oi_1.pxi.spice -* Created: Fri Aug 28 16:55:49 2020 +* Created: Wed Sep 2 11:49:40 2020 * x_PM_SKY130_FD_SC_MS__A2111OI_1%D1 N_D1_M1007_g N_D1_M1003_g D1 N_D1_c_60_n + N_D1_c_61_n PM_SKY130_FD_SC_MS__A2111OI_1%D1
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.spice index 52d4c62..52d4e5d 100644 --- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.spice +++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111oi_1.spice -* Created: Fri Aug 28 16:55:49 2020 +* Created: Wed Sep 2 11:49:40 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.lvs.report b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.lvs.report new file mode 100644 index 0000000..67b9a65 --- /dev/null +++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a2111oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a2111oi_2.sp ('sky130_fd_sc_ms__a2111oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.spice ('sky130_fd_sc_ms__a2111oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:49:43 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a2111oi_2 sky130_fd_sc_ms__a2111oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a2111oi_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a2111oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 7 7 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 18 17 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 14 layout mos transistors were reduced to 7. + 7 mos transistors were deleted by parallel reduction. + 14 source mos transistors were reduced to 7. + 7 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pex.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pex.spice index e55fbeb..c3a980d 100644 --- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pex.spice +++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111oi_2.pex.spice -* Created: Fri Aug 28 16:55:58 2020 +* Created: Wed Sep 2 11:49:46 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pxi.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pxi.spice index 02fe4d6..1fb1acc 100644 --- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pxi.spice +++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111oi_2.pxi.spice -* Created: Fri Aug 28 16:55:58 2020 +* Created: Wed Sep 2 11:49:46 2020 * x_PM_SKY130_FD_SC_MS__A2111OI_2%D1 N_D1_M1003_g N_D1_M1007_g N_D1_M1004_g D1 D1 + N_D1_c_92_n PM_SKY130_FD_SC_MS__A2111OI_2%D1
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.spice index cbe0cbf..f943d46 100644 --- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.spice +++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111oi_2.spice -* Created: Fri Aug 28 16:55:58 2020 +* Created: Wed Sep 2 11:49:46 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.lvs.report b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.lvs.report new file mode 100644 index 0000000..49f72e9 --- /dev/null +++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a2111oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a2111oi_4.sp ('sky130_fd_sc_ms__a2111oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.spice ('sky130_fd_sc_ms__a2111oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:49:50 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a2111oi_4 sky130_fd_sc_ms__a2111oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a2111oi_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a2111oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 14 14 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 35 34 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 34 layout mos transistors were reduced to 10. + 24 mos transistors were deleted by parallel reduction. + 34 source mos transistors were reduced to 10. + 24 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pex.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pex.spice index e196fb8..4f56a07 100644 --- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pex.spice +++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111oi_4.pex.spice -* Created: Fri Aug 28 16:56:28 2020 +* Created: Wed Sep 2 11:49:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pxi.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pxi.spice index 54a53e1..89a8d3a 100644 --- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pxi.spice +++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111oi_4.pxi.spice -* Created: Fri Aug 28 16:56:28 2020 +* Created: Wed Sep 2 11:49:52 2020 * x_PM_SKY130_FD_SC_MS__A2111OI_4%D1 N_D1_M1021_g N_D1_M1022_g N_D1_M1026_g + N_D1_c_142_n N_D1_M1017_g N_D1_c_143_n N_D1_M1029_g N_D1_M1031_g D1 D1 D1
diff --git a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.spice b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.spice index 9625235..c74d289 100644 --- a/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.spice +++ b/cells/a2111oi/sky130_fd_sc_ms__a2111oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2111oi_4.spice -* Created: Fri Aug 28 16:56:28 2020 +* Created: Wed Sep 2 11:49:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_1.lvs.report b/cells/a211o/sky130_fd_sc_ms__a211o_1.lvs.report new file mode 100644 index 0000000..ab2a5e4 --- /dev/null +++ b/cells/a211o/sky130_fd_sc_ms__a211o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a211o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a211o_1.sp ('sky130_fd_sc_ms__a211o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a211o/sky130_fd_sc_ms__a211o_1.spice ('sky130_fd_sc_ms__a211o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:49:56 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a211o_1 sky130_fd_sc_ms__a211o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a211o_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a211o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_1.pex.spice b/cells/a211o/sky130_fd_sc_ms__a211o_1.pex.spice index e2d7ed6..b5e9de8 100644 --- a/cells/a211o/sky130_fd_sc_ms__a211o_1.pex.spice +++ b/cells/a211o/sky130_fd_sc_ms__a211o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211o_1.pex.spice -* Created: Fri Aug 28 16:56:38 2020 +* Created: Wed Sep 2 11:49:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_1.pxi.spice b/cells/a211o/sky130_fd_sc_ms__a211o_1.pxi.spice index bce9c50..8981bee 100644 --- a/cells/a211o/sky130_fd_sc_ms__a211o_1.pxi.spice +++ b/cells/a211o/sky130_fd_sc_ms__a211o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211o_1.pxi.spice -* Created: Fri Aug 28 16:56:38 2020 +* Created: Wed Sep 2 11:49:59 2020 * x_PM_SKY130_FD_SC_MS__A211O_1%A_81_264# N_A_81_264#_M1008_d N_A_81_264#_M1004_d + N_A_81_264#_M1001_d N_A_81_264#_M1007_g N_A_81_264#_M1000_g N_A_81_264#_c_66_n
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_1.spice b/cells/a211o/sky130_fd_sc_ms__a211o_1.spice index 207d1cd..2176f70 100644 --- a/cells/a211o/sky130_fd_sc_ms__a211o_1.spice +++ b/cells/a211o/sky130_fd_sc_ms__a211o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211o_1.spice -* Created: Fri Aug 28 16:56:38 2020 +* Created: Wed Sep 2 11:49:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_2.lvs.report b/cells/a211o/sky130_fd_sc_ms__a211o_2.lvs.report new file mode 100644 index 0000000..f256c73 --- /dev/null +++ b/cells/a211o/sky130_fd_sc_ms__a211o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a211o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a211o_2.sp ('sky130_fd_sc_ms__a211o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a211o/sky130_fd_sc_ms__a211o_2.spice ('sky130_fd_sc_ms__a211o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:50:03 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a211o_2 sky130_fd_sc_ms__a211o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a211o_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a211o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 C1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_2.pex.spice b/cells/a211o/sky130_fd_sc_ms__a211o_2.pex.spice index b7983ea..624e1fe 100644 --- a/cells/a211o/sky130_fd_sc_ms__a211o_2.pex.spice +++ b/cells/a211o/sky130_fd_sc_ms__a211o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211o_2.pex.spice -* Created: Fri Aug 28 16:56:47 2020 +* Created: Wed Sep 2 11:50:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_2.pxi.spice b/cells/a211o/sky130_fd_sc_ms__a211o_2.pxi.spice index e6f4da8..3aeabea 100644 --- a/cells/a211o/sky130_fd_sc_ms__a211o_2.pxi.spice +++ b/cells/a211o/sky130_fd_sc_ms__a211o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211o_2.pxi.spice -* Created: Fri Aug 28 16:56:47 2020 +* Created: Wed Sep 2 11:50:05 2020 * x_PM_SKY130_FD_SC_MS__A211O_2%A_85_270# N_A_85_270#_M1001_d N_A_85_270#_M1009_d + N_A_85_270#_M1006_d N_A_85_270#_M1010_g N_A_85_270#_M1004_g
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_2.spice b/cells/a211o/sky130_fd_sc_ms__a211o_2.spice index 06fe3a9..53f6554 100644 --- a/cells/a211o/sky130_fd_sc_ms__a211o_2.spice +++ b/cells/a211o/sky130_fd_sc_ms__a211o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211o_2.spice -* Created: Fri Aug 28 16:56:47 2020 +* Created: Wed Sep 2 11:50:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_4.lvs.report b/cells/a211o/sky130_fd_sc_ms__a211o_4.lvs.report new file mode 100644 index 0000000..3587cc8 --- /dev/null +++ b/cells/a211o/sky130_fd_sc_ms__a211o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a211o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a211o_4.sp ('sky130_fd_sc_ms__a211o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a211o/sky130_fd_sc_ms__a211o_4.spice ('sky130_fd_sc_ms__a211o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:50:09 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a211o_4 sky130_fd_sc_ms__a211o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a211o_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a211o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 C1 A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_4.pex.spice b/cells/a211o/sky130_fd_sc_ms__a211o_4.pex.spice index 6abfd2b..86ddd67 100644 --- a/cells/a211o/sky130_fd_sc_ms__a211o_4.pex.spice +++ b/cells/a211o/sky130_fd_sc_ms__a211o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211o_4.pex.spice -* Created: Fri Aug 28 16:56:56 2020 +* Created: Wed Sep 2 11:50:12 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_4.pxi.spice b/cells/a211o/sky130_fd_sc_ms__a211o_4.pxi.spice index 6815851..be24969 100644 --- a/cells/a211o/sky130_fd_sc_ms__a211o_4.pxi.spice +++ b/cells/a211o/sky130_fd_sc_ms__a211o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211o_4.pxi.spice -* Created: Fri Aug 28 16:56:56 2020 +* Created: Wed Sep 2 11:50:12 2020 * x_PM_SKY130_FD_SC_MS__A211O_4%A_105_280# N_A_105_280#_M1005_d + N_A_105_280#_M1021_d N_A_105_280#_M1002_d N_A_105_280#_M1009_d
diff --git a/cells/a211o/sky130_fd_sc_ms__a211o_4.spice b/cells/a211o/sky130_fd_sc_ms__a211o_4.spice index b90b325..d5ced42 100644 --- a/cells/a211o/sky130_fd_sc_ms__a211o_4.spice +++ b/cells/a211o/sky130_fd_sc_ms__a211o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211o_4.spice -* Created: Fri Aug 28 16:56:56 2020 +* Created: Wed Sep 2 11:50:12 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_1.lvs.report b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.lvs.report new file mode 100644 index 0000000..79800ac --- /dev/null +++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a211oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a211oi_1.sp ('sky130_fd_sc_ms__a211oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a211oi/sky130_fd_sc_ms__a211oi_1.spice ('sky130_fd_sc_ms__a211oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:50:16 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a211oi_1 sky130_fd_sc_ms__a211oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a211oi_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a211oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pex.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pex.spice index 0d3ddb8..bdb35c7 100644 --- a/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pex.spice +++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211oi_1.pex.spice -* Created: Fri Aug 28 16:57:05 2020 +* Created: Wed Sep 2 11:50:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pxi.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pxi.spice index a377506..c9d199a 100644 --- a/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pxi.spice +++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211oi_1.pxi.spice -* Created: Fri Aug 28 16:57:05 2020 +* Created: Wed Sep 2 11:50:18 2020 * x_PM_SKY130_FD_SC_MS__A211OI_1%A2 N_A2_M1005_g N_A2_M1003_g A2 N_A2_c_52_n + N_A2_c_53_n PM_SKY130_FD_SC_MS__A211OI_1%A2
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_1.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.spice index e2ddb4e..77e5418 100644 --- a/cells/a211oi/sky130_fd_sc_ms__a211oi_1.spice +++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211oi_1.spice -* Created: Fri Aug 28 16:57:05 2020 +* Created: Wed Sep 2 11:50:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_2.lvs.report b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.lvs.report new file mode 100644 index 0000000..71cbbb4 --- /dev/null +++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a211oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a211oi_2.sp ('sky130_fd_sc_ms__a211oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a211oi/sky130_fd_sc_ms__a211oi_2.spice ('sky130_fd_sc_ms__a211oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:50:22 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a211oi_2 sky130_fd_sc_ms__a211oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a211oi_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a211oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 6 6 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pex.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pex.spice index c9eceea..24acffc 100644 --- a/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pex.spice +++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211oi_2.pex.spice -* Created: Fri Aug 28 16:57:34 2020 +* Created: Wed Sep 2 11:50:25 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pxi.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pxi.spice index b7a8569..bdc1c27 100644 --- a/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pxi.spice +++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211oi_2.pxi.spice -* Created: Fri Aug 28 16:57:34 2020 +* Created: Wed Sep 2 11:50:25 2020 * x_PM_SKY130_FD_SC_MS__A211OI_2%A1 N_A1_M1010_g N_A1_c_79_n N_A1_M1007_g + N_A1_M1011_g N_A1_c_81_n N_A1_M1009_g A1 N_A1_c_83_n
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_2.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.spice index f266de1..0e415d3 100644 --- a/cells/a211oi/sky130_fd_sc_ms__a211oi_2.spice +++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211oi_2.spice -* Created: Fri Aug 28 16:57:34 2020 +* Created: Wed Sep 2 11:50:25 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_4.lvs.report b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.lvs.report new file mode 100644 index 0000000..557e18a --- /dev/null +++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a211oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a211oi_4.sp ('sky130_fd_sc_ms__a211oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a211oi/sky130_fd_sc_ms__a211oi_4.spice ('sky130_fd_sc_ms__a211oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:50:28 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a211oi_4 sky130_fd_sc_ms__a211oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a211oi_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a211oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 12 12 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1_1 (6 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 8. + 20 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 8. + 20 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pex.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pex.spice index e64db34..3e312de 100644 --- a/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pex.spice +++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211oi_4.pex.spice -* Created: Fri Aug 28 16:57:43 2020 +* Created: Wed Sep 2 11:50:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pxi.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pxi.spice index 604315f..0692723 100644 --- a/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pxi.spice +++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211oi_4.pxi.spice -* Created: Fri Aug 28 16:57:43 2020 +* Created: Wed Sep 2 11:50:31 2020 * x_PM_SKY130_FD_SC_MS__A211OI_4%A2 N_A2_M1006_g N_A2_M1003_g N_A2_M1009_g + N_A2_M1005_g N_A2_M1011_g N_A2_M1010_g N_A2_M1016_g N_A2_M1012_g A2 A2 A2 A2
diff --git a/cells/a211oi/sky130_fd_sc_ms__a211oi_4.spice b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.spice index d721eac..7cab312 100644 --- a/cells/a211oi/sky130_fd_sc_ms__a211oi_4.spice +++ b/cells/a211oi/sky130_fd_sc_ms__a211oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a211oi_4.spice -* Created: Fri Aug 28 16:57:43 2020 +* Created: Wed Sep 2 11:50:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_1.lvs.report b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.lvs.report new file mode 100644 index 0000000..8664121 --- /dev/null +++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a21bo_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a21bo_1.sp ('sky130_fd_sc_ms__a21bo_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21bo/sky130_fd_sc_ms__a21bo_1.spice ('sky130_fd_sc_ms__a21bo_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:50:35 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a21bo_1 sky130_fd_sc_ms__a21bo_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a21bo_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a21bo_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1_N VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pex.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pex.spice index b15499e..d047161 100644 --- a/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pex.spice +++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21bo_1.pex.spice -* Created: Fri Aug 28 16:57:52 2020 +* Created: Wed Sep 2 11:50:38 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pxi.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pxi.spice index 828bf31..2ba28f8 100644 --- a/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pxi.spice +++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21bo_1.pxi.spice -* Created: Fri Aug 28 16:57:52 2020 +* Created: Wed Sep 2 11:50:38 2020 * x_PM_SKY130_FD_SC_MS__A21BO_1%A2 N_A2_c_75_n N_A2_M1006_g N_A2_M1002_g + N_A2_c_78_n A2 N_A2_c_79_n PM_SKY130_FD_SC_MS__A21BO_1%A2
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_1.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.spice index e8f64a6..4535001 100644 --- a/cells/a21bo/sky130_fd_sc_ms__a21bo_1.spice +++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21bo_1.spice -* Created: Fri Aug 28 16:57:52 2020 +* Created: Wed Sep 2 11:50:38 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_2.lvs.report b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.lvs.report new file mode 100644 index 0000000..d051597 --- /dev/null +++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a21bo_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a21bo_2.sp ('sky130_fd_sc_ms__a21bo_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21bo/sky130_fd_sc_ms__a21bo_2.spice ('sky130_fd_sc_ms__a21bo_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:50:41 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a21bo_2 sky130_fd_sc_ms__a21bo_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a21bo_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a21bo_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pex.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pex.spice index 1f80591..d6d7c0e 100644 --- a/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pex.spice +++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21bo_2.pex.spice -* Created: Fri Aug 28 16:58:00 2020 +* Created: Wed Sep 2 11:50:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pxi.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pxi.spice index 37a627a..06bfdbb 100644 --- a/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pxi.spice +++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21bo_2.pxi.spice -* Created: Fri Aug 28 16:58:00 2020 +* Created: Wed Sep 2 11:50:44 2020 * x_PM_SKY130_FD_SC_MS__A21BO_2%B1_N N_B1_N_M1001_g N_B1_N_c_74_n N_B1_N_M1010_g + B1_N N_B1_N_c_75_n N_B1_N_c_76_n PM_SKY130_FD_SC_MS__A21BO_2%B1_N
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_2.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.spice index d5a85d5..ad19a6c 100644 --- a/cells/a21bo/sky130_fd_sc_ms__a21bo_2.spice +++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21bo_2.spice -* Created: Fri Aug 28 16:58:00 2020 +* Created: Wed Sep 2 11:50:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_4.lvs.report b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.lvs.report new file mode 100644 index 0000000..b8298d9 --- /dev/null +++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a21bo_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a21bo_4.sp ('sky130_fd_sc_ms__a21bo_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21bo/sky130_fd_sc_ms__a21bo_4.spice ('sky130_fd_sc_ms__a21bo_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:50:48 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a21bo_4 sky130_fd_sc_ms__a21bo_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a21bo_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a21bo_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pex.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pex.spice index 04e4aeb..456750f 100644 --- a/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pex.spice +++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21bo_4.pex.spice -* Created: Fri Aug 28 16:58:09 2020 +* Created: Wed Sep 2 11:50:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pxi.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pxi.spice index 37d4dbe..c799c42 100644 --- a/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pxi.spice +++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21bo_4.pxi.spice -* Created: Fri Aug 28 16:58:09 2020 +* Created: Wed Sep 2 11:50:50 2020 * x_PM_SKY130_FD_SC_MS__A21BO_4%B1_N N_B1_N_M1016_g N_B1_N_M1009_g N_B1_N_c_115_n + B1_N N_B1_N_c_117_n PM_SKY130_FD_SC_MS__A21BO_4%B1_N
diff --git a/cells/a21bo/sky130_fd_sc_ms__a21bo_4.spice b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.spice index e65c355..2eafcf2 100644 --- a/cells/a21bo/sky130_fd_sc_ms__a21bo_4.spice +++ b/cells/a21bo/sky130_fd_sc_ms__a21bo_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21bo_4.spice -* Created: Fri Aug 28 16:58:09 2020 +* Created: Wed Sep 2 11:50:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_1.lvs.report b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.lvs.report new file mode 100644 index 0000000..b67edb7 --- /dev/null +++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a21boi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a21boi_1.sp ('sky130_fd_sc_ms__a21boi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21boi/sky130_fd_sc_ms__a21boi_1.spice ('sky130_fd_sc_ms__a21boi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:50:54 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a21boi_1 sky130_fd_sc_ms__a21boi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a21boi_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a21boi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A1 A2 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pex.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pex.spice index 4c747fa..3fb6593 100644 --- a/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pex.spice +++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21boi_1.pex.spice -* Created: Fri Aug 28 16:58:38 2020 +* Created: Wed Sep 2 11:50:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pxi.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pxi.spice index ca0a5db..b3c399a 100644 --- a/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pxi.spice +++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21boi_1.pxi.spice -* Created: Fri Aug 28 16:58:38 2020 +* Created: Wed Sep 2 11:50:57 2020 * x_PM_SKY130_FD_SC_MS__A21BOI_1%B1_N N_B1_N_c_60_n N_B1_N_M1007_g N_B1_N_c_61_n + N_B1_N_c_62_n N_B1_N_M1001_g B1_N B1_N B1_N N_B1_N_c_63_n N_B1_N_c_64_n
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_1.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.spice index 3ba2ab0..20da2f6 100644 --- a/cells/a21boi/sky130_fd_sc_ms__a21boi_1.spice +++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21boi_1.spice -* Created: Fri Aug 28 16:58:38 2020 +* Created: Wed Sep 2 11:50:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_2.lvs.report b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.lvs.report new file mode 100644 index 0000000..0ece6b3 --- /dev/null +++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a21boi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a21boi_2.sp ('sky130_fd_sc_ms__a21boi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21boi/sky130_fd_sc_ms__a21boi_2.spice ('sky130_fd_sc_ms__a21boi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:51:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a21boi_2 sky130_fd_sc_ms__a21boi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a21boi_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a21boi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A1 A2 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pex.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pex.spice index 22a6a52..098014c 100644 --- a/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pex.spice +++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21boi_2.pex.spice -* Created: Fri Aug 28 16:58:47 2020 +* Created: Wed Sep 2 11:51:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pxi.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pxi.spice index e0e12d4..e389ef4 100644 --- a/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pxi.spice +++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21boi_2.pxi.spice -* Created: Fri Aug 28 16:58:47 2020 +* Created: Wed Sep 2 11:51:03 2020 * x_PM_SKY130_FD_SC_MS__A21BOI_2%B1_N N_B1_N_M1010_g N_B1_N_M1003_g N_B1_N_c_84_n + N_B1_N_c_85_n B1_N PM_SKY130_FD_SC_MS__A21BOI_2%B1_N
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_2.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.spice index 68f5091..6963a30 100644 --- a/cells/a21boi/sky130_fd_sc_ms__a21boi_2.spice +++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21boi_2.spice -* Created: Fri Aug 28 16:58:47 2020 +* Created: Wed Sep 2 11:51:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_4.lvs.report b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.lvs.report new file mode 100644 index 0000000..3c3c507 --- /dev/null +++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a21boi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a21boi_4.sp ('sky130_fd_sc_ms__a21boi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21boi/sky130_fd_sc_ms__a21boi_4.spice ('sky130_fd_sc_ms__a21boi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:51:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a21boi_4 sky130_fd_sc_ms__a21boi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a21boi_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a21boi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 13 13 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 28 27 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 26 layout mos transistors were reduced to 7. + 19 mos transistors were deleted by parallel reduction. + 26 source mos transistors were reduced to 7. + 19 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1_N VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pex.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pex.spice index ac82c44..b8be4d3 100644 --- a/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pex.spice +++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21boi_4.pex.spice -* Created: Fri Aug 28 16:58:57 2020 +* Created: Wed Sep 2 11:51:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pxi.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pxi.spice index 5f3c5f4..ec7b7c5 100644 --- a/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pxi.spice +++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21boi_4.pxi.spice -* Created: Fri Aug 28 16:58:57 2020 +* Created: Wed Sep 2 11:51:10 2020 * x_PM_SKY130_FD_SC_MS__A21BOI_4%A1 N_A1_M1008_g N_A1_M1003_g N_A1_M1009_g + N_A1_M1005_g N_A1_M1010_g N_A1_M1006_g N_A1_M1014_g N_A1_M1015_g A1 A1 A1 A1
diff --git a/cells/a21boi/sky130_fd_sc_ms__a21boi_4.spice b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.spice index 5ff5554..2cc175f 100644 --- a/cells/a21boi/sky130_fd_sc_ms__a21boi_4.spice +++ b/cells/a21boi/sky130_fd_sc_ms__a21boi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21boi_4.spice -* Created: Fri Aug 28 16:58:57 2020 +* Created: Wed Sep 2 11:51:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_1.lvs.report b/cells/a21o/sky130_fd_sc_ms__a21o_1.lvs.report new file mode 100644 index 0000000..e7f11b7 --- /dev/null +++ b/cells/a21o/sky130_fd_sc_ms__a21o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a21o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a21o_1.sp ('sky130_fd_sc_ms__a21o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21o/sky130_fd_sc_ms__a21o_1.spice ('sky130_fd_sc_ms__a21o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:51:14 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a21o_1 sky130_fd_sc_ms__a21o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a21o_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a21o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_1.pex.spice b/cells/a21o/sky130_fd_sc_ms__a21o_1.pex.spice index ea1e74e..23bddaa 100644 --- a/cells/a21o/sky130_fd_sc_ms__a21o_1.pex.spice +++ b/cells/a21o/sky130_fd_sc_ms__a21o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21o_1.pex.spice -* Created: Fri Aug 28 16:59:05 2020 +* Created: Wed Sep 2 11:51:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_1.pxi.spice b/cells/a21o/sky130_fd_sc_ms__a21o_1.pxi.spice index 229c4d2..4d328be 100644 --- a/cells/a21o/sky130_fd_sc_ms__a21o_1.pxi.spice +++ b/cells/a21o/sky130_fd_sc_ms__a21o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21o_1.pxi.spice -* Created: Fri Aug 28 16:59:05 2020 +* Created: Wed Sep 2 11:51:16 2020 * x_PM_SKY130_FD_SC_MS__A21O_1%A_81_264# N_A_81_264#_M1003_d N_A_81_264#_M1006_s + N_A_81_264#_M1005_g N_A_81_264#_c_63_n N_A_81_264#_c_64_n N_A_81_264#_M1000_g
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_1.spice b/cells/a21o/sky130_fd_sc_ms__a21o_1.spice index ab1e19e..36b208b 100644 --- a/cells/a21o/sky130_fd_sc_ms__a21o_1.spice +++ b/cells/a21o/sky130_fd_sc_ms__a21o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21o_1.spice -* Created: Fri Aug 28 16:59:05 2020 +* Created: Wed Sep 2 11:51:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_2.lvs.report b/cells/a21o/sky130_fd_sc_ms__a21o_2.lvs.report new file mode 100644 index 0000000..272e692 --- /dev/null +++ b/cells/a21o/sky130_fd_sc_ms__a21o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a21o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a21o_2.sp ('sky130_fd_sc_ms__a21o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21o/sky130_fd_sc_ms__a21o_2.spice ('sky130_fd_sc_ms__a21o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:51:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a21o_2 sky130_fd_sc_ms__a21o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a21o_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a21o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_2.pex.spice b/cells/a21o/sky130_fd_sc_ms__a21o_2.pex.spice index ecc2512..6b4700d 100644 --- a/cells/a21o/sky130_fd_sc_ms__a21o_2.pex.spice +++ b/cells/a21o/sky130_fd_sc_ms__a21o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21o_2.pex.spice -* Created: Fri Aug 28 16:59:14 2020 +* Created: Wed Sep 2 11:51:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_2.pxi.spice b/cells/a21o/sky130_fd_sc_ms__a21o_2.pxi.spice index dcafd8e..9101271 100644 --- a/cells/a21o/sky130_fd_sc_ms__a21o_2.pxi.spice +++ b/cells/a21o/sky130_fd_sc_ms__a21o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21o_2.pxi.spice -* Created: Fri Aug 28 16:59:14 2020 +* Created: Wed Sep 2 11:51:23 2020 * x_PM_SKY130_FD_SC_MS__A21O_2%A_84_244# N_A_84_244#_M1004_d N_A_84_244#_M1007_s + N_A_84_244#_M1001_g N_A_84_244#_c_61_n N_A_84_244#_M1003_g N_A_84_244#_M1002_g
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_2.spice b/cells/a21o/sky130_fd_sc_ms__a21o_2.spice index e55aad2..bfe8441 100644 --- a/cells/a21o/sky130_fd_sc_ms__a21o_2.spice +++ b/cells/a21o/sky130_fd_sc_ms__a21o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21o_2.spice -* Created: Fri Aug 28 16:59:14 2020 +* Created: Wed Sep 2 11:51:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_4.lvs.report b/cells/a21o/sky130_fd_sc_ms__a21o_4.lvs.report new file mode 100644 index 0000000..db01b4e --- /dev/null +++ b/cells/a21o/sky130_fd_sc_ms__a21o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a21o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a21o_4.sp ('sky130_fd_sc_ms__a21o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21o/sky130_fd_sc_ms__a21o_4.spice ('sky130_fd_sc_ms__a21o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:51:26 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a21o_4 sky130_fd_sc_ms__a21o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a21o_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a21o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_4.pex.spice b/cells/a21o/sky130_fd_sc_ms__a21o_4.pex.spice index ce1bc76..8c8db2c 100644 --- a/cells/a21o/sky130_fd_sc_ms__a21o_4.pex.spice +++ b/cells/a21o/sky130_fd_sc_ms__a21o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21o_4.pex.spice -* Created: Fri Aug 28 16:59:43 2020 +* Created: Wed Sep 2 11:51:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_4.pxi.spice b/cells/a21o/sky130_fd_sc_ms__a21o_4.pxi.spice index dc8dde6..182a3a7 100644 --- a/cells/a21o/sky130_fd_sc_ms__a21o_4.pxi.spice +++ b/cells/a21o/sky130_fd_sc_ms__a21o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21o_4.pxi.spice -* Created: Fri Aug 28 16:59:43 2020 +* Created: Wed Sep 2 11:51:29 2020 * x_PM_SKY130_FD_SC_MS__A21O_4%A_91_48# N_A_91_48#_M1005_d N_A_91_48#_M1003_s + N_A_91_48#_M1006_d N_A_91_48#_M1001_g N_A_91_48#_M1007_g N_A_91_48#_M1004_g
diff --git a/cells/a21o/sky130_fd_sc_ms__a21o_4.spice b/cells/a21o/sky130_fd_sc_ms__a21o_4.spice index a5fa17e..e374455 100644 --- a/cells/a21o/sky130_fd_sc_ms__a21o_4.spice +++ b/cells/a21o/sky130_fd_sc_ms__a21o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21o_4.spice -* Created: Fri Aug 28 16:59:43 2020 +* Created: Wed Sep 2 11:51:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_1.lvs.report b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.lvs.report new file mode 100644 index 0000000..a7f060b --- /dev/null +++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a21oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a21oi_1.sp ('sky130_fd_sc_ms__a21oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21oi/sky130_fd_sc_ms__a21oi_1.spice ('sky130_fd_sc_ms__a21oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:51:32 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a21oi_1 sky130_fd_sc_ms__a21oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a21oi_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a21oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pex.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pex.spice index dfe616d..bec2dab 100644 --- a/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pex.spice +++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21oi_1.pex.spice -* Created: Fri Aug 28 16:59:52 2020 +* Created: Wed Sep 2 11:51:35 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pxi.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pxi.spice index 1d573d4..39cd5a8 100644 --- a/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pxi.spice +++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21oi_1.pxi.spice -* Created: Fri Aug 28 16:59:52 2020 +* Created: Wed Sep 2 11:51:35 2020 * x_PM_SKY130_FD_SC_MS__A21OI_1%A2 N_A2_M1003_g N_A2_c_40_n N_A2_M1005_g A2 + N_A2_c_42_n PM_SKY130_FD_SC_MS__A21OI_1%A2
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_1.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.spice index 753d8c7..f4994c5 100644 --- a/cells/a21oi/sky130_fd_sc_ms__a21oi_1.spice +++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21oi_1.spice -* Created: Fri Aug 28 16:59:52 2020 +* Created: Wed Sep 2 11:51:35 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_2.lvs.report b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.lvs.report new file mode 100644 index 0000000..29aa6d3 --- /dev/null +++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a21oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a21oi_2.sp ('sky130_fd_sc_ms__a21oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21oi/sky130_fd_sc_ms__a21oi_2.spice ('sky130_fd_sc_ms__a21oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:51:39 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a21oi_2 sky130_fd_sc_ms__a21oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a21oi_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a21oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 12 11 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 10 layout mos transistors were reduced to 5. + 5 mos transistors were deleted by parallel reduction. + 10 source mos transistors were reduced to 5. + 5 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A2 A1 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pex.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pex.spice index d628d53..c0f6903 100644 --- a/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pex.spice +++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21oi_2.pex.spice -* Created: Fri Aug 28 17:00:01 2020 +* Created: Wed Sep 2 11:51:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pxi.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pxi.spice index e16db12..ca0c3a5 100644 --- a/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pxi.spice +++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21oi_2.pxi.spice -* Created: Fri Aug 28 17:00:01 2020 +* Created: Wed Sep 2 11:51:41 2020 * x_PM_SKY130_FD_SC_MS__A21OI_2%B1 N_B1_M1007_g N_B1_c_70_n N_B1_c_76_n + N_B1_M1003_g N_B1_c_71_n N_B1_c_78_n N_B1_M1004_g N_B1_c_72_n B1 N_B1_c_74_n
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_2.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.spice index 4bc5ffc..ea3b633 100644 --- a/cells/a21oi/sky130_fd_sc_ms__a21oi_2.spice +++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21oi_2.spice -* Created: Fri Aug 28 17:00:01 2020 +* Created: Wed Sep 2 11:51:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_4.lvs.report b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.lvs.report new file mode 100644 index 0000000..d009a6b --- /dev/null +++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a21oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a21oi_4.sp ('sky130_fd_sc_ms__a21oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a21oi/sky130_fd_sc_ms__a21oi_4.spice ('sky130_fd_sc_ms__a21oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:51:48 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a21oi_4 sky130_fd_sc_ms__a21oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a21oi_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a21oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 10 10 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 22 layout mos transistors were reduced to 6. + 16 mos transistors were deleted by parallel reduction. + 22 source mos transistors were reduced to 6. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pex.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pex.spice index 098cd8f..83d264b 100644 --- a/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pex.spice +++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21oi_4.pex.spice -* Created: Fri Aug 28 17:00:10 2020 +* Created: Wed Sep 2 11:51:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pxi.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pxi.spice index 3fec3d1..936e6d0 100644 --- a/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pxi.spice +++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21oi_4.pxi.spice -* Created: Fri Aug 28 17:00:10 2020 +* Created: Wed Sep 2 11:51:51 2020 * x_PM_SKY130_FD_SC_MS__A21OI_4%A2 N_A2_M1003_g N_A2_M1002_g N_A2_M1005_g + N_A2_M1014_g N_A2_M1007_g N_A2_M1015_g N_A2_M1008_g N_A2_M1017_g A2 A2 A2
diff --git a/cells/a21oi/sky130_fd_sc_ms__a21oi_4.spice b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.spice index fd40fe8..9c652ea 100644 --- a/cells/a21oi/sky130_fd_sc_ms__a21oi_4.spice +++ b/cells/a21oi/sky130_fd_sc_ms__a21oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a21oi_4.spice -* Created: Fri Aug 28 17:00:10 2020 +* Created: Wed Sep 2 11:51:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_1.lvs.report b/cells/a221o/sky130_fd_sc_ms__a221o_1.lvs.report new file mode 100644 index 0000000..2f2a8c0 --- /dev/null +++ b/cells/a221o/sky130_fd_sc_ms__a221o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a221o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a221o_1.sp ('sky130_fd_sc_ms__a221o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a221o/sky130_fd_sc_ms__a221o_1.spice ('sky130_fd_sc_ms__a221o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:51:55 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a221o_1 sky130_fd_sc_ms__a221o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a221o_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a221o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 B2 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_1.pex.spice b/cells/a221o/sky130_fd_sc_ms__a221o_1.pex.spice index 1d9a268..3c97388 100644 --- a/cells/a221o/sky130_fd_sc_ms__a221o_1.pex.spice +++ b/cells/a221o/sky130_fd_sc_ms__a221o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221o_1.pex.spice -* Created: Fri Aug 28 17:00:19 2020 +* Created: Wed Sep 2 11:51:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_1.pxi.spice b/cells/a221o/sky130_fd_sc_ms__a221o_1.pxi.spice index 56eccdd..5d115d1 100644 --- a/cells/a221o/sky130_fd_sc_ms__a221o_1.pxi.spice +++ b/cells/a221o/sky130_fd_sc_ms__a221o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221o_1.pxi.spice -* Created: Fri Aug 28 17:00:19 2020 +* Created: Wed Sep 2 11:51:58 2020 * x_PM_SKY130_FD_SC_MS__A221O_1%A_148_260# N_A_148_260#_M1005_d + N_A_148_260#_M1003_d N_A_148_260#_M1006_d N_A_148_260#_M1000_g
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_1.spice b/cells/a221o/sky130_fd_sc_ms__a221o_1.spice index 8f50bd9..9e5c1cc 100644 --- a/cells/a221o/sky130_fd_sc_ms__a221o_1.spice +++ b/cells/a221o/sky130_fd_sc_ms__a221o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221o_1.spice -* Created: Fri Aug 28 17:00:19 2020 +* Created: Wed Sep 2 11:51:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_2.lvs.report b/cells/a221o/sky130_fd_sc_ms__a221o_2.lvs.report new file mode 100644 index 0000000..5e85d43 --- /dev/null +++ b/cells/a221o/sky130_fd_sc_ms__a221o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a221o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a221o_2.sp ('sky130_fd_sc_ms__a221o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a221o/sky130_fd_sc_ms__a221o_2.spice ('sky130_fd_sc_ms__a221o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:52:02 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a221o_2 sky130_fd_sc_ms__a221o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a221o_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a221o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 B2 C1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_2.pex.spice b/cells/a221o/sky130_fd_sc_ms__a221o_2.pex.spice index 7483897..ed2fd09 100644 --- a/cells/a221o/sky130_fd_sc_ms__a221o_2.pex.spice +++ b/cells/a221o/sky130_fd_sc_ms__a221o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221o_2.pex.spice -* Created: Fri Aug 28 17:00:49 2020 +* Created: Wed Sep 2 11:52:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_2.pxi.spice b/cells/a221o/sky130_fd_sc_ms__a221o_2.pxi.spice index 7830601..93587f1 100644 --- a/cells/a221o/sky130_fd_sc_ms__a221o_2.pxi.spice +++ b/cells/a221o/sky130_fd_sc_ms__a221o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221o_2.pxi.spice -* Created: Fri Aug 28 17:00:49 2020 +* Created: Wed Sep 2 11:52:05 2020 * x_PM_SKY130_FD_SC_MS__A221O_2%A_89_260# N_A_89_260#_M1001_d N_A_89_260#_M1010_d + N_A_89_260#_M1006_d N_A_89_260#_M1011_g N_A_89_260#_M1002_g
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_2.spice b/cells/a221o/sky130_fd_sc_ms__a221o_2.spice index 48fb8b1..7151669 100644 --- a/cells/a221o/sky130_fd_sc_ms__a221o_2.spice +++ b/cells/a221o/sky130_fd_sc_ms__a221o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221o_2.spice -* Created: Fri Aug 28 17:00:49 2020 +* Created: Wed Sep 2 11:52:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_4.lvs.report b/cells/a221o/sky130_fd_sc_ms__a221o_4.lvs.report new file mode 100644 index 0000000..cbcf357 --- /dev/null +++ b/cells/a221o/sky130_fd_sc_ms__a221o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a221o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a221o_4.sp ('sky130_fd_sc_ms__a221o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a221o/sky130_fd_sc_ms__a221o_4.spice ('sky130_fd_sc_ms__a221o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:52:08 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a221o_4 sky130_fd_sc_ms__a221o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a221o_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a221o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 C1 B2 B1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_4.pex.spice b/cells/a221o/sky130_fd_sc_ms__a221o_4.pex.spice index 53c7bb7..3d8257b 100644 --- a/cells/a221o/sky130_fd_sc_ms__a221o_4.pex.spice +++ b/cells/a221o/sky130_fd_sc_ms__a221o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221o_4.pex.spice -* Created: Fri Aug 28 17:00:58 2020 +* Created: Wed Sep 2 11:52:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_4.pxi.spice b/cells/a221o/sky130_fd_sc_ms__a221o_4.pxi.spice index d64241f..c07cb98 100644 --- a/cells/a221o/sky130_fd_sc_ms__a221o_4.pxi.spice +++ b/cells/a221o/sky130_fd_sc_ms__a221o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221o_4.pxi.spice -* Created: Fri Aug 28 17:00:58 2020 +* Created: Wed Sep 2 11:52:11 2020 * x_PM_SKY130_FD_SC_MS__A221O_4%A1 N_A1_M1009_g N_A1_c_157_n N_A1_M1016_g + N_A1_c_159_n N_A1_c_160_n N_A1_M1011_g N_A1_c_162_n N_A1_M1018_g N_A1_c_164_n
diff --git a/cells/a221o/sky130_fd_sc_ms__a221o_4.spice b/cells/a221o/sky130_fd_sc_ms__a221o_4.spice index 47883c4..2df5b15 100644 --- a/cells/a221o/sky130_fd_sc_ms__a221o_4.spice +++ b/cells/a221o/sky130_fd_sc_ms__a221o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221o_4.spice -* Created: Fri Aug 28 17:00:58 2020 +* Created: Wed Sep 2 11:52:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221oi/sky130_fd_sc_ms__a221oi_1.lvs.report b/cells/a221oi/sky130_fd_sc_ms__a221oi_1.lvs.report new file mode 100644 index 0000000..dabd36f --- /dev/null +++ b/cells/a221oi/sky130_fd_sc_ms__a221oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a221oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a221oi_1.sp ('sky130_fd_sc_ms__a221oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a221oi/sky130_fd_sc_ms__a221oi_1.spice ('sky130_fd_sc_ms__a221oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:52:15 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a221oi_1 sky130_fd_sc_ms__a221oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a221oi_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a221oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B2 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_ms__a221oi_1.pex.spice b/cells/a221oi/sky130_fd_sc_ms__a221oi_1.pex.spice index 5f7a23a..3734c22 100644 --- a/cells/a221oi/sky130_fd_sc_ms__a221oi_1.pex.spice +++ b/cells/a221oi/sky130_fd_sc_ms__a221oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221oi_1.pex.spice -* Created: Fri Aug 28 17:01:07 2020 +* Created: Wed Sep 2 11:52:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_ms__a221oi_1.pxi.spice b/cells/a221oi/sky130_fd_sc_ms__a221oi_1.pxi.spice index 3d101b0..5e772a0 100644 --- a/cells/a221oi/sky130_fd_sc_ms__a221oi_1.pxi.spice +++ b/cells/a221oi/sky130_fd_sc_ms__a221oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221oi_1.pxi.spice -* Created: Fri Aug 28 17:01:07 2020 +* Created: Wed Sep 2 11:52:18 2020 * x_PM_SKY130_FD_SC_MS__A221OI_1%C1 N_C1_M1009_g N_C1_M1003_g C1 N_C1_c_58_n + N_C1_c_59_n PM_SKY130_FD_SC_MS__A221OI_1%C1
diff --git a/cells/a221oi/sky130_fd_sc_ms__a221oi_1.spice b/cells/a221oi/sky130_fd_sc_ms__a221oi_1.spice index 48e6fb1..b750b85 100644 --- a/cells/a221oi/sky130_fd_sc_ms__a221oi_1.spice +++ b/cells/a221oi/sky130_fd_sc_ms__a221oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221oi_1.spice -* Created: Fri Aug 28 17:01:07 2020 +* Created: Wed Sep 2 11:52:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221oi/sky130_fd_sc_ms__a221oi_2.lvs.report b/cells/a221oi/sky130_fd_sc_ms__a221oi_2.lvs.report new file mode 100644 index 0000000..2ef6b1b --- /dev/null +++ b/cells/a221oi/sky130_fd_sc_ms__a221oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a221oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a221oi_2.sp ('sky130_fd_sc_ms__a221oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a221oi/sky130_fd_sc_ms__a221oi_2.spice ('sky130_fd_sc_ms__a221oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:52:21 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a221oi_2 sky130_fd_sc_ms__a221oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a221oi_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a221oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 B2 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_ms__a221oi_2.pex.spice b/cells/a221oi/sky130_fd_sc_ms__a221oi_2.pex.spice index 24d0d45..a530159 100644 --- a/cells/a221oi/sky130_fd_sc_ms__a221oi_2.pex.spice +++ b/cells/a221oi/sky130_fd_sc_ms__a221oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221oi_2.pex.spice -* Created: Fri Aug 28 17:01:16 2020 +* Created: Wed Sep 2 11:52:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_ms__a221oi_2.pxi.spice b/cells/a221oi/sky130_fd_sc_ms__a221oi_2.pxi.spice index 23b125a..235deaf 100644 --- a/cells/a221oi/sky130_fd_sc_ms__a221oi_2.pxi.spice +++ b/cells/a221oi/sky130_fd_sc_ms__a221oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221oi_2.pxi.spice -* Created: Fri Aug 28 17:01:16 2020 +* Created: Wed Sep 2 11:52:24 2020 * x_PM_SKY130_FD_SC_MS__A221OI_2%C1 N_C1_M1016_g N_C1_M1015_g N_C1_M1017_g + N_C1_M1019_g C1 N_C1_c_103_n N_C1_c_104_n PM_SKY130_FD_SC_MS__A221OI_2%C1
diff --git a/cells/a221oi/sky130_fd_sc_ms__a221oi_2.spice b/cells/a221oi/sky130_fd_sc_ms__a221oi_2.spice index cfe2b01..9c831be 100644 --- a/cells/a221oi/sky130_fd_sc_ms__a221oi_2.spice +++ b/cells/a221oi/sky130_fd_sc_ms__a221oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221oi_2.spice -* Created: Fri Aug 28 17:01:16 2020 +* Created: Wed Sep 2 11:52:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a221oi/sky130_fd_sc_ms__a221oi_4.lvs.report b/cells/a221oi/sky130_fd_sc_ms__a221oi_4.lvs.report new file mode 100644 index 0000000..4335aef --- /dev/null +++ b/cells/a221oi/sky130_fd_sc_ms__a221oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a221oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a221oi_4.sp ('sky130_fd_sc_ms__a221oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a221oi/sky130_fd_sc_ms__a221oi_4.spice ('sky130_fd_sc_ms__a221oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:52:28 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a221oi_4 sky130_fd_sc_ms__a221oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a221oi_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a221oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 40 layout mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + 40 source mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 A2 A1 B1 B2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_ms__a221oi_4.pex.spice b/cells/a221oi/sky130_fd_sc_ms__a221oi_4.pex.spice index fc87688..7c23ed1 100644 --- a/cells/a221oi/sky130_fd_sc_ms__a221oi_4.pex.spice +++ b/cells/a221oi/sky130_fd_sc_ms__a221oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221oi_4.pex.spice -* Created: Fri Aug 28 17:01:24 2020 +* Created: Wed Sep 2 11:52:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_ms__a221oi_4.pxi.spice b/cells/a221oi/sky130_fd_sc_ms__a221oi_4.pxi.spice index 1f407ca..ba13338 100644 --- a/cells/a221oi/sky130_fd_sc_ms__a221oi_4.pxi.spice +++ b/cells/a221oi/sky130_fd_sc_ms__a221oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221oi_4.pxi.spice -* Created: Fri Aug 28 17:01:24 2020 +* Created: Wed Sep 2 11:52:31 2020 * x_PM_SKY130_FD_SC_MS__A221OI_4%C1 N_C1_M1031_g N_C1_M1016_g N_C1_M1032_g + N_C1_M1022_g N_C1_M1035_g N_C1_M1026_g N_C1_M1037_g N_C1_M1038_g C1 C1 C1
diff --git a/cells/a221oi/sky130_fd_sc_ms__a221oi_4.spice b/cells/a221oi/sky130_fd_sc_ms__a221oi_4.spice index 1999efd..d4e035e 100644 --- a/cells/a221oi/sky130_fd_sc_ms__a221oi_4.spice +++ b/cells/a221oi/sky130_fd_sc_ms__a221oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a221oi_4.spice -* Created: Fri Aug 28 17:01:24 2020 +* Created: Wed Sep 2 11:52:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a222o/sky130_fd_sc_ms__a222o_1.lvs.report b/cells/a222o/sky130_fd_sc_ms__a222o_1.lvs.report new file mode 100644 index 0000000..0074f9f --- /dev/null +++ b/cells/a222o/sky130_fd_sc_ms__a222o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a222o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a222o_1.sp ('sky130_fd_sc_ms__a222o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a222o/sky130_fd_sc_ms__a222o_1.spice ('sky130_fd_sc_ms__a222o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:52:34 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a222o_1 sky130_fd_sc_ms__a222o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a222o_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a222o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 17 17 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 12 12 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SPMP_2_2_2 (8 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 11 11 0 0 + + Nets: 12 12 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 1 1 0 0 SPMP_2_2_2 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 C2 B2 B1 A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a222o/sky130_fd_sc_ms__a222o_1.pex.spice b/cells/a222o/sky130_fd_sc_ms__a222o_1.pex.spice index 0d3dfb6..9795acc 100644 --- a/cells/a222o/sky130_fd_sc_ms__a222o_1.pex.spice +++ b/cells/a222o/sky130_fd_sc_ms__a222o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a222o_1.pex.spice -* Created: Fri Aug 28 17:01:54 2020 +* Created: Wed Sep 2 11:52:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a222o/sky130_fd_sc_ms__a222o_1.pxi.spice b/cells/a222o/sky130_fd_sc_ms__a222o_1.pxi.spice index 9a4b13d..9a93fbe 100644 --- a/cells/a222o/sky130_fd_sc_ms__a222o_1.pxi.spice +++ b/cells/a222o/sky130_fd_sc_ms__a222o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a222o_1.pxi.spice -* Created: Fri Aug 28 17:01:54 2020 +* Created: Wed Sep 2 11:52:37 2020 * x_PM_SKY130_FD_SC_MS__A222O_1%C1 N_C1_M1001_g N_C1_M1005_g C1 C1 N_C1_c_82_n + N_C1_c_83_n N_C1_c_84_n PM_SKY130_FD_SC_MS__A222O_1%C1
diff --git a/cells/a222o/sky130_fd_sc_ms__a222o_1.spice b/cells/a222o/sky130_fd_sc_ms__a222o_1.spice index d0091b1..ddc44cc 100644 --- a/cells/a222o/sky130_fd_sc_ms__a222o_1.spice +++ b/cells/a222o/sky130_fd_sc_ms__a222o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a222o_1.spice -* Created: Fri Aug 28 17:01:54 2020 +* Created: Wed Sep 2 11:52:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a222o/sky130_fd_sc_ms__a222o_2.lvs.report b/cells/a222o/sky130_fd_sc_ms__a222o_2.lvs.report new file mode 100644 index 0000000..854f24c --- /dev/null +++ b/cells/a222o/sky130_fd_sc_ms__a222o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a222o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a222o_2.sp ('sky130_fd_sc_ms__a222o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a222o/sky130_fd_sc_ms__a222o_2.spice ('sky130_fd_sc_ms__a222o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:52:41 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a222o_2 sky130_fd_sc_ms__a222o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a222o_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a222o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 17 17 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 12 12 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SPMP_2_2_2 (8 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 11 11 0 0 + + Nets: 12 12 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 1 1 0 0 SPMP_2_2_2 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 C2 A1 B1 B2 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a222o/sky130_fd_sc_ms__a222o_2.pex.spice b/cells/a222o/sky130_fd_sc_ms__a222o_2.pex.spice index 3f22cc5..e608b55 100644 --- a/cells/a222o/sky130_fd_sc_ms__a222o_2.pex.spice +++ b/cells/a222o/sky130_fd_sc_ms__a222o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a222o_2.pex.spice -* Created: Fri Aug 28 17:02:03 2020 +* Created: Wed Sep 2 11:52:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a222o/sky130_fd_sc_ms__a222o_2.pxi.spice b/cells/a222o/sky130_fd_sc_ms__a222o_2.pxi.spice index c3115b4..2cb3076 100644 --- a/cells/a222o/sky130_fd_sc_ms__a222o_2.pxi.spice +++ b/cells/a222o/sky130_fd_sc_ms__a222o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a222o_2.pxi.spice -* Created: Fri Aug 28 17:02:03 2020 +* Created: Wed Sep 2 11:52:44 2020 * x_PM_SKY130_FD_SC_MS__A222O_2%C1 N_C1_c_98_n N_C1_M1001_g N_C1_M1004_g + N_C1_c_95_n C1 N_C1_c_96_n N_C1_c_97_n PM_SKY130_FD_SC_MS__A222O_2%C1
diff --git a/cells/a222o/sky130_fd_sc_ms__a222o_2.spice b/cells/a222o/sky130_fd_sc_ms__a222o_2.spice index 9c84c0e..26d32bf 100644 --- a/cells/a222o/sky130_fd_sc_ms__a222o_2.spice +++ b/cells/a222o/sky130_fd_sc_ms__a222o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a222o_2.spice -* Created: Fri Aug 28 17:02:03 2020 +* Created: Wed Sep 2 11:52:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a222oi/sky130_fd_sc_ms__a222oi_1.lvs.report b/cells/a222oi/sky130_fd_sc_ms__a222oi_1.lvs.report new file mode 100644 index 0000000..d105bb9 --- /dev/null +++ b/cells/a222oi/sky130_fd_sc_ms__a222oi_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a222oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a222oi_1.sp ('sky130_fd_sc_ms__a222oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a222oi/sky130_fd_sc_ms__a222oi_1.spice ('sky130_fd_sc_ms__a222oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:52:47 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a222oi_1 sky130_fd_sc_ms__a222oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a222oi_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a222oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 16 16 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 11 11 + + Instances: 3 3 SMN2 (4 pins) + 1 1 SPMP_2_2_2 (8 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 11 11 0 0 + + Nets: 11 11 0 0 + + Instances: 3 3 0 0 SMN2 + 1 1 0 0 SPMP_2_2_2 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 C2 B2 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a222oi/sky130_fd_sc_ms__a222oi_1.pex.spice b/cells/a222oi/sky130_fd_sc_ms__a222oi_1.pex.spice index 3d72073..e624647 100644 --- a/cells/a222oi/sky130_fd_sc_ms__a222oi_1.pex.spice +++ b/cells/a222oi/sky130_fd_sc_ms__a222oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a222oi_1.pex.spice -* Created: Fri Aug 28 17:02:12 2020 +* Created: Wed Sep 2 11:52:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a222oi/sky130_fd_sc_ms__a222oi_1.pxi.spice b/cells/a222oi/sky130_fd_sc_ms__a222oi_1.pxi.spice index b877b8f..2ab0de2 100644 --- a/cells/a222oi/sky130_fd_sc_ms__a222oi_1.pxi.spice +++ b/cells/a222oi/sky130_fd_sc_ms__a222oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a222oi_1.pxi.spice -* Created: Fri Aug 28 17:02:12 2020 +* Created: Wed Sep 2 11:52:50 2020 * x_PM_SKY130_FD_SC_MS__A222OI_1%C1 N_C1_M1001_g N_C1_M1003_g C1 N_C1_c_73_n + N_C1_c_74_n N_C1_c_75_n PM_SKY130_FD_SC_MS__A222OI_1%C1
diff --git a/cells/a222oi/sky130_fd_sc_ms__a222oi_1.spice b/cells/a222oi/sky130_fd_sc_ms__a222oi_1.spice index 87bbc87..59f9f96 100644 --- a/cells/a222oi/sky130_fd_sc_ms__a222oi_1.spice +++ b/cells/a222oi/sky130_fd_sc_ms__a222oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a222oi_1.spice -* Created: Fri Aug 28 17:02:12 2020 +* Created: Wed Sep 2 11:52:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a222oi/sky130_fd_sc_ms__a222oi_2.lvs.report b/cells/a222oi/sky130_fd_sc_ms__a222oi_2.lvs.report new file mode 100644 index 0000000..f938657 --- /dev/null +++ b/cells/a222oi/sky130_fd_sc_ms__a222oi_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a222oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a222oi_2.sp ('sky130_fd_sc_ms__a222oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a222oi/sky130_fd_sc_ms__a222oi_2.spice ('sky130_fd_sc_ms__a222oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:52:54 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a222oi_2 sky130_fd_sc_ms__a222oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a222oi_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a222oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 16 16 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 11 11 + + Instances: 3 3 SMN2 (4 pins) + 1 1 SPMP_2_2_2 (8 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 11 11 0 0 + + Nets: 11 11 0 0 + + Instances: 3 3 0 0 SMN2 + 1 1 0 0 SPMP_2_2_2 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 12. + 12 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 12. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C2 C1 B1 B2 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a222oi/sky130_fd_sc_ms__a222oi_2.pex.spice b/cells/a222oi/sky130_fd_sc_ms__a222oi_2.pex.spice index 997ea65..48856c8 100644 --- a/cells/a222oi/sky130_fd_sc_ms__a222oi_2.pex.spice +++ b/cells/a222oi/sky130_fd_sc_ms__a222oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a222oi_2.pex.spice -* Created: Fri Aug 28 17:02:20 2020 +* Created: Wed Sep 2 11:52:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a222oi/sky130_fd_sc_ms__a222oi_2.pxi.spice b/cells/a222oi/sky130_fd_sc_ms__a222oi_2.pxi.spice index 0196c13..1dead2d 100644 --- a/cells/a222oi/sky130_fd_sc_ms__a222oi_2.pxi.spice +++ b/cells/a222oi/sky130_fd_sc_ms__a222oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a222oi_2.pxi.spice -* Created: Fri Aug 28 17:02:20 2020 +* Created: Wed Sep 2 11:52:57 2020 * x_PM_SKY130_FD_SC_MS__A222OI_2%C2 N_C2_M1002_g N_C2_M1008_g N_C2_M1018_g + N_C2_M1010_g N_C2_c_128_n N_C2_c_129_n N_C2_c_130_n N_C2_c_131_n N_C2_c_139_n
diff --git a/cells/a222oi/sky130_fd_sc_ms__a222oi_2.spice b/cells/a222oi/sky130_fd_sc_ms__a222oi_2.spice index d54c0b1..1d497bc 100644 --- a/cells/a222oi/sky130_fd_sc_ms__a222oi_2.spice +++ b/cells/a222oi/sky130_fd_sc_ms__a222oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a222oi_2.spice -* Created: Fri Aug 28 17:02:20 2020 +* Created: Wed Sep 2 11:52:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22o/sky130_fd_sc_ms__a22o_1.lvs.report b/cells/a22o/sky130_fd_sc_ms__a22o_1.lvs.report new file mode 100644 index 0000000..2ff488b --- /dev/null +++ b/cells/a22o/sky130_fd_sc_ms__a22o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a22o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a22o_1.sp ('sky130_fd_sc_ms__a22o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a22o/sky130_fd_sc_ms__a22o_1.spice ('sky130_fd_sc_ms__a22o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:53:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a22o_1 sky130_fd_sc_ms__a22o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a22o_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a22o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 B2 B1 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_ms__a22o_1.pex.spice b/cells/a22o/sky130_fd_sc_ms__a22o_1.pex.spice index c35981c..bd609a7 100644 --- a/cells/a22o/sky130_fd_sc_ms__a22o_1.pex.spice +++ b/cells/a22o/sky130_fd_sc_ms__a22o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22o_1.pex.spice -* Created: Fri Aug 28 17:02:29 2020 +* Created: Wed Sep 2 11:53:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_ms__a22o_1.pxi.spice b/cells/a22o/sky130_fd_sc_ms__a22o_1.pxi.spice index 7775b2a..f529323 100644 --- a/cells/a22o/sky130_fd_sc_ms__a22o_1.pxi.spice +++ b/cells/a22o/sky130_fd_sc_ms__a22o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22o_1.pxi.spice -* Created: Fri Aug 28 17:02:29 2020 +* Created: Wed Sep 2 11:53:03 2020 * x_PM_SKY130_FD_SC_MS__A22O_1%A2 N_A2_c_60_n N_A2_M1005_g N_A2_M1001_g A2 + N_A2_c_64_n PM_SKY130_FD_SC_MS__A22O_1%A2
diff --git a/cells/a22o/sky130_fd_sc_ms__a22o_1.spice b/cells/a22o/sky130_fd_sc_ms__a22o_1.spice index 0b77083..cbd5611 100644 --- a/cells/a22o/sky130_fd_sc_ms__a22o_1.spice +++ b/cells/a22o/sky130_fd_sc_ms__a22o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22o_1.spice -* Created: Fri Aug 28 17:02:29 2020 +* Created: Wed Sep 2 11:53:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22o/sky130_fd_sc_ms__a22o_2.lvs.report b/cells/a22o/sky130_fd_sc_ms__a22o_2.lvs.report new file mode 100644 index 0000000..0aafa63 --- /dev/null +++ b/cells/a22o/sky130_fd_sc_ms__a22o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a22o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a22o_2.sp ('sky130_fd_sc_ms__a22o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a22o/sky130_fd_sc_ms__a22o_2.spice ('sky130_fd_sc_ms__a22o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:53:08 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a22o_2 sky130_fd_sc_ms__a22o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a22o_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a22o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 B1 B2 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_ms__a22o_2.pex.spice b/cells/a22o/sky130_fd_sc_ms__a22o_2.pex.spice index 6a4233f..f861c66 100644 --- a/cells/a22o/sky130_fd_sc_ms__a22o_2.pex.spice +++ b/cells/a22o/sky130_fd_sc_ms__a22o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22o_2.pex.spice -* Created: Fri Aug 28 17:02:59 2020 +* Created: Wed Sep 2 11:53:12 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_ms__a22o_2.pxi.spice b/cells/a22o/sky130_fd_sc_ms__a22o_2.pxi.spice index 016b507..fdb1d74 100644 --- a/cells/a22o/sky130_fd_sc_ms__a22o_2.pxi.spice +++ b/cells/a22o/sky130_fd_sc_ms__a22o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22o_2.pxi.spice -* Created: Fri Aug 28 17:02:59 2020 +* Created: Wed Sep 2 11:53:12 2020 * x_PM_SKY130_FD_SC_MS__A22O_2%A_81_48# N_A_81_48#_M1008_d N_A_81_48#_M1003_d + N_A_81_48#_c_70_n N_A_81_48#_M1002_g N_A_81_48#_M1005_g N_A_81_48#_c_72_n
diff --git a/cells/a22o/sky130_fd_sc_ms__a22o_2.spice b/cells/a22o/sky130_fd_sc_ms__a22o_2.spice index b77f165..efd153f 100644 --- a/cells/a22o/sky130_fd_sc_ms__a22o_2.spice +++ b/cells/a22o/sky130_fd_sc_ms__a22o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22o_2.spice -* Created: Fri Aug 28 17:02:59 2020 +* Created: Wed Sep 2 11:53:12 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22o/sky130_fd_sc_ms__a22o_4.lvs.report b/cells/a22o/sky130_fd_sc_ms__a22o_4.lvs.report new file mode 100644 index 0000000..b12b7f7 --- /dev/null +++ b/cells/a22o/sky130_fd_sc_ms__a22o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a22o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a22o_4.sp ('sky130_fd_sc_ms__a22o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a22o/sky130_fd_sc_ms__a22o_4.spice ('sky130_fd_sc_ms__a22o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:53:16 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a22o_4 sky130_fd_sc_ms__a22o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a22o_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a22o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_ms__a22o_4.pex.spice b/cells/a22o/sky130_fd_sc_ms__a22o_4.pex.spice index d78b232..0b3ce24 100644 --- a/cells/a22o/sky130_fd_sc_ms__a22o_4.pex.spice +++ b/cells/a22o/sky130_fd_sc_ms__a22o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22o_4.pex.spice -* Created: Fri Aug 28 17:03:08 2020 +* Created: Wed Sep 2 11:53:19 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_ms__a22o_4.pxi.spice b/cells/a22o/sky130_fd_sc_ms__a22o_4.pxi.spice index 58c24ea..2ca1f1c 100644 --- a/cells/a22o/sky130_fd_sc_ms__a22o_4.pxi.spice +++ b/cells/a22o/sky130_fd_sc_ms__a22o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22o_4.pxi.spice -* Created: Fri Aug 28 17:03:08 2020 +* Created: Wed Sep 2 11:53:19 2020 * x_PM_SKY130_FD_SC_MS__A22O_4%A_95_306# N_A_95_306#_M1001_d N_A_95_306#_M1003_d + N_A_95_306#_M1008_d N_A_95_306#_M1014_s N_A_95_306#_M1009_g
diff --git a/cells/a22o/sky130_fd_sc_ms__a22o_4.spice b/cells/a22o/sky130_fd_sc_ms__a22o_4.spice index ec28ffb..217dfd4 100644 --- a/cells/a22o/sky130_fd_sc_ms__a22o_4.spice +++ b/cells/a22o/sky130_fd_sc_ms__a22o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22o_4.spice -* Created: Fri Aug 28 17:03:08 2020 +* Created: Wed Sep 2 11:53:19 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22oi/sky130_fd_sc_ms__a22oi_1.lvs.report b/cells/a22oi/sky130_fd_sc_ms__a22oi_1.lvs.report new file mode 100644 index 0000000..580131d --- /dev/null +++ b/cells/a22oi/sky130_fd_sc_ms__a22oi_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a22oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a22oi_1.sp ('sky130_fd_sc_ms__a22oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a22oi/sky130_fd_sc_ms__a22oi_1.spice ('sky130_fd_sc_ms__a22oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:53:23 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a22oi_1 sky130_fd_sc_ms__a22oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a22oi_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a22oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_ms__a22oi_1.pex.spice b/cells/a22oi/sky130_fd_sc_ms__a22oi_1.pex.spice index 4468508..022f2a9 100644 --- a/cells/a22oi/sky130_fd_sc_ms__a22oi_1.pex.spice +++ b/cells/a22oi/sky130_fd_sc_ms__a22oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22oi_1.pex.spice -* Created: Fri Aug 28 17:03:18 2020 +* Created: Wed Sep 2 11:53:26 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_ms__a22oi_1.pxi.spice b/cells/a22oi/sky130_fd_sc_ms__a22oi_1.pxi.spice index c73d78c..18d62e6 100644 --- a/cells/a22oi/sky130_fd_sc_ms__a22oi_1.pxi.spice +++ b/cells/a22oi/sky130_fd_sc_ms__a22oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22oi_1.pxi.spice -* Created: Fri Aug 28 17:03:18 2020 +* Created: Wed Sep 2 11:53:26 2020 * x_PM_SKY130_FD_SC_MS__A22OI_1%B2 N_B2_M1004_g N_B2_c_51_n N_B2_M1001_g + N_B2_c_52_n N_B2_c_53_n B2 B2 PM_SKY130_FD_SC_MS__A22OI_1%B2
diff --git a/cells/a22oi/sky130_fd_sc_ms__a22oi_1.spice b/cells/a22oi/sky130_fd_sc_ms__a22oi_1.spice index db7d952..0ccb537 100644 --- a/cells/a22oi/sky130_fd_sc_ms__a22oi_1.spice +++ b/cells/a22oi/sky130_fd_sc_ms__a22oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22oi_1.spice -* Created: Fri Aug 28 17:03:18 2020 +* Created: Wed Sep 2 11:53:26 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22oi/sky130_fd_sc_ms__a22oi_2.lvs.report b/cells/a22oi/sky130_fd_sc_ms__a22oi_2.lvs.report new file mode 100644 index 0000000..19df353 --- /dev/null +++ b/cells/a22oi/sky130_fd_sc_ms__a22oi_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a22oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a22oi_2.sp ('sky130_fd_sc_ms__a22oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a22oi/sky130_fd_sc_ms__a22oi_2.spice ('sky130_fd_sc_ms__a22oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:53:30 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a22oi_2 sky130_fd_sc_ms__a22oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a22oi_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a22oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1 B2 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_ms__a22oi_2.pex.spice b/cells/a22oi/sky130_fd_sc_ms__a22oi_2.pex.spice index 1f0b70c..296e431 100644 --- a/cells/a22oi/sky130_fd_sc_ms__a22oi_2.pex.spice +++ b/cells/a22oi/sky130_fd_sc_ms__a22oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22oi_2.pex.spice -* Created: Fri Aug 28 17:03:26 2020 +* Created: Wed Sep 2 11:53:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_ms__a22oi_2.pxi.spice b/cells/a22oi/sky130_fd_sc_ms__a22oi_2.pxi.spice index 8d3a0a9..d6e35f6 100644 --- a/cells/a22oi/sky130_fd_sc_ms__a22oi_2.pxi.spice +++ b/cells/a22oi/sky130_fd_sc_ms__a22oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22oi_2.pxi.spice -* Created: Fri Aug 28 17:03:26 2020 +* Created: Wed Sep 2 11:53:32 2020 * x_PM_SKY130_FD_SC_MS__A22OI_2%A1 N_A1_M1002_g N_A1_M1000_g N_A1_M1013_g + N_A1_M1008_g N_A1_c_85_n N_A1_c_92_n N_A1_c_101_p N_A1_c_125_p N_A1_c_93_n A1
diff --git a/cells/a22oi/sky130_fd_sc_ms__a22oi_2.spice b/cells/a22oi/sky130_fd_sc_ms__a22oi_2.spice index 68bf79d..95a9028 100644 --- a/cells/a22oi/sky130_fd_sc_ms__a22oi_2.spice +++ b/cells/a22oi/sky130_fd_sc_ms__a22oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22oi_2.spice -* Created: Fri Aug 28 17:03:26 2020 +* Created: Wed Sep 2 11:53:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a22oi/sky130_fd_sc_ms__a22oi_4.lvs.report b/cells/a22oi/sky130_fd_sc_ms__a22oi_4.lvs.report new file mode 100644 index 0000000..68eb879 --- /dev/null +++ b/cells/a22oi/sky130_fd_sc_ms__a22oi_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a22oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a22oi_4.sp ('sky130_fd_sc_ms__a22oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a22oi/sky130_fd_sc_ms__a22oi_4.spice ('sky130_fd_sc_ms__a22oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:53:36 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a22oi_4 sky130_fd_sc_ms__a22oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a22oi_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a22oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 SMN2 (4 pins) + 1 1 SPMP_2_2 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 SMN2 + 1 1 0 0 SPMP_2_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 32 layout mos transistors were reduced to 8. + 24 mos transistors were deleted by parallel reduction. + 32 source mos transistors were reduced to 8. + 24 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_ms__a22oi_4.pex.spice b/cells/a22oi/sky130_fd_sc_ms__a22oi_4.pex.spice index 7ddbedd..0b33084 100644 --- a/cells/a22oi/sky130_fd_sc_ms__a22oi_4.pex.spice +++ b/cells/a22oi/sky130_fd_sc_ms__a22oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22oi_4.pex.spice -* Created: Fri Aug 28 17:03:35 2020 +* Created: Wed Sep 2 11:53:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_ms__a22oi_4.pxi.spice b/cells/a22oi/sky130_fd_sc_ms__a22oi_4.pxi.spice index ac8d3b6..fbbf36f 100644 --- a/cells/a22oi/sky130_fd_sc_ms__a22oi_4.pxi.spice +++ b/cells/a22oi/sky130_fd_sc_ms__a22oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22oi_4.pxi.spice -* Created: Fri Aug 28 17:03:35 2020 +* Created: Wed Sep 2 11:53:39 2020 * x_PM_SKY130_FD_SC_MS__A22OI_4%B2 N_B2_c_125_n N_B2_M1003_g N_B2_M1005_g + N_B2_M1010_g N_B2_M1004_g N_B2_M1014_g N_B2_M1006_g N_B2_M1028_g N_B2_M1007_g
diff --git a/cells/a22oi/sky130_fd_sc_ms__a22oi_4.spice b/cells/a22oi/sky130_fd_sc_ms__a22oi_4.spice index d92ceda..a108c57 100644 --- a/cells/a22oi/sky130_fd_sc_ms__a22oi_4.spice +++ b/cells/a22oi/sky130_fd_sc_ms__a22oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a22oi_4.spice -* Created: Fri Aug 28 17:03:35 2020 +* Created: Wed Sep 2 11:53:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.lvs.report b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.lvs.report new file mode 100644 index 0000000..e7322c5 --- /dev/null +++ b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a2bb2o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a2bb2o_1.sp ('sky130_fd_sc_ms__a2bb2o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.spice ('sky130_fd_sc_ms__a2bb2o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:53:43 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a2bb2o_1 sky130_fd_sc_ms__a2bb2o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a2bb2o_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a2bb2o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1_N A2_N B2 B1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.pex.spice b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.pex.spice index c8541cd..d1101e5 100644 --- a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.pex.spice +++ b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2o_1.pex.spice -* Created: Fri Aug 28 17:04:06 2020 +* Created: Wed Sep 2 11:53:46 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.pxi.spice b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.pxi.spice index 9c2c8f9..1160386 100644 --- a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.pxi.spice +++ b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2o_1.pxi.spice -* Created: Fri Aug 28 17:04:06 2020 +* Created: Wed Sep 2 11:53:46 2020 * x_PM_SKY130_FD_SC_MS__A2BB2O_1%A_93_264# N_A_93_264#_M1002_d N_A_93_264#_M1009_s + N_A_93_264#_M1000_g N_A_93_264#_M1006_g N_A_93_264#_c_85_n N_A_93_264#_c_92_n
diff --git a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.spice b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.spice index 5ec6e16..1392b55 100644 --- a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.spice +++ b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2o_1.spice -* Created: Fri Aug 28 17:04:06 2020 +* Created: Wed Sep 2 11:53:46 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.lvs.report b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.lvs.report new file mode 100644 index 0000000..d4c60d9 --- /dev/null +++ b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a2bb2o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a2bb2o_2.sp ('sky130_fd_sc_ms__a2bb2o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.spice ('sky130_fd_sc_ms__a2bb2o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:53:49 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a2bb2o_2 sky130_fd_sc_ms__a2bb2o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a2bb2o_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a2bb2o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 B2 A2_N A1_N VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.pex.spice b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.pex.spice index f8f3134..3b9ce41 100644 --- a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.pex.spice +++ b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2o_2.pex.spice -* Created: Fri Aug 28 17:04:15 2020 +* Created: Wed Sep 2 11:53:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.pxi.spice b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.pxi.spice index 9debe44..e9bf590 100644 --- a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.pxi.spice +++ b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2o_2.pxi.spice -* Created: Fri Aug 28 17:04:15 2020 +* Created: Wed Sep 2 11:53:52 2020 * x_PM_SKY130_FD_SC_MS__A2BB2O_2%B1 N_B1_M1005_g N_B1_c_88_n N_B1_M1007_g + N_B1_c_89_n N_B1_c_90_n B1 PM_SKY130_FD_SC_MS__A2BB2O_2%B1
diff --git a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.spice b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.spice index c30b088..286aa05 100644 --- a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.spice +++ b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2o_2.spice -* Created: Fri Aug 28 17:04:15 2020 +* Created: Wed Sep 2 11:53:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.lvs.report b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.lvs.report new file mode 100644 index 0000000..cbbc93f --- /dev/null +++ b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a2bb2o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a2bb2o_4.sp ('sky130_fd_sc_ms__a2bb2o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.spice ('sky130_fd_sc_ms__a2bb2o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:53:55 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a2bb2o_4 sky130_fd_sc_ms__a2bb2o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a2bb2o_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a2bb2o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 11 11 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 24 23 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 18 layout mos transistors were reduced to 7. + 11 mos transistors were deleted by parallel reduction. + 18 source mos transistors were reduced to 7. + 11 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1_N A2_N B2 B1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.pex.spice b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.pex.spice index 22f8d69..8a3d8d5 100644 --- a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.pex.spice +++ b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2o_4.pex.spice -* Created: Fri Aug 28 17:04:24 2020 +* Created: Wed Sep 2 11:53:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.pxi.spice b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.pxi.spice index cf4c533..61522ce 100644 --- a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.pxi.spice +++ b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2o_4.pxi.spice -* Created: Fri Aug 28 17:04:24 2020 +* Created: Wed Sep 2 11:53:58 2020 * x_PM_SKY130_FD_SC_MS__A2BB2O_4%A_162_48# N_A_162_48#_M1017_d N_A_162_48#_M1001_s + N_A_162_48#_M1003_d N_A_162_48#_M1000_g N_A_162_48#_M1012_g
diff --git a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.spice b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.spice index a536a01..70ebbff 100644 --- a/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.spice +++ b/cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2o_4.spice -* Created: Fri Aug 28 17:04:24 2020 +* Created: Wed Sep 2 11:53:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.lvs.report b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.lvs.report new file mode 100644 index 0000000..9f4ca90 --- /dev/null +++ b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a2bb2oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a2bb2oi_1.sp ('sky130_fd_sc_ms__a2bb2oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.spice ('sky130_fd_sc_ms__a2bb2oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:54:02 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a2bb2oi_1 sky130_fd_sc_ms__a2bb2oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a2bb2oi_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a2bb2oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.pex.spice b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.pex.spice index b1af907..43d6448 100644 --- a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.pex.spice +++ b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2oi_1.pex.spice -* Created: Fri Aug 28 17:04:33 2020 +* Created: Wed Sep 2 11:54:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.pxi.spice index ecac18c..33caa5d 100644 --- a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.pxi.spice +++ b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2oi_1.pxi.spice -* Created: Fri Aug 28 17:04:33 2020 +* Created: Wed Sep 2 11:54:04 2020 * x_PM_SKY130_FD_SC_MS__A2BB2OI_1%A1_N N_A1_N_M1008_g N_A1_N_M1000_g A1_N + N_A1_N_c_66_n N_A1_N_c_67_n PM_SKY130_FD_SC_MS__A2BB2OI_1%A1_N
diff --git a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.spice b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.spice index 0fd506c..58d9720 100644 --- a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.spice +++ b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2oi_1.spice -* Created: Fri Aug 28 17:04:33 2020 +* Created: Wed Sep 2 11:54:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.lvs.report b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.lvs.report new file mode 100644 index 0000000..37dc185 --- /dev/null +++ b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a2bb2oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a2bb2oi_2.sp ('sky130_fd_sc_ms__a2bb2oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.spice ('sky130_fd_sc_ms__a2bb2oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:54:08 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a2bb2oi_2 sky130_fd_sc_ms__a2bb2oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a2bb2oi_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a2bb2oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.pex.spice b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.pex.spice index f7aeb83..2eba1b9 100644 --- a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.pex.spice +++ b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2oi_2.pex.spice -* Created: Fri Aug 28 17:04:42 2020 +* Created: Wed Sep 2 11:54:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.pxi.spice index ea9075b..bc6513c 100644 --- a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.pxi.spice +++ b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2oi_2.pxi.spice -* Created: Fri Aug 28 17:04:42 2020 +* Created: Wed Sep 2 11:54:11 2020 * x_PM_SKY130_FD_SC_MS__A2BB2OI_2%A1_N N_A1_N_c_94_n N_A1_N_c_95_n N_A1_N_M1001_g + N_A1_N_M1011_g A1_N N_A1_N_c_98_n N_A1_N_c_99_n
diff --git a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.spice b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.spice index b8693a5..4c93c7a 100644 --- a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.spice +++ b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2oi_2.spice -* Created: Fri Aug 28 17:04:42 2020 +* Created: Wed Sep 2 11:54:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.lvs.report b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.lvs.report new file mode 100644 index 0000000..2c34e24 --- /dev/null +++ b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a2bb2oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a2bb2oi_4.sp ('sky130_fd_sc_ms__a2bb2oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.spice ('sky130_fd_sc_ms__a2bb2oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:54:14 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a2bb2oi_4 sky130_fd_sc_ms__a2bb2oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a2bb2oi_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a2bb2oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 14 14 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 31 30 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 8. + 20 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 8. + 20 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2_N A1_N B2 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.pex.spice b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.pex.spice index 25b9f7b..816fcf2 100644 --- a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.pex.spice +++ b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2oi_4.pex.spice -* Created: Fri Aug 28 17:05:14 2020 +* Created: Wed Sep 2 11:54:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.pxi.spice index c76f0fb..e324126 100644 --- a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.pxi.spice +++ b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2oi_4.pxi.spice -* Created: Fri Aug 28 17:05:14 2020 +* Created: Wed Sep 2 11:54:17 2020 * x_PM_SKY130_FD_SC_MS__A2BB2OI_4%A2_N N_A2_N_M1017_g N_A2_N_M1018_g + N_A2_N_c_142_n N_A2_N_c_143_n N_A2_N_c_144_n N_A2_N_M1027_g A2_N A2_N A2_N
diff --git a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.spice b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.spice index f3af661..166b867 100644 --- a/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.spice +++ b/cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a2bb2oi_4.spice -* Created: Fri Aug 28 17:05:14 2020 +* Created: Wed Sep 2 11:54:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311o/sky130_fd_sc_ms__a311o_1.lvs.report b/cells/a311o/sky130_fd_sc_ms__a311o_1.lvs.report new file mode 100644 index 0000000..8a79948 --- /dev/null +++ b/cells/a311o/sky130_fd_sc_ms__a311o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a311o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a311o_1.sp ('sky130_fd_sc_ms__a311o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a311o/sky130_fd_sc_ms__a311o_1.spice ('sky130_fd_sc_ms__a311o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:54:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a311o_1 sky130_fd_sc_ms__a311o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a311o_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a311o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_ms__a311o_1.pex.spice b/cells/a311o/sky130_fd_sc_ms__a311o_1.pex.spice index dfb5086..b74a4db 100644 --- a/cells/a311o/sky130_fd_sc_ms__a311o_1.pex.spice +++ b/cells/a311o/sky130_fd_sc_ms__a311o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311o_1.pex.spice -* Created: Fri Aug 28 17:05:23 2020 +* Created: Wed Sep 2 11:54:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_ms__a311o_1.pxi.spice b/cells/a311o/sky130_fd_sc_ms__a311o_1.pxi.spice index 6bcba8d..23b9f2a 100644 --- a/cells/a311o/sky130_fd_sc_ms__a311o_1.pxi.spice +++ b/cells/a311o/sky130_fd_sc_ms__a311o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311o_1.pxi.spice -* Created: Fri Aug 28 17:05:23 2020 +* Created: Wed Sep 2 11:54:23 2020 * x_PM_SKY130_FD_SC_MS__A311O_1%A_89_270# N_A_89_270#_M1007_d N_A_89_270#_M1003_d + N_A_89_270#_M1005_d N_A_89_270#_M1010_g N_A_89_270#_c_75_n N_A_89_270#_M1006_g
diff --git a/cells/a311o/sky130_fd_sc_ms__a311o_1.spice b/cells/a311o/sky130_fd_sc_ms__a311o_1.spice index b0f35c4..d8a0b96 100644 --- a/cells/a311o/sky130_fd_sc_ms__a311o_1.spice +++ b/cells/a311o/sky130_fd_sc_ms__a311o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311o_1.spice -* Created: Fri Aug 28 17:05:23 2020 +* Created: Wed Sep 2 11:54:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311o/sky130_fd_sc_ms__a311o_2.lvs.report b/cells/a311o/sky130_fd_sc_ms__a311o_2.lvs.report new file mode 100644 index 0000000..d5577c8 --- /dev/null +++ b/cells/a311o/sky130_fd_sc_ms__a311o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a311o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a311o_2.sp ('sky130_fd_sc_ms__a311o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a311o/sky130_fd_sc_ms__a311o_2.spice ('sky130_fd_sc_ms__a311o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:54:27 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a311o_2 sky130_fd_sc_ms__a311o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a311o_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a311o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_ms__a311o_2.pex.spice b/cells/a311o/sky130_fd_sc_ms__a311o_2.pex.spice index 895eeee..0ecda05 100644 --- a/cells/a311o/sky130_fd_sc_ms__a311o_2.pex.spice +++ b/cells/a311o/sky130_fd_sc_ms__a311o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311o_2.pex.spice -* Created: Fri Aug 28 17:05:32 2020 +* Created: Wed Sep 2 11:54:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_ms__a311o_2.pxi.spice b/cells/a311o/sky130_fd_sc_ms__a311o_2.pxi.spice index 43493d9..f0a3f46 100644 --- a/cells/a311o/sky130_fd_sc_ms__a311o_2.pxi.spice +++ b/cells/a311o/sky130_fd_sc_ms__a311o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311o_2.pxi.spice -* Created: Fri Aug 28 17:05:32 2020 +* Created: Wed Sep 2 11:54:29 2020 * x_PM_SKY130_FD_SC_MS__A311O_2%A_21_270# N_A_21_270#_M1011_d N_A_21_270#_M1006_d + N_A_21_270#_M1013_d N_A_21_270#_M1000_g N_A_21_270#_M1002_g N_A_21_270#_c_81_n
diff --git a/cells/a311o/sky130_fd_sc_ms__a311o_2.spice b/cells/a311o/sky130_fd_sc_ms__a311o_2.spice index bcc6c8c..3c9fd26 100644 --- a/cells/a311o/sky130_fd_sc_ms__a311o_2.spice +++ b/cells/a311o/sky130_fd_sc_ms__a311o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311o_2.spice -* Created: Fri Aug 28 17:05:32 2020 +* Created: Wed Sep 2 11:54:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311o/sky130_fd_sc_ms__a311o_4.lvs.report b/cells/a311o/sky130_fd_sc_ms__a311o_4.lvs.report new file mode 100644 index 0000000..8f255ae --- /dev/null +++ b/cells/a311o/sky130_fd_sc_ms__a311o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a311o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a311o_4.sp ('sky130_fd_sc_ms__a311o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a311o/sky130_fd_sc_ms__a311o_4.spice ('sky130_fd_sc_ms__a311o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:54:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a311o_4 sky130_fd_sc_ms__a311o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a311o_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a311o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 A3 A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_ms__a311o_4.pex.spice b/cells/a311o/sky130_fd_sc_ms__a311o_4.pex.spice index ef828bb..0cd9333 100644 --- a/cells/a311o/sky130_fd_sc_ms__a311o_4.pex.spice +++ b/cells/a311o/sky130_fd_sc_ms__a311o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311o_4.pex.spice -* Created: Fri Aug 28 17:05:41 2020 +* Created: Wed Sep 2 11:54:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_ms__a311o_4.pxi.spice b/cells/a311o/sky130_fd_sc_ms__a311o_4.pxi.spice index 28071b7..00aa624 100644 --- a/cells/a311o/sky130_fd_sc_ms__a311o_4.pxi.spice +++ b/cells/a311o/sky130_fd_sc_ms__a311o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311o_4.pxi.spice -* Created: Fri Aug 28 17:05:41 2020 +* Created: Wed Sep 2 11:54:36 2020 * x_PM_SKY130_FD_SC_MS__A311O_4%C1 N_C1_M1000_g N_C1_M1017_g N_C1_M1001_g + N_C1_M1027_g C1 N_C1_c_141_n PM_SKY130_FD_SC_MS__A311O_4%C1
diff --git a/cells/a311o/sky130_fd_sc_ms__a311o_4.spice b/cells/a311o/sky130_fd_sc_ms__a311o_4.spice index bf280c1..d15cf91 100644 --- a/cells/a311o/sky130_fd_sc_ms__a311o_4.spice +++ b/cells/a311o/sky130_fd_sc_ms__a311o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311o_4.spice -* Created: Fri Aug 28 17:05:41 2020 +* Created: Wed Sep 2 11:54:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311oi/sky130_fd_sc_ms__a311oi_1.lvs.report b/cells/a311oi/sky130_fd_sc_ms__a311oi_1.lvs.report new file mode 100644 index 0000000..4a9ac8e --- /dev/null +++ b/cells/a311oi/sky130_fd_sc_ms__a311oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a311oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a311oi_1.sp ('sky130_fd_sc_ms__a311oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a311oi/sky130_fd_sc_ms__a311oi_1.spice ('sky130_fd_sc_ms__a311oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:54:39 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a311oi_1 sky130_fd_sc_ms__a311oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a311oi_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a311oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_ms__a311oi_1.pex.spice b/cells/a311oi/sky130_fd_sc_ms__a311oi_1.pex.spice index f17ef90..063bc38 100644 --- a/cells/a311oi/sky130_fd_sc_ms__a311oi_1.pex.spice +++ b/cells/a311oi/sky130_fd_sc_ms__a311oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311oi_1.pex.spice -* Created: Fri Aug 28 17:05:49 2020 +* Created: Wed Sep 2 11:54:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_ms__a311oi_1.pxi.spice b/cells/a311oi/sky130_fd_sc_ms__a311oi_1.pxi.spice index dc9b8e4..eae6316 100644 --- a/cells/a311oi/sky130_fd_sc_ms__a311oi_1.pxi.spice +++ b/cells/a311oi/sky130_fd_sc_ms__a311oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311oi_1.pxi.spice -* Created: Fri Aug 28 17:05:49 2020 +* Created: Wed Sep 2 11:54:42 2020 * x_PM_SKY130_FD_SC_MS__A311OI_1%A3 N_A3_M1007_g N_A3_c_62_n N_A3_M1005_g + N_A3_c_63_n N_A3_c_64_n A3 A3 PM_SKY130_FD_SC_MS__A311OI_1%A3
diff --git a/cells/a311oi/sky130_fd_sc_ms__a311oi_1.spice b/cells/a311oi/sky130_fd_sc_ms__a311oi_1.spice index 6ad62b6..326f23a 100644 --- a/cells/a311oi/sky130_fd_sc_ms__a311oi_1.spice +++ b/cells/a311oi/sky130_fd_sc_ms__a311oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311oi_1.spice -* Created: Fri Aug 28 17:05:49 2020 +* Created: Wed Sep 2 11:54:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311oi/sky130_fd_sc_ms__a311oi_2.lvs.report b/cells/a311oi/sky130_fd_sc_ms__a311oi_2.lvs.report new file mode 100644 index 0000000..1f811c4 --- /dev/null +++ b/cells/a311oi/sky130_fd_sc_ms__a311oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a311oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a311oi_2.sp ('sky130_fd_sc_ms__a311oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a311oi/sky130_fd_sc_ms__a311oi_2.spice ('sky130_fd_sc_ms__a311oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:54:46 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a311oi_2 sky130_fd_sc_ms__a311oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a311oi_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a311oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 8 8 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 19 18 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_ms__a311oi_2.pex.spice b/cells/a311oi/sky130_fd_sc_ms__a311oi_2.pex.spice index 23984df..d4efd7b 100644 --- a/cells/a311oi/sky130_fd_sc_ms__a311oi_2.pex.spice +++ b/cells/a311oi/sky130_fd_sc_ms__a311oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311oi_2.pex.spice -* Created: Fri Aug 28 17:06:19 2020 +* Created: Wed Sep 2 11:54:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_ms__a311oi_2.pxi.spice b/cells/a311oi/sky130_fd_sc_ms__a311oi_2.pxi.spice index a1e3f44..fb7c60f 100644 --- a/cells/a311oi/sky130_fd_sc_ms__a311oi_2.pxi.spice +++ b/cells/a311oi/sky130_fd_sc_ms__a311oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311oi_2.pxi.spice -* Created: Fri Aug 28 17:06:19 2020 +* Created: Wed Sep 2 11:54:49 2020 * x_PM_SKY130_FD_SC_MS__A311OI_2%A3 N_A3_M1016_g N_A3_c_92_n N_A3_M1009_g + N_A3_c_93_n N_A3_M1010_g N_A3_M1017_g A3 N_A3_c_96_n
diff --git a/cells/a311oi/sky130_fd_sc_ms__a311oi_2.spice b/cells/a311oi/sky130_fd_sc_ms__a311oi_2.spice index 5a706c5..acc183b 100644 --- a/cells/a311oi/sky130_fd_sc_ms__a311oi_2.spice +++ b/cells/a311oi/sky130_fd_sc_ms__a311oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311oi_2.spice -* Created: Fri Aug 28 17:06:19 2020 +* Created: Wed Sep 2 11:54:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a311oi/sky130_fd_sc_ms__a311oi_4.lvs.report b/cells/a311oi/sky130_fd_sc_ms__a311oi_4.lvs.report new file mode 100644 index 0000000..bfb3da5 --- /dev/null +++ b/cells/a311oi/sky130_fd_sc_ms__a311oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a311oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a311oi_4.sp ('sky130_fd_sc_ms__a311oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a311oi/sky130_fd_sc_ms__a311oi_4.spice ('sky130_fd_sc_ms__a311oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:54:52 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a311oi_4 sky130_fd_sc_ms__a311oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a311oi_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a311oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 16 16 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 37 36 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 36 layout mos transistors were reduced to 10. + 26 mos transistors were deleted by parallel reduction. + 36 source mos transistors were reduced to 10. + 26 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_ms__a311oi_4.pex.spice b/cells/a311oi/sky130_fd_sc_ms__a311oi_4.pex.spice index cd44b6f..d9c0b32 100644 --- a/cells/a311oi/sky130_fd_sc_ms__a311oi_4.pex.spice +++ b/cells/a311oi/sky130_fd_sc_ms__a311oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311oi_4.pex.spice -* Created: Fri Aug 28 17:06:28 2020 +* Created: Wed Sep 2 11:54:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_ms__a311oi_4.pxi.spice b/cells/a311oi/sky130_fd_sc_ms__a311oi_4.pxi.spice index 18e36f9..8e3c050 100644 --- a/cells/a311oi/sky130_fd_sc_ms__a311oi_4.pxi.spice +++ b/cells/a311oi/sky130_fd_sc_ms__a311oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311oi_4.pxi.spice -* Created: Fri Aug 28 17:06:28 2020 +* Created: Wed Sep 2 11:54:55 2020 * x_PM_SKY130_FD_SC_MS__A311OI_4%A3 N_A3_M1028_g N_A3_M1010_g N_A3_M1029_g + N_A3_M1023_g N_A3_M1031_g N_A3_M1026_g N_A3_M1027_g N_A3_M1034_g A3 A3 A3
diff --git a/cells/a311oi/sky130_fd_sc_ms__a311oi_4.spice b/cells/a311oi/sky130_fd_sc_ms__a311oi_4.spice index 640dc01..4d036a5 100644 --- a/cells/a311oi/sky130_fd_sc_ms__a311oi_4.spice +++ b/cells/a311oi/sky130_fd_sc_ms__a311oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a311oi_4.spice -* Created: Fri Aug 28 17:06:28 2020 +* Created: Wed Sep 2 11:54:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31o/sky130_fd_sc_ms__a31o_1.lvs.report b/cells/a31o/sky130_fd_sc_ms__a31o_1.lvs.report new file mode 100644 index 0000000..8ed75b9 --- /dev/null +++ b/cells/a31o/sky130_fd_sc_ms__a31o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a31o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a31o_1.sp ('sky130_fd_sc_ms__a31o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a31o/sky130_fd_sc_ms__a31o_1.spice ('sky130_fd_sc_ms__a31o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:54:58 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a31o_1 sky130_fd_sc_ms__a31o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a31o_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a31o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_ms__a31o_1.pex.spice b/cells/a31o/sky130_fd_sc_ms__a31o_1.pex.spice index 29f2c3e..9ee1214 100644 --- a/cells/a31o/sky130_fd_sc_ms__a31o_1.pex.spice +++ b/cells/a31o/sky130_fd_sc_ms__a31o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31o_1.pex.spice -* Created: Fri Aug 28 17:06:37 2020 +* Created: Wed Sep 2 11:55:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_ms__a31o_1.pxi.spice b/cells/a31o/sky130_fd_sc_ms__a31o_1.pxi.spice index e73be01..c4b433d 100644 --- a/cells/a31o/sky130_fd_sc_ms__a31o_1.pxi.spice +++ b/cells/a31o/sky130_fd_sc_ms__a31o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31o_1.pxi.spice -* Created: Fri Aug 28 17:06:37 2020 +* Created: Wed Sep 2 11:55:01 2020 * x_PM_SKY130_FD_SC_MS__A31O_1%A_81_270# N_A_81_270#_M1009_d N_A_81_270#_M1002_d + N_A_81_270#_M1007_g N_A_81_270#_M1006_g N_A_81_270#_c_60_n N_A_81_270#_c_97_p
diff --git a/cells/a31o/sky130_fd_sc_ms__a31o_1.spice b/cells/a31o/sky130_fd_sc_ms__a31o_1.spice index 648f860..ff45dfd 100644 --- a/cells/a31o/sky130_fd_sc_ms__a31o_1.spice +++ b/cells/a31o/sky130_fd_sc_ms__a31o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31o_1.spice -* Created: Fri Aug 28 17:06:37 2020 +* Created: Wed Sep 2 11:55:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31o/sky130_fd_sc_ms__a31o_2.lvs.report b/cells/a31o/sky130_fd_sc_ms__a31o_2.lvs.report new file mode 100644 index 0000000..3deef39 --- /dev/null +++ b/cells/a31o/sky130_fd_sc_ms__a31o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a31o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a31o_2.sp ('sky130_fd_sc_ms__a31o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a31o/sky130_fd_sc_ms__a31o_2.spice ('sky130_fd_sc_ms__a31o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:55:05 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a31o_2 sky130_fd_sc_ms__a31o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a31o_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a31o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_ms__a31o_2.pex.spice b/cells/a31o/sky130_fd_sc_ms__a31o_2.pex.spice index f445a3c..c756957 100644 --- a/cells/a31o/sky130_fd_sc_ms__a31o_2.pex.spice +++ b/cells/a31o/sky130_fd_sc_ms__a31o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31o_2.pex.spice -* Created: Fri Aug 28 17:06:45 2020 +* Created: Wed Sep 2 11:55:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_ms__a31o_2.pxi.spice b/cells/a31o/sky130_fd_sc_ms__a31o_2.pxi.spice index efb4626..83c2381 100644 --- a/cells/a31o/sky130_fd_sc_ms__a31o_2.pxi.spice +++ b/cells/a31o/sky130_fd_sc_ms__a31o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31o_2.pxi.spice -* Created: Fri Aug 28 17:06:45 2020 +* Created: Wed Sep 2 11:55:08 2020 * x_PM_SKY130_FD_SC_MS__A31O_2%A_97_296# N_A_97_296#_M1011_d N_A_97_296#_M1010_d + N_A_97_296#_M1002_g N_A_97_296#_M1007_g N_A_97_296#_M1008_g
diff --git a/cells/a31o/sky130_fd_sc_ms__a31o_2.spice b/cells/a31o/sky130_fd_sc_ms__a31o_2.spice index 617f54e..8d04987 100644 --- a/cells/a31o/sky130_fd_sc_ms__a31o_2.spice +++ b/cells/a31o/sky130_fd_sc_ms__a31o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31o_2.spice -* Created: Fri Aug 28 17:06:45 2020 +* Created: Wed Sep 2 11:55:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31o/sky130_fd_sc_ms__a31o_4.lvs.report b/cells/a31o/sky130_fd_sc_ms__a31o_4.lvs.report new file mode 100644 index 0000000..aac28ee --- /dev/null +++ b/cells/a31o/sky130_fd_sc_ms__a31o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a31o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a31o_4.sp ('sky130_fd_sc_ms__a31o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a31o/sky130_fd_sc_ms__a31o_4.spice ('sky130_fd_sc_ms__a31o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:55:12 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a31o_4 sky130_fd_sc_ms__a31o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a31o_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a31o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 A3 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_ms__a31o_4.pex.spice b/cells/a31o/sky130_fd_sc_ms__a31o_4.pex.spice index d050d54..85cca79 100644 --- a/cells/a31o/sky130_fd_sc_ms__a31o_4.pex.spice +++ b/cells/a31o/sky130_fd_sc_ms__a31o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31o_4.pex.spice -* Created: Fri Aug 28 17:06:54 2020 +* Created: Wed Sep 2 11:55:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_ms__a31o_4.pxi.spice b/cells/a31o/sky130_fd_sc_ms__a31o_4.pxi.spice index 88e7389..6546228 100644 --- a/cells/a31o/sky130_fd_sc_ms__a31o_4.pxi.spice +++ b/cells/a31o/sky130_fd_sc_ms__a31o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31o_4.pxi.spice -* Created: Fri Aug 28 17:06:54 2020 +* Created: Wed Sep 2 11:55:15 2020 * x_PM_SKY130_FD_SC_MS__A31O_4%A_83_274# N_A_83_274#_M1002_d N_A_83_274#_M1007_d + N_A_83_274#_M1015_d N_A_83_274#_M1010_d N_A_83_274#_M1001_g
diff --git a/cells/a31o/sky130_fd_sc_ms__a31o_4.spice b/cells/a31o/sky130_fd_sc_ms__a31o_4.spice index 3bc28a6..5c49db9 100644 --- a/cells/a31o/sky130_fd_sc_ms__a31o_4.spice +++ b/cells/a31o/sky130_fd_sc_ms__a31o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31o_4.spice -* Created: Fri Aug 28 17:06:54 2020 +* Created: Wed Sep 2 11:55:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31oi/sky130_fd_sc_ms__a31oi_1.lvs.report b/cells/a31oi/sky130_fd_sc_ms__a31oi_1.lvs.report new file mode 100644 index 0000000..0852b8e --- /dev/null +++ b/cells/a31oi/sky130_fd_sc_ms__a31oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a31oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a31oi_1.sp ('sky130_fd_sc_ms__a31oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a31oi/sky130_fd_sc_ms__a31oi_1.spice ('sky130_fd_sc_ms__a31oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:55:18 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a31oi_1 sky130_fd_sc_ms__a31oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a31oi_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a31oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_ms__a31oi_1.pex.spice b/cells/a31oi/sky130_fd_sc_ms__a31oi_1.pex.spice index 9668831..3bbb158 100644 --- a/cells/a31oi/sky130_fd_sc_ms__a31oi_1.pex.spice +++ b/cells/a31oi/sky130_fd_sc_ms__a31oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31oi_1.pex.spice -* Created: Fri Aug 28 17:07:23 2020 +* Created: Wed Sep 2 11:55:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_ms__a31oi_1.pxi.spice b/cells/a31oi/sky130_fd_sc_ms__a31oi_1.pxi.spice index 616a76e..99bebeb 100644 --- a/cells/a31oi/sky130_fd_sc_ms__a31oi_1.pxi.spice +++ b/cells/a31oi/sky130_fd_sc_ms__a31oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31oi_1.pxi.spice -* Created: Fri Aug 28 17:07:23 2020 +* Created: Wed Sep 2 11:55:21 2020 * x_PM_SKY130_FD_SC_MS__A31OI_1%A3 N_A3_M1007_g N_A3_c_48_n N_A3_M1006_g + N_A3_c_49_n N_A3_c_50_n A3 PM_SKY130_FD_SC_MS__A31OI_1%A3
diff --git a/cells/a31oi/sky130_fd_sc_ms__a31oi_1.spice b/cells/a31oi/sky130_fd_sc_ms__a31oi_1.spice index 36d644c..e917560 100644 --- a/cells/a31oi/sky130_fd_sc_ms__a31oi_1.spice +++ b/cells/a31oi/sky130_fd_sc_ms__a31oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31oi_1.spice -* Created: Fri Aug 28 17:07:23 2020 +* Created: Wed Sep 2 11:55:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31oi/sky130_fd_sc_ms__a31oi_2.lvs.report b/cells/a31oi/sky130_fd_sc_ms__a31oi_2.lvs.report new file mode 100644 index 0000000..bb5d330 --- /dev/null +++ b/cells/a31oi/sky130_fd_sc_ms__a31oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a31oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a31oi_2.sp ('sky130_fd_sc_ms__a31oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a31oi/sky130_fd_sc_ms__a31oi_2.spice ('sky130_fd_sc_ms__a31oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:55:25 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a31oi_2 sky130_fd_sc_ms__a31oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a31oi_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a31oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 7 7 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 16 15 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 14 layout mos transistors were reduced to 7. + 7 mos transistors were deleted by parallel reduction. + 14 source mos transistors were reduced to 7. + 7 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 B1 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_ms__a31oi_2.pex.spice b/cells/a31oi/sky130_fd_sc_ms__a31oi_2.pex.spice index 49393f9..b8ee378 100644 --- a/cells/a31oi/sky130_fd_sc_ms__a31oi_2.pex.spice +++ b/cells/a31oi/sky130_fd_sc_ms__a31oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31oi_2.pex.spice -* Created: Fri Aug 28 17:07:32 2020 +* Created: Wed Sep 2 11:55:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_ms__a31oi_2.pxi.spice b/cells/a31oi/sky130_fd_sc_ms__a31oi_2.pxi.spice index 0659640..bfd4c69 100644 --- a/cells/a31oi/sky130_fd_sc_ms__a31oi_2.pxi.spice +++ b/cells/a31oi/sky130_fd_sc_ms__a31oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31oi_2.pxi.spice -* Created: Fri Aug 28 17:07:32 2020 +* Created: Wed Sep 2 11:55:28 2020 * x_PM_SKY130_FD_SC_MS__A31OI_2%A3 N_A3_M1002_g N_A3_c_75_n N_A3_M1006_g + N_A3_M1011_g N_A3_M1004_g N_A3_c_77_n N_A3_c_78_n N_A3_c_79_n A3 N_A3_c_80_n
diff --git a/cells/a31oi/sky130_fd_sc_ms__a31oi_2.spice b/cells/a31oi/sky130_fd_sc_ms__a31oi_2.spice index 6f4a880..d9cf3ad 100644 --- a/cells/a31oi/sky130_fd_sc_ms__a31oi_2.spice +++ b/cells/a31oi/sky130_fd_sc_ms__a31oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31oi_2.spice -* Created: Fri Aug 28 17:07:32 2020 +* Created: Wed Sep 2 11:55:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a31oi/sky130_fd_sc_ms__a31oi_4.lvs.report b/cells/a31oi/sky130_fd_sc_ms__a31oi_4.lvs.report new file mode 100644 index 0000000..c5ef4b6 --- /dev/null +++ b/cells/a31oi/sky130_fd_sc_ms__a31oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a31oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a31oi_4.sp ('sky130_fd_sc_ms__a31oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a31oi/sky130_fd_sc_ms__a31oi_4.spice ('sky130_fd_sc_ms__a31oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:55:31 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a31oi_4 sky130_fd_sc_ms__a31oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a31oi_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a31oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 14 14 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 31 30 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 30 layout mos transistors were reduced to 8. + 22 mos transistors were deleted by parallel reduction. + 30 source mos transistors were reduced to 8. + 22 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_ms__a31oi_4.pex.spice b/cells/a31oi/sky130_fd_sc_ms__a31oi_4.pex.spice index 150605b..67bd07d 100644 --- a/cells/a31oi/sky130_fd_sc_ms__a31oi_4.pex.spice +++ b/cells/a31oi/sky130_fd_sc_ms__a31oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31oi_4.pex.spice -* Created: Fri Aug 28 17:07:42 2020 +* Created: Wed Sep 2 11:55:34 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_ms__a31oi_4.pxi.spice b/cells/a31oi/sky130_fd_sc_ms__a31oi_4.pxi.spice index 86f43a2..9ff1a0b 100644 --- a/cells/a31oi/sky130_fd_sc_ms__a31oi_4.pxi.spice +++ b/cells/a31oi/sky130_fd_sc_ms__a31oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31oi_4.pxi.spice -* Created: Fri Aug 28 17:07:42 2020 +* Created: Wed Sep 2 11:55:34 2020 * x_PM_SKY130_FD_SC_MS__A31OI_4%A3 N_A3_M1008_g N_A3_M1015_g N_A3_M1021_g + N_A3_M1009_g N_A3_M1028_g N_A3_M1011_g N_A3_M1013_g N_A3_M1029_g A3 A3 A3
diff --git a/cells/a31oi/sky130_fd_sc_ms__a31oi_4.spice b/cells/a31oi/sky130_fd_sc_ms__a31oi_4.spice index e5f5631..50f56a1 100644 --- a/cells/a31oi/sky130_fd_sc_ms__a31oi_4.spice +++ b/cells/a31oi/sky130_fd_sc_ms__a31oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a31oi_4.spice -* Created: Fri Aug 28 17:07:42 2020 +* Created: Wed Sep 2 11:55:34 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32o/sky130_fd_sc_ms__a32o_1.lvs.report b/cells/a32o/sky130_fd_sc_ms__a32o_1.lvs.report new file mode 100644 index 0000000..d179e8e --- /dev/null +++ b/cells/a32o/sky130_fd_sc_ms__a32o_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a32o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a32o_1.sp ('sky130_fd_sc_ms__a32o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a32o/sky130_fd_sc_ms__a32o_1.spice ('sky130_fd_sc_ms__a32o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:55:38 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a32o_1 sky130_fd_sc_ms__a32o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a32o_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a32o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 B2 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_ms__a32o_1.pex.spice b/cells/a32o/sky130_fd_sc_ms__a32o_1.pex.spice index cd7b1cc..8a54f23 100644 --- a/cells/a32o/sky130_fd_sc_ms__a32o_1.pex.spice +++ b/cells/a32o/sky130_fd_sc_ms__a32o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32o_1.pex.spice -* Created: Fri Aug 28 17:07:50 2020 +* Created: Wed Sep 2 11:55:40 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_ms__a32o_1.pxi.spice b/cells/a32o/sky130_fd_sc_ms__a32o_1.pxi.spice index 8a2ea1d..fc738ec 100644 --- a/cells/a32o/sky130_fd_sc_ms__a32o_1.pxi.spice +++ b/cells/a32o/sky130_fd_sc_ms__a32o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32o_1.pxi.spice -* Created: Fri Aug 28 17:07:50 2020 +* Created: Wed Sep 2 11:55:40 2020 * x_PM_SKY130_FD_SC_MS__A32O_1%A_84_48# N_A_84_48#_M1011_d N_A_84_48#_M1002_d + N_A_84_48#_M1010_g N_A_84_48#_M1008_g N_A_84_48#_c_62_n N_A_84_48#_c_138_p
diff --git a/cells/a32o/sky130_fd_sc_ms__a32o_1.spice b/cells/a32o/sky130_fd_sc_ms__a32o_1.spice index 92592f9..cdf4435 100644 --- a/cells/a32o/sky130_fd_sc_ms__a32o_1.spice +++ b/cells/a32o/sky130_fd_sc_ms__a32o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32o_1.spice -* Created: Fri Aug 28 17:07:50 2020 +* Created: Wed Sep 2 11:55:40 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32o/sky130_fd_sc_ms__a32o_2.lvs.report b/cells/a32o/sky130_fd_sc_ms__a32o_2.lvs.report new file mode 100644 index 0000000..1012196 --- /dev/null +++ b/cells/a32o/sky130_fd_sc_ms__a32o_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a32o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a32o_2.sp ('sky130_fd_sc_ms__a32o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a32o/sky130_fd_sc_ms__a32o_2.spice ('sky130_fd_sc_ms__a32o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:55:44 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a32o_2 sky130_fd_sc_ms__a32o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a32o_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a32o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A3 A2 A1 B1 B2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_ms__a32o_2.pex.spice b/cells/a32o/sky130_fd_sc_ms__a32o_2.pex.spice index 7a42c19..e28c596 100644 --- a/cells/a32o/sky130_fd_sc_ms__a32o_2.pex.spice +++ b/cells/a32o/sky130_fd_sc_ms__a32o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32o_2.pex.spice -* Created: Fri Aug 28 17:07:59 2020 +* Created: Wed Sep 2 11:55:47 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_ms__a32o_2.pxi.spice b/cells/a32o/sky130_fd_sc_ms__a32o_2.pxi.spice index 4280d21..10521b8 100644 --- a/cells/a32o/sky130_fd_sc_ms__a32o_2.pxi.spice +++ b/cells/a32o/sky130_fd_sc_ms__a32o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32o_2.pxi.spice -* Created: Fri Aug 28 17:07:59 2020 +* Created: Wed Sep 2 11:55:47 2020 * x_PM_SKY130_FD_SC_MS__A32O_2%A_45_264# N_A_45_264#_M1011_d N_A_45_264#_M1001_d + N_A_45_264#_M1004_g N_A_45_264#_M1003_g N_A_45_264#_M1005_g
diff --git a/cells/a32o/sky130_fd_sc_ms__a32o_2.spice b/cells/a32o/sky130_fd_sc_ms__a32o_2.spice index e9cfa90..e8549a4 100644 --- a/cells/a32o/sky130_fd_sc_ms__a32o_2.spice +++ b/cells/a32o/sky130_fd_sc_ms__a32o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32o_2.spice -* Created: Fri Aug 28 17:07:59 2020 +* Created: Wed Sep 2 11:55:47 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32o/sky130_fd_sc_ms__a32o_4.lvs.report b/cells/a32o/sky130_fd_sc_ms__a32o_4.lvs.report new file mode 100644 index 0000000..d9d90fb --- /dev/null +++ b/cells/a32o/sky130_fd_sc_ms__a32o_4.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a32o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a32o_4.sp ('sky130_fd_sc_ms__a32o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a32o/sky130_fd_sc_ms__a32o_4.spice ('sky130_fd_sc_ms__a32o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:55:50 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a32o_4 sky130_fd_sc_ms__a32o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a32o_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a32o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A2 A1 A3 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_ms__a32o_4.pex.spice b/cells/a32o/sky130_fd_sc_ms__a32o_4.pex.spice index 558e573..d9efcdf 100644 --- a/cells/a32o/sky130_fd_sc_ms__a32o_4.pex.spice +++ b/cells/a32o/sky130_fd_sc_ms__a32o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32o_4.pex.spice -* Created: Fri Aug 28 17:08:28 2020 +* Created: Wed Sep 2 11:55:53 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_ms__a32o_4.pxi.spice b/cells/a32o/sky130_fd_sc_ms__a32o_4.pxi.spice index 42e3dfa..9ac9f35 100644 --- a/cells/a32o/sky130_fd_sc_ms__a32o_4.pxi.spice +++ b/cells/a32o/sky130_fd_sc_ms__a32o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32o_4.pxi.spice -* Created: Fri Aug 28 17:08:28 2020 +* Created: Wed Sep 2 11:55:53 2020 * x_PM_SKY130_FD_SC_MS__A32O_4%A_83_283# N_A_83_283#_M1001_d N_A_83_283#_M1025_d + N_A_83_283#_M1015_s N_A_83_283#_M1019_s N_A_83_283#_M1003_g
diff --git a/cells/a32o/sky130_fd_sc_ms__a32o_4.spice b/cells/a32o/sky130_fd_sc_ms__a32o_4.spice index 8adfcfb..ef5a688 100644 --- a/cells/a32o/sky130_fd_sc_ms__a32o_4.spice +++ b/cells/a32o/sky130_fd_sc_ms__a32o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32o_4.spice -* Created: Fri Aug 28 17:08:28 2020 +* Created: Wed Sep 2 11:55:53 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32oi/sky130_fd_sc_ms__a32oi_1.lvs.report b/cells/a32oi/sky130_fd_sc_ms__a32oi_1.lvs.report new file mode 100644 index 0000000..fd1dfa4 --- /dev/null +++ b/cells/a32oi/sky130_fd_sc_ms__a32oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a32oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a32oi_1.sp ('sky130_fd_sc_ms__a32oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a32oi/sky130_fd_sc_ms__a32oi_1.spice ('sky130_fd_sc_ms__a32oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:55:57 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a32oi_1 sky130_fd_sc_ms__a32oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a32oi_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a32oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_ms__a32oi_1.pex.spice b/cells/a32oi/sky130_fd_sc_ms__a32oi_1.pex.spice index c3169ab..fc2f68a 100644 --- a/cells/a32oi/sky130_fd_sc_ms__a32oi_1.pex.spice +++ b/cells/a32oi/sky130_fd_sc_ms__a32oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32oi_1.pex.spice -* Created: Fri Aug 28 17:08:37 2020 +* Created: Wed Sep 2 11:56:00 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_ms__a32oi_1.pxi.spice b/cells/a32oi/sky130_fd_sc_ms__a32oi_1.pxi.spice index 705a640..97a25fd 100644 --- a/cells/a32oi/sky130_fd_sc_ms__a32oi_1.pxi.spice +++ b/cells/a32oi/sky130_fd_sc_ms__a32oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32oi_1.pxi.spice -* Created: Fri Aug 28 17:08:37 2020 +* Created: Wed Sep 2 11:56:00 2020 * x_PM_SKY130_FD_SC_MS__A32OI_1%B2 N_B2_M1003_g N_B2_c_52_n N_B2_M1005_g B2 + N_B2_c_54_n PM_SKY130_FD_SC_MS__A32OI_1%B2
diff --git a/cells/a32oi/sky130_fd_sc_ms__a32oi_1.spice b/cells/a32oi/sky130_fd_sc_ms__a32oi_1.spice index 207822d..4a724e3 100644 --- a/cells/a32oi/sky130_fd_sc_ms__a32oi_1.spice +++ b/cells/a32oi/sky130_fd_sc_ms__a32oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32oi_1.spice -* Created: Fri Aug 28 17:08:37 2020 +* Created: Wed Sep 2 11:56:00 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32oi/sky130_fd_sc_ms__a32oi_2.lvs.report b/cells/a32oi/sky130_fd_sc_ms__a32oi_2.lvs.report new file mode 100644 index 0000000..8a63353 --- /dev/null +++ b/cells/a32oi/sky130_fd_sc_ms__a32oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a32oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a32oi_2.sp ('sky130_fd_sc_ms__a32oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a32oi/sky130_fd_sc_ms__a32oi_2.spice ('sky130_fd_sc_ms__a32oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:56:04 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a32oi_2 sky130_fd_sc_ms__a32oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a32oi_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a32oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_ms__a32oi_2.pex.spice b/cells/a32oi/sky130_fd_sc_ms__a32oi_2.pex.spice index 1b23ca1..c40641e 100644 --- a/cells/a32oi/sky130_fd_sc_ms__a32oi_2.pex.spice +++ b/cells/a32oi/sky130_fd_sc_ms__a32oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32oi_2.pex.spice -* Created: Fri Aug 28 17:08:47 2020 +* Created: Wed Sep 2 11:56:07 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_ms__a32oi_2.pxi.spice b/cells/a32oi/sky130_fd_sc_ms__a32oi_2.pxi.spice index c234fb5..d601cda 100644 --- a/cells/a32oi/sky130_fd_sc_ms__a32oi_2.pxi.spice +++ b/cells/a32oi/sky130_fd_sc_ms__a32oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32oi_2.pxi.spice -* Created: Fri Aug 28 17:08:47 2020 +* Created: Wed Sep 2 11:56:07 2020 * x_PM_SKY130_FD_SC_MS__A32OI_2%B2 N_B2_M1011_g N_B2_M1000_g N_B2_M1017_g + N_B2_M1006_g N_B2_c_107_n B2 N_B2_c_108_n N_B2_c_109_n
diff --git a/cells/a32oi/sky130_fd_sc_ms__a32oi_2.spice b/cells/a32oi/sky130_fd_sc_ms__a32oi_2.spice index 2e538b4..83364cc 100644 --- a/cells/a32oi/sky130_fd_sc_ms__a32oi_2.spice +++ b/cells/a32oi/sky130_fd_sc_ms__a32oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32oi_2.spice -* Created: Fri Aug 28 17:08:47 2020 +* Created: Wed Sep 2 11:56:07 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a32oi/sky130_fd_sc_ms__a32oi_4.lvs.report b/cells/a32oi/sky130_fd_sc_ms__a32oi_4.lvs.report new file mode 100644 index 0000000..dbd3dd8 --- /dev/null +++ b/cells/a32oi/sky130_fd_sc_ms__a32oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a32oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a32oi_4.sp ('sky130_fd_sc_ms__a32oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a32oi/sky130_fd_sc_ms__a32oi_4.spice ('sky130_fd_sc_ms__a32oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:56:10 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a32oi_4 sky130_fd_sc_ms__a32oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a32oi_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a32oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SPMP_3_2 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SPMP_3_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 40 layout mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + 40 source mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_ms__a32oi_4.pex.spice b/cells/a32oi/sky130_fd_sc_ms__a32oi_4.pex.spice index 2caa4ff..f2b9986 100644 --- a/cells/a32oi/sky130_fd_sc_ms__a32oi_4.pex.spice +++ b/cells/a32oi/sky130_fd_sc_ms__a32oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32oi_4.pex.spice -* Created: Fri Aug 28 17:08:55 2020 +* Created: Wed Sep 2 11:56:13 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_ms__a32oi_4.pxi.spice b/cells/a32oi/sky130_fd_sc_ms__a32oi_4.pxi.spice index 1e5c089..05f4482 100644 --- a/cells/a32oi/sky130_fd_sc_ms__a32oi_4.pxi.spice +++ b/cells/a32oi/sky130_fd_sc_ms__a32oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32oi_4.pxi.spice -* Created: Fri Aug 28 17:08:55 2020 +* Created: Wed Sep 2 11:56:13 2020 * x_PM_SKY130_FD_SC_MS__A32OI_4%B2 N_B2_M1008_g N_B2_M1000_g N_B2_M1007_g + N_B2_M1015_g N_B2_M1032_g N_B2_M1010_g N_B2_M1014_g N_B2_M1035_g B2 B2 B2 B2
diff --git a/cells/a32oi/sky130_fd_sc_ms__a32oi_4.spice b/cells/a32oi/sky130_fd_sc_ms__a32oi_4.spice index 5161387..29c839b 100644 --- a/cells/a32oi/sky130_fd_sc_ms__a32oi_4.spice +++ b/cells/a32oi/sky130_fd_sc_ms__a32oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a32oi_4.spice -* Created: Fri Aug 28 17:08:55 2020 +* Created: Wed Sep 2 11:56:13 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41o/sky130_fd_sc_ms__a41o_1.lvs.report b/cells/a41o/sky130_fd_sc_ms__a41o_1.lvs.report new file mode 100644 index 0000000..43c5a88 --- /dev/null +++ b/cells/a41o/sky130_fd_sc_ms__a41o_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a41o_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a41o_1.sp ('sky130_fd_sc_ms__a41o_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a41o/sky130_fd_sc_ms__a41o_1.spice ('sky130_fd_sc_ms__a41o_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:56:17 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a41o_1 sky130_fd_sc_ms__a41o_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a41o_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a41o_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 A3 A4 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_ms__a41o_1.pex.spice b/cells/a41o/sky130_fd_sc_ms__a41o_1.pex.spice index 0b76226..b2e12ec 100644 --- a/cells/a41o/sky130_fd_sc_ms__a41o_1.pex.spice +++ b/cells/a41o/sky130_fd_sc_ms__a41o_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41o_1.pex.spice -* Created: Fri Aug 28 17:09:04 2020 +* Created: Wed Sep 2 11:56:20 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_ms__a41o_1.pxi.spice b/cells/a41o/sky130_fd_sc_ms__a41o_1.pxi.spice index f6edb6a..b07688b 100644 --- a/cells/a41o/sky130_fd_sc_ms__a41o_1.pxi.spice +++ b/cells/a41o/sky130_fd_sc_ms__a41o_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41o_1.pxi.spice -* Created: Fri Aug 28 17:09:04 2020 +* Created: Wed Sep 2 11:56:20 2020 * x_PM_SKY130_FD_SC_MS__A41O_1%A_83_244# N_A_83_244#_M1008_d N_A_83_244#_M1010_s + N_A_83_244#_M1001_g N_A_83_244#_c_73_n N_A_83_244#_M1005_g N_A_83_244#_c_74_n
diff --git a/cells/a41o/sky130_fd_sc_ms__a41o_1.spice b/cells/a41o/sky130_fd_sc_ms__a41o_1.spice index d54472e..af80998 100644 --- a/cells/a41o/sky130_fd_sc_ms__a41o_1.spice +++ b/cells/a41o/sky130_fd_sc_ms__a41o_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41o_1.spice -* Created: Fri Aug 28 17:09:04 2020 +* Created: Wed Sep 2 11:56:20 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41o/sky130_fd_sc_ms__a41o_2.lvs.report b/cells/a41o/sky130_fd_sc_ms__a41o_2.lvs.report new file mode 100644 index 0000000..7df86eb --- /dev/null +++ b/cells/a41o/sky130_fd_sc_ms__a41o_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a41o_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a41o_2.sp ('sky130_fd_sc_ms__a41o_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a41o/sky130_fd_sc_ms__a41o_2.spice ('sky130_fd_sc_ms__a41o_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:56:23 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a41o_2 sky130_fd_sc_ms__a41o_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a41o_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a41o_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A4 A3 A2 A1 B1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_ms__a41o_2.pex.spice b/cells/a41o/sky130_fd_sc_ms__a41o_2.pex.spice index e5d2e52..3673be9 100644 --- a/cells/a41o/sky130_fd_sc_ms__a41o_2.pex.spice +++ b/cells/a41o/sky130_fd_sc_ms__a41o_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41o_2.pex.spice -* Created: Fri Aug 28 17:09:33 2020 +* Created: Wed Sep 2 11:56:26 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_ms__a41o_2.pxi.spice b/cells/a41o/sky130_fd_sc_ms__a41o_2.pxi.spice index 7cc029a..f0e867a 100644 --- a/cells/a41o/sky130_fd_sc_ms__a41o_2.pxi.spice +++ b/cells/a41o/sky130_fd_sc_ms__a41o_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41o_2.pxi.spice -* Created: Fri Aug 28 17:09:33 2020 +* Created: Wed Sep 2 11:56:26 2020 * x_PM_SKY130_FD_SC_MS__A41O_2%A4 N_A4_M1002_g N_A4_c_82_n N_A4_M1005_g A4 + N_A4_c_84_n PM_SKY130_FD_SC_MS__A41O_2%A4
diff --git a/cells/a41o/sky130_fd_sc_ms__a41o_2.spice b/cells/a41o/sky130_fd_sc_ms__a41o_2.spice index adf6838..0e96c77 100644 --- a/cells/a41o/sky130_fd_sc_ms__a41o_2.spice +++ b/cells/a41o/sky130_fd_sc_ms__a41o_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41o_2.spice -* Created: Fri Aug 28 17:09:33 2020 +* Created: Wed Sep 2 11:56:26 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41o/sky130_fd_sc_ms__a41o_4.lvs.report b/cells/a41o/sky130_fd_sc_ms__a41o_4.lvs.report new file mode 100644 index 0000000..9e2fff6 --- /dev/null +++ b/cells/a41o/sky130_fd_sc_ms__a41o_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a41o_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a41o_4.sp ('sky130_fd_sc_ms__a41o_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a41o/sky130_fd_sc_ms__a41o_4.spice ('sky130_fd_sc_ms__a41o_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:56:29 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a41o_4 sky130_fd_sc_ms__a41o_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a41o_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a41o_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 A3 A4 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_ms__a41o_4.pex.spice b/cells/a41o/sky130_fd_sc_ms__a41o_4.pex.spice index 4358e17..f285691 100644 --- a/cells/a41o/sky130_fd_sc_ms__a41o_4.pex.spice +++ b/cells/a41o/sky130_fd_sc_ms__a41o_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41o_4.pex.spice -* Created: Fri Aug 28 17:09:42 2020 +* Created: Wed Sep 2 11:56:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_ms__a41o_4.pxi.spice b/cells/a41o/sky130_fd_sc_ms__a41o_4.pxi.spice index c7f9c92..5a7ec52 100644 --- a/cells/a41o/sky130_fd_sc_ms__a41o_4.pxi.spice +++ b/cells/a41o/sky130_fd_sc_ms__a41o_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41o_4.pxi.spice -* Created: Fri Aug 28 17:09:42 2020 +* Created: Wed Sep 2 11:56:32 2020 * x_PM_SKY130_FD_SC_MS__A41O_4%B1 N_B1_M1006_g N_B1_M1000_g N_B1_M1019_g + N_B1_M1027_g B1 N_B1_c_137_n N_B1_c_138_n PM_SKY130_FD_SC_MS__A41O_4%B1
diff --git a/cells/a41o/sky130_fd_sc_ms__a41o_4.spice b/cells/a41o/sky130_fd_sc_ms__a41o_4.spice index 4736070..8fd3a2b 100644 --- a/cells/a41o/sky130_fd_sc_ms__a41o_4.spice +++ b/cells/a41o/sky130_fd_sc_ms__a41o_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41o_4.spice -* Created: Fri Aug 28 17:09:42 2020 +* Created: Wed Sep 2 11:56:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41oi/sky130_fd_sc_ms__a41oi_1.lvs.report b/cells/a41oi/sky130_fd_sc_ms__a41oi_1.lvs.report new file mode 100644 index 0000000..dc4cd65 --- /dev/null +++ b/cells/a41oi/sky130_fd_sc_ms__a41oi_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a41oi_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a41oi_1.sp ('sky130_fd_sc_ms__a41oi_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a41oi/sky130_fd_sc_ms__a41oi_1.spice ('sky130_fd_sc_ms__a41oi_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:56:36 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a41oi_1 sky130_fd_sc_ms__a41oi_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a41oi_1 +SOURCE CELL NAME: sky130_fd_sc_ms__a41oi_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A4 A3 A2 A1 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_ms__a41oi_1.pex.spice b/cells/a41oi/sky130_fd_sc_ms__a41oi_1.pex.spice index 05c2883..a04c689 100644 --- a/cells/a41oi/sky130_fd_sc_ms__a41oi_1.pex.spice +++ b/cells/a41oi/sky130_fd_sc_ms__a41oi_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41oi_1.pex.spice -* Created: Fri Aug 28 17:09:51 2020 +* Created: Wed Sep 2 11:56:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_ms__a41oi_1.pxi.spice b/cells/a41oi/sky130_fd_sc_ms__a41oi_1.pxi.spice index 696f03e..9c01e48 100644 --- a/cells/a41oi/sky130_fd_sc_ms__a41oi_1.pxi.spice +++ b/cells/a41oi/sky130_fd_sc_ms__a41oi_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41oi_1.pxi.spice -* Created: Fri Aug 28 17:09:51 2020 +* Created: Wed Sep 2 11:56:39 2020 * x_PM_SKY130_FD_SC_MS__A41OI_1%B1 N_B1_M1003_g N_B1_M1007_g B1 N_B1_c_55_n + N_B1_c_56_n PM_SKY130_FD_SC_MS__A41OI_1%B1
diff --git a/cells/a41oi/sky130_fd_sc_ms__a41oi_1.spice b/cells/a41oi/sky130_fd_sc_ms__a41oi_1.spice index 21a00d8..e26e2ee 100644 --- a/cells/a41oi/sky130_fd_sc_ms__a41oi_1.spice +++ b/cells/a41oi/sky130_fd_sc_ms__a41oi_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41oi_1.spice -* Created: Fri Aug 28 17:09:51 2020 +* Created: Wed Sep 2 11:56:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41oi/sky130_fd_sc_ms__a41oi_2.lvs.report b/cells/a41oi/sky130_fd_sc_ms__a41oi_2.lvs.report new file mode 100644 index 0000000..d4ffef6 --- /dev/null +++ b/cells/a41oi/sky130_fd_sc_ms__a41oi_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a41oi_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a41oi_2.sp ('sky130_fd_sc_ms__a41oi_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a41oi/sky130_fd_sc_ms__a41oi_2.spice ('sky130_fd_sc_ms__a41oi_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:56:43 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a41oi_2 sky130_fd_sc_ms__a41oi_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a41oi_2 +SOURCE CELL NAME: sky130_fd_sc_ms__a41oi_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 9 9 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 20 19 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 18 layout mos transistors were reduced to 9. + 9 mos transistors were deleted by parallel reduction. + 18 source mos transistors were reduced to 9. + 9 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 A3 A4 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_ms__a41oi_2.pex.spice b/cells/a41oi/sky130_fd_sc_ms__a41oi_2.pex.spice index 3e09c41..c93dc6e 100644 --- a/cells/a41oi/sky130_fd_sc_ms__a41oi_2.pex.spice +++ b/cells/a41oi/sky130_fd_sc_ms__a41oi_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41oi_2.pex.spice -* Created: Fri Aug 28 17:10:00 2020 +* Created: Wed Sep 2 11:56:45 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_ms__a41oi_2.pxi.spice b/cells/a41oi/sky130_fd_sc_ms__a41oi_2.pxi.spice index 443468e..16d4aee 100644 --- a/cells/a41oi/sky130_fd_sc_ms__a41oi_2.pxi.spice +++ b/cells/a41oi/sky130_fd_sc_ms__a41oi_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41oi_2.pxi.spice -* Created: Fri Aug 28 17:10:00 2020 +* Created: Wed Sep 2 11:56:45 2020 * x_PM_SKY130_FD_SC_MS__A41OI_2%B1 N_B1_M1007_g N_B1_M1013_g N_B1_M1009_g B1 B1 + N_B1_c_91_n N_B1_c_92_n PM_SKY130_FD_SC_MS__A41OI_2%B1
diff --git a/cells/a41oi/sky130_fd_sc_ms__a41oi_2.spice b/cells/a41oi/sky130_fd_sc_ms__a41oi_2.spice index 3b8ce47..783e708 100644 --- a/cells/a41oi/sky130_fd_sc_ms__a41oi_2.spice +++ b/cells/a41oi/sky130_fd_sc_ms__a41oi_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41oi_2.spice -* Created: Fri Aug 28 17:10:00 2020 +* Created: Wed Sep 2 11:56:45 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/a41oi/sky130_fd_sc_ms__a41oi_4.lvs.report b/cells/a41oi/sky130_fd_sc_ms__a41oi_4.lvs.report new file mode 100644 index 0000000..2a557ee --- /dev/null +++ b/cells/a41oi/sky130_fd_sc_ms__a41oi_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__a41oi_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__a41oi_4.sp ('sky130_fd_sc_ms__a41oi_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/a41oi/sky130_fd_sc_ms__a41oi_4.spice ('sky130_fd_sc_ms__a41oi_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:56:49 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__a41oi_4 sky130_fd_sc_ms__a41oi_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__a41oi_4 +SOURCE CELL NAME: sky130_fd_sc_ms__a41oi_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 18 18 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 39 38 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 SMN4 (6 pins) + 1 1 SPMP_4_1 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 SMN4 + 1 1 0 0 SPMP_4_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 38 layout mos transistors were reduced to 10. + 28 mos transistors were deleted by parallel reduction. + 38 source mos transistors were reduced to 10. + 28 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A1 A2 A3 A4 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_ms__a41oi_4.pex.spice b/cells/a41oi/sky130_fd_sc_ms__a41oi_4.pex.spice index 97d0f64..81c6def 100644 --- a/cells/a41oi/sky130_fd_sc_ms__a41oi_4.pex.spice +++ b/cells/a41oi/sky130_fd_sc_ms__a41oi_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41oi_4.pex.spice -* Created: Fri Aug 28 17:10:08 2020 +* Created: Wed Sep 2 11:56:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_ms__a41oi_4.pxi.spice b/cells/a41oi/sky130_fd_sc_ms__a41oi_4.pxi.spice index 752c6f0..054ffca 100644 --- a/cells/a41oi/sky130_fd_sc_ms__a41oi_4.pxi.spice +++ b/cells/a41oi/sky130_fd_sc_ms__a41oi_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41oi_4.pxi.spice -* Created: Fri Aug 28 17:10:08 2020 +* Created: Wed Sep 2 11:56:52 2020 * x_PM_SKY130_FD_SC_MS__A41OI_4%B1 N_B1_M1015_g N_B1_c_157_n N_B1_M1002_g + N_B1_c_158_n N_B1_M1007_g N_B1_M1032_g N_B1_c_159_n N_B1_M1009_g N_B1_c_154_n
diff --git a/cells/a41oi/sky130_fd_sc_ms__a41oi_4.spice b/cells/a41oi/sky130_fd_sc_ms__a41oi_4.spice index aabf9e2..de70284 100644 --- a/cells/a41oi/sky130_fd_sc_ms__a41oi_4.spice +++ b/cells/a41oi/sky130_fd_sc_ms__a41oi_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__a41oi_4.spice -* Created: Fri Aug 28 17:10:08 2020 +* Created: Wed Sep 2 11:56:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and2/sky130_fd_sc_ms__and2_1.lvs.report b/cells/and2/sky130_fd_sc_ms__and2_1.lvs.report new file mode 100644 index 0000000..765a4cb --- /dev/null +++ b/cells/and2/sky130_fd_sc_ms__and2_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and2_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and2_1.sp ('sky130_fd_sc_ms__and2_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and2/sky130_fd_sc_ms__and2_1.spice ('sky130_fd_sc_ms__and2_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:56:56 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and2_1 sky130_fd_sc_ms__and2_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and2_1 +SOURCE CELL NAME: sky130_fd_sc_ms__and2_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMN2 (4 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_ms__and2_1.pex.spice b/cells/and2/sky130_fd_sc_ms__and2_1.pex.spice index e072bed..f1dfc41 100644 --- a/cells/and2/sky130_fd_sc_ms__and2_1.pex.spice +++ b/cells/and2/sky130_fd_sc_ms__and2_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2_1.pex.spice -* Created: Fri Aug 28 17:10:38 2020 +* Created: Wed Sep 2 11:56:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_ms__and2_1.pxi.spice b/cells/and2/sky130_fd_sc_ms__and2_1.pxi.spice index b4eb1e0..97cb79c 100644 --- a/cells/and2/sky130_fd_sc_ms__and2_1.pxi.spice +++ b/cells/and2/sky130_fd_sc_ms__and2_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2_1.pxi.spice -* Created: Fri Aug 28 17:10:38 2020 +* Created: Wed Sep 2 11:56:59 2020 * x_PM_SKY130_FD_SC_MS__AND2_1%A N_A_c_46_n N_A_M1004_g N_A_M1000_g N_A_c_49_n A A + N_A_c_51_n PM_SKY130_FD_SC_MS__AND2_1%A
diff --git a/cells/and2/sky130_fd_sc_ms__and2_1.spice b/cells/and2/sky130_fd_sc_ms__and2_1.spice index cf61f2e..c959e12 100644 --- a/cells/and2/sky130_fd_sc_ms__and2_1.spice +++ b/cells/and2/sky130_fd_sc_ms__and2_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2_1.spice -* Created: Fri Aug 28 17:10:38 2020 +* Created: Wed Sep 2 11:56:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and2/sky130_fd_sc_ms__and2_2.lvs.report b/cells/and2/sky130_fd_sc_ms__and2_2.lvs.report new file mode 100644 index 0000000..aa9451d --- /dev/null +++ b/cells/and2/sky130_fd_sc_ms__and2_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and2_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and2_2.sp ('sky130_fd_sc_ms__and2_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and2/sky130_fd_sc_ms__and2_2.spice ('sky130_fd_sc_ms__and2_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:57:02 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and2_2 sky130_fd_sc_ms__and2_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and2_2 +SOURCE CELL NAME: sky130_fd_sc_ms__and2_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMN2 (4 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_ms__and2_2.pex.spice b/cells/and2/sky130_fd_sc_ms__and2_2.pex.spice index c3b38f8..dd0a48a 100644 --- a/cells/and2/sky130_fd_sc_ms__and2_2.pex.spice +++ b/cells/and2/sky130_fd_sc_ms__and2_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2_2.pex.spice -* Created: Fri Aug 28 17:10:47 2020 +* Created: Wed Sep 2 11:57:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_ms__and2_2.pxi.spice b/cells/and2/sky130_fd_sc_ms__and2_2.pxi.spice index 01f03a3..70eba01 100644 --- a/cells/and2/sky130_fd_sc_ms__and2_2.pxi.spice +++ b/cells/and2/sky130_fd_sc_ms__and2_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2_2.pxi.spice -* Created: Fri Aug 28 17:10:47 2020 +* Created: Wed Sep 2 11:57:05 2020 * x_PM_SKY130_FD_SC_MS__AND2_2%A N_A_M1002_g N_A_M1006_g A N_A_c_53_n N_A_c_54_n + PM_SKY130_FD_SC_MS__AND2_2%A
diff --git a/cells/and2/sky130_fd_sc_ms__and2_2.spice b/cells/and2/sky130_fd_sc_ms__and2_2.spice index 3246b59..eb07707 100644 --- a/cells/and2/sky130_fd_sc_ms__and2_2.spice +++ b/cells/and2/sky130_fd_sc_ms__and2_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2_2.spice -* Created: Fri Aug 28 17:10:47 2020 +* Created: Wed Sep 2 11:57:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and2/sky130_fd_sc_ms__and2_4.lvs.report b/cells/and2/sky130_fd_sc_ms__and2_4.lvs.report new file mode 100644 index 0000000..a1d99fc --- /dev/null +++ b/cells/and2/sky130_fd_sc_ms__and2_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and2_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and2_4.sp ('sky130_fd_sc_ms__and2_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and2/sky130_fd_sc_ms__and2_4.spice ('sky130_fd_sc_ms__and2_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:57:08 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and2_4 sky130_fd_sc_ms__and2_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and2_4 +SOURCE CELL NAME: sky130_fd_sc_ms__and2_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMN2 (4 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_ms__and2_4.pex.spice b/cells/and2/sky130_fd_sc_ms__and2_4.pex.spice index 0b3456d..dd0d31c 100644 --- a/cells/and2/sky130_fd_sc_ms__and2_4.pex.spice +++ b/cells/and2/sky130_fd_sc_ms__and2_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2_4.pex.spice -* Created: Fri Aug 28 17:10:57 2020 +* Created: Wed Sep 2 11:57:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_ms__and2_4.pxi.spice b/cells/and2/sky130_fd_sc_ms__and2_4.pxi.spice index 2d571c5..a958082 100644 --- a/cells/and2/sky130_fd_sc_ms__and2_4.pxi.spice +++ b/cells/and2/sky130_fd_sc_ms__and2_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2_4.pxi.spice -* Created: Fri Aug 28 17:10:57 2020 +* Created: Wed Sep 2 11:57:11 2020 * x_PM_SKY130_FD_SC_MS__AND2_4%A_83_269# N_A_83_269#_M1002_d N_A_83_269#_M1013_d + N_A_83_269#_M1014_s N_A_83_269#_M1006_g N_A_83_269#_c_82_n N_A_83_269#_M1000_g
diff --git a/cells/and2/sky130_fd_sc_ms__and2_4.spice b/cells/and2/sky130_fd_sc_ms__and2_4.spice index 67a3252..e1ff36f 100644 --- a/cells/and2/sky130_fd_sc_ms__and2_4.spice +++ b/cells/and2/sky130_fd_sc_ms__and2_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2_4.spice -* Created: Fri Aug 28 17:10:57 2020 +* Created: Wed Sep 2 11:57:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and2b/sky130_fd_sc_ms__and2b_1.lvs.report b/cells/and2b/sky130_fd_sc_ms__and2b_1.lvs.report new file mode 100644 index 0000000..d36648f --- /dev/null +++ b/cells/and2b/sky130_fd_sc_ms__and2b_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and2b_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and2b_1.sp ('sky130_fd_sc_ms__and2b_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and2b/sky130_fd_sc_ms__and2b_1.spice ('sky130_fd_sc_ms__and2b_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:57:15 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and2b_1 sky130_fd_sc_ms__and2b_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and2b_1 +SOURCE CELL NAME: sky130_fd_sc_ms__and2b_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 10 10 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMN2 (4 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and2b/sky130_fd_sc_ms__and2b_1.pex.spice b/cells/and2b/sky130_fd_sc_ms__and2b_1.pex.spice index fc9cf0f..558aade 100644 --- a/cells/and2b/sky130_fd_sc_ms__and2b_1.pex.spice +++ b/cells/and2b/sky130_fd_sc_ms__and2b_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2b_1.pex.spice -* Created: Fri Aug 28 17:11:05 2020 +* Created: Wed Sep 2 11:57:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and2b/sky130_fd_sc_ms__and2b_1.pxi.spice b/cells/and2b/sky130_fd_sc_ms__and2b_1.pxi.spice index 74f7932..79aee10 100644 --- a/cells/and2b/sky130_fd_sc_ms__and2b_1.pxi.spice +++ b/cells/and2b/sky130_fd_sc_ms__and2b_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2b_1.pxi.spice -* Created: Fri Aug 28 17:11:05 2020 +* Created: Wed Sep 2 11:57:18 2020 * x_PM_SKY130_FD_SC_MS__AND2B_1%A_N N_A_N_M1006_g N_A_N_c_63_n N_A_N_c_67_n + N_A_N_M1004_g A_N A_N N_A_N_c_64_n N_A_N_c_65_n
diff --git a/cells/and2b/sky130_fd_sc_ms__and2b_1.spice b/cells/and2b/sky130_fd_sc_ms__and2b_1.spice index 507a3ef..6b5bf23 100644 --- a/cells/and2b/sky130_fd_sc_ms__and2b_1.spice +++ b/cells/and2b/sky130_fd_sc_ms__and2b_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2b_1.spice -* Created: Fri Aug 28 17:11:05 2020 +* Created: Wed Sep 2 11:57:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and2b/sky130_fd_sc_ms__and2b_2.lvs.report b/cells/and2b/sky130_fd_sc_ms__and2b_2.lvs.report new file mode 100644 index 0000000..df8f795 --- /dev/null +++ b/cells/and2b/sky130_fd_sc_ms__and2b_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and2b_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and2b_2.sp ('sky130_fd_sc_ms__and2b_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and2b/sky130_fd_sc_ms__and2b_2.spice ('sky130_fd_sc_ms__and2b_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:57:22 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and2b_2 sky130_fd_sc_ms__and2b_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and2b_2 +SOURCE CELL NAME: sky130_fd_sc_ms__and2b_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMN2 (4 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and2b/sky130_fd_sc_ms__and2b_2.pex.spice b/cells/and2b/sky130_fd_sc_ms__and2b_2.pex.spice index 2783389..2e26729 100644 --- a/cells/and2b/sky130_fd_sc_ms__and2b_2.pex.spice +++ b/cells/and2b/sky130_fd_sc_ms__and2b_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2b_2.pex.spice -* Created: Fri Aug 28 17:11:14 2020 +* Created: Wed Sep 2 11:57:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and2b/sky130_fd_sc_ms__and2b_2.pxi.spice b/cells/and2b/sky130_fd_sc_ms__and2b_2.pxi.spice index 7b06d30..4ac0ad8 100644 --- a/cells/and2b/sky130_fd_sc_ms__and2b_2.pxi.spice +++ b/cells/and2b/sky130_fd_sc_ms__and2b_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2b_2.pxi.spice -* Created: Fri Aug 28 17:11:14 2020 +* Created: Wed Sep 2 11:57:24 2020 * x_PM_SKY130_FD_SC_MS__AND2B_2%A_N N_A_N_M1003_g N_A_N_M1007_g A_N N_A_N_c_61_n + N_A_N_c_62_n PM_SKY130_FD_SC_MS__AND2B_2%A_N
diff --git a/cells/and2b/sky130_fd_sc_ms__and2b_2.spice b/cells/and2b/sky130_fd_sc_ms__and2b_2.spice index dc50963..3f53426 100644 --- a/cells/and2b/sky130_fd_sc_ms__and2b_2.spice +++ b/cells/and2b/sky130_fd_sc_ms__and2b_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2b_2.spice -* Created: Fri Aug 28 17:11:14 2020 +* Created: Wed Sep 2 11:57:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and2b/sky130_fd_sc_ms__and2b_4.lvs.report b/cells/and2b/sky130_fd_sc_ms__and2b_4.lvs.report new file mode 100644 index 0000000..909a8cf --- /dev/null +++ b/cells/and2b/sky130_fd_sc_ms__and2b_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and2b_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and2b_4.sp ('sky130_fd_sc_ms__and2b_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and2b/sky130_fd_sc_ms__and2b_4.spice ('sky130_fd_sc_ms__and2b_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:57:28 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and2b_4 sky130_fd_sc_ms__and2b_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and2b_4 +SOURCE CELL NAME: sky130_fd_sc_ms__and2b_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 10 10 + + Instances: 9 9 MN (4 pins) + 9 9 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 19 18 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMN2 (4 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and2b/sky130_fd_sc_ms__and2b_4.pex.spice b/cells/and2b/sky130_fd_sc_ms__and2b_4.pex.spice index f7c816a..0feeeb8 100644 --- a/cells/and2b/sky130_fd_sc_ms__and2b_4.pex.spice +++ b/cells/and2b/sky130_fd_sc_ms__and2b_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2b_4.pex.spice -* Created: Fri Aug 28 17:11:47 2020 +* Created: Wed Sep 2 11:57:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and2b/sky130_fd_sc_ms__and2b_4.pxi.spice b/cells/and2b/sky130_fd_sc_ms__and2b_4.pxi.spice index 9cd703c..3eb5761 100644 --- a/cells/and2b/sky130_fd_sc_ms__and2b_4.pxi.spice +++ b/cells/and2b/sky130_fd_sc_ms__and2b_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2b_4.pxi.spice -* Created: Fri Aug 28 17:11:47 2020 +* Created: Wed Sep 2 11:57:31 2020 * x_PM_SKY130_FD_SC_MS__AND2B_4%A_N N_A_N_M1008_g N_A_N_M1010_g A_N N_A_N_c_113_n + PM_SKY130_FD_SC_MS__AND2B_4%A_N
diff --git a/cells/and2b/sky130_fd_sc_ms__and2b_4.spice b/cells/and2b/sky130_fd_sc_ms__and2b_4.spice index 25d1075..df336df 100644 --- a/cells/and2b/sky130_fd_sc_ms__and2b_4.spice +++ b/cells/and2b/sky130_fd_sc_ms__and2b_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and2b_4.spice -* Created: Fri Aug 28 17:11:47 2020 +* Created: Wed Sep 2 11:57:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and3/sky130_fd_sc_ms__and3_1.lvs.report b/cells/and3/sky130_fd_sc_ms__and3_1.lvs.report new file mode 100644 index 0000000..cbd33c7 --- /dev/null +++ b/cells/and3/sky130_fd_sc_ms__and3_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and3_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and3_1.sp ('sky130_fd_sc_ms__and3_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and3/sky130_fd_sc_ms__and3_1.spice ('sky130_fd_sc_ms__and3_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:57:35 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and3_1 sky130_fd_sc_ms__and3_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and3_1 +SOURCE CELL NAME: sky130_fd_sc_ms__and3_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMN3 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B C VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and3/sky130_fd_sc_ms__and3_1.pex.spice b/cells/and3/sky130_fd_sc_ms__and3_1.pex.spice index ab534ff..1658c0c 100644 --- a/cells/and3/sky130_fd_sc_ms__and3_1.pex.spice +++ b/cells/and3/sky130_fd_sc_ms__and3_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3_1.pex.spice -* Created: Fri Aug 28 17:11:56 2020 +* Created: Wed Sep 2 11:57:38 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and3/sky130_fd_sc_ms__and3_1.pxi.spice b/cells/and3/sky130_fd_sc_ms__and3_1.pxi.spice index 9f9b44c..5e315eb 100644 --- a/cells/and3/sky130_fd_sc_ms__and3_1.pxi.spice +++ b/cells/and3/sky130_fd_sc_ms__and3_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3_1.pxi.spice -* Created: Fri Aug 28 17:11:56 2020 +* Created: Wed Sep 2 11:57:38 2020 * x_PM_SKY130_FD_SC_MS__AND3_1%A N_A_M1006_g N_A_c_57_n N_A_M1001_g N_A_c_59_n + N_A_c_60_n A N_A_c_62_n PM_SKY130_FD_SC_MS__AND3_1%A
diff --git a/cells/and3/sky130_fd_sc_ms__and3_1.spice b/cells/and3/sky130_fd_sc_ms__and3_1.spice index ecc1b27..6446479 100644 --- a/cells/and3/sky130_fd_sc_ms__and3_1.spice +++ b/cells/and3/sky130_fd_sc_ms__and3_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3_1.spice -* Created: Fri Aug 28 17:11:56 2020 +* Created: Wed Sep 2 11:57:38 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and3/sky130_fd_sc_ms__and3_2.lvs.report b/cells/and3/sky130_fd_sc_ms__and3_2.lvs.report new file mode 100644 index 0000000..52e457f --- /dev/null +++ b/cells/and3/sky130_fd_sc_ms__and3_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and3_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and3_2.sp ('sky130_fd_sc_ms__and3_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and3/sky130_fd_sc_ms__and3_2.spice ('sky130_fd_sc_ms__and3_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:57:41 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and3_2 sky130_fd_sc_ms__and3_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and3_2 +SOURCE CELL NAME: sky130_fd_sc_ms__and3_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMN3 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B C VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and3/sky130_fd_sc_ms__and3_2.pex.spice b/cells/and3/sky130_fd_sc_ms__and3_2.pex.spice index 642b1f5..2e1e309 100644 --- a/cells/and3/sky130_fd_sc_ms__and3_2.pex.spice +++ b/cells/and3/sky130_fd_sc_ms__and3_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3_2.pex.spice -* Created: Fri Aug 28 17:12:05 2020 +* Created: Wed Sep 2 11:57:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and3/sky130_fd_sc_ms__and3_2.pxi.spice b/cells/and3/sky130_fd_sc_ms__and3_2.pxi.spice index 4846146..bb75430 100644 --- a/cells/and3/sky130_fd_sc_ms__and3_2.pxi.spice +++ b/cells/and3/sky130_fd_sc_ms__and3_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3_2.pxi.spice -* Created: Fri Aug 28 17:12:05 2020 +* Created: Wed Sep 2 11:57:44 2020 * x_PM_SKY130_FD_SC_MS__AND3_2%A N_A_c_57_n N_A_M1006_g N_A_c_59_n N_A_M1005_g A A + A N_A_c_62_n PM_SKY130_FD_SC_MS__AND3_2%A
diff --git a/cells/and3/sky130_fd_sc_ms__and3_2.spice b/cells/and3/sky130_fd_sc_ms__and3_2.spice index a37ab2b..33d0e00 100644 --- a/cells/and3/sky130_fd_sc_ms__and3_2.spice +++ b/cells/and3/sky130_fd_sc_ms__and3_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3_2.spice -* Created: Fri Aug 28 17:12:05 2020 +* Created: Wed Sep 2 11:57:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and3/sky130_fd_sc_ms__and3_4.lvs.report b/cells/and3/sky130_fd_sc_ms__and3_4.lvs.report new file mode 100644 index 0000000..be4e0f3 --- /dev/null +++ b/cells/and3/sky130_fd_sc_ms__and3_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and3_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and3_4.sp ('sky130_fd_sc_ms__and3_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and3/sky130_fd_sc_ms__and3_4.spice ('sky130_fd_sc_ms__and3_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:57:48 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and3_4 sky130_fd_sc_ms__and3_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and3_4 +SOURCE CELL NAME: sky130_fd_sc_ms__and3_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMN3 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C B A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and3/sky130_fd_sc_ms__and3_4.pex.spice b/cells/and3/sky130_fd_sc_ms__and3_4.pex.spice index eeac0f5..db7c378 100644 --- a/cells/and3/sky130_fd_sc_ms__and3_4.pex.spice +++ b/cells/and3/sky130_fd_sc_ms__and3_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3_4.pex.spice -* Created: Fri Aug 28 17:12:14 2020 +* Created: Wed Sep 2 11:57:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and3/sky130_fd_sc_ms__and3_4.pxi.spice b/cells/and3/sky130_fd_sc_ms__and3_4.pxi.spice index 3ef4846..3a9b733 100644 --- a/cells/and3/sky130_fd_sc_ms__and3_4.pxi.spice +++ b/cells/and3/sky130_fd_sc_ms__and3_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3_4.pxi.spice -* Created: Fri Aug 28 17:12:14 2020 +* Created: Wed Sep 2 11:57:51 2020 * x_PM_SKY130_FD_SC_MS__AND3_4%A_83_260# N_A_83_260#_M1010_d N_A_83_260#_M1007_d + N_A_83_260#_M1001_s N_A_83_260#_M1012_d N_A_83_260#_M1003_g
diff --git a/cells/and3/sky130_fd_sc_ms__and3_4.spice b/cells/and3/sky130_fd_sc_ms__and3_4.spice index c4cee72..a4f792b 100644 --- a/cells/and3/sky130_fd_sc_ms__and3_4.spice +++ b/cells/and3/sky130_fd_sc_ms__and3_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3_4.spice -* Created: Fri Aug 28 17:12:14 2020 +* Created: Wed Sep 2 11:57:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and3b/sky130_fd_sc_ms__and3b_1.lvs.report b/cells/and3b/sky130_fd_sc_ms__and3b_1.lvs.report new file mode 100644 index 0000000..3d590be --- /dev/null +++ b/cells/and3b/sky130_fd_sc_ms__and3b_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and3b_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and3b_1.sp ('sky130_fd_sc_ms__and3b_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and3b/sky130_fd_sc_ms__and3b_1.spice ('sky130_fd_sc_ms__and3b_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:57:54 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and3b_1 sky130_fd_sc_ms__and3b_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and3b_1 +SOURCE CELL NAME: sky130_fd_sc_ms__and3b_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 5 5 MP (4 pins) + 1 1 SMN3 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B C VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and3b/sky130_fd_sc_ms__and3b_1.pex.spice b/cells/and3b/sky130_fd_sc_ms__and3b_1.pex.spice index c44d5a8..1204d52 100644 --- a/cells/and3b/sky130_fd_sc_ms__and3b_1.pex.spice +++ b/cells/and3b/sky130_fd_sc_ms__and3b_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3b_1.pex.spice -* Created: Fri Aug 28 17:12:23 2020 +* Created: Wed Sep 2 11:57:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and3b/sky130_fd_sc_ms__and3b_1.pxi.spice b/cells/and3b/sky130_fd_sc_ms__and3b_1.pxi.spice index 1d072a7..d904859 100644 --- a/cells/and3b/sky130_fd_sc_ms__and3b_1.pxi.spice +++ b/cells/and3b/sky130_fd_sc_ms__and3b_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3b_1.pxi.spice -* Created: Fri Aug 28 17:12:23 2020 +* Created: Wed Sep 2 11:57:57 2020 * x_PM_SKY130_FD_SC_MS__AND3B_1%A_N N_A_N_M1006_g N_A_N_c_75_n N_A_N_M1002_g + N_A_N_c_71_n N_A_N_c_72_n N_A_N_c_77_n A_N A_N N_A_N_c_73_n N_A_N_c_74_n
diff --git a/cells/and3b/sky130_fd_sc_ms__and3b_1.spice b/cells/and3b/sky130_fd_sc_ms__and3b_1.spice index b947c3d..d34f172 100644 --- a/cells/and3b/sky130_fd_sc_ms__and3b_1.spice +++ b/cells/and3b/sky130_fd_sc_ms__and3b_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3b_1.spice -* Created: Fri Aug 28 17:12:23 2020 +* Created: Wed Sep 2 11:57:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and3b/sky130_fd_sc_ms__and3b_2.lvs.report b/cells/and3b/sky130_fd_sc_ms__and3b_2.lvs.report new file mode 100644 index 0000000..9de0bd8 --- /dev/null +++ b/cells/and3b/sky130_fd_sc_ms__and3b_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and3b_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and3b_2.sp ('sky130_fd_sc_ms__and3b_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and3b/sky130_fd_sc_ms__and3b_2.spice ('sky130_fd_sc_ms__and3b_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:58:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and3b_2 sky130_fd_sc_ms__and3b_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and3b_2 +SOURCE CELL NAME: sky130_fd_sc_ms__and3b_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 5 5 MP (4 pins) + 1 1 SMN3 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B C VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and3b/sky130_fd_sc_ms__and3b_2.pex.spice b/cells/and3b/sky130_fd_sc_ms__and3b_2.pex.spice index 0355d44..37bf297 100644 --- a/cells/and3b/sky130_fd_sc_ms__and3b_2.pex.spice +++ b/cells/and3b/sky130_fd_sc_ms__and3b_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3b_2.pex.spice -* Created: Fri Aug 28 17:12:52 2020 +* Created: Wed Sep 2 11:58:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and3b/sky130_fd_sc_ms__and3b_2.pxi.spice b/cells/and3b/sky130_fd_sc_ms__and3b_2.pxi.spice index efbe74f..5ae7625 100644 --- a/cells/and3b/sky130_fd_sc_ms__and3b_2.pxi.spice +++ b/cells/and3b/sky130_fd_sc_ms__and3b_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3b_2.pxi.spice -* Created: Fri Aug 28 17:12:52 2020 +* Created: Wed Sep 2 11:58:03 2020 * x_PM_SKY130_FD_SC_MS__AND3B_2%A_N N_A_N_c_79_n N_A_N_c_84_n N_A_N_M1005_g + N_A_N_M1009_g A_N N_A_N_c_81_n N_A_N_c_82_n PM_SKY130_FD_SC_MS__AND3B_2%A_N
diff --git a/cells/and3b/sky130_fd_sc_ms__and3b_2.spice b/cells/and3b/sky130_fd_sc_ms__and3b_2.spice index 911c9cf..17e43e4 100644 --- a/cells/and3b/sky130_fd_sc_ms__and3b_2.spice +++ b/cells/and3b/sky130_fd_sc_ms__and3b_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3b_2.spice -* Created: Fri Aug 28 17:12:52 2020 +* Created: Wed Sep 2 11:58:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and3b/sky130_fd_sc_ms__and3b_4.lvs.report b/cells/and3b/sky130_fd_sc_ms__and3b_4.lvs.report new file mode 100644 index 0000000..167f092 --- /dev/null +++ b/cells/and3b/sky130_fd_sc_ms__and3b_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and3b_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and3b_4.sp ('sky130_fd_sc_ms__and3b_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and3b/sky130_fd_sc_ms__and3b_4.spice ('sky130_fd_sc_ms__and3b_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:58:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and3b_4 sky130_fd_sc_ms__and3b_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and3b_4 +SOURCE CELL NAME: sky130_fd_sc_ms__and3b_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 5 5 MP (4 pins) + 1 1 SMN3 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B C VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and3b/sky130_fd_sc_ms__and3b_4.pex.spice b/cells/and3b/sky130_fd_sc_ms__and3b_4.pex.spice index bacf121..ba0143b 100644 --- a/cells/and3b/sky130_fd_sc_ms__and3b_4.pex.spice +++ b/cells/and3b/sky130_fd_sc_ms__and3b_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3b_4.pex.spice -* Created: Fri Aug 28 17:13:01 2020 +* Created: Wed Sep 2 11:58:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and3b/sky130_fd_sc_ms__and3b_4.pxi.spice b/cells/and3b/sky130_fd_sc_ms__and3b_4.pxi.spice index 0be0311..c37cfc6 100644 --- a/cells/and3b/sky130_fd_sc_ms__and3b_4.pxi.spice +++ b/cells/and3b/sky130_fd_sc_ms__and3b_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3b_4.pxi.spice -* Created: Fri Aug 28 17:13:01 2020 +* Created: Wed Sep 2 11:58:10 2020 * x_PM_SKY130_FD_SC_MS__AND3B_4%A_N N_A_N_M1018_g N_A_N_M1000_g A_N N_A_N_c_129_n + PM_SKY130_FD_SC_MS__AND3B_4%A_N
diff --git a/cells/and3b/sky130_fd_sc_ms__and3b_4.spice b/cells/and3b/sky130_fd_sc_ms__and3b_4.spice index 143db57..e86eef9 100644 --- a/cells/and3b/sky130_fd_sc_ms__and3b_4.spice +++ b/cells/and3b/sky130_fd_sc_ms__and3b_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and3b_4.spice -* Created: Fri Aug 28 17:13:01 2020 +* Created: Wed Sep 2 11:58:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and4/sky130_fd_sc_ms__and4_1.lvs.report b/cells/and4/sky130_fd_sc_ms__and4_1.lvs.report new file mode 100644 index 0000000..7f35d8e --- /dev/null +++ b/cells/and4/sky130_fd_sc_ms__and4_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and4_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and4_1.sp ('sky130_fd_sc_ms__and4_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and4/sky130_fd_sc_ms__and4_1.spice ('sky130_fd_sc_ms__and4_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:58:14 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and4_1 sky130_fd_sc_ms__and4_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and4_1 +SOURCE CELL NAME: sky130_fd_sc_ms__and4_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 5 5 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B C D VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and4/sky130_fd_sc_ms__and4_1.pex.spice b/cells/and4/sky130_fd_sc_ms__and4_1.pex.spice index 712a6bd..fa95513 100644 --- a/cells/and4/sky130_fd_sc_ms__and4_1.pex.spice +++ b/cells/and4/sky130_fd_sc_ms__and4_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4_1.pex.spice -* Created: Fri Aug 28 17:13:10 2020 +* Created: Wed Sep 2 11:58:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and4/sky130_fd_sc_ms__and4_1.pxi.spice b/cells/and4/sky130_fd_sc_ms__and4_1.pxi.spice index 04c7e78..2903ad0 100644 --- a/cells/and4/sky130_fd_sc_ms__and4_1.pxi.spice +++ b/cells/and4/sky130_fd_sc_ms__and4_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4_1.pxi.spice -* Created: Fri Aug 28 17:13:10 2020 +* Created: Wed Sep 2 11:58:17 2020 * x_PM_SKY130_FD_SC_MS__AND4_1%A N_A_M1004_g N_A_M1009_g N_A_c_68_n N_A_c_69_n + N_A_c_70_n A A N_A_c_71_n N_A_c_72_n PM_SKY130_FD_SC_MS__AND4_1%A
diff --git a/cells/and4/sky130_fd_sc_ms__and4_1.spice b/cells/and4/sky130_fd_sc_ms__and4_1.spice index fb7c981..d103cd7 100644 --- a/cells/and4/sky130_fd_sc_ms__and4_1.spice +++ b/cells/and4/sky130_fd_sc_ms__and4_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4_1.spice -* Created: Fri Aug 28 17:13:10 2020 +* Created: Wed Sep 2 11:58:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and4/sky130_fd_sc_ms__and4_2.lvs.report b/cells/and4/sky130_fd_sc_ms__and4_2.lvs.report new file mode 100644 index 0000000..d0e5ce6 --- /dev/null +++ b/cells/and4/sky130_fd_sc_ms__and4_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and4_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and4_2.sp ('sky130_fd_sc_ms__and4_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and4/sky130_fd_sc_ms__and4_2.spice ('sky130_fd_sc_ms__and4_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:58:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and4_2 sky130_fd_sc_ms__and4_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and4_2 +SOURCE CELL NAME: sky130_fd_sc_ms__and4_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 5 5 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B C D VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and4/sky130_fd_sc_ms__and4_2.pex.spice b/cells/and4/sky130_fd_sc_ms__and4_2.pex.spice index 2a61007..fe9551c 100644 --- a/cells/and4/sky130_fd_sc_ms__and4_2.pex.spice +++ b/cells/and4/sky130_fd_sc_ms__and4_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4_2.pex.spice -* Created: Fri Aug 28 17:13:19 2020 +* Created: Wed Sep 2 11:58:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and4/sky130_fd_sc_ms__and4_2.pxi.spice b/cells/and4/sky130_fd_sc_ms__and4_2.pxi.spice index b024d96..d3e3d9a 100644 --- a/cells/and4/sky130_fd_sc_ms__and4_2.pxi.spice +++ b/cells/and4/sky130_fd_sc_ms__and4_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4_2.pxi.spice -* Created: Fri Aug 28 17:13:19 2020 +* Created: Wed Sep 2 11:58:23 2020 * x_PM_SKY130_FD_SC_MS__AND4_2%A N_A_M1001_g N_A_M1005_g N_A_c_69_n N_A_c_70_n A + N_A_c_71_n PM_SKY130_FD_SC_MS__AND4_2%A
diff --git a/cells/and4/sky130_fd_sc_ms__and4_2.spice b/cells/and4/sky130_fd_sc_ms__and4_2.spice index fc14911..28644f5 100644 --- a/cells/and4/sky130_fd_sc_ms__and4_2.spice +++ b/cells/and4/sky130_fd_sc_ms__and4_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4_2.spice -* Created: Fri Aug 28 17:13:19 2020 +* Created: Wed Sep 2 11:58:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and4/sky130_fd_sc_ms__and4_4.lvs.report b/cells/and4/sky130_fd_sc_ms__and4_4.lvs.report new file mode 100644 index 0000000..31f4572 --- /dev/null +++ b/cells/and4/sky130_fd_sc_ms__and4_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and4_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and4_4.sp ('sky130_fd_sc_ms__and4_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and4/sky130_fd_sc_ms__and4_4.spice ('sky130_fd_sc_ms__and4_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:58:26 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and4_4 sky130_fd_sc_ms__and4_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and4_4 +SOURCE CELL NAME: sky130_fd_sc_ms__and4_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 5 5 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B D C VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and4/sky130_fd_sc_ms__and4_4.pex.spice b/cells/and4/sky130_fd_sc_ms__and4_4.pex.spice index 66a88fd..d472c9a 100644 --- a/cells/and4/sky130_fd_sc_ms__and4_4.pex.spice +++ b/cells/and4/sky130_fd_sc_ms__and4_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4_4.pex.spice -* Created: Fri Aug 28 17:13:28 2020 +* Created: Wed Sep 2 11:58:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and4/sky130_fd_sc_ms__and4_4.pxi.spice b/cells/and4/sky130_fd_sc_ms__and4_4.pxi.spice index a8d16f7..e890cb4 100644 --- a/cells/and4/sky130_fd_sc_ms__and4_4.pxi.spice +++ b/cells/and4/sky130_fd_sc_ms__and4_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4_4.pxi.spice -* Created: Fri Aug 28 17:13:28 2020 +* Created: Wed Sep 2 11:58:29 2020 * x_PM_SKY130_FD_SC_MS__AND4_4%A N_A_c_140_n N_A_M1002_g N_A_M1003_g N_A_M1006_g + N_A_M1004_g A N_A_c_139_n PM_SKY130_FD_SC_MS__AND4_4%A
diff --git a/cells/and4/sky130_fd_sc_ms__and4_4.spice b/cells/and4/sky130_fd_sc_ms__and4_4.spice index 4754dfb..a8aa8da 100644 --- a/cells/and4/sky130_fd_sc_ms__and4_4.spice +++ b/cells/and4/sky130_fd_sc_ms__and4_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4_4.spice -* Created: Fri Aug 28 17:13:28 2020 +* Created: Wed Sep 2 11:58:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and4b/sky130_fd_sc_ms__and4b_1.lvs.report b/cells/and4b/sky130_fd_sc_ms__and4b_1.lvs.report new file mode 100644 index 0000000..2af58da --- /dev/null +++ b/cells/and4b/sky130_fd_sc_ms__and4b_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and4b_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and4b_1.sp ('sky130_fd_sc_ms__and4b_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and4b/sky130_fd_sc_ms__and4b_1.spice ('sky130_fd_sc_ms__and4b_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:58:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and4b_1 sky130_fd_sc_ms__and4b_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and4b_1 +SOURCE CELL NAME: sky130_fd_sc_ms__and4b_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 6 6 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 9 9 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 9 9 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B C D VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and4b/sky130_fd_sc_ms__and4b_1.pex.spice b/cells/and4b/sky130_fd_sc_ms__and4b_1.pex.spice index 0a4232b..34e962f 100644 --- a/cells/and4b/sky130_fd_sc_ms__and4b_1.pex.spice +++ b/cells/and4b/sky130_fd_sc_ms__and4b_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4b_1.pex.spice -* Created: Fri Aug 28 17:13:58 2020 +* Created: Wed Sep 2 11:58:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and4b/sky130_fd_sc_ms__and4b_1.pxi.spice b/cells/and4b/sky130_fd_sc_ms__and4b_1.pxi.spice index 56ff784..cad165d 100644 --- a/cells/and4b/sky130_fd_sc_ms__and4b_1.pxi.spice +++ b/cells/and4b/sky130_fd_sc_ms__and4b_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4b_1.pxi.spice -* Created: Fri Aug 28 17:13:58 2020 +* Created: Wed Sep 2 11:58:36 2020 * x_PM_SKY130_FD_SC_MS__AND4B_1%A_N N_A_N_M1004_g N_A_N_M1007_g N_A_N_c_86_n + N_A_N_c_91_n A_N N_A_N_c_87_n N_A_N_c_88_n PM_SKY130_FD_SC_MS__AND4B_1%A_N
diff --git a/cells/and4b/sky130_fd_sc_ms__and4b_1.spice b/cells/and4b/sky130_fd_sc_ms__and4b_1.spice index c81c202..d5b2f6b 100644 --- a/cells/and4b/sky130_fd_sc_ms__and4b_1.spice +++ b/cells/and4b/sky130_fd_sc_ms__and4b_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4b_1.spice -* Created: Fri Aug 28 17:13:58 2020 +* Created: Wed Sep 2 11:58:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and4b/sky130_fd_sc_ms__and4b_2.lvs.report b/cells/and4b/sky130_fd_sc_ms__and4b_2.lvs.report new file mode 100644 index 0000000..cfc4d3f --- /dev/null +++ b/cells/and4b/sky130_fd_sc_ms__and4b_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and4b_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and4b_2.sp ('sky130_fd_sc_ms__and4b_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and4b/sky130_fd_sc_ms__and4b_2.spice ('sky130_fd_sc_ms__and4b_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:58:39 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and4b_2 sky130_fd_sc_ms__and4b_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and4b_2 +SOURCE CELL NAME: sky130_fd_sc_ms__and4b_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 6 6 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 9 9 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 9 9 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N D C B VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and4b/sky130_fd_sc_ms__and4b_2.pex.spice b/cells/and4b/sky130_fd_sc_ms__and4b_2.pex.spice index ee6d275..484aac4 100644 --- a/cells/and4b/sky130_fd_sc_ms__and4b_2.pex.spice +++ b/cells/and4b/sky130_fd_sc_ms__and4b_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4b_2.pex.spice -* Created: Fri Aug 28 17:14:06 2020 +* Created: Wed Sep 2 11:58:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and4b/sky130_fd_sc_ms__and4b_2.pxi.spice b/cells/and4b/sky130_fd_sc_ms__and4b_2.pxi.spice index 35ab4b8..a3c00e5 100644 --- a/cells/and4b/sky130_fd_sc_ms__and4b_2.pxi.spice +++ b/cells/and4b/sky130_fd_sc_ms__and4b_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4b_2.pxi.spice -* Created: Fri Aug 28 17:14:06 2020 +* Created: Wed Sep 2 11:58:42 2020 * x_PM_SKY130_FD_SC_MS__AND4B_2%A_N N_A_N_M1005_g N_A_N_M1010_g A_N N_A_N_c_80_n + N_A_N_c_81_n PM_SKY130_FD_SC_MS__AND4B_2%A_N
diff --git a/cells/and4b/sky130_fd_sc_ms__and4b_2.spice b/cells/and4b/sky130_fd_sc_ms__and4b_2.spice index 130fcfa..319d8d0 100644 --- a/cells/and4b/sky130_fd_sc_ms__and4b_2.spice +++ b/cells/and4b/sky130_fd_sc_ms__and4b_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4b_2.spice -* Created: Fri Aug 28 17:14:06 2020 +* Created: Wed Sep 2 11:58:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and4b/sky130_fd_sc_ms__and4b_4.lvs.report b/cells/and4b/sky130_fd_sc_ms__and4b_4.lvs.report new file mode 100644 index 0000000..f7c4eb0 --- /dev/null +++ b/cells/and4b/sky130_fd_sc_ms__and4b_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and4b_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and4b_4.sp ('sky130_fd_sc_ms__and4b_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and4b/sky130_fd_sc_ms__and4b_4.spice ('sky130_fd_sc_ms__and4b_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:58:46 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and4b_4 sky130_fd_sc_ms__and4b_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and4b_4 +SOURCE CELL NAME: sky130_fd_sc_ms__and4b_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 13 13 MN (4 pins) + 13 13 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 27 26 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 6 6 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 9 9 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 9 9 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N D C B VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and4b/sky130_fd_sc_ms__and4b_4.pex.spice b/cells/and4b/sky130_fd_sc_ms__and4b_4.pex.spice index 72c4410..8ff8927 100644 --- a/cells/and4b/sky130_fd_sc_ms__and4b_4.pex.spice +++ b/cells/and4b/sky130_fd_sc_ms__and4b_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4b_4.pex.spice -* Created: Fri Aug 28 17:14:16 2020 +* Created: Wed Sep 2 11:58:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and4b/sky130_fd_sc_ms__and4b_4.pxi.spice b/cells/and4b/sky130_fd_sc_ms__and4b_4.pxi.spice index aeff0a8..90f956f 100644 --- a/cells/and4b/sky130_fd_sc_ms__and4b_4.pxi.spice +++ b/cells/and4b/sky130_fd_sc_ms__and4b_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4b_4.pxi.spice -* Created: Fri Aug 28 17:14:16 2020 +* Created: Wed Sep 2 11:58:49 2020 * x_PM_SKY130_FD_SC_MS__AND4B_4%A_N N_A_N_M1004_g N_A_N_M1011_g A_N N_A_N_c_145_n + N_A_N_c_146_n PM_SKY130_FD_SC_MS__AND4B_4%A_N
diff --git a/cells/and4b/sky130_fd_sc_ms__and4b_4.spice b/cells/and4b/sky130_fd_sc_ms__and4b_4.spice index 2208498..d16d19a 100644 --- a/cells/and4b/sky130_fd_sc_ms__and4b_4.spice +++ b/cells/and4b/sky130_fd_sc_ms__and4b_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4b_4.spice -* Created: Fri Aug 28 17:14:16 2020 +* Created: Wed Sep 2 11:58:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and4bb/sky130_fd_sc_ms__and4bb_1.lvs.report b/cells/and4bb/sky130_fd_sc_ms__and4bb_1.lvs.report new file mode 100644 index 0000000..29cecba --- /dev/null +++ b/cells/and4bb/sky130_fd_sc_ms__and4bb_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and4bb_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and4bb_1.sp ('sky130_fd_sc_ms__and4bb_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and4bb/sky130_fd_sc_ms__and4bb_1.spice ('sky130_fd_sc_ms__and4bb_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:58:52 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and4bb_1 sky130_fd_sc_ms__and4bb_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and4bb_1 +SOURCE CELL NAME: sky130_fd_sc_ms__and4bb_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 3 3 MN (4 pins) + 7 7 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 11 11 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 12 12 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 7 7 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 11 11 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N C D B_N VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and4bb/sky130_fd_sc_ms__and4bb_1.pex.spice b/cells/and4bb/sky130_fd_sc_ms__and4bb_1.pex.spice index b987ab1..2af68bd 100644 --- a/cells/and4bb/sky130_fd_sc_ms__and4bb_1.pex.spice +++ b/cells/and4bb/sky130_fd_sc_ms__and4bb_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4bb_1.pex.spice -* Created: Fri Aug 28 17:14:25 2020 +* Created: Wed Sep 2 11:58:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and4bb/sky130_fd_sc_ms__and4bb_1.pxi.spice b/cells/and4bb/sky130_fd_sc_ms__and4bb_1.pxi.spice index 0248be9..55a9360 100644 --- a/cells/and4bb/sky130_fd_sc_ms__and4bb_1.pxi.spice +++ b/cells/and4bb/sky130_fd_sc_ms__and4bb_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4bb_1.pxi.spice -* Created: Fri Aug 28 17:14:25 2020 +* Created: Wed Sep 2 11:58:55 2020 * x_PM_SKY130_FD_SC_MS__AND4BB_1%A_N N_A_N_M1002_g N_A_N_M1013_g A_N N_A_N_c_102_n + N_A_N_c_103_n PM_SKY130_FD_SC_MS__AND4BB_1%A_N
diff --git a/cells/and4bb/sky130_fd_sc_ms__and4bb_1.spice b/cells/and4bb/sky130_fd_sc_ms__and4bb_1.spice index 1fb2c5f..8616096 100644 --- a/cells/and4bb/sky130_fd_sc_ms__and4bb_1.spice +++ b/cells/and4bb/sky130_fd_sc_ms__and4bb_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4bb_1.spice -* Created: Fri Aug 28 17:14:25 2020 +* Created: Wed Sep 2 11:58:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and4bb/sky130_fd_sc_ms__and4bb_2.lvs.report b/cells/and4bb/sky130_fd_sc_ms__and4bb_2.lvs.report new file mode 100644 index 0000000..721c5d3 --- /dev/null +++ b/cells/and4bb/sky130_fd_sc_ms__and4bb_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and4bb_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and4bb_2.sp ('sky130_fd_sc_ms__and4bb_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and4bb/sky130_fd_sc_ms__and4bb_2.spice ('sky130_fd_sc_ms__and4bb_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:58:59 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and4bb_2 sky130_fd_sc_ms__and4bb_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and4bb_2 +SOURCE CELL NAME: sky130_fd_sc_ms__and4bb_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 15 15 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 3 3 MN (4 pins) + 7 7 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 11 11 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 12 12 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 7 7 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 11 11 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N C D B_N VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and4bb/sky130_fd_sc_ms__and4bb_2.pex.spice b/cells/and4bb/sky130_fd_sc_ms__and4bb_2.pex.spice index 4d7e489..db70675 100644 --- a/cells/and4bb/sky130_fd_sc_ms__and4bb_2.pex.spice +++ b/cells/and4bb/sky130_fd_sc_ms__and4bb_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4bb_2.pex.spice -* Created: Fri Aug 28 17:14:33 2020 +* Created: Wed Sep 2 11:59:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and4bb/sky130_fd_sc_ms__and4bb_2.pxi.spice b/cells/and4bb/sky130_fd_sc_ms__and4bb_2.pxi.spice index 16fe2de..a8eb762 100644 --- a/cells/and4bb/sky130_fd_sc_ms__and4bb_2.pxi.spice +++ b/cells/and4bb/sky130_fd_sc_ms__and4bb_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4bb_2.pxi.spice -* Created: Fri Aug 28 17:14:33 2020 +* Created: Wed Sep 2 11:59:02 2020 * x_PM_SKY130_FD_SC_MS__AND4BB_2%A_N N_A_N_M1014_g N_A_N_c_99_n N_A_N_M1015_g A_N + N_A_N_c_100_n PM_SKY130_FD_SC_MS__AND4BB_2%A_N
diff --git a/cells/and4bb/sky130_fd_sc_ms__and4bb_2.spice b/cells/and4bb/sky130_fd_sc_ms__and4bb_2.spice index c5d997d..1c41d63 100644 --- a/cells/and4bb/sky130_fd_sc_ms__and4bb_2.spice +++ b/cells/and4bb/sky130_fd_sc_ms__and4bb_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4bb_2.spice -* Created: Fri Aug 28 17:14:33 2020 +* Created: Wed Sep 2 11:59:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/and4bb/sky130_fd_sc_ms__and4bb_4.lvs.report b/cells/and4bb/sky130_fd_sc_ms__and4bb_4.lvs.report new file mode 100644 index 0000000..272cf7c --- /dev/null +++ b/cells/and4bb/sky130_fd_sc_ms__and4bb_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__and4bb_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__and4bb_4.sp ('sky130_fd_sc_ms__and4bb_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/and4bb/sky130_fd_sc_ms__and4bb_4.spice ('sky130_fd_sc_ms__and4bb_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:59:05 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__and4bb_4 sky130_fd_sc_ms__and4bb_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__and4bb_4 +SOURCE CELL NAME: sky130_fd_sc_ms__and4bb_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 3 3 MN (4 pins) + 7 7 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 11 11 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 12 12 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 7 7 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 11 11 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B_N A_N C D VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/and4bb/sky130_fd_sc_ms__and4bb_4.pex.spice b/cells/and4bb/sky130_fd_sc_ms__and4bb_4.pex.spice index 138025e..0f2e948 100644 --- a/cells/and4bb/sky130_fd_sc_ms__and4bb_4.pex.spice +++ b/cells/and4bb/sky130_fd_sc_ms__and4bb_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4bb_4.pex.spice -* Created: Fri Aug 28 17:15:03 2020 +* Created: Wed Sep 2 11:59:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/and4bb/sky130_fd_sc_ms__and4bb_4.pxi.spice b/cells/and4bb/sky130_fd_sc_ms__and4bb_4.pxi.spice index d5116a6..6564d83 100644 --- a/cells/and4bb/sky130_fd_sc_ms__and4bb_4.pxi.spice +++ b/cells/and4bb/sky130_fd_sc_ms__and4bb_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4bb_4.pxi.spice -* Created: Fri Aug 28 17:15:03 2020 +* Created: Wed Sep 2 11:59:08 2020 * x_PM_SKY130_FD_SC_MS__AND4BB_4%B_N N_B_N_c_154_n N_B_N_M1003_g N_B_N_M1023_g B_N + B_N PM_SKY130_FD_SC_MS__AND4BB_4%B_N
diff --git a/cells/and4bb/sky130_fd_sc_ms__and4bb_4.spice b/cells/and4bb/sky130_fd_sc_ms__and4bb_4.spice index 47f07ad..185afc7 100644 --- a/cells/and4bb/sky130_fd_sc_ms__and4bb_4.spice +++ b/cells/and4bb/sky130_fd_sc_ms__and4bb_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__and4bb_4.spice -* Created: Fri Aug 28 17:15:03 2020 +* Created: Wed Sep 2 11:59:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/buf/sky130_fd_sc_ms__buf_1.lvs.report b/cells/buf/sky130_fd_sc_ms__buf_1.lvs.report new file mode 100644 index 0000000..4233f92 --- /dev/null +++ b/cells/buf/sky130_fd_sc_ms__buf_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__buf_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__buf_1.sp ('sky130_fd_sc_ms__buf_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/buf/sky130_fd_sc_ms__buf_1.spice ('sky130_fd_sc_ms__buf_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:59:18 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__buf_1 sky130_fd_sc_ms__buf_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__buf_1 +SOURCE CELL NAME: sky130_fd_sc_ms__buf_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 5 4 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_ms__buf_1.pex.spice b/cells/buf/sky130_fd_sc_ms__buf_1.pex.spice index b585e09..cc30d6e 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_1.pex.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_1.pex.spice -* Created: Fri Aug 28 17:15:21 2020 +* Created: Wed Sep 2 11:59:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_ms__buf_1.pxi.spice b/cells/buf/sky130_fd_sc_ms__buf_1.pxi.spice index 0c3a0d4..df759e8 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_1.pxi.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_1.pxi.spice -* Created: Fri Aug 28 17:15:21 2020 +* Created: Wed Sep 2 11:59:21 2020 * x_PM_SKY130_FD_SC_MS__BUF_1%A N_A_M1002_g N_A_M1001_g N_A_c_39_n N_A_c_40_n A A + PM_SKY130_FD_SC_MS__BUF_1%A
diff --git a/cells/buf/sky130_fd_sc_ms__buf_1.spice b/cells/buf/sky130_fd_sc_ms__buf_1.spice index 5808242..7b62dc8 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_1.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_1.spice -* Created: Fri Aug 28 17:15:21 2020 +* Created: Wed Sep 2 11:59:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/buf/sky130_fd_sc_ms__buf_16.lvs.report b/cells/buf/sky130_fd_sc_ms__buf_16.lvs.report new file mode 100644 index 0000000..386e3f8 --- /dev/null +++ b/cells/buf/sky130_fd_sc_ms__buf_16.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__buf_16.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__buf_16.sp ('sky130_fd_sc_ms__buf_16') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/buf/sky130_fd_sc_ms__buf_16.spice ('sky130_fd_sc_ms__buf_16') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:59:12 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__buf_16 sky130_fd_sc_ms__buf_16 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__buf_16 +SOURCE CELL NAME: sky130_fd_sc_ms__buf_16 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 22 22 MN (4 pins) + 22 22 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 45 44 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 44 layout mos transistors were reduced to 4. + 40 mos transistors were deleted by parallel reduction. + 44 source mos transistors were reduced to 4. + 40 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_ms__buf_16.pex.spice b/cells/buf/sky130_fd_sc_ms__buf_16.pex.spice index 7b1ca45..292db7d 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_16.pex.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_16.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_16.pex.spice -* Created: Fri Aug 28 17:15:12 2020 +* Created: Wed Sep 2 11:59:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_ms__buf_16.pxi.spice b/cells/buf/sky130_fd_sc_ms__buf_16.pxi.spice index 2f6adef..3f0ecee 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_16.pxi.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_16.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_16.pxi.spice -* Created: Fri Aug 28 17:15:12 2020 +* Created: Wed Sep 2 11:59:15 2020 * x_PM_SKY130_FD_SC_MS__BUF_16%A_83_260# N_A_83_260#_M1000_d N_A_83_260#_M1008_d + N_A_83_260#_M1015_d N_A_83_260#_M1022_d N_A_83_260#_M1027_d
diff --git a/cells/buf/sky130_fd_sc_ms__buf_16.spice b/cells/buf/sky130_fd_sc_ms__buf_16.spice index 00599cd..e8bbe4c 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_16.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_16.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_16.spice -* Created: Fri Aug 28 17:15:12 2020 +* Created: Wed Sep 2 11:59:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/buf/sky130_fd_sc_ms__buf_2.lvs.report b/cells/buf/sky130_fd_sc_ms__buf_2.lvs.report new file mode 100644 index 0000000..facc68a --- /dev/null +++ b/cells/buf/sky130_fd_sc_ms__buf_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__buf_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__buf_2.sp ('sky130_fd_sc_ms__buf_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/buf/sky130_fd_sc_ms__buf_2.spice ('sky130_fd_sc_ms__buf_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:59:25 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__buf_2 sky130_fd_sc_ms__buf_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__buf_2 +SOURCE CELL NAME: sky130_fd_sc_ms__buf_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_ms__buf_2.pex.spice b/cells/buf/sky130_fd_sc_ms__buf_2.pex.spice index 8f073cb..05bc017 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_2.pex.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_2.pex.spice -* Created: Fri Aug 28 17:15:30 2020 +* Created: Wed Sep 2 11:59:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_ms__buf_2.pxi.spice b/cells/buf/sky130_fd_sc_ms__buf_2.pxi.spice index 702b878..e6ca6fb 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_2.pxi.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_2.pxi.spice -* Created: Fri Aug 28 17:15:30 2020 +* Created: Wed Sep 2 11:59:28 2020 * x_PM_SKY130_FD_SC_MS__BUF_2%A_21_260# N_A_21_260#_M1003_d N_A_21_260#_M1004_d + N_A_21_260#_M1000_g N_A_21_260#_M1002_g N_A_21_260#_M1001_g
diff --git a/cells/buf/sky130_fd_sc_ms__buf_2.spice b/cells/buf/sky130_fd_sc_ms__buf_2.spice index 427f28a..a473c8d 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_2.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_2.spice -* Created: Fri Aug 28 17:15:30 2020 +* Created: Wed Sep 2 11:59:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/buf/sky130_fd_sc_ms__buf_4.lvs.report b/cells/buf/sky130_fd_sc_ms__buf_4.lvs.report new file mode 100644 index 0000000..c5eae0d --- /dev/null +++ b/cells/buf/sky130_fd_sc_ms__buf_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__buf_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__buf_4.sp ('sky130_fd_sc_ms__buf_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/buf/sky130_fd_sc_ms__buf_4.spice ('sky130_fd_sc_ms__buf_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:59:31 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__buf_4 sky130_fd_sc_ms__buf_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__buf_4 +SOURCE CELL NAME: sky130_fd_sc_ms__buf_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 5 5 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 12 11 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 10 layout mos transistors were reduced to 3. + 7 mos transistors were deleted by parallel reduction. + 10 source mos transistors were reduced to 3. + 7 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_ms__buf_4.pex.spice b/cells/buf/sky130_fd_sc_ms__buf_4.pex.spice index 5e77529..e6f745c 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_4.pex.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_4.pex.spice -* Created: Fri Aug 28 17:15:38 2020 +* Created: Wed Sep 2 11:59:35 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_ms__buf_4.pxi.spice b/cells/buf/sky130_fd_sc_ms__buf_4.pxi.spice index b585adf..296566b 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_4.pxi.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_4.pxi.spice -* Created: Fri Aug 28 17:15:38 2020 +* Created: Wed Sep 2 11:59:35 2020 * x_PM_SKY130_FD_SC_MS__BUF_4%A_86_260# N_A_86_260#_M1007_d N_A_86_260#_M1001_d + N_A_86_260#_M1005_g N_A_86_260#_M1000_g N_A_86_260#_M1006_g
diff --git a/cells/buf/sky130_fd_sc_ms__buf_4.spice b/cells/buf/sky130_fd_sc_ms__buf_4.spice index 4246acc..4c64811 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_4.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_4.spice -* Created: Fri Aug 28 17:15:38 2020 +* Created: Wed Sep 2 11:59:35 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/buf/sky130_fd_sc_ms__buf_8.lvs.report b/cells/buf/sky130_fd_sc_ms__buf_8.lvs.report new file mode 100644 index 0000000..1f1b38f --- /dev/null +++ b/cells/buf/sky130_fd_sc_ms__buf_8.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__buf_8.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__buf_8.sp ('sky130_fd_sc_ms__buf_8') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/buf/sky130_fd_sc_ms__buf_8.spice ('sky130_fd_sc_ms__buf_8') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:59:38 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__buf_8 sky130_fd_sc_ms__buf_8 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__buf_8 +SOURCE CELL NAME: sky130_fd_sc_ms__buf_8 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 22 layout mos transistors were reduced to 4. + 18 mos transistors were deleted by parallel reduction. + 22 source mos transistors were reduced to 4. + 18 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_ms__buf_8.pex.spice b/cells/buf/sky130_fd_sc_ms__buf_8.pex.spice index 5779d6c..0abfe81 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_8.pex.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_8.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_8.pex.spice -* Created: Fri Aug 28 17:16:08 2020 +* Created: Wed Sep 2 11:59:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_ms__buf_8.pxi.spice b/cells/buf/sky130_fd_sc_ms__buf_8.pxi.spice index 493d9d4..7ae62b1 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_8.pxi.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_8.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_8.pxi.spice -* Created: Fri Aug 28 17:16:08 2020 +* Created: Wed Sep 2 11:59:41 2020 * x_PM_SKY130_FD_SC_MS__BUF_8%A N_A_M1006_g N_A_M1001_g N_A_M1002_g N_A_M1015_g + N_A_M1003_g N_A_M1018_g A A A N_A_c_113_n N_A_c_114_n
diff --git a/cells/buf/sky130_fd_sc_ms__buf_8.spice b/cells/buf/sky130_fd_sc_ms__buf_8.spice index 44e171f..fa230c4 100644 --- a/cells/buf/sky130_fd_sc_ms__buf_8.spice +++ b/cells/buf/sky130_fd_sc_ms__buf_8.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__buf_8.spice -* Created: Fri Aug 28 17:16:08 2020 +* Created: Wed Sep 2 11:59:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.lvs.report b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.lvs.report new file mode 100644 index 0000000..f8d07a6 --- /dev/null +++ b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__bufbuf_16.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__bufbuf_16.sp ('sky130_fd_sc_ms__bufbuf_16') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.spice ('sky130_fd_sc_ms__bufbuf_16') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:59:45 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__bufbuf_16 sky130_fd_sc_ms__bufbuf_16 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__bufbuf_16 +SOURCE CELL NAME: sky130_fd_sc_ms__bufbuf_16 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 9 9 + + Instances: 26 26 MN (4 pins) + 26 26 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 53 52 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 50 layout mos transistors were reduced to 6. + 44 mos transistors were deleted by parallel reduction. + 50 source mos transistors were reduced to 6. + 44 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.pex.spice b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.pex.spice index d3637fb..c1587f5 100644 --- a/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.pex.spice +++ b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__bufbuf_16.pex.spice -* Created: Fri Aug 28 17:16:17 2020 +* Created: Wed Sep 2 11:59:48 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.pxi.spice b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.pxi.spice index a04a224..2248d73 100644 --- a/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.pxi.spice +++ b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__bufbuf_16.pxi.spice -* Created: Fri Aug 28 17:16:17 2020 +* Created: Wed Sep 2 11:59:48 2020 * x_PM_SKY130_FD_SC_MS__BUFBUF_16%A N_A_M1011_g N_A_M1050_g A N_A_c_260_n + N_A_c_261_n PM_SKY130_FD_SC_MS__BUFBUF_16%A
diff --git a/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.spice b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.spice index b01f28a..a553e45 100644 --- a/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.spice +++ b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__bufbuf_16.spice -* Created: Fri Aug 28 17:16:17 2020 +* Created: Wed Sep 2 11:59:48 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.lvs.report b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.lvs.report new file mode 100644 index 0000000..8aa9cb2 --- /dev/null +++ b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__bufbuf_8.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__bufbuf_8.sp ('sky130_fd_sc_ms__bufbuf_8') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.spice ('sky130_fd_sc_ms__bufbuf_8') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:59:52 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__bufbuf_8 sky130_fd_sc_ms__bufbuf_8 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__bufbuf_8 +SOURCE CELL NAME: sky130_fd_sc_ms__bufbuf_8 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 9 9 + + Instances: 13 13 MN (4 pins) + 13 13 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 27 26 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 22 layout mos transistors were reduced to 4. + 18 mos transistors were deleted by parallel reduction. + 22 source mos transistors were reduced to 4. + 18 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.pex.spice b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.pex.spice index 0adac67..4ebe1aa 100644 --- a/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.pex.spice +++ b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__bufbuf_8.pex.spice -* Created: Fri Aug 28 17:16:26 2020 +* Created: Wed Sep 2 11:59:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.pxi.spice b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.pxi.spice index 182f6c0..8244514 100644 --- a/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.pxi.spice +++ b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__bufbuf_8.pxi.spice -* Created: Fri Aug 28 17:16:26 2020 +* Created: Wed Sep 2 11:59:55 2020 * x_PM_SKY130_FD_SC_MS__BUFBUF_8%A N_A_c_135_n N_A_M1011_g N_A_M1016_g A + N_A_c_137_n PM_SKY130_FD_SC_MS__BUFBUF_8%A
diff --git a/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.spice b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.spice index d4fd943..4a1ce91 100644 --- a/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.spice +++ b/cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__bufbuf_8.spice -* Created: Fri Aug 28 17:16:26 2020 +* Created: Wed Sep 2 11:59:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/bufinv/sky130_fd_sc_ms__bufinv_16.lvs.report b/cells/bufinv/sky130_fd_sc_ms__bufinv_16.lvs.report new file mode 100644 index 0000000..ba6978e --- /dev/null +++ b/cells/bufinv/sky130_fd_sc_ms__bufinv_16.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__bufinv_16.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__bufinv_16.sp ('sky130_fd_sc_ms__bufinv_16') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/bufinv/sky130_fd_sc_ms__bufinv_16.spice ('sky130_fd_sc_ms__bufinv_16') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 11:59:59 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__bufinv_16 sky130_fd_sc_ms__bufinv_16 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__bufinv_16 +SOURCE CELL NAME: sky130_fd_sc_ms__bufinv_16 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 8 8 + + Instances: 25 25 MN (4 pins) + 25 25 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 51 50 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 50 layout mos transistors were reduced to 6. + 44 mos transistors were deleted by parallel reduction. + 50 source mos transistors were reduced to 6. + 44 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/bufinv/sky130_fd_sc_ms__bufinv_16.pex.spice b/cells/bufinv/sky130_fd_sc_ms__bufinv_16.pex.spice index 6908155..21575f2 100644 --- a/cells/bufinv/sky130_fd_sc_ms__bufinv_16.pex.spice +++ b/cells/bufinv/sky130_fd_sc_ms__bufinv_16.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__bufinv_16.pex.spice -* Created: Fri Aug 28 17:16:35 2020 +* Created: Wed Sep 2 12:00:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/bufinv/sky130_fd_sc_ms__bufinv_16.pxi.spice b/cells/bufinv/sky130_fd_sc_ms__bufinv_16.pxi.spice index 1320763..c1f6a23 100644 --- a/cells/bufinv/sky130_fd_sc_ms__bufinv_16.pxi.spice +++ b/cells/bufinv/sky130_fd_sc_ms__bufinv_16.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__bufinv_16.pxi.spice -* Created: Fri Aug 28 17:16:35 2020 +* Created: Wed Sep 2 12:00:01 2020 * x_PM_SKY130_FD_SC_MS__BUFINV_16%A N_A_M1000_g N_A_M1001_g N_A_M1002_g + N_A_M1035_g N_A_M1005_g N_A_M1047_g A A A N_A_c_234_n N_A_c_235_n
diff --git a/cells/bufinv/sky130_fd_sc_ms__bufinv_16.spice b/cells/bufinv/sky130_fd_sc_ms__bufinv_16.spice index a3f0b8a..32d5dc7 100644 --- a/cells/bufinv/sky130_fd_sc_ms__bufinv_16.spice +++ b/cells/bufinv/sky130_fd_sc_ms__bufinv_16.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__bufinv_16.spice -* Created: Fri Aug 28 17:16:35 2020 +* Created: Wed Sep 2 12:00:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/bufinv/sky130_fd_sc_ms__bufinv_8.lvs.report b/cells/bufinv/sky130_fd_sc_ms__bufinv_8.lvs.report new file mode 100644 index 0000000..d0c3953 --- /dev/null +++ b/cells/bufinv/sky130_fd_sc_ms__bufinv_8.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__bufinv_8.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__bufinv_8.sp ('sky130_fd_sc_ms__bufinv_8') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/bufinv/sky130_fd_sc_ms__bufinv_8.spice ('sky130_fd_sc_ms__bufinv_8') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:00:05 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__bufinv_8 sky130_fd_sc_ms__bufinv_8 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__bufinv_8 +SOURCE CELL NAME: sky130_fd_sc_ms__bufinv_8 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 8 8 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 22 layout mos transistors were reduced to 4. + 18 mos transistors were deleted by parallel reduction. + 22 source mos transistors were reduced to 4. + 18 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/bufinv/sky130_fd_sc_ms__bufinv_8.pex.spice b/cells/bufinv/sky130_fd_sc_ms__bufinv_8.pex.spice index 47965aa..9e9cd6b 100644 --- a/cells/bufinv/sky130_fd_sc_ms__bufinv_8.pex.spice +++ b/cells/bufinv/sky130_fd_sc_ms__bufinv_8.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__bufinv_8.pex.spice -* Created: Fri Aug 28 17:16:44 2020 +* Created: Wed Sep 2 12:00:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/bufinv/sky130_fd_sc_ms__bufinv_8.pxi.spice b/cells/bufinv/sky130_fd_sc_ms__bufinv_8.pxi.spice index c0c486b..952c485 100644 --- a/cells/bufinv/sky130_fd_sc_ms__bufinv_8.pxi.spice +++ b/cells/bufinv/sky130_fd_sc_ms__bufinv_8.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__bufinv_8.pxi.spice -* Created: Fri Aug 28 17:16:44 2020 +* Created: Wed Sep 2 12:00:08 2020 * x_PM_SKY130_FD_SC_MS__BUFINV_8%A N_A_M1007_g N_A_M1023_g A N_A_c_117_n + N_A_c_118_n PM_SKY130_FD_SC_MS__BUFINV_8%A
diff --git a/cells/bufinv/sky130_fd_sc_ms__bufinv_8.spice b/cells/bufinv/sky130_fd_sc_ms__bufinv_8.spice index 23e5d23..c583e0e 100644 --- a/cells/bufinv/sky130_fd_sc_ms__bufinv_8.spice +++ b/cells/bufinv/sky130_fd_sc_ms__bufinv_8.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__bufinv_8.spice -* Created: Fri Aug 28 17:16:44 2020 +* Created: Wed Sep 2 12:00:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.lvs.report b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.lvs.report new file mode 100644 index 0000000..0c7d185 --- /dev/null +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkbuf_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkbuf_1.sp ('sky130_fd_sc_ms__clkbuf_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.spice ('sky130_fd_sc_ms__clkbuf_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:00:19 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkbuf_1 sky130_fd_sc_ms__clkbuf_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkbuf_1 +SOURCE CELL NAME: sky130_fd_sc_ms__clkbuf_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 5 4 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.pex.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.pex.spice index fbcadcf..8f3157c 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.pex.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_1.pex.spice -* Created: Fri Aug 28 17:17:23 2020 +* Created: Wed Sep 2 12:00:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.pxi.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.pxi.spice index 3b80f84..1747986 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.pxi.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_1.pxi.spice -* Created: Fri Aug 28 17:17:23 2020 +* Created: Wed Sep 2 12:00:22 2020 * x_PM_SKY130_FD_SC_MS__CLKBUF_1%A N_A_M1003_g N_A_M1001_g A A N_A_c_41_n + PM_SKY130_FD_SC_MS__CLKBUF_1%A
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.spice index 6212b4a..1077857 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_1.spice -* Created: Fri Aug 28 17:17:23 2020 +* Created: Wed Sep 2 12:00:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.lvs.report b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.lvs.report new file mode 100644 index 0000000..bdd3cd2 --- /dev/null +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkbuf_16.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkbuf_16.sp ('sky130_fd_sc_ms__clkbuf_16') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.spice ('sky130_fd_sc_ms__clkbuf_16') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:00:12 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkbuf_16 sky130_fd_sc_ms__clkbuf_16 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkbuf_16 +SOURCE CELL NAME: sky130_fd_sc_ms__clkbuf_16 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 40 layout mos transistors were reduced to 4. + 36 mos transistors were deleted by parallel reduction. + 40 source mos transistors were reduced to 4. + 36 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.pex.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.pex.spice index c53967b..4bfca62 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.pex.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_16.pex.spice -* Created: Fri Aug 28 17:17:14 2020 +* Created: Wed Sep 2 12:00:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.pxi.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.pxi.spice index c377da6..dc8224b 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.pxi.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_16.pxi.spice -* Created: Fri Aug 28 17:17:14 2020 +* Created: Wed Sep 2 12:00:15 2020 * x_PM_SKY130_FD_SC_MS__CLKBUF_16%A N_A_M1000_g N_A_M1003_g N_A_M1024_g + N_A_M1004_g N_A_M1032_g N_A_M1006_g N_A_M1033_g N_A_M1007_g A A A A
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.spice index e9e4a2c..8a10027 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_16.spice -* Created: Fri Aug 28 17:17:14 2020 +* Created: Wed Sep 2 12:00:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.lvs.report b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.lvs.report new file mode 100644 index 0000000..7f7b42d --- /dev/null +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkbuf_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkbuf_2.sp ('sky130_fd_sc_ms__clkbuf_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.spice ('sky130_fd_sc_ms__clkbuf_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:00:25 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkbuf_2 sky130_fd_sc_ms__clkbuf_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkbuf_2 +SOURCE CELL NAME: sky130_fd_sc_ms__clkbuf_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.pex.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.pex.spice index ec166fc..7a0989f 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.pex.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_2.pex.spice -* Created: Fri Aug 28 17:17:32 2020 +* Created: Wed Sep 2 12:00:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.pxi.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.pxi.spice index de20c39..76e9f23 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.pxi.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_2.pxi.spice -* Created: Fri Aug 28 17:17:32 2020 +* Created: Wed Sep 2 12:00:28 2020 * x_PM_SKY130_FD_SC_MS__CLKBUF_2%A_43_192# N_A_43_192#_M1002_d N_A_43_192#_M1003_d + N_A_43_192#_M1000_g N_A_43_192#_M1004_g N_A_43_192#_M1005_g
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.spice index 1f8e46d..35d6f7b 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_2.spice -* Created: Fri Aug 28 17:17:32 2020 +* Created: Wed Sep 2 12:00:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.lvs.report b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.lvs.report new file mode 100644 index 0000000..aa7ce7c --- /dev/null +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkbuf_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkbuf_4.sp ('sky130_fd_sc_ms__clkbuf_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.spice ('sky130_fd_sc_ms__clkbuf_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:00:31 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkbuf_4 sky130_fd_sc_ms__clkbuf_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkbuf_4 +SOURCE CELL NAME: sky130_fd_sc_ms__clkbuf_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 2. + 6 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 2. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.pex.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.pex.spice index c12c075..8d13b4c 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.pex.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_4.pex.spice -* Created: Fri Aug 28 17:17:40 2020 +* Created: Wed Sep 2 12:00:34 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.pxi.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.pxi.spice index 65d2125..1e8c22a 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.pxi.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_4.pxi.spice -* Created: Fri Aug 28 17:17:40 2020 +* Created: Wed Sep 2 12:00:34 2020 * x_PM_SKY130_FD_SC_MS__CLKBUF_4%A_83_270# N_A_83_270#_M1004_d N_A_83_270#_M1005_d + N_A_83_270#_M1001_g N_A_83_270#_M1000_g N_A_83_270#_M1007_g
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.spice index 89b629e..78ab420 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_4.spice -* Created: Fri Aug 28 17:17:40 2020 +* Created: Wed Sep 2 12:00:34 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.lvs.report b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.lvs.report new file mode 100644 index 0000000..8ec4f74 --- /dev/null +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkbuf_8.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkbuf_8.sp ('sky130_fd_sc_ms__clkbuf_8') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.spice ('sky130_fd_sc_ms__clkbuf_8') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:00:38 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkbuf_8 sky130_fd_sc_ms__clkbuf_8 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkbuf_8 +SOURCE CELL NAME: sky130_fd_sc_ms__clkbuf_8 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 4. + 16 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 4. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.pex.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.pex.spice index 1509780..8a8c12e 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.pex.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_8.pex.spice -* Created: Fri Aug 28 17:17:49 2020 +* Created: Wed Sep 2 12:00:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.pxi.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.pxi.spice index 1811cba..f270532 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.pxi.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_8.pxi.spice -* Created: Fri Aug 28 17:17:49 2020 +* Created: Wed Sep 2 12:00:41 2020 * x_PM_SKY130_FD_SC_MS__CLKBUF_8%A N_A_M1004_g N_A_M1012_g N_A_M1016_g N_A_M1015_g + A A N_A_c_106_n N_A_c_107_n PM_SKY130_FD_SC_MS__CLKBUF_8%A
diff --git a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.spice b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.spice index 5c29dcf..41228e5 100644 --- a/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.spice +++ b/cells/clkbuf/sky130_fd_sc_ms__clkbuf_8.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkbuf_8.spice -* Created: Fri Aug 28 17:17:49 2020 +* Created: Wed Sep 2 12:00:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.lvs.report b/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.lvs.report new file mode 100644 index 0000000..6b82f31 --- /dev/null +++ b/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkdlyinv3sd1_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkdlyinv3sd1_1.sp ('sky130_fd_sc_ms__clkdlyinv3sd1_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.spice ('sky130_fd_sc_ms__clkdlyinv3sd1_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:00:44 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkdlyinv3sd1_1 sky130_fd_sc_ms__clkdlyinv3sd1_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkdlyinv3sd1_1 +SOURCE CELL NAME: sky130_fd_sc_ms__clkdlyinv3sd1_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.pex.spice b/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.pex.spice index 8bbbd26..1e6d305 100644 --- a/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.pex.spice +++ b/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv3sd1_1.pex.spice -* Created: Fri Aug 28 17:18:19 2020 +* Created: Wed Sep 2 12:00:47 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.pxi.spice b/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.pxi.spice index f704f4f..3937b82 100644 --- a/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.pxi.spice +++ b/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv3sd1_1.pxi.spice -* Created: Fri Aug 28 17:18:19 2020 +* Created: Wed Sep 2 12:00:47 2020 * x_PM_SKY130_FD_SC_MS__CLKDLYINV3SD1_1%A N_A_M1003_g N_A_M1002_g A A N_A_c_53_n + PM_SKY130_FD_SC_MS__CLKDLYINV3SD1_1%A
diff --git a/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.spice b/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.spice index e44c368..bd36ab6 100644 --- a/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.spice +++ b/cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv3sd1_1.spice -* Created: Fri Aug 28 17:18:19 2020 +* Created: Wed Sep 2 12:00:47 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.lvs.report b/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.lvs.report new file mode 100644 index 0000000..156ea85 --- /dev/null +++ b/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkdlyinv3sd2_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkdlyinv3sd2_1.sp ('sky130_fd_sc_ms__clkdlyinv3sd2_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.spice ('sky130_fd_sc_ms__clkdlyinv3sd2_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:00:51 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkdlyinv3sd2_1 sky130_fd_sc_ms__clkdlyinv3sd2_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkdlyinv3sd2_1 +SOURCE CELL NAME: sky130_fd_sc_ms__clkdlyinv3sd2_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.pex.spice b/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.pex.spice index 63fbc1e..03a0279 100644 --- a/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.pex.spice +++ b/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv3sd2_1.pex.spice -* Created: Fri Aug 28 17:18:28 2020 +* Created: Wed Sep 2 12:00:54 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.pxi.spice b/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.pxi.spice index b057e32..b4247bd 100644 --- a/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.pxi.spice +++ b/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv3sd2_1.pxi.spice -* Created: Fri Aug 28 17:18:28 2020 +* Created: Wed Sep 2 12:00:54 2020 * x_PM_SKY130_FD_SC_MS__CLKDLYINV3SD2_1%A N_A_M1003_g N_A_M1002_g A A N_A_c_53_n + PM_SKY130_FD_SC_MS__CLKDLYINV3SD2_1%A
diff --git a/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.spice b/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.spice index 4a23495..9567b5c 100644 --- a/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.spice +++ b/cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv3sd2_1.spice -* Created: Fri Aug 28 17:18:28 2020 +* Created: Wed Sep 2 12:00:54 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.lvs.report b/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.lvs.report new file mode 100644 index 0000000..73eddda --- /dev/null +++ b/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkdlyinv3sd3_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkdlyinv3sd3_1.sp ('sky130_fd_sc_ms__clkdlyinv3sd3_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.spice ('sky130_fd_sc_ms__clkdlyinv3sd3_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:00:57 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkdlyinv3sd3_1 sky130_fd_sc_ms__clkdlyinv3sd3_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkdlyinv3sd3_1 +SOURCE CELL NAME: sky130_fd_sc_ms__clkdlyinv3sd3_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.pex.spice b/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.pex.spice index a0ab2a9..d9a3e3b 100644 --- a/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.pex.spice +++ b/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv3sd3_1.pex.spice -* Created: Fri Aug 28 17:18:38 2020 +* Created: Wed Sep 2 12:01:00 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.pxi.spice b/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.pxi.spice index d2e95f6..66ded51 100644 --- a/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.pxi.spice +++ b/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv3sd3_1.pxi.spice -* Created: Fri Aug 28 17:18:38 2020 +* Created: Wed Sep 2 12:01:00 2020 * x_PM_SKY130_FD_SC_MS__CLKDLYINV3SD3_1%A N_A_M1004_g N_A_M1003_g A A N_A_c_52_n + PM_SKY130_FD_SC_MS__CLKDLYINV3SD3_1%A
diff --git a/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.spice b/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.spice index 6c7884a..6f06acf 100644 --- a/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.spice +++ b/cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv3sd3_1.spice -* Created: Fri Aug 28 17:18:38 2020 +* Created: Wed Sep 2 12:01:00 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.lvs.report b/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.lvs.report new file mode 100644 index 0000000..1efc347 --- /dev/null +++ b/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkdlyinv5sd1_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkdlyinv5sd1_1.sp ('sky130_fd_sc_ms__clkdlyinv5sd1_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.spice ('sky130_fd_sc_ms__clkdlyinv5sd1_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:01:04 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkdlyinv5sd1_1 sky130_fd_sc_ms__clkdlyinv5sd1_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkdlyinv5sd1_1 +SOURCE CELL NAME: sky130_fd_sc_ms__clkdlyinv5sd1_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + ------ ------ + Total Inst: 10 10 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 10 10 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 10 10 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.pex.spice b/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.pex.spice index 1002c6b..a91fcd2 100644 --- a/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.pex.spice +++ b/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv5sd1_1.pex.spice -* Created: Fri Aug 28 17:18:47 2020 +* Created: Wed Sep 2 12:01:07 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.pxi.spice b/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.pxi.spice index 855f291..457d3dd 100644 --- a/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.pxi.spice +++ b/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv5sd1_1.pxi.spice -* Created: Fri Aug 28 17:18:47 2020 +* Created: Wed Sep 2 12:01:07 2020 * x_PM_SKY130_FD_SC_MS__CLKDLYINV5SD1_1%A N_A_M1007_g N_A_M1006_g A A N_A_c_83_n + PM_SKY130_FD_SC_MS__CLKDLYINV5SD1_1%A
diff --git a/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.spice b/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.spice index 444f2df..a09e93c 100644 --- a/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.spice +++ b/cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv5sd1_1.spice -* Created: Fri Aug 28 17:18:47 2020 +* Created: Wed Sep 2 12:01:07 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.lvs.report b/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.lvs.report new file mode 100644 index 0000000..1ef67c6 --- /dev/null +++ b/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkdlyinv5sd2_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkdlyinv5sd2_1.sp ('sky130_fd_sc_ms__clkdlyinv5sd2_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.spice ('sky130_fd_sc_ms__clkdlyinv5sd2_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:01:10 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkdlyinv5sd2_1 sky130_fd_sc_ms__clkdlyinv5sd2_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkdlyinv5sd2_1 +SOURCE CELL NAME: sky130_fd_sc_ms__clkdlyinv5sd2_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + ------ ------ + Total Inst: 10 10 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 10 10 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 10 10 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.pex.spice b/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.pex.spice index 209fc12..2642406 100644 --- a/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.pex.spice +++ b/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv5sd2_1.pex.spice -* Created: Fri Aug 28 17:18:56 2020 +* Created: Wed Sep 2 12:01:13 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.pxi.spice b/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.pxi.spice index 6fb2c6c..2883ee4 100644 --- a/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.pxi.spice +++ b/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv5sd2_1.pxi.spice -* Created: Fri Aug 28 17:18:56 2020 +* Created: Wed Sep 2 12:01:13 2020 * x_PM_SKY130_FD_SC_MS__CLKDLYINV5SD2_1%A N_A_M1007_g N_A_M1006_g A A N_A_c_80_n + PM_SKY130_FD_SC_MS__CLKDLYINV5SD2_1%A
diff --git a/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.spice b/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.spice index c342522..0529eb2 100644 --- a/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.spice +++ b/cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv5sd2_1.spice -* Created: Fri Aug 28 17:18:56 2020 +* Created: Wed Sep 2 12:01:13 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.lvs.report b/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.lvs.report new file mode 100644 index 0000000..f0d2c4d --- /dev/null +++ b/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkdlyinv5sd3_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkdlyinv5sd3_1.sp ('sky130_fd_sc_ms__clkdlyinv5sd3_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.spice ('sky130_fd_sc_ms__clkdlyinv5sd3_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:01:17 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkdlyinv5sd3_1 sky130_fd_sc_ms__clkdlyinv5sd3_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkdlyinv5sd3_1 +SOURCE CELL NAME: sky130_fd_sc_ms__clkdlyinv5sd3_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + ------ ------ + Total Inst: 10 10 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 10 10 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 10 10 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.pex.spice b/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.pex.spice index d95d81e..06e78a3 100644 --- a/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.pex.spice +++ b/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv5sd3_1.pex.spice -* Created: Fri Aug 28 17:19:28 2020 +* Created: Wed Sep 2 12:01:20 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.pxi.spice b/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.pxi.spice index 3ad5652..d7b9c5d 100644 --- a/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.pxi.spice +++ b/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv5sd3_1.pxi.spice -* Created: Fri Aug 28 17:19:28 2020 +* Created: Wed Sep 2 12:01:20 2020 * x_PM_SKY130_FD_SC_MS__CLKDLYINV5SD3_1%A N_A_M1008_g N_A_M1006_g A A N_A_c_79_n + PM_SKY130_FD_SC_MS__CLKDLYINV5SD3_1%A
diff --git a/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.spice b/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.spice index ab78af9..dbe3e16 100644 --- a/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.spice +++ b/cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkdlyinv5sd3_1.spice -* Created: Fri Aug 28 17:19:28 2020 +* Created: Wed Sep 2 12:01:20 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_1.lvs.report b/cells/clkinv/sky130_fd_sc_ms__clkinv_1.lvs.report new file mode 100644 index 0000000..2699cba --- /dev/null +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_1.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkinv_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkinv_1.sp ('sky130_fd_sc_ms__clkinv_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkinv/sky130_fd_sc_ms__clkinv_1.spice ('sky130_fd_sc_ms__clkinv_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:01:30 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkinv_1 sky130_fd_sc_ms__clkinv_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkinv_1 +SOURCE CELL NAME: sky130_fd_sc_ms__clkinv_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 4 3 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + ------ ------ + Total Inst: 2 2 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 6 6 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 2 2 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 2 layout mos transistors were reduced to 1. + 1 mos transistor was deleted by parallel reduction. + 2 source mos transistors were reduced to 1. + 1 mos transistor was deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_1.pex.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_1.pex.spice index 536c352..0f26917 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_1.pex.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_1.pex.spice -* Created: Fri Aug 28 17:19:47 2020 +* Created: Wed Sep 2 12:01:34 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_1.pxi.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_1.pxi.spice index d117865..188c093 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_1.pxi.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_1.pxi.spice -* Created: Fri Aug 28 17:19:47 2020 +* Created: Wed Sep 2 12:01:34 2020 * x_PM_SKY130_FD_SC_MS__CLKINV_1%A N_A_M1001_g N_A_M1000_g N_A_M1002_g A A + N_A_c_28_n N_A_c_29_n N_A_c_30_n PM_SKY130_FD_SC_MS__CLKINV_1%A
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_1.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_1.spice index 315b83c..4bf9c2c 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_1.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_1.spice -* Created: Fri Aug 28 17:19:47 2020 +* Created: Wed Sep 2 12:01:34 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_16.lvs.report b/cells/clkinv/sky130_fd_sc_ms__clkinv_16.lvs.report new file mode 100644 index 0000000..c9ff11b --- /dev/null +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_16.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkinv_16.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkinv_16.sp ('sky130_fd_sc_ms__clkinv_16') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkinv/sky130_fd_sc_ms__clkinv_16.spice ('sky130_fd_sc_ms__clkinv_16') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:01:24 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkinv_16 sky130_fd_sc_ms__clkinv_16 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkinv_16 +SOURCE CELL NAME: sky130_fd_sc_ms__clkinv_16 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 16 16 MN (4 pins) + 24 24 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + ------ ------ + Total Inst: 2 2 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 6 6 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 2 2 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 40 layout mos transistors were reduced to 2. + 38 mos transistors were deleted by parallel reduction. + 40 source mos transistors were reduced to 2. + 38 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_16.pex.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_16.pex.spice index 88c4d4a..0e7b920 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_16.pex.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_16.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_16.pex.spice -* Created: Fri Aug 28 17:19:37 2020 +* Created: Wed Sep 2 12:01:27 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_16.pxi.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_16.pxi.spice index bf25cbf..c076e25 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_16.pxi.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_16.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_16.pxi.spice -* Created: Fri Aug 28 17:19:37 2020 +* Created: Wed Sep 2 12:01:27 2020 * x_PM_SKY130_FD_SC_MS__CLKINV_16%A N_A_M1000_g N_A_M1001_g N_A_M1003_g + N_A_M1002_g N_A_M1005_g N_A_M1004_g N_A_M1007_g N_A_M1006_g N_A_M1008_g
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_16.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_16.spice index 1a6111f..bfa98ea 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_16.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_16.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_16.spice -* Created: Fri Aug 28 17:19:37 2020 +* Created: Wed Sep 2 12:01:27 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_2.lvs.report b/cells/clkinv/sky130_fd_sc_ms__clkinv_2.lvs.report new file mode 100644 index 0000000..5371304 --- /dev/null +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkinv_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkinv_2.sp ('sky130_fd_sc_ms__clkinv_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkinv/sky130_fd_sc_ms__clkinv_2.spice ('sky130_fd_sc_ms__clkinv_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:01:37 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkinv_2 sky130_fd_sc_ms__clkinv_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkinv_2 +SOURCE CELL NAME: sky130_fd_sc_ms__clkinv_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 2 2 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 6 5 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + ------ ------ + Total Inst: 2 2 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 6 6 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 2 2 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 5 layout mos transistors were reduced to 2. + 3 mos transistors were deleted by parallel reduction. + 5 source mos transistors were reduced to 2. + 3 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_2.pex.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_2.pex.spice index b392ac3..5956d40 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_2.pex.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_2.pex.spice -* Created: Fri Aug 28 17:19:55 2020 +* Created: Wed Sep 2 12:01:40 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_2.pxi.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_2.pxi.spice index efbb2a3..f8daec0 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_2.pxi.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_2.pxi.spice -* Created: Fri Aug 28 17:19:55 2020 +* Created: Wed Sep 2 12:01:40 2020 * x_PM_SKY130_FD_SC_MS__CLKINV_2%A N_A_M1002_g N_A_M1000_g N_A_M1001_g N_A_M1003_g + N_A_M1004_g A A A N_A_c_34_n PM_SKY130_FD_SC_MS__CLKINV_2%A
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_2.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_2.spice index be25bb9..4f78271 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_2.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_2.spice -* Created: Fri Aug 28 17:19:55 2020 +* Created: Wed Sep 2 12:01:40 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_4.lvs.report b/cells/clkinv/sky130_fd_sc_ms__clkinv_4.lvs.report new file mode 100644 index 0000000..bbcc99b --- /dev/null +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkinv_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkinv_4.sp ('sky130_fd_sc_ms__clkinv_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkinv/sky130_fd_sc_ms__clkinv_4.spice ('sky130_fd_sc_ms__clkinv_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:01:44 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkinv_4 sky130_fd_sc_ms__clkinv_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkinv_4 +SOURCE CELL NAME: sky130_fd_sc_ms__clkinv_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 4 4 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + ------ ------ + Total Inst: 2 2 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 6 6 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 2 2 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 10 layout mos transistors were reduced to 2. + 8 mos transistors were deleted by parallel reduction. + 10 source mos transistors were reduced to 2. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_4.pex.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_4.pex.spice index d0a3071..10d3705 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_4.pex.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_4.pex.spice -* Created: Fri Aug 28 17:20:04 2020 +* Created: Wed Sep 2 12:01:48 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_4.pxi.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_4.pxi.spice index 10da92c..64f5d1a 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_4.pxi.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_4.pxi.spice -* Created: Fri Aug 28 17:20:04 2020 +* Created: Wed Sep 2 12:01:48 2020 * x_PM_SKY130_FD_SC_MS__CLKINV_4%A N_A_M1002_g N_A_c_55_n N_A_M1000_g N_A_M1003_g + N_A_M1004_g N_A_M1001_g N_A_M1005_g N_A_M1006_g N_A_M1008_g N_A_M1007_g
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_4.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_4.spice index 06ef8bf..225df6b 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_4.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_4.spice -* Created: Fri Aug 28 17:20:04 2020 +* Created: Wed Sep 2 12:01:48 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_8.lvs.report b/cells/clkinv/sky130_fd_sc_ms__clkinv_8.lvs.report new file mode 100644 index 0000000..5e051aa --- /dev/null +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_8.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__clkinv_8.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__clkinv_8.sp ('sky130_fd_sc_ms__clkinv_8') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/clkinv/sky130_fd_sc_ms__clkinv_8.spice ('sky130_fd_sc_ms__clkinv_8') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:01:51 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__clkinv_8 sky130_fd_sc_ms__clkinv_8 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__clkinv_8 +SOURCE CELL NAME: sky130_fd_sc_ms__clkinv_8 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 8 8 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + ------ ------ + Total Inst: 2 2 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 6 6 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 2 2 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 2. + 18 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 2. + 18 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_8.pex.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_8.pex.spice index cbf1f91..f1d9522 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_8.pex.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_8.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_8.pex.spice -* Created: Fri Aug 28 17:20:34 2020 +* Created: Wed Sep 2 12:01:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_8.pxi.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_8.pxi.spice index 88661b4..812220d 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_8.pxi.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_8.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_8.pxi.spice -* Created: Fri Aug 28 17:20:34 2020 +* Created: Wed Sep 2 12:01:55 2020 * x_PM_SKY130_FD_SC_MS__CLKINV_8%A N_A_M1000_g N_A_M1002_g N_A_M1003_g N_A_M1004_g + N_A_M1005_g N_A_M1006_g N_A_M1001_g N_A_M1007_g N_A_M1012_g N_A_M1008_g
diff --git a/cells/clkinv/sky130_fd_sc_ms__clkinv_8.spice b/cells/clkinv/sky130_fd_sc_ms__clkinv_8.spice index 8cf0661..1797b56 100644 --- a/cells/clkinv/sky130_fd_sc_ms__clkinv_8.spice +++ b/cells/clkinv/sky130_fd_sc_ms__clkinv_8.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__clkinv_8.spice -* Created: Fri Aug 28 17:20:34 2020 +* Created: Wed Sep 2 12:01:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/conb/sky130_fd_sc_ms__conb_1.lvs.report b/cells/conb/sky130_fd_sc_ms__conb_1.lvs.report new file mode 100644 index 0000000..bddb0ab --- /dev/null +++ b/cells/conb/sky130_fd_sc_ms__conb_1.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__conb_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__conb_1.sp ('sky130_fd_sc_ms__conb_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/conb/sky130_fd_sc_ms__conb_1.spice ('sky130_fd_sc_ms__conb_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:01:59 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__conb_1 sky130_fd_sc_ms__conb_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__conb_1 +SOURCE CELL NAME: sky130_fd_sc_ms__conb_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 2 2 R (2 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 3 2 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 2 2 R (2 pins) + ------ ------ + Total Inst: 2 2 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 6 6 0 0 + + Instances: 2 2 0 0 R(SHORT) + ------- ------- --------- --------- + Total Inst: 2 2 0 0 + + +o Statistics: + + 2 passthrough layout nets were found. + 2 passthrough source nets were found. + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Passthrough Layout Nets And Their Ports: + + (Layout nets which are connected only to ports). + + VPB (port: VPB), VNB (port: VNB), + + +o Initial Correspondence Points: + + Ports: VNB VPB HI VPWR VGND LO + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/conb/sky130_fd_sc_ms__conb_1.pex.spice b/cells/conb/sky130_fd_sc_ms__conb_1.pex.spice index 61ef50c..e75b9916 100644 --- a/cells/conb/sky130_fd_sc_ms__conb_1.pex.spice +++ b/cells/conb/sky130_fd_sc_ms__conb_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__conb_1.pex.spice -* Created: Fri Aug 28 17:20:43 2020 +* Created: Wed Sep 2 12:02:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/conb/sky130_fd_sc_ms__conb_1.pxi.spice b/cells/conb/sky130_fd_sc_ms__conb_1.pxi.spice index 32d7522..b9c1cbe 100644 --- a/cells/conb/sky130_fd_sc_ms__conb_1.pxi.spice +++ b/cells/conb/sky130_fd_sc_ms__conb_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__conb_1.pxi.spice -* Created: Fri Aug 28 17:20:43 2020 +* Created: Wed Sep 2 12:02:02 2020 * x_PM_SKY130_FD_SC_MS__CONB_1%HI HI HI HI HI HI N_HI_R0_pos N_HI_c_24_n + N_HI_c_25_n HI PM_SKY130_FD_SC_MS__CONB_1%HI
diff --git a/cells/conb/sky130_fd_sc_ms__conb_1.spice b/cells/conb/sky130_fd_sc_ms__conb_1.spice index 64ac0a5..b30af61 100644 --- a/cells/conb/sky130_fd_sc_ms__conb_1.spice +++ b/cells/conb/sky130_fd_sc_ms__conb_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__conb_1.spice -* Created: Fri Aug 28 17:20:43 2020 +* Created: Wed Sep 2 12:02:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/decap/sky130_fd_sc_ms__decap_4.lvs.report b/cells/decap/sky130_fd_sc_ms__decap_4.lvs.report new file mode 100644 index 0000000..197430d --- /dev/null +++ b/cells/decap/sky130_fd_sc_ms__decap_4.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__decap_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__decap_4.sp ('sky130_fd_sc_ms__decap_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/decap/sky130_fd_sc_ms__decap_4.spice ('sky130_fd_sc_ms__decap_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:02:06 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__decap_4 sky130_fd_sc_ms__decap_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__decap_4 +SOURCE CELL NAME: sky130_fd_sc_ms__decap_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 4 4 + + Nets: 4 4 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 3 2 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 4 4 + + Nets: 4 4 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + ------ ------ + Total Inst: 2 2 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 4 4 0 0 + + Nets: 4 4 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 2 2 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB VGND VPWR + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/decap/sky130_fd_sc_ms__decap_4.pex.spice b/cells/decap/sky130_fd_sc_ms__decap_4.pex.spice index aa36d18..5512141 100644 --- a/cells/decap/sky130_fd_sc_ms__decap_4.pex.spice +++ b/cells/decap/sky130_fd_sc_ms__decap_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__decap_4.pex.spice -* Created: Fri Aug 28 17:20:53 2020 +* Created: Wed Sep 2 12:02:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/decap/sky130_fd_sc_ms__decap_4.pxi.spice b/cells/decap/sky130_fd_sc_ms__decap_4.pxi.spice index c8e024b..3770890 100644 --- a/cells/decap/sky130_fd_sc_ms__decap_4.pxi.spice +++ b/cells/decap/sky130_fd_sc_ms__decap_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__decap_4.pxi.spice -* Created: Fri Aug 28 17:20:53 2020 +* Created: Wed Sep 2 12:02:09 2020 * x_PM_SKY130_FD_SC_MS__DECAP_4%VGND N_VGND_M1001_s N_VGND_M1000_g N_VGND_c_20_n + N_VGND_c_21_n N_VGND_c_22_n N_VGND_c_23_n N_VGND_c_24_n VGND N_VGND_c_25_n
diff --git a/cells/decap/sky130_fd_sc_ms__decap_4.spice b/cells/decap/sky130_fd_sc_ms__decap_4.spice index ecf2cc1..6953366 100644 --- a/cells/decap/sky130_fd_sc_ms__decap_4.spice +++ b/cells/decap/sky130_fd_sc_ms__decap_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__decap_4.spice -* Created: Fri Aug 28 17:20:53 2020 +* Created: Wed Sep 2 12:02:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/decap/sky130_fd_sc_ms__decap_8.lvs.report b/cells/decap/sky130_fd_sc_ms__decap_8.lvs.report new file mode 100644 index 0000000..918a6de --- /dev/null +++ b/cells/decap/sky130_fd_sc_ms__decap_8.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__decap_8.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__decap_8.sp ('sky130_fd_sc_ms__decap_8') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/decap/sky130_fd_sc_ms__decap_8.spice ('sky130_fd_sc_ms__decap_8') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:02:12 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__decap_8 sky130_fd_sc_ms__decap_8 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__decap_8 +SOURCE CELL NAME: sky130_fd_sc_ms__decap_8 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 4 4 + + Nets: 4 4 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 5 4 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 4 4 + + Nets: 4 4 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + ------ ------ + Total Inst: 2 2 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 4 4 0 0 + + Nets: 4 4 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 2 2 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB VGND VPWR + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/decap/sky130_fd_sc_ms__decap_8.pex.spice b/cells/decap/sky130_fd_sc_ms__decap_8.pex.spice index 47aa0df..72fea59 100644 --- a/cells/decap/sky130_fd_sc_ms__decap_8.pex.spice +++ b/cells/decap/sky130_fd_sc_ms__decap_8.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__decap_8.pex.spice -* Created: Fri Aug 28 17:21:01 2020 +* Created: Wed Sep 2 12:02:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/decap/sky130_fd_sc_ms__decap_8.pxi.spice b/cells/decap/sky130_fd_sc_ms__decap_8.pxi.spice index 37769c9..8b0262f 100644 --- a/cells/decap/sky130_fd_sc_ms__decap_8.pxi.spice +++ b/cells/decap/sky130_fd_sc_ms__decap_8.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__decap_8.pxi.spice -* Created: Fri Aug 28 17:21:01 2020 +* Created: Wed Sep 2 12:02:15 2020 * x_PM_SKY130_FD_SC_MS__DECAP_8%VGND N_VGND_M1001_s N_VGND_M1000_g N_VGND_M1002_g + N_VGND_c_30_n N_VGND_c_31_n N_VGND_c_32_n N_VGND_c_33_n N_VGND_c_34_n
diff --git a/cells/decap/sky130_fd_sc_ms__decap_8.spice b/cells/decap/sky130_fd_sc_ms__decap_8.spice index 198b493..3536cc9 100644 --- a/cells/decap/sky130_fd_sc_ms__decap_8.spice +++ b/cells/decap/sky130_fd_sc_ms__decap_8.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__decap_8.spice -* Created: Fri Aug 28 17:21:01 2020 +* Created: Wed Sep 2 12:02:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.lvs.report b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.lvs.report new file mode 100644 index 0000000..8bffe1d --- /dev/null +++ b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfbbn_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfbbn_1.sp ('sky130_fd_sc_ms__dfbbn_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.spice ('sky130_fd_sc_ms__dfbbn_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:02:19 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfbbn_1 sky130_fd_sc_ms__dfbbn_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfbbn_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dfbbn_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 29 29 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 19 19 + + Instances: 8 8 MN (4 pins) + 10 10 MP (4 pins) + 3 3 SMN2 (4 pins) + 5 5 SMP2 (4 pins) + 2 2 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 28 28 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 19 19 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 5 5 0 0 SMP2 + 2 2 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 28 28 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB CLK_N D SET_B RESET_B VPWR Q_N Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.pex.spice b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.pex.spice index 25af836..5d5b08f 100644 --- a/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.pex.spice +++ b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfbbn_1.pex.spice -* Created: Fri Aug 28 17:21:10 2020 +* Created: Wed Sep 2 12:02:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.pxi.spice b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.pxi.spice index 665c439..af661b7 100644 --- a/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.pxi.spice +++ b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfbbn_1.pxi.spice -* Created: Fri Aug 28 17:21:10 2020 +* Created: Wed Sep 2 12:02:22 2020 * x_PM_SKY130_FD_SC_MS__DFBBN_1%CLK_N N_CLK_N_M1030_g N_CLK_N_M1035_g CLK_N + N_CLK_N_c_281_n N_CLK_N_c_282_n PM_SKY130_FD_SC_MS__DFBBN_1%CLK_N
diff --git a/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.spice b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.spice index 15cba7a..4219aac 100644 --- a/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.spice +++ b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfbbn_1.spice -* Created: Fri Aug 28 17:21:10 2020 +* Created: Wed Sep 2 12:02:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.lvs.report b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.lvs.report new file mode 100644 index 0000000..cf79714 --- /dev/null +++ b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfbbn_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfbbn_2.sp ('sky130_fd_sc_ms__dfbbn_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.spice ('sky130_fd_sc_ms__dfbbn_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:02:26 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfbbn_2 sky130_fd_sc_ms__dfbbn_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfbbn_2 +SOURCE CELL NAME: sky130_fd_sc_ms__dfbbn_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 29 29 + + Instances: 22 22 MN (4 pins) + 22 22 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 45 44 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 19 19 + + Instances: 8 8 MN (4 pins) + 10 10 MP (4 pins) + 3 3 SMN2 (4 pins) + 5 5 SMP2 (4 pins) + 2 2 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 28 28 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 19 19 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 5 5 0 0 SMP2 + 2 2 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 28 28 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB CLK_N D SET_B RESET_B VPWR Q_N Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.pex.spice b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.pex.spice index 4f7ad06..420a373 100644 --- a/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.pex.spice +++ b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfbbn_2.pex.spice -* Created: Fri Aug 28 17:21:40 2020 +* Created: Wed Sep 2 12:02:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.pxi.spice b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.pxi.spice index 4840d6e..862faab 100644 --- a/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.pxi.spice +++ b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfbbn_2.pxi.spice -* Created: Fri Aug 28 17:21:40 2020 +* Created: Wed Sep 2 12:02:29 2020 * x_PM_SKY130_FD_SC_MS__DFBBN_2%CLK_N N_CLK_N_M1033_g N_CLK_N_M1037_g CLK_N + N_CLK_N_c_300_n N_CLK_N_c_301_n PM_SKY130_FD_SC_MS__DFBBN_2%CLK_N
diff --git a/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.spice b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.spice index 0b999de..ff9c1d4 100644 --- a/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.spice +++ b/cells/dfbbn/sky130_fd_sc_ms__dfbbn_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfbbn_2.spice -* Created: Fri Aug 28 17:21:40 2020 +* Created: Wed Sep 2 12:02:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.lvs.report b/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.lvs.report new file mode 100644 index 0000000..eda6d90 --- /dev/null +++ b/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfbbp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfbbp_1.sp ('sky130_fd_sc_ms__dfbbp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.spice ('sky130_fd_sc_ms__dfbbp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:02:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfbbp_1 sky130_fd_sc_ms__dfbbp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfbbp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dfbbp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 29 29 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 19 19 + + Instances: 8 8 MN (4 pins) + 10 10 MP (4 pins) + 3 3 SMN2 (4 pins) + 5 5 SMP2 (4 pins) + 2 2 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 28 28 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 19 19 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 5 5 0 0 SMP2 + 2 2 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 28 28 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB CLK D SET_B RESET_B VPWR Q_N Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.pex.spice b/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.pex.spice index 40b2804..ebded67 100644 --- a/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.pex.spice +++ b/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfbbp_1.pex.spice -* Created: Fri Aug 28 17:21:49 2020 +* Created: Wed Sep 2 12:02:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.pxi.spice b/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.pxi.spice index 1dbe329..939355d 100644 --- a/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.pxi.spice +++ b/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfbbp_1.pxi.spice -* Created: Fri Aug 28 17:21:49 2020 +* Created: Wed Sep 2 12:02:36 2020 * x_PM_SKY130_FD_SC_MS__DFBBP_1%CLK N_CLK_M1029_g N_CLK_M1018_g CLK N_CLK_c_266_n + N_CLK_c_267_n PM_SKY130_FD_SC_MS__DFBBP_1%CLK
diff --git a/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.spice b/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.spice index ce17b55..35b129c 100644 --- a/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.spice +++ b/cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfbbp_1.spice -* Created: Fri Aug 28 17:21:49 2020 +* Created: Wed Sep 2 12:02:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.lvs.report b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.lvs.report new file mode 100644 index 0000000..ab6183d --- /dev/null +++ b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfrbp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfrbp_1.sp ('sky130_fd_sc_ms__dfrbp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.spice ('sky130_fd_sc_ms__dfrbp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:02:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfrbp_1 sky130_fd_sc_ms__dfrbp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfrbp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dfrbp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 24 24 + + Instances: 17 17 MN (4 pins) + 17 17 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 35 34 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 17 17 + + Instances: 8 8 MN (4 pins) + 13 13 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 27 27 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 17 17 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 13 13 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 1 1 0 0 SMN3 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 27 27 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D CLK RESET_B VPWR Q_N Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.pex.spice b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.pex.spice index 1bd60a6..b6c81e3 100644 --- a/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.pex.spice +++ b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrbp_1.pex.spice -* Created: Fri Aug 28 17:22:00 2020 +* Created: Wed Sep 2 12:02:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.pxi.spice b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.pxi.spice index 1b4f294..441b308 100644 --- a/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.pxi.spice +++ b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrbp_1.pxi.spice -* Created: Fri Aug 28 17:22:00 2020 +* Created: Wed Sep 2 12:02:43 2020 * x_PM_SKY130_FD_SC_MS__DFRBP_1%D N_D_M1023_g N_D_M1010_g N_D_c_241_n D D D + N_D_c_237_n N_D_c_238_n N_D_c_239_n PM_SKY130_FD_SC_MS__DFRBP_1%D
diff --git a/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.spice b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.spice index e5136cb..d2e4b3a 100644 --- a/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.spice +++ b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrbp_1.spice -* Created: Fri Aug 28 17:22:00 2020 +* Created: Wed Sep 2 12:02:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.lvs.report b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.lvs.report new file mode 100644 index 0000000..9cdf88e --- /dev/null +++ b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfrbp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfrbp_2.sp ('sky130_fd_sc_ms__dfrbp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.spice ('sky130_fd_sc_ms__dfrbp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:02:46 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfrbp_2 sky130_fd_sc_ms__dfrbp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfrbp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__dfrbp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 24 24 + + Instances: 19 19 MN (4 pins) + 19 19 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 39 38 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 17 17 + + Instances: 8 8 MN (4 pins) + 13 13 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 27 27 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 17 17 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 13 13 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 1 1 0 0 SMN3 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 27 27 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D RESET_B CLK VPWR Q_N Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.pex.spice b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.pex.spice index e14a1eb..dc2661d 100644 --- a/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.pex.spice +++ b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrbp_2.pex.spice -* Created: Fri Aug 28 17:22:09 2020 +* Created: Wed Sep 2 12:02:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.pxi.spice b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.pxi.spice index 9a25fd1..8697bd9 100644 --- a/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.pxi.spice +++ b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrbp_2.pxi.spice -* Created: Fri Aug 28 17:22:09 2020 +* Created: Wed Sep 2 12:02:49 2020 * x_PM_SKY130_FD_SC_MS__DFRBP_2%D N_D_M1036_g N_D_M1012_g N_D_c_266_n N_D_c_267_n + N_D_c_268_n D D N_D_c_270_n PM_SKY130_FD_SC_MS__DFRBP_2%D
diff --git a/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.spice b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.spice index 08bff3b..929f12a 100644 --- a/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.spice +++ b/cells/dfrbp/sky130_fd_sc_ms__dfrbp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrbp_2.spice -* Created: Fri Aug 28 17:22:09 2020 +* Created: Wed Sep 2 12:02:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.lvs.report b/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.lvs.report new file mode 100644 index 0000000..8d0c313 --- /dev/null +++ b/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfrtn_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfrtn_1.sp ('sky130_fd_sc_ms__dfrtn_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.spice ('sky130_fd_sc_ms__dfrtn_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:02:53 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfrtn_1 sky130_fd_sc_ms__dfrtn_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfrtn_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dfrtn_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 23 23 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 16 16 + + Instances: 7 7 MN (4 pins) + 12 12 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 25 25 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 16 16 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 12 12 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 1 1 0 0 SMN3 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 25 25 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D CLK_N RESET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.pex.spice b/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.pex.spice index 8276871..68c1d3e 100644 --- a/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.pex.spice +++ b/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrtn_1.pex.spice -* Created: Fri Aug 28 17:22:18 2020 +* Created: Wed Sep 2 12:02:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.pxi.spice b/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.pxi.spice index 06665ce..ef2e1a5 100644 --- a/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.pxi.spice +++ b/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrtn_1.pxi.spice -* Created: Fri Aug 28 17:22:18 2020 +* Created: Wed Sep 2 12:02:56 2020 * x_PM_SKY130_FD_SC_MS__DFRTN_1%D N_D_c_232_n N_D_c_239_n N_D_M1030_g N_D_M1028_g + N_D_c_234_n N_D_c_235_n D D D N_D_c_236_n N_D_c_237_n
diff --git a/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.spice b/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.spice index 223b465..c5569f7 100644 --- a/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.spice +++ b/cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrtn_1.spice -* Created: Fri Aug 28 17:22:18 2020 +* Created: Wed Sep 2 12:02:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.lvs.report b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.lvs.report new file mode 100644 index 0000000..def04d2 --- /dev/null +++ b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfrtp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfrtp_1.sp ('sky130_fd_sc_ms__dfrtp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.spice ('sky130_fd_sc_ms__dfrtp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:03:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfrtp_1 sky130_fd_sc_ms__dfrtp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfrtp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dfrtp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 23 23 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 16 16 + + Instances: 7 7 MN (4 pins) + 12 12 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 25 25 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 16 16 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 12 12 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 1 1 0 0 SMN3 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 25 25 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D CLK RESET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.pex.spice b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.pex.spice index 974fe77..d229027 100644 --- a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.pex.spice +++ b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrtp_1.pex.spice -* Created: Fri Aug 28 17:22:52 2020 +* Created: Wed Sep 2 12:03:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.pxi.spice b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.pxi.spice index edd00ed..c6ff77a 100644 --- a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.pxi.spice +++ b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrtp_1.pxi.spice -* Created: Fri Aug 28 17:22:52 2020 +* Created: Wed Sep 2 12:03:03 2020 * x_PM_SKY130_FD_SC_MS__DFRTP_1%D N_D_c_232_n N_D_M1018_g N_D_M1026_g D D D + N_D_c_234_n N_D_c_235_n N_D_c_239_n PM_SKY130_FD_SC_MS__DFRTP_1%D
diff --git a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.spice b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.spice index 2ce7a0c..35f8227 100644 --- a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.spice +++ b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrtp_1.spice -* Created: Fri Aug 28 17:22:52 2020 +* Created: Wed Sep 2 12:03:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.lvs.report b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.lvs.report new file mode 100644 index 0000000..1f62a9d --- /dev/null +++ b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfrtp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfrtp_2.sp ('sky130_fd_sc_ms__dfrtp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.spice ('sky130_fd_sc_ms__dfrtp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:03:06 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfrtp_2 sky130_fd_sc_ms__dfrtp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfrtp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__dfrtp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 23 23 + + Instances: 17 17 MN (4 pins) + 17 17 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 35 34 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 16 16 + + Instances: 7 7 MN (4 pins) + 12 12 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 25 25 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 16 16 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 12 12 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 1 1 0 0 SMN3 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 25 25 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D CLK RESET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.pex.spice b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.pex.spice index 214f1fd..f7495a6 100644 --- a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.pex.spice +++ b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrtp_2.pex.spice -* Created: Fri Aug 28 17:23:02 2020 +* Created: Wed Sep 2 12:03:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.pxi.spice b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.pxi.spice index 05c69be..6f3a2b5 100644 --- a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.pxi.spice +++ b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrtp_2.pxi.spice -* Created: Fri Aug 28 17:23:02 2020 +* Created: Wed Sep 2 12:03:09 2020 * x_PM_SKY130_FD_SC_MS__DFRTP_2%D N_D_c_242_n N_D_M1014_g N_D_M1028_g D D D + N_D_c_244_n N_D_c_245_n N_D_c_249_n PM_SKY130_FD_SC_MS__DFRTP_2%D
diff --git a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.spice b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.spice index d3aa67a..4e55337 100644 --- a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.spice +++ b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrtp_2.spice -* Created: Fri Aug 28 17:23:02 2020 +* Created: Wed Sep 2 12:03:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.lvs.report b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.lvs.report new file mode 100644 index 0000000..bcd7290 --- /dev/null +++ b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfrtp_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfrtp_4.sp ('sky130_fd_sc_ms__dfrtp_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.spice ('sky130_fd_sc_ms__dfrtp_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:03:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfrtp_4 sky130_fd_sc_ms__dfrtp_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfrtp_4 +SOURCE CELL NAME: sky130_fd_sc_ms__dfrtp_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 23 23 + + Instances: 19 19 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 40 39 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 16 16 + + Instances: 7 7 MN (4 pins) + 12 12 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 25 25 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 16 16 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 12 12 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 1 1 0 0 SMN3 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 25 25 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 10 layout mos transistors were reduced to 3. + 7 mos transistors were deleted by parallel reduction. + 10 source mos transistors were reduced to 3. + 7 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D CLK RESET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.pex.spice b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.pex.spice index 9557db3..13a803e 100644 --- a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.pex.spice +++ b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrtp_4.pex.spice -* Created: Fri Aug 28 17:23:10 2020 +* Created: Wed Sep 2 12:03:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.pxi.spice b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.pxi.spice index 6a38072..d6c34d0 100644 --- a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.pxi.spice +++ b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrtp_4.pxi.spice -* Created: Fri Aug 28 17:23:10 2020 +* Created: Wed Sep 2 12:03:16 2020 * x_PM_SKY130_FD_SC_MS__DFRTP_4%D N_D_c_276_n N_D_c_281_n N_D_M1034_g N_D_M1017_g + N_D_c_283_n D D D N_D_c_278_n N_D_c_279_n N_D_c_285_n
diff --git a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.spice b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.spice index 5ab1133..f3c3942 100644 --- a/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.spice +++ b/cells/dfrtp/sky130_fd_sc_ms__dfrtp_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfrtp_4.spice -* Created: Fri Aug 28 17:23:10 2020 +* Created: Wed Sep 2 12:03:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.lvs.report b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.lvs.report new file mode 100644 index 0000000..3797f60 --- /dev/null +++ b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfsbp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfsbp_1.sp ('sky130_fd_sc_ms__dfsbp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.spice ('sky130_fd_sc_ms__dfsbp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:03:19 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfsbp_1 sky130_fd_sc_ms__dfsbp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfsbp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dfsbp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 25 25 + + Instances: 17 17 MN (4 pins) + 17 17 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 35 34 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 17 17 + + Instances: 8 8 MN (4 pins) + 11 11 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 3 3 SMP2 (4 pins) + ------ ------ + Total Inst: 26 26 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 17 17 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 11 11 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 1 1 0 0 SMN3 + 3 3 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 26 26 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D CLK SET_B VPWR Q_N Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.pex.spice b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.pex.spice index 87275d4..cbb666b 100644 --- a/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.pex.spice +++ b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfsbp_1.pex.spice -* Created: Fri Aug 28 17:23:19 2020 +* Created: Wed Sep 2 12:03:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.pxi.spice b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.pxi.spice index 4e82fdc..d95b97b 100644 --- a/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.pxi.spice +++ b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfsbp_1.pxi.spice -* Created: Fri Aug 28 17:23:19 2020 +* Created: Wed Sep 2 12:03:23 2020 * x_PM_SKY130_FD_SC_MS__DFSBP_1%D N_D_c_270_n N_D_M1023_g N_D_M1003_g D D + N_D_c_272_n N_D_c_273_n N_D_c_277_n PM_SKY130_FD_SC_MS__DFSBP_1%D
diff --git a/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.spice b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.spice index f0fdbba..c3b4557 100644 --- a/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.spice +++ b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfsbp_1.spice -* Created: Fri Aug 28 17:23:19 2020 +* Created: Wed Sep 2 12:03:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.lvs.report b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.lvs.report new file mode 100644 index 0000000..cf05cdf --- /dev/null +++ b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfsbp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfsbp_2.sp ('sky130_fd_sc_ms__dfsbp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.spice ('sky130_fd_sc_ms__dfsbp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:03:26 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfsbp_2 sky130_fd_sc_ms__dfsbp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfsbp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__dfsbp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 25 25 + + Instances: 19 19 MN (4 pins) + 19 19 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 39 38 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 17 17 + + Instances: 8 8 MN (4 pins) + 11 11 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 3 3 SMP2 (4 pins) + ------ ------ + Total Inst: 26 26 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 17 17 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 11 11 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 1 1 0 0 SMN3 + 3 3 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 26 26 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D CLK SET_B VPWR Q_N Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.pex.spice b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.pex.spice index 09cca00..2e51494 100644 --- a/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.pex.spice +++ b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfsbp_2.pex.spice -* Created: Fri Aug 28 17:23:40 2020 +* Created: Wed Sep 2 12:03:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.pxi.spice b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.pxi.spice index 8155cd2..070a892 100644 --- a/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.pxi.spice +++ b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfsbp_2.pxi.spice -* Created: Fri Aug 28 17:23:40 2020 +* Created: Wed Sep 2 12:03:29 2020 * x_PM_SKY130_FD_SC_MS__DFSBP_2%D N_D_c_278_n N_D_M1029_g N_D_M1033_g D D + N_D_c_280_n N_D_c_281_n N_D_c_285_n PM_SKY130_FD_SC_MS__DFSBP_2%D
diff --git a/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.spice b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.spice index 9286aab..62da47a 100644 --- a/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.spice +++ b/cells/dfsbp/sky130_fd_sc_ms__dfsbp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfsbp_2.spice -* Created: Fri Aug 28 17:23:40 2020 +* Created: Wed Sep 2 12:03:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfstp/sky130_fd_sc_ms__dfstp_1.lvs.report b/cells/dfstp/sky130_fd_sc_ms__dfstp_1.lvs.report new file mode 100644 index 0000000..96e76df --- /dev/null +++ b/cells/dfstp/sky130_fd_sc_ms__dfstp_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfstp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfstp_1.sp ('sky130_fd_sc_ms__dfstp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfstp/sky130_fd_sc_ms__dfstp_1.spice ('sky130_fd_sc_ms__dfstp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:03:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfstp_1 sky130_fd_sc_ms__dfstp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfstp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dfstp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 24 24 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 16 16 + + Instances: 7 7 MN (4 pins) + 10 10 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 3 3 SMP2 (4 pins) + ------ ------ + Total Inst: 24 24 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 16 16 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 1 1 0 0 SMN3 + 3 3 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 24 24 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D CLK SET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfstp/sky130_fd_sc_ms__dfstp_1.pex.spice b/cells/dfstp/sky130_fd_sc_ms__dfstp_1.pex.spice index 3f64148..a8aae76 100644 --- a/cells/dfstp/sky130_fd_sc_ms__dfstp_1.pex.spice +++ b/cells/dfstp/sky130_fd_sc_ms__dfstp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfstp_1.pex.spice -* Created: Fri Aug 28 17:24:01 2020 +* Created: Wed Sep 2 12:03:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfstp/sky130_fd_sc_ms__dfstp_1.pxi.spice b/cells/dfstp/sky130_fd_sc_ms__dfstp_1.pxi.spice index 92e0718..a766b8e 100644 --- a/cells/dfstp/sky130_fd_sc_ms__dfstp_1.pxi.spice +++ b/cells/dfstp/sky130_fd_sc_ms__dfstp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfstp_1.pxi.spice -* Created: Fri Aug 28 17:24:01 2020 +* Created: Wed Sep 2 12:03:36 2020 * x_PM_SKY130_FD_SC_MS__DFSTP_1%D N_D_c_239_n N_D_M1008_g N_D_M1028_g D D + N_D_c_241_n N_D_c_242_n N_D_c_246_n PM_SKY130_FD_SC_MS__DFSTP_1%D
diff --git a/cells/dfstp/sky130_fd_sc_ms__dfstp_1.spice b/cells/dfstp/sky130_fd_sc_ms__dfstp_1.spice index f2a51a6..0869cfd 100644 --- a/cells/dfstp/sky130_fd_sc_ms__dfstp_1.spice +++ b/cells/dfstp/sky130_fd_sc_ms__dfstp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfstp_1.spice -* Created: Fri Aug 28 17:24:01 2020 +* Created: Wed Sep 2 12:03:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfstp/sky130_fd_sc_ms__dfstp_2.lvs.report b/cells/dfstp/sky130_fd_sc_ms__dfstp_2.lvs.report new file mode 100644 index 0000000..285091b --- /dev/null +++ b/cells/dfstp/sky130_fd_sc_ms__dfstp_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfstp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfstp_2.sp ('sky130_fd_sc_ms__dfstp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfstp/sky130_fd_sc_ms__dfstp_2.spice ('sky130_fd_sc_ms__dfstp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:03:39 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfstp_2 sky130_fd_sc_ms__dfstp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfstp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__dfstp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 24 24 + + Instances: 17 17 MN (4 pins) + 17 17 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 35 34 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 16 16 + + Instances: 7 7 MN (4 pins) + 10 10 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 3 3 SMP2 (4 pins) + ------ ------ + Total Inst: 24 24 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 16 16 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 1 1 0 0 SMN3 + 3 3 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 24 24 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D CLK SET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfstp/sky130_fd_sc_ms__dfstp_2.pex.spice b/cells/dfstp/sky130_fd_sc_ms__dfstp_2.pex.spice index cf4b266..852c901 100644 --- a/cells/dfstp/sky130_fd_sc_ms__dfstp_2.pex.spice +++ b/cells/dfstp/sky130_fd_sc_ms__dfstp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfstp_2.pex.spice -* Created: Fri Aug 28 17:24:11 2020 +* Created: Wed Sep 2 12:03:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfstp/sky130_fd_sc_ms__dfstp_2.pxi.spice b/cells/dfstp/sky130_fd_sc_ms__dfstp_2.pxi.spice index 54386af..7582614 100644 --- a/cells/dfstp/sky130_fd_sc_ms__dfstp_2.pxi.spice +++ b/cells/dfstp/sky130_fd_sc_ms__dfstp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfstp_2.pxi.spice -* Created: Fri Aug 28 17:24:11 2020 +* Created: Wed Sep 2 12:03:42 2020 * x_PM_SKY130_FD_SC_MS__DFSTP_2%D N_D_c_246_n N_D_M1020_g N_D_M1031_g D D + N_D_c_248_n N_D_c_249_n N_D_c_253_n PM_SKY130_FD_SC_MS__DFSTP_2%D
diff --git a/cells/dfstp/sky130_fd_sc_ms__dfstp_2.spice b/cells/dfstp/sky130_fd_sc_ms__dfstp_2.spice index dad1637..28c4333 100644 --- a/cells/dfstp/sky130_fd_sc_ms__dfstp_2.spice +++ b/cells/dfstp/sky130_fd_sc_ms__dfstp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfstp_2.spice -* Created: Fri Aug 28 17:24:11 2020 +* Created: Wed Sep 2 12:03:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfstp/sky130_fd_sc_ms__dfstp_4.lvs.report b/cells/dfstp/sky130_fd_sc_ms__dfstp_4.lvs.report new file mode 100644 index 0000000..348da8b --- /dev/null +++ b/cells/dfstp/sky130_fd_sc_ms__dfstp_4.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfstp_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfstp_4.sp ('sky130_fd_sc_ms__dfstp_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfstp/sky130_fd_sc_ms__dfstp_4.spice ('sky130_fd_sc_ms__dfstp_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:03:46 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfstp_4 sky130_fd_sc_ms__dfstp_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfstp_4 +SOURCE CELL NAME: sky130_fd_sc_ms__dfstp_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 24 24 + + Instances: 19 19 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 40 39 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 16 16 + + Instances: 7 7 MN (4 pins) + 10 10 MP (4 pins) + 3 3 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 3 3 SMP2 (4 pins) + ------ ------ + Total Inst: 24 24 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 16 16 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 1 1 0 0 SMN3 + 3 3 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 24 24 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 10 layout mos transistors were reduced to 3. + 7 mos transistors were deleted by parallel reduction. + 10 source mos transistors were reduced to 3. + 7 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D CLK SET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfstp/sky130_fd_sc_ms__dfstp_4.pex.spice b/cells/dfstp/sky130_fd_sc_ms__dfstp_4.pex.spice index 3e57209..a4f6bad 100644 --- a/cells/dfstp/sky130_fd_sc_ms__dfstp_4.pex.spice +++ b/cells/dfstp/sky130_fd_sc_ms__dfstp_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfstp_4.pex.spice -* Created: Fri Aug 28 17:24:20 2020 +* Created: Wed Sep 2 12:03:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfstp/sky130_fd_sc_ms__dfstp_4.pxi.spice b/cells/dfstp/sky130_fd_sc_ms__dfstp_4.pxi.spice index cbf8382..6b44f34 100644 --- a/cells/dfstp/sky130_fd_sc_ms__dfstp_4.pxi.spice +++ b/cells/dfstp/sky130_fd_sc_ms__dfstp_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfstp_4.pxi.spice -* Created: Fri Aug 28 17:24:20 2020 +* Created: Wed Sep 2 12:03:49 2020 * x_PM_SKY130_FD_SC_MS__DFSTP_4%D N_D_c_274_n N_D_M1031_g N_D_M1032_g D D + N_D_c_276_n N_D_c_277_n N_D_c_281_n PM_SKY130_FD_SC_MS__DFSTP_4%D
diff --git a/cells/dfstp/sky130_fd_sc_ms__dfstp_4.spice b/cells/dfstp/sky130_fd_sc_ms__dfstp_4.spice index 4eb3b10..8ff290c 100644 --- a/cells/dfstp/sky130_fd_sc_ms__dfstp_4.spice +++ b/cells/dfstp/sky130_fd_sc_ms__dfstp_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfstp_4.spice -* Created: Fri Aug 28 17:24:20 2020 +* Created: Wed Sep 2 12:03:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.lvs.report b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.lvs.report new file mode 100644 index 0000000..45f6285 --- /dev/null +++ b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfxbp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfxbp_1.sp ('sky130_fd_sc_ms__dfxbp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.spice ('sky130_fd_sc_ms__dfxbp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:03:53 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfxbp_1 sky130_fd_sc_ms__dfxbp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfxbp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dfxbp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 20 20 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 16 16 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 24 24 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 16 16 0 0 + + Instances: 10 10 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 24 24 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB CLK D VPWR Q Q_N VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.pex.spice b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.pex.spice index e38bf86..33d0e55 100644 --- a/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.pex.spice +++ b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxbp_1.pex.spice -* Created: Fri Aug 28 17:24:30 2020 +* Created: Wed Sep 2 12:03:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.pxi.spice b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.pxi.spice index 5d4c523..cee4696 100644 --- a/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.pxi.spice +++ b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxbp_1.pxi.spice -* Created: Fri Aug 28 17:24:30 2020 +* Created: Wed Sep 2 12:03:56 2020 * x_PM_SKY130_FD_SC_MS__DFXBP_1%CLK N_CLK_M1015_g N_CLK_c_208_n N_CLK_M1025_g CLK + N_CLK_c_209_n N_CLK_c_210_n PM_SKY130_FD_SC_MS__DFXBP_1%CLK
diff --git a/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.spice b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.spice index 69a3ebb..d0993df 100644 --- a/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.spice +++ b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxbp_1.spice -* Created: Fri Aug 28 17:24:30 2020 +* Created: Wed Sep 2 12:03:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.lvs.report b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.lvs.report new file mode 100644 index 0000000..905dc94 --- /dev/null +++ b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfxbp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfxbp_2.sp ('sky130_fd_sc_ms__dfxbp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.spice ('sky130_fd_sc_ms__dfxbp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:04:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfxbp_2 sky130_fd_sc_ms__dfxbp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfxbp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__dfxbp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 20 20 + + Instances: 16 16 MN (4 pins) + 17 17 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 34 33 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 16 16 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 24 24 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 16 16 0 0 + + Instances: 10 10 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 24 24 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 10 layout mos transistors were reduced to 5. + 5 mos transistors were deleted by parallel reduction. + 10 source mos transistors were reduced to 5. + 5 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB CLK D VPWR Q Q_N VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.pex.spice b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.pex.spice index fe954b2..cbd089c 100644 --- a/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.pex.spice +++ b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxbp_2.pex.spice -* Created: Fri Aug 28 17:24:48 2020 +* Created: Wed Sep 2 12:04:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.pxi.spice b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.pxi.spice index e01a3a8..02cba4f 100644 --- a/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.pxi.spice +++ b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxbp_2.pxi.spice -* Created: Fri Aug 28 17:24:48 2020 +* Created: Wed Sep 2 12:04:03 2020 * x_PM_SKY130_FD_SC_MS__DFXBP_2%CLK N_CLK_M1010_g N_CLK_M1031_g CLK N_CLK_c_224_n + N_CLK_c_225_n N_CLK_c_226_n PM_SKY130_FD_SC_MS__DFXBP_2%CLK
diff --git a/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.spice b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.spice index 45e49d1..1dad7f6 100644 --- a/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.spice +++ b/cells/dfxbp/sky130_fd_sc_ms__dfxbp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxbp_2.spice -* Created: Fri Aug 28 17:24:48 2020 +* Created: Wed Sep 2 12:04:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.lvs.report b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.lvs.report new file mode 100644 index 0000000..ff8f017 --- /dev/null +++ b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfxtp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfxtp_1.sp ('sky130_fd_sc_ms__dfxtp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.spice ('sky130_fd_sc_ms__dfxtp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:04:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfxtp_1 sky130_fd_sc_ms__dfxtp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfxtp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dfxtp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 18 18 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 14 14 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 20 20 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 14 14 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 8 8 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 20 20 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB CLK D VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.pex.spice b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.pex.spice index f50bebf..1bad99b 100644 --- a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.pex.spice +++ b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxtp_1.pex.spice -* Created: Fri Aug 28 17:25:07 2020 +* Created: Wed Sep 2 12:04:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.pxi.spice b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.pxi.spice index 2f0c2b1..9d17ad2 100644 --- a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.pxi.spice +++ b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxtp_1.pxi.spice -* Created: Fri Aug 28 17:25:07 2020 +* Created: Wed Sep 2 12:04:10 2020 * x_PM_SKY130_FD_SC_MS__DFXTP_1%CLK N_CLK_M1009_g N_CLK_M1022_g CLK N_CLK_c_187_n + N_CLK_c_188_n PM_SKY130_FD_SC_MS__DFXTP_1%CLK
diff --git a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.spice b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.spice index 7ed9d93..0145a5c 100644 --- a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.spice +++ b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxtp_1.spice -* Created: Fri Aug 28 17:25:07 2020 +* Created: Wed Sep 2 12:04:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.lvs.report b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.lvs.report new file mode 100644 index 0000000..14d4a8f --- /dev/null +++ b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfxtp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfxtp_2.sp ('sky130_fd_sc_ms__dfxtp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.spice ('sky130_fd_sc_ms__dfxtp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:04:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfxtp_2 sky130_fd_sc_ms__dfxtp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfxtp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__dfxtp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 18 18 + + Instances: 13 13 MN (4 pins) + 13 13 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 27 26 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 14 14 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 20 20 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 14 14 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 8 8 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 20 20 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB CLK D VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.pex.spice b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.pex.spice index fe318b8..906f6ea 100644 --- a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.pex.spice +++ b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxtp_2.pex.spice -* Created: Fri Aug 28 17:25:17 2020 +* Created: Wed Sep 2 12:04:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.pxi.spice b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.pxi.spice index eb29bf3..a3c39c9 100644 --- a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.pxi.spice +++ b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxtp_2.pxi.spice -* Created: Fri Aug 28 17:25:17 2020 +* Created: Wed Sep 2 12:04:16 2020 * x_PM_SKY130_FD_SC_MS__DFXTP_2%CLK N_CLK_M1010_g N_CLK_M1024_g CLK N_CLK_c_192_n + N_CLK_c_193_n PM_SKY130_FD_SC_MS__DFXTP_2%CLK
diff --git a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.spice b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.spice index a645407..6d2f688 100644 --- a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.spice +++ b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxtp_2.spice -* Created: Fri Aug 28 17:25:17 2020 +* Created: Wed Sep 2 12:04:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.lvs.report b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.lvs.report new file mode 100644 index 0000000..be138fe --- /dev/null +++ b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dfxtp_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dfxtp_4.sp ('sky130_fd_sc_ms__dfxtp_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.spice ('sky130_fd_sc_ms__dfxtp_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:04:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dfxtp_4 sky130_fd_sc_ms__dfxtp_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dfxtp_4 +SOURCE CELL NAME: sky130_fd_sc_ms__dfxtp_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 18 18 + + Instances: 15 15 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 32 31 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 14 14 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 20 20 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 14 14 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 8 8 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 20 20 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 10 layout mos transistors were reduced to 3. + 7 mos transistors were deleted by parallel reduction. + 10 source mos transistors were reduced to 3. + 7 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB CLK D VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.pex.spice b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.pex.spice index 368b570..38ac1f3 100644 --- a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.pex.spice +++ b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxtp_4.pex.spice -* Created: Fri Aug 28 17:25:26 2020 +* Created: Wed Sep 2 12:04:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.pxi.spice b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.pxi.spice index 92edb6b..12a04c7 100644 --- a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.pxi.spice +++ b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxtp_4.pxi.spice -* Created: Fri Aug 28 17:25:26 2020 +* Created: Wed Sep 2 12:04:23 2020 * x_PM_SKY130_FD_SC_MS__DFXTP_4%CLK N_CLK_M1012_g N_CLK_M1028_g CLK N_CLK_c_220_n + N_CLK_c_221_n PM_SKY130_FD_SC_MS__DFXTP_4%CLK
diff --git a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.spice b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.spice index d39978b..2dbaa87 100644 --- a/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.spice +++ b/cells/dfxtp/sky130_fd_sc_ms__dfxtp_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dfxtp_4.spice -* Created: Fri Aug 28 17:25:26 2020 +* Created: Wed Sep 2 12:04:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/diode/sky130_fd_sc_ms__diode_2.lvs.report b/cells/diode/sky130_fd_sc_ms__diode_2.lvs.report new file mode 100644 index 0000000..4210b95 --- /dev/null +++ b/cells/diode/sky130_fd_sc_ms__diode_2.lvs.report
@@ -0,0 +1,497 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__diode_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__diode_2.sp ('sky130_fd_sc_ms__diode_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/diode/sky130_fd_sc_ms__diode_2.spice ('sky130_fd_sc_ms__diode_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:04:27 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # # ##################### + # # # # + # # INCORRECT # + # # # # + # # ##################### + + + Error: Different numbers of instances. + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + INCORRECT sky130_fd_sc_ms__diode_2 sky130_fd_sc_ms__diode_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # # ##################### + # # # # + # # INCORRECT # + # # # # + # # ##################### + + + Error: Different numbers of instances (see below). + +LAYOUT CELL NAME: sky130_fd_sc_ms__diode_2 +SOURCE CELL NAME: sky130_fd_sc_ms__diode_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 5 5 + + Nets: 5 5 + + Instances: 0 1 * D (2 pins): p n + 1 0 * D (2 pins): p n + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 2 1 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 5 5 + + Nets: 5 5 + + Instances: 1 0 * D (2 pins): p n + ------ ------ + Total Inst: 1 0 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INCORRECT OBJECTS +************************************************************************************************************** + + +LEGEND: +------- + + ne = Naming Error (same layout name found in source + circuit, but object was matched otherwise). + + +************************************************************************************************************** + INCORRECT INSTANCES + +DISC# LAYOUT NAME SOURCE NAME +************************************************************************************************************** + + 1 D0(0.135,0.320) D(NDIODE) ** missing instance ** + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 5 5 0 0 + + Nets: 5 5 0 0 + + Instances: 0 0 1 0 D(NDIODE) + ------- ------- --------- --------- + Total Inst: 0 0 1 0 + + +o Statistics: + + 3 passthrough layout nets were found. + 5 passthrough source nets were found. + + 1 layout instance was filtered and its pins removed from adjoining nets. + 1 source instance was filtered and its pins removed from adjoining nets. + + +o Passthrough Layout Nets And Their Ports: + + (Layout nets which are connected only to ports). + + VPWR (port: VPWR), VGND (port: VGND), VPB (port: VPB), + + +o Initial Correspondence Points: + + Ports: VNB VPB DIODE VGND VPWR + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/diode/sky130_fd_sc_ms__diode_2.pex.spice b/cells/diode/sky130_fd_sc_ms__diode_2.pex.spice index 52a2a85..475f163 100644 --- a/cells/diode/sky130_fd_sc_ms__diode_2.pex.spice +++ b/cells/diode/sky130_fd_sc_ms__diode_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__diode_2.pex.spice -* Created: Fri Aug 28 17:25:36 2020 +* Created: Wed Sep 2 12:04:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/diode/sky130_fd_sc_ms__diode_2.pxi.spice b/cells/diode/sky130_fd_sc_ms__diode_2.pxi.spice index 6f2e2c5..e5cfd2e 100644 --- a/cells/diode/sky130_fd_sc_ms__diode_2.pxi.spice +++ b/cells/diode/sky130_fd_sc_ms__diode_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__diode_2.pxi.spice -* Created: Fri Aug 28 17:25:36 2020 +* Created: Wed Sep 2 12:04:30 2020 * x_PM_SKY130_FD_SC_MS__DIODE_2%DIODE N_DIODE_D0_noxref_neg DIODE DIODE DIODE + DIODE DIODE DIODE DIODE N_DIODE_c_7_n PM_SKY130_FD_SC_MS__DIODE_2%DIODE
diff --git a/cells/diode/sky130_fd_sc_ms__diode_2.spice b/cells/diode/sky130_fd_sc_ms__diode_2.spice index e1e6987..30268a7 100644 --- a/cells/diode/sky130_fd_sc_ms__diode_2.spice +++ b/cells/diode/sky130_fd_sc_ms__diode_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__diode_2.spice -* Created: Fri Aug 28 17:25:36 2020 +* Created: Wed Sep 2 12:04:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.lvs.report b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.lvs.report new file mode 100644 index 0000000..1c4949a --- /dev/null +++ b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlclkp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlclkp_1.sp ('sky130_fd_sc_ms__dlclkp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.spice ('sky130_fd_sc_ms__dlclkp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:04:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlclkp_1 sky130_fd_sc_ms__dlclkp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlclkp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlclkp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 17 17 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 6 6 MP (4 pins) + 3 3 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 15 15 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 12 12 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 15 15 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB GATE CLK VPWR GCLK VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.pex.spice b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.pex.spice index a676d94..987dcb1 100644 --- a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.pex.spice +++ b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlclkp_1.pex.spice -* Created: Fri Aug 28 17:25:54 2020 +* Created: Wed Sep 2 12:04:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.pxi.spice b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.pxi.spice index 90f7bf6..c6e787c 100644 --- a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.pxi.spice +++ b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlclkp_1.pxi.spice -* Created: Fri Aug 28 17:25:54 2020 +* Created: Wed Sep 2 12:04:36 2020 * x_PM_SKY130_FD_SC_MS__DLCLKP_1%A_83_260# N_A_83_260#_M1019_d N_A_83_260#_M1003_d + N_A_83_260#_M1006_g N_A_83_260#_M1017_g N_A_83_260#_c_126_n
diff --git a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.spice b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.spice index e655ba6..da20136 100644 --- a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.spice +++ b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlclkp_1.spice -* Created: Fri Aug 28 17:25:54 2020 +* Created: Wed Sep 2 12:04:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.lvs.report b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.lvs.report new file mode 100644 index 0000000..9839dc8 --- /dev/null +++ b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlclkp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlclkp_2.sp ('sky130_fd_sc_ms__dlclkp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.spice ('sky130_fd_sc_ms__dlclkp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:04:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlclkp_2 sky130_fd_sc_ms__dlclkp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlclkp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__dlclkp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 17 17 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 6 6 MP (4 pins) + 3 3 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 15 15 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 12 12 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 15 15 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB GATE CLK VPWR GCLK VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.pex.spice b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.pex.spice index b68b900..f7a2195 100644 --- a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.pex.spice +++ b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlclkp_2.pex.spice -* Created: Fri Aug 28 17:26:13 2020 +* Created: Wed Sep 2 12:04:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.pxi.spice b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.pxi.spice index 6295669..3206d0c 100644 --- a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.pxi.spice +++ b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlclkp_2.pxi.spice -* Created: Fri Aug 28 17:26:13 2020 +* Created: Wed Sep 2 12:04:43 2020 * x_PM_SKY130_FD_SC_MS__DLCLKP_2%A_83_244# N_A_83_244#_M1013_d N_A_83_244#_M1000_d + N_A_83_244#_M1004_g N_A_83_244#_M1021_g N_A_83_244#_c_142_n
diff --git a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.spice b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.spice index 0ada3bf..2040484 100644 --- a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.spice +++ b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlclkp_2.spice -* Created: Fri Aug 28 17:26:13 2020 +* Created: Wed Sep 2 12:04:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.lvs.report b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.lvs.report new file mode 100644 index 0000000..7c8b9e8 --- /dev/null +++ b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlclkp_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlclkp_4.sp ('sky130_fd_sc_ms__dlclkp_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.spice ('sky130_fd_sc_ms__dlclkp_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:04:47 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlclkp_4 sky130_fd_sc_ms__dlclkp_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlclkp_4 +SOURCE CELL NAME: sky130_fd_sc_ms__dlclkp_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 17 17 + + Instances: 13 13 MN (4 pins) + 13 13 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 27 26 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 6 6 MP (4 pins) + 3 3 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 15 15 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 12 12 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 15 15 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 2. + 6 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 2. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB GATE CLK VPWR GCLK VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.pex.spice b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.pex.spice index 086fc04..c041ce0 100644 --- a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.pex.spice +++ b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlclkp_4.pex.spice -* Created: Fri Aug 28 17:26:23 2020 +* Created: Wed Sep 2 12:04:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.pxi.spice b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.pxi.spice index 1cf9afb..7931d37 100644 --- a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.pxi.spice +++ b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlclkp_4.pxi.spice -* Created: Fri Aug 28 17:26:23 2020 +* Created: Wed Sep 2 12:04:50 2020 * x_PM_SKY130_FD_SC_MS__DLCLKP_4%A_84_48# N_A_84_48#_M1018_d N_A_84_48#_M1000_d + N_A_84_48#_c_150_n N_A_84_48#_M1020_g N_A_84_48#_M1003_g N_A_84_48#_c_152_n
diff --git a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.spice b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.spice index de8295a..0b2982d 100644 --- a/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.spice +++ b/cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlclkp_4.spice -* Created: Fri Aug 28 17:26:23 2020 +* Created: Wed Sep 2 12:04:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.lvs.report b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.lvs.report new file mode 100644 index 0000000..348fce6 --- /dev/null +++ b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlrbn_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlrbn_1.sp ('sky130_fd_sc_ms__dlrbn_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.spice ('sky130_fd_sc_ms__dlrbn_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:04:53 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlrbn_1 sky130_fd_sc_ms__dlrbn_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlrbn_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlrbn_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 20 20 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 8 8 MP (4 pins) + 3 3 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 19 19 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 15 15 0 0 + + Instances: 6 6 0 0 MN(NLOWVT) + 8 8 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 19 19 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE_N RESET_B VPWR Q Q_N VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.pex.spice b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.pex.spice index a4ec448..64c854d 100644 --- a/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.pex.spice +++ b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrbn_1.pex.spice -* Created: Fri Aug 28 17:26:32 2020 +* Created: Wed Sep 2 12:04:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.pxi.spice b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.pxi.spice index fd3d88c..c2601e9 100644 --- a/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.pxi.spice +++ b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrbn_1.pxi.spice -* Created: Fri Aug 28 17:26:32 2020 +* Created: Wed Sep 2 12:04:56 2020 * x_PM_SKY130_FD_SC_MS__DLRBN_1%D N_D_c_162_n N_D_M1012_g N_D_M1008_g N_D_c_168_n + D N_D_c_165_n PM_SKY130_FD_SC_MS__DLRBN_1%D
diff --git a/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.spice b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.spice index a6fdc9c..cacff5f 100644 --- a/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.spice +++ b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrbn_1.spice -* Created: Fri Aug 28 17:26:32 2020 +* Created: Wed Sep 2 12:04:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.lvs.report b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.lvs.report new file mode 100644 index 0000000..40479c0 --- /dev/null +++ b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlrbn_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlrbn_2.sp ('sky130_fd_sc_ms__dlrbn_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.spice ('sky130_fd_sc_ms__dlrbn_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:05:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlrbn_2 sky130_fd_sc_ms__dlrbn_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlrbn_2 +SOURCE CELL NAME: sky130_fd_sc_ms__dlrbn_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 20 20 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 8 8 MP (4 pins) + 3 3 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 19 19 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 15 15 0 0 + + Instances: 6 6 0 0 MN(NLOWVT) + 8 8 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 19 19 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE_N RESET_B VPWR Q Q_N VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.pex.spice b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.pex.spice index e7e437d..6dbac08 100644 --- a/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.pex.spice +++ b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrbn_2.pex.spice -* Created: Fri Aug 28 17:26:42 2020 +* Created: Wed Sep 2 12:05:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.pxi.spice b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.pxi.spice index f38a9f0..495c313 100644 --- a/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.pxi.spice +++ b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrbn_2.pxi.spice -* Created: Fri Aug 28 17:26:42 2020 +* Created: Wed Sep 2 12:05:03 2020 * x_PM_SKY130_FD_SC_MS__DLRBN_2%D N_D_c_181_n N_D_M1012_g N_D_M1016_g N_D_c_187_n + D N_D_c_184_n PM_SKY130_FD_SC_MS__DLRBN_2%D
diff --git a/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.spice b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.spice index c624ab0..f1be522 100644 --- a/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.spice +++ b/cells/dlrbn/sky130_fd_sc_ms__dlrbn_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrbn_2.spice -* Created: Fri Aug 28 17:26:42 2020 +* Created: Wed Sep 2 12:05:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.lvs.report b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.lvs.report new file mode 100644 index 0000000..bf8b0f7 --- /dev/null +++ b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlrbp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlrbp_1.sp ('sky130_fd_sc_ms__dlrbp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.spice ('sky130_fd_sc_ms__dlrbp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:05:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlrbp_1 sky130_fd_sc_ms__dlrbp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlrbp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlrbp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 20 20 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 8 8 MP (4 pins) + 3 3 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 19 19 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 15 15 0 0 + + Instances: 6 6 0 0 MN(NLOWVT) + 8 8 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 19 19 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE RESET_B VPWR Q Q_N VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.pex.spice b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.pex.spice index 8ee0ae0..b66c639 100644 --- a/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.pex.spice +++ b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrbp_1.pex.spice -* Created: Fri Aug 28 17:27:00 2020 +* Created: Wed Sep 2 12:05:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.pxi.spice b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.pxi.spice index ab7b801..7df8ac7 100644 --- a/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.pxi.spice +++ b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrbp_1.pxi.spice -* Created: Fri Aug 28 17:27:00 2020 +* Created: Wed Sep 2 12:05:10 2020 * x_PM_SKY130_FD_SC_MS__DLRBP_1%D N_D_M1023_g N_D_M1002_g D N_D_c_167_n + PM_SKY130_FD_SC_MS__DLRBP_1%D
diff --git a/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.spice b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.spice index bef9fd4..69e56f8 100644 --- a/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.spice +++ b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrbp_1.spice -* Created: Fri Aug 28 17:27:00 2020 +* Created: Wed Sep 2 12:05:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.lvs.report b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.lvs.report new file mode 100644 index 0000000..33c9488 --- /dev/null +++ b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlrbp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlrbp_2.sp ('sky130_fd_sc_ms__dlrbp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.spice ('sky130_fd_sc_ms__dlrbp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:05:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlrbp_2 sky130_fd_sc_ms__dlrbp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlrbp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__dlrbp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 20 20 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 8 8 MP (4 pins) + 3 3 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 19 19 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 15 15 0 0 + + Instances: 6 6 0 0 MN(NLOWVT) + 8 8 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 19 19 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE RESET_B VPWR Q Q_N VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.pex.spice b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.pex.spice index c1203c5..e372d67 100644 --- a/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.pex.spice +++ b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrbp_2.pex.spice -* Created: Fri Aug 28 17:27:20 2020 +* Created: Wed Sep 2 12:05:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.pxi.spice b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.pxi.spice index 02fe48a..cf745cc 100644 --- a/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.pxi.spice +++ b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrbp_2.pxi.spice -* Created: Fri Aug 28 17:27:20 2020 +* Created: Wed Sep 2 12:05:16 2020 * x_PM_SKY130_FD_SC_MS__DLRBP_2%D N_D_M1000_g N_D_M1015_g D N_D_c_180_n + PM_SKY130_FD_SC_MS__DLRBP_2%D
diff --git a/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.spice b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.spice index 461445c..f83d1c5 100644 --- a/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.spice +++ b/cells/dlrbp/sky130_fd_sc_ms__dlrbp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrbp_2.spice -* Created: Fri Aug 28 17:27:20 2020 +* Created: Wed Sep 2 12:05:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.lvs.report b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.lvs.report new file mode 100644 index 0000000..27818ab --- /dev/null +++ b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlrtn_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlrtn_1.sp ('sky130_fd_sc_ms__dlrtn_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.spice ('sky130_fd_sc_ms__dlrtn_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:05:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlrtn_1 sky130_fd_sc_ms__dlrtn_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlrtn_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlrtn_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 18 18 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 13 13 + + Instances: 4 4 MN (4 pins) + 6 6 MP (4 pins) + 3 3 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 15 15 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 13 13 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 15 15 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE_N RESET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.pex.spice b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.pex.spice index 7d17f0a..7d6c5f8 100644 --- a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.pex.spice +++ b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtn_1.pex.spice -* Created: Fri Aug 28 17:27:30 2020 +* Created: Wed Sep 2 12:05:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.pxi.spice b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.pxi.spice index b1ac3eb..334b186 100644 --- a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.pxi.spice +++ b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtn_1.pxi.spice -* Created: Fri Aug 28 17:27:30 2020 +* Created: Wed Sep 2 12:05:23 2020 * x_PM_SKY130_FD_SC_MS__DLRTN_1%D N_D_M1013_g N_D_M1012_g D N_D_c_133_n + PM_SKY130_FD_SC_MS__DLRTN_1%D
diff --git a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.spice b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.spice index 6f00294..3d4cb92 100644 --- a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.spice +++ b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtn_1.spice -* Created: Fri Aug 28 17:27:30 2020 +* Created: Wed Sep 2 12:05:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.lvs.report b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.lvs.report new file mode 100644 index 0000000..3a6a563 --- /dev/null +++ b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlrtn_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlrtn_2.sp ('sky130_fd_sc_ms__dlrtn_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.spice ('sky130_fd_sc_ms__dlrtn_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:05:26 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlrtn_2 sky130_fd_sc_ms__dlrtn_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlrtn_2 +SOURCE CELL NAME: sky130_fd_sc_ms__dlrtn_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 18 18 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 13 13 + + Instances: 4 4 MN (4 pins) + 6 6 MP (4 pins) + 3 3 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 15 15 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 13 13 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 15 15 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE_N RESET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.pex.spice b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.pex.spice index bbcd5fa..d20da5c 100644 --- a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.pex.spice +++ b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtn_2.pex.spice -* Created: Fri Aug 28 17:27:39 2020 +* Created: Wed Sep 2 12:05:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.pxi.spice b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.pxi.spice index d2187ac..6072515 100644 --- a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.pxi.spice +++ b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtn_2.pxi.spice -* Created: Fri Aug 28 17:27:39 2020 +* Created: Wed Sep 2 12:05:30 2020 * x_PM_SKY130_FD_SC_MS__DLRTN_2%D N_D_M1017_g N_D_M1015_g D N_D_c_145_n + PM_SKY130_FD_SC_MS__DLRTN_2%D
diff --git a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.spice b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.spice index cae20b5..2fcff75 100644 --- a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.spice +++ b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtn_2.spice -* Created: Fri Aug 28 17:27:39 2020 +* Created: Wed Sep 2 12:05:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.lvs.report b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.lvs.report new file mode 100644 index 0000000..3624016 --- /dev/null +++ b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlrtn_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlrtn_4.sp ('sky130_fd_sc_ms__dlrtn_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.spice ('sky130_fd_sc_ms__dlrtn_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:05:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlrtn_4 sky130_fd_sc_ms__dlrtn_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlrtn_4 +SOURCE CELL NAME: sky130_fd_sc_ms__dlrtn_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 18 18 + + Instances: 15 15 MN (4 pins) + 15 15 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 31 30 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 13 13 + + Instances: 4 4 MN (4 pins) + 6 6 MP (4 pins) + 3 3 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 15 15 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 13 13 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 15 15 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE_N RESET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.pex.spice b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.pex.spice index 2e61d52..45f80b0 100644 --- a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.pex.spice +++ b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtn_4.pex.spice -* Created: Fri Aug 28 17:27:48 2020 +* Created: Wed Sep 2 12:05:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.pxi.spice b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.pxi.spice index f5e9050..7c18e81 100644 --- a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.pxi.spice +++ b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtn_4.pxi.spice -* Created: Fri Aug 28 17:27:48 2020 +* Created: Wed Sep 2 12:05:36 2020 * x_PM_SKY130_FD_SC_MS__DLRTN_4%D N_D_M1024_g N_D_M1013_g D N_D_c_174_n + PM_SKY130_FD_SC_MS__DLRTN_4%D
diff --git a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.spice b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.spice index d9a960c..45747b8 100644 --- a/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.spice +++ b/cells/dlrtn/sky130_fd_sc_ms__dlrtn_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtn_4.spice -* Created: Fri Aug 28 17:27:48 2020 +* Created: Wed Sep 2 12:05:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.lvs.report b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.lvs.report new file mode 100644 index 0000000..26ebd4a --- /dev/null +++ b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlrtp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlrtp_1.sp ('sky130_fd_sc_ms__dlrtp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.spice ('sky130_fd_sc_ms__dlrtp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:05:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlrtp_1 sky130_fd_sc_ms__dlrtp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlrtp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlrtp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 18 18 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 13 13 + + Instances: 4 4 MN (4 pins) + 6 6 MP (4 pins) + 3 3 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 15 15 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 13 13 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 15 15 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE RESET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.pex.spice b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.pex.spice index 909f7d7..8b5a8b7 100644 --- a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.pex.spice +++ b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtp_1.pex.spice -* Created: Fri Aug 28 17:28:06 2020 +* Created: Wed Sep 2 12:05:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.pxi.spice b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.pxi.spice index cfd50cc..2c4080a 100644 --- a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.pxi.spice +++ b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtp_1.pxi.spice -* Created: Fri Aug 28 17:28:06 2020 +* Created: Wed Sep 2 12:05:43 2020 * x_PM_SKY130_FD_SC_MS__DLRTP_1%D N_D_M1008_g N_D_M1017_g D N_D_c_137_n + N_D_c_138_n PM_SKY130_FD_SC_MS__DLRTP_1%D
diff --git a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.spice b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.spice index 99326f3..64481ed 100644 --- a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.spice +++ b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtp_1.spice -* Created: Fri Aug 28 17:28:06 2020 +* Created: Wed Sep 2 12:05:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.lvs.report b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.lvs.report new file mode 100644 index 0000000..3f13be6 --- /dev/null +++ b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlrtp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlrtp_2.sp ('sky130_fd_sc_ms__dlrtp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.spice ('sky130_fd_sc_ms__dlrtp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:05:47 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlrtp_2 sky130_fd_sc_ms__dlrtp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlrtp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__dlrtp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 18 18 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 13 13 + + Instances: 4 4 MN (4 pins) + 6 6 MP (4 pins) + 3 3 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 15 15 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 13 13 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 15 15 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE RESET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.pex.spice b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.pex.spice index 04b186b..391b381 100644 --- a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.pex.spice +++ b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtp_2.pex.spice -* Created: Fri Aug 28 17:28:26 2020 +* Created: Wed Sep 2 12:05:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.pxi.spice b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.pxi.spice index 58b8396..5494c89 100644 --- a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.pxi.spice +++ b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtp_2.pxi.spice -* Created: Fri Aug 28 17:28:26 2020 +* Created: Wed Sep 2 12:05:50 2020 * x_PM_SKY130_FD_SC_MS__DLRTP_2%D N_D_M1002_g N_D_M1012_g D N_D_c_145_n + N_D_c_146_n PM_SKY130_FD_SC_MS__DLRTP_2%D
diff --git a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.spice b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.spice index a76b8d2..d391bb0 100644 --- a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.spice +++ b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtp_2.spice -* Created: Fri Aug 28 17:28:26 2020 +* Created: Wed Sep 2 12:05:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.lvs.report b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.lvs.report new file mode 100644 index 0000000..1de0202 --- /dev/null +++ b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlrtp_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlrtp_4.sp ('sky130_fd_sc_ms__dlrtp_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.spice ('sky130_fd_sc_ms__dlrtp_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:05:53 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlrtp_4 sky130_fd_sc_ms__dlrtp_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlrtp_4 +SOURCE CELL NAME: sky130_fd_sc_ms__dlrtp_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 18 18 + + Instances: 15 15 MN (4 pins) + 15 15 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 31 30 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 13 13 + + Instances: 4 4 MN (4 pins) + 6 6 MP (4 pins) + 3 3 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 15 15 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 13 13 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 15 15 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE RESET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.pex.spice b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.pex.spice index 17da253..6901c72 100644 --- a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.pex.spice +++ b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtp_4.pex.spice -* Created: Fri Aug 28 17:28:36 2020 +* Created: Wed Sep 2 12:05:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.pxi.spice b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.pxi.spice index 470c6f9..eea1b41 100644 --- a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.pxi.spice +++ b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtp_4.pxi.spice -* Created: Fri Aug 28 17:28:36 2020 +* Created: Wed Sep 2 12:05:56 2020 * x_PM_SKY130_FD_SC_MS__DLRTP_4%D N_D_M1000_g N_D_M1017_g D N_D_c_184_n + N_D_c_185_n PM_SKY130_FD_SC_MS__DLRTP_4%D
diff --git a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.spice b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.spice index 2104422..63505eb 100644 --- a/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.spice +++ b/cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlrtp_4.spice -* Created: Fri Aug 28 17:28:36 2020 +* Created: Wed Sep 2 12:05:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.lvs.report b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.lvs.report new file mode 100644 index 0000000..e0e77c0 --- /dev/null +++ b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlxbn_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlxbn_1.sp ('sky130_fd_sc_ms__dlxbn_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.spice ('sky130_fd_sc_ms__dlxbn_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:06:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlxbn_1 sky130_fd_sc_ms__dlxbn_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlxbn_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlxbn_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 18 18 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 14 14 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 18 18 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 14 14 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 7 7 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 18 18 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE_N VPWR Q Q_N VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.pex.spice b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.pex.spice index eac2e3c..643e0c1 100644 --- a/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.pex.spice +++ b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxbn_1.pex.spice -* Created: Fri Aug 28 17:28:44 2020 +* Created: Wed Sep 2 12:06:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.pxi.spice b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.pxi.spice index f11cb53..a0f5e5b 100644 --- a/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.pxi.spice +++ b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxbn_1.pxi.spice -* Created: Fri Aug 28 17:28:44 2020 +* Created: Wed Sep 2 12:06:03 2020 * x_PM_SKY130_FD_SC_MS__DLXBN_1%D N_D_M1020_g N_D_c_143_n N_D_M1000_g N_D_c_149_n + D N_D_c_145_n N_D_c_146_n PM_SKY130_FD_SC_MS__DLXBN_1%D
diff --git a/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.spice b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.spice index ff88e0f..776b8f2 100644 --- a/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.spice +++ b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxbn_1.spice -* Created: Fri Aug 28 17:28:44 2020 +* Created: Wed Sep 2 12:06:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.lvs.report b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.lvs.report new file mode 100644 index 0000000..118eeca --- /dev/null +++ b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlxbn_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlxbn_2.sp ('sky130_fd_sc_ms__dlxbn_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.spice ('sky130_fd_sc_ms__dlxbn_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:06:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlxbn_2 sky130_fd_sc_ms__dlxbn_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlxbn_2 +SOURCE CELL NAME: sky130_fd_sc_ms__dlxbn_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 18 18 + + Instances: 13 13 MN (4 pins) + 13 13 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 27 26 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 14 14 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 18 18 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 14 14 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 7 7 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 18 18 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE_N VPWR Q Q_N VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.pex.spice b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.pex.spice index 1db30c4..010c78b 100644 --- a/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.pex.spice +++ b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxbn_2.pex.spice -* Created: Fri Aug 28 17:28:55 2020 +* Created: Wed Sep 2 12:06:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.pxi.spice b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.pxi.spice index e0a17e7..9fbdede 100644 --- a/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.pxi.spice +++ b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxbn_2.pxi.spice -* Created: Fri Aug 28 17:28:55 2020 +* Created: Wed Sep 2 12:06:10 2020 * x_PM_SKY130_FD_SC_MS__DLXBN_2%D N_D_M1018_g N_D_M1020_g D N_D_c_169_n + PM_SKY130_FD_SC_MS__DLXBN_2%D
diff --git a/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.spice b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.spice index 5b1cc96..bbe7b96 100644 --- a/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.spice +++ b/cells/dlxbn/sky130_fd_sc_ms__dlxbn_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxbn_2.spice -* Created: Fri Aug 28 17:28:55 2020 +* Created: Wed Sep 2 12:06:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.lvs.report b/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.lvs.report new file mode 100644 index 0000000..59a9fca --- /dev/null +++ b/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlxbp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlxbp_1.sp ('sky130_fd_sc_ms__dlxbp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.spice ('sky130_fd_sc_ms__dlxbp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:06:14 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlxbp_1 sky130_fd_sc_ms__dlxbp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlxbp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlxbp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 18 18 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 14 14 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 18 18 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 14 14 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 7 7 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 18 18 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE VPWR Q Q_N VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.pex.spice b/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.pex.spice index 9a57a0d..b159337 100644 --- a/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.pex.spice +++ b/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxbp_1.pex.spice -* Created: Fri Aug 28 17:29:13 2020 +* Created: Wed Sep 2 12:06:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.pxi.spice b/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.pxi.spice index dab88c3..eacebd2 100644 --- a/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.pxi.spice +++ b/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxbp_1.pxi.spice -* Created: Fri Aug 28 17:29:13 2020 +* Created: Wed Sep 2 12:06:17 2020 * x_PM_SKY130_FD_SC_MS__DLXBP_1%D N_D_c_146_n N_D_M1010_g N_D_M1005_g N_D_c_152_n + D N_D_c_148_n N_D_c_149_n PM_SKY130_FD_SC_MS__DLXBP_1%D
diff --git a/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.spice b/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.spice index b0e0322..b7abda6 100644 --- a/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.spice +++ b/cells/dlxbp/sky130_fd_sc_ms__dlxbp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxbp_1.spice -* Created: Fri Aug 28 17:29:13 2020 +* Created: Wed Sep 2 12:06:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.lvs.report b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.lvs.report new file mode 100644 index 0000000..2a274e4 --- /dev/null +++ b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlxtn_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlxtn_1.sp ('sky130_fd_sc_ms__dlxtn_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.spice ('sky130_fd_sc_ms__dlxtn_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:06:21 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlxtn_1 sky130_fd_sc_ms__dlxtn_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlxtn_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlxtn_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 16 16 + + Instances: 9 9 MN (4 pins) + 9 9 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 19 18 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 12 12 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 14 14 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 12 12 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 14 14 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE_N VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.pex.spice b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.pex.spice index ec9a67e..e118ba1 100644 --- a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.pex.spice +++ b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxtn_1.pex.spice -* Created: Fri Aug 28 17:29:32 2020 +* Created: Wed Sep 2 12:06:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.pxi.spice b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.pxi.spice index 16a19f4..41f48db 100644 --- a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.pxi.spice +++ b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxtn_1.pxi.spice -* Created: Fri Aug 28 17:29:32 2020 +* Created: Wed Sep 2 12:06:24 2020 * x_PM_SKY130_FD_SC_MS__DLXTN_1%D N_D_c_126_n N_D_M1005_g N_D_M1014_g D + N_D_c_129_n PM_SKY130_FD_SC_MS__DLXTN_1%D
diff --git a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.spice b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.spice index 68341cd..bb7209b 100644 --- a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.spice +++ b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxtn_1.spice -* Created: Fri Aug 28 17:29:32 2020 +* Created: Wed Sep 2 12:06:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.lvs.report b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.lvs.report new file mode 100644 index 0000000..b74f94b --- /dev/null +++ b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlxtn_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlxtn_2.sp ('sky130_fd_sc_ms__dlxtn_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.spice ('sky130_fd_sc_ms__dlxtn_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:06:28 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlxtn_2 sky130_fd_sc_ms__dlxtn_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlxtn_2 +SOURCE CELL NAME: sky130_fd_sc_ms__dlxtn_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 16 16 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 12 12 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 14 14 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 12 12 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 14 14 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE_N VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.pex.spice b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.pex.spice index 7aa71f5..c7b478f 100644 --- a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.pex.spice +++ b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxtn_2.pex.spice -* Created: Fri Aug 28 17:29:42 2020 +* Created: Wed Sep 2 12:06:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.pxi.spice b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.pxi.spice index 5d6330c..afa0837 100644 --- a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.pxi.spice +++ b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxtn_2.pxi.spice -* Created: Fri Aug 28 17:29:42 2020 +* Created: Wed Sep 2 12:06:31 2020 * x_PM_SKY130_FD_SC_MS__DLXTN_2%D N_D_M1016_g N_D_M1001_g D N_D_c_135_n + N_D_c_136_n PM_SKY130_FD_SC_MS__DLXTN_2%D
diff --git a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.spice b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.spice index 10a60a1..3340fc7 100644 --- a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.spice +++ b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxtn_2.spice -* Created: Fri Aug 28 17:29:42 2020 +* Created: Wed Sep 2 12:06:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.lvs.report b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.lvs.report new file mode 100644 index 0000000..31ee9e3 --- /dev/null +++ b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlxtn_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlxtn_4.sp ('sky130_fd_sc_ms__dlxtn_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.spice ('sky130_fd_sc_ms__dlxtn_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:06:35 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlxtn_4 sky130_fd_sc_ms__dlxtn_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlxtn_4 +SOURCE CELL NAME: sky130_fd_sc_ms__dlxtn_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 16 16 + + Instances: 13 13 MN (4 pins) + 13 13 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 27 26 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 12 12 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 14 14 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 12 12 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 14 14 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 4. + 8 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 4. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE_N VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.pex.spice b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.pex.spice index 15635fa..679eab3 100644 --- a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.pex.spice +++ b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxtn_4.pex.spice -* Created: Fri Aug 28 17:29:51 2020 +* Created: Wed Sep 2 12:06:38 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.pxi.spice b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.pxi.spice index 9ad587c..802fbd4 100644 --- a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.pxi.spice +++ b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxtn_4.pxi.spice -* Created: Fri Aug 28 17:29:51 2020 +* Created: Wed Sep 2 12:06:38 2020 * x_PM_SKY130_FD_SC_MS__DLXTN_4%D N_D_M1010_g N_D_M1011_g D N_D_c_158_n + N_D_c_159_n PM_SKY130_FD_SC_MS__DLXTN_4%D
diff --git a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.spice b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.spice index da89773..5eec36e 100644 --- a/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.spice +++ b/cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxtn_4.spice -* Created: Fri Aug 28 17:29:51 2020 +* Created: Wed Sep 2 12:06:38 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.lvs.report b/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.lvs.report new file mode 100644 index 0000000..02d07a5 --- /dev/null +++ b/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlxtp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlxtp_1.sp ('sky130_fd_sc_ms__dlxtp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.spice ('sky130_fd_sc_ms__dlxtp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:06:42 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlxtp_1 sky130_fd_sc_ms__dlxtp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlxtp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlxtp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 16 16 + + Instances: 9 9 MN (4 pins) + 9 9 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 19 18 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 12 12 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 14 14 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 12 12 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 14 14 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D GATE VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.pex.spice b/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.pex.spice index b2a3b32..8fa8b77 100644 --- a/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.pex.spice +++ b/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxtp_1.pex.spice -* Created: Fri Aug 28 17:30:01 2020 +* Created: Wed Sep 2 12:06:45 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.pxi.spice b/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.pxi.spice index f31b0ad..2e6eb57 100644 --- a/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.pxi.spice +++ b/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxtp_1.pxi.spice -* Created: Fri Aug 28 17:30:01 2020 +* Created: Wed Sep 2 12:06:45 2020 * x_PM_SKY130_FD_SC_MS__DLXTP_1%D N_D_M1008_g N_D_M1006_g N_D_c_148_n N_D_c_153_n + D D N_D_c_150_n PM_SKY130_FD_SC_MS__DLXTP_1%D
diff --git a/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.spice b/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.spice index 09b7fd9..3b6a35f 100644 --- a/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.spice +++ b/cells/dlxtp/sky130_fd_sc_ms__dlxtp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlxtp_1.spice -* Created: Fri Aug 28 17:30:01 2020 +* Created: Wed Sep 2 12:06:45 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.lvs.report b/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.lvs.report new file mode 100644 index 0000000..cb830e7 --- /dev/null +++ b/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlygate4sd1_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlygate4sd1_1.sp ('sky130_fd_sc_ms__dlygate4sd1_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.spice ('sky130_fd_sc_ms__dlygate4sd1_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:06:49 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlygate4sd1_1 sky130_fd_sc_ms__dlygate4sd1_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlygate4sd1_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlygate4sd1_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.pex.spice b/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.pex.spice index 4859c30..beceec9 100644 --- a/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.pex.spice +++ b/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlygate4sd1_1.pex.spice -* Created: Fri Aug 28 17:30:19 2020 +* Created: Wed Sep 2 12:06:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.pxi.spice b/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.pxi.spice index b19a5c0..c56d672 100644 --- a/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.pxi.spice +++ b/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlygate4sd1_1.pxi.spice -* Created: Fri Aug 28 17:30:19 2020 +* Created: Wed Sep 2 12:06:52 2020 * x_PM_SKY130_FD_SC_MS__DLYGATE4SD1_1%A N_A_M1005_g N_A_M1004_g A A N_A_c_68_n + PM_SKY130_FD_SC_MS__DLYGATE4SD1_1%A
diff --git a/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.spice b/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.spice index 6af1fbc..134e2ec 100644 --- a/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.spice +++ b/cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlygate4sd1_1.spice -* Created: Fri Aug 28 17:30:19 2020 +* Created: Wed Sep 2 12:06:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.lvs.report b/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.lvs.report new file mode 100644 index 0000000..2a6be68 --- /dev/null +++ b/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlygate4sd2_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlygate4sd2_1.sp ('sky130_fd_sc_ms__dlygate4sd2_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.spice ('sky130_fd_sc_ms__dlygate4sd2_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:06:55 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlygate4sd2_1 sky130_fd_sc_ms__dlygate4sd2_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlygate4sd2_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlygate4sd2_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.pex.spice b/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.pex.spice index 29b9956..80f826e 100644 --- a/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.pex.spice +++ b/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlygate4sd2_1.pex.spice -* Created: Fri Aug 28 17:30:39 2020 +* Created: Wed Sep 2 12:06:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.pxi.spice b/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.pxi.spice index bbd725b..fbaf94e 100644 --- a/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.pxi.spice +++ b/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlygate4sd2_1.pxi.spice -* Created: Fri Aug 28 17:30:39 2020 +* Created: Wed Sep 2 12:06:58 2020 * x_PM_SKY130_FD_SC_MS__DLYGATE4SD2_1%A N_A_M1003_g N_A_M1001_g A A N_A_c_67_n + PM_SKY130_FD_SC_MS__DLYGATE4SD2_1%A
diff --git a/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.spice b/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.spice index 51eab7d..8aea4bb 100644 --- a/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.spice +++ b/cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlygate4sd2_1.spice -* Created: Fri Aug 28 17:30:39 2020 +* Created: Wed Sep 2 12:06:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.lvs.report b/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.lvs.report new file mode 100644 index 0000000..e3683f5 --- /dev/null +++ b/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlygate4sd3_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlygate4sd3_1.sp ('sky130_fd_sc_ms__dlygate4sd3_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.spice ('sky130_fd_sc_ms__dlygate4sd3_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:07:02 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlygate4sd3_1 sky130_fd_sc_ms__dlygate4sd3_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlygate4sd3_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlygate4sd3_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.pex.spice b/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.pex.spice index 5a2e947..f5eb869 100644 --- a/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.pex.spice +++ b/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlygate4sd3_1.pex.spice -* Created: Fri Aug 28 17:30:49 2020 +* Created: Wed Sep 2 12:07:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.pxi.spice b/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.pxi.spice index 4526abe..c9a9080 100644 --- a/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.pxi.spice +++ b/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlygate4sd3_1.pxi.spice -* Created: Fri Aug 28 17:30:49 2020 +* Created: Wed Sep 2 12:07:05 2020 * x_PM_SKY130_FD_SC_MS__DLYGATE4SD3_1%A N_A_M1005_g N_A_M1004_g A A N_A_c_66_n + PM_SKY130_FD_SC_MS__DLYGATE4SD3_1%A
diff --git a/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.spice b/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.spice index d3f76da..882f186 100644 --- a/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.spice +++ b/cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlygate4sd3_1.spice -* Created: Fri Aug 28 17:30:49 2020 +* Created: Wed Sep 2 12:07:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.lvs.report b/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.lvs.report new file mode 100644 index 0000000..2be963e --- /dev/null +++ b/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlymetal6s2s_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlymetal6s2s_1.sp ('sky130_fd_sc_ms__dlymetal6s2s_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.spice ('sky130_fd_sc_ms__dlymetal6s2s_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:07:08 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlymetal6s2s_1 sky130_fd_sc_ms__dlymetal6s2s_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlymetal6s2s_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlymetal6s2s_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 11 11 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 11 11 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + ------ ------ + Total Inst: 12 12 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 11 11 0 0 + + Instances: 6 6 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 12 12 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.pex.spice b/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.pex.spice index 513f19b..3c5809e 100644 --- a/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.pex.spice +++ b/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlymetal6s2s_1.pex.spice -* Created: Fri Aug 28 17:30:58 2020 +* Created: Wed Sep 2 12:07:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.pxi.spice b/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.pxi.spice index d18bb46..e79b278 100644 --- a/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.pxi.spice +++ b/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlymetal6s2s_1.pxi.spice -* Created: Fri Aug 28 17:30:58 2020 +* Created: Wed Sep 2 12:07:11 2020 * x_PM_SKY130_FD_SC_MS__DLYMETAL6S2S_1%A N_A_M1000_g N_A_M1006_g A N_A_c_95_n + N_A_c_96_n PM_SKY130_FD_SC_MS__DLYMETAL6S2S_1%A
diff --git a/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.spice b/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.spice index 4c74d89..7234b2a 100644 --- a/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.spice +++ b/cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlymetal6s2s_1.spice -* Created: Fri Aug 28 17:30:58 2020 +* Created: Wed Sep 2 12:07:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.lvs.report b/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.lvs.report new file mode 100644 index 0000000..80ee371 --- /dev/null +++ b/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlymetal6s4s_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlymetal6s4s_1.sp ('sky130_fd_sc_ms__dlymetal6s4s_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.spice ('sky130_fd_sc_ms__dlymetal6s4s_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:07:15 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlymetal6s4s_1 sky130_fd_sc_ms__dlymetal6s4s_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlymetal6s4s_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlymetal6s4s_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 11 11 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 11 11 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + ------ ------ + Total Inst: 12 12 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 11 11 0 0 + + Instances: 6 6 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 12 12 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.pex.spice b/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.pex.spice index cf4a922..06af38e 100644 --- a/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.pex.spice +++ b/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlymetal6s4s_1.pex.spice -* Created: Fri Aug 28 17:31:08 2020 +* Created: Wed Sep 2 12:07:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.pxi.spice b/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.pxi.spice index 4d27424..48f165c 100644 --- a/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.pxi.spice +++ b/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlymetal6s4s_1.pxi.spice -* Created: Fri Aug 28 17:31:08 2020 +* Created: Wed Sep 2 12:07:18 2020 * x_PM_SKY130_FD_SC_MS__DLYMETAL6S4S_1%A N_A_M1000_g N_A_M1006_g A N_A_c_96_n + N_A_c_97_n PM_SKY130_FD_SC_MS__DLYMETAL6S4S_1%A
diff --git a/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.spice b/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.spice index 8d84c6f..b390961 100644 --- a/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.spice +++ b/cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlymetal6s4s_1.spice -* Created: Fri Aug 28 17:31:08 2020 +* Created: Wed Sep 2 12:07:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.lvs.report b/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.lvs.report new file mode 100644 index 0000000..95fd1bd --- /dev/null +++ b/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__dlymetal6s6s_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__dlymetal6s6s_1.sp ('sky130_fd_sc_ms__dlymetal6s6s_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.spice ('sky130_fd_sc_ms__dlymetal6s6s_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:07:22 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__dlymetal6s6s_1 sky130_fd_sc_ms__dlymetal6s6s_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__dlymetal6s6s_1 +SOURCE CELL NAME: sky130_fd_sc_ms__dlymetal6s6s_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 11 11 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 11 11 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + ------ ------ + Total Inst: 12 12 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 11 11 0 0 + + Instances: 6 6 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 12 12 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.pex.spice b/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.pex.spice index e5187d1..50e4a5e 100644 --- a/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.pex.spice +++ b/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlymetal6s6s_1.pex.spice -* Created: Fri Aug 28 17:31:25 2020 +* Created: Wed Sep 2 12:07:25 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.pxi.spice b/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.pxi.spice index 70eb69e..4b2100e 100644 --- a/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.pxi.spice +++ b/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlymetal6s6s_1.pxi.spice -* Created: Fri Aug 28 17:31:25 2020 +* Created: Wed Sep 2 12:07:25 2020 * x_PM_SKY130_FD_SC_MS__DLYMETAL6S6S_1%A N_A_M1000_g N_A_M1006_g A N_A_c_95_n + N_A_c_96_n PM_SKY130_FD_SC_MS__DLYMETAL6S6S_1%A
diff --git a/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.spice b/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.spice index 55725c0..83433ba 100644 --- a/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.spice +++ b/cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__dlymetal6s6s_1.spice -* Created: Fri Aug 28 17:31:25 2020 +* Created: Wed Sep 2 12:07:25 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_1.lvs.report b/cells/ebufn/sky130_fd_sc_ms__ebufn_1.lvs.report new file mode 100644 index 0000000..73f796e --- /dev/null +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__ebufn_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__ebufn_1.sp ('sky130_fd_sc_ms__ebufn_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/ebufn/sky130_fd_sc_ms__ebufn_1.spice ('sky130_fd_sc_ms__ebufn_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:07:28 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__ebufn_1 sky130_fd_sc_ms__ebufn_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__ebufn_1 +SOURCE CELL NAME: sky130_fd_sc_ms__ebufn_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB TE_B A VPWR Z VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_1.pex.spice b/cells/ebufn/sky130_fd_sc_ms__ebufn_1.pex.spice index 7435313..fb0fca4 100644 --- a/cells/ebufn/sky130_fd_sc_ms__ebufn_1.pex.spice +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ebufn_1.pex.spice -* Created: Fri Aug 28 17:31:45 2020 +* Created: Wed Sep 2 12:07:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_1.pxi.spice b/cells/ebufn/sky130_fd_sc_ms__ebufn_1.pxi.spice index 3e6860e..bb9c7f9 100644 --- a/cells/ebufn/sky130_fd_sc_ms__ebufn_1.pxi.spice +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ebufn_1.pxi.spice -* Created: Fri Aug 28 17:31:45 2020 +* Created: Wed Sep 2 12:07:32 2020 * x_PM_SKY130_FD_SC_MS__EBUFN_1%TE_B N_TE_B_M1000_g N_TE_B_M1007_g N_TE_B_c_72_n + N_TE_B_c_73_n N_TE_B_c_79_n N_TE_B_M1001_g N_TE_B_c_80_n N_TE_B_c_81_n
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_1.spice b/cells/ebufn/sky130_fd_sc_ms__ebufn_1.spice index 3b71529..8a90d54 100644 --- a/cells/ebufn/sky130_fd_sc_ms__ebufn_1.spice +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ebufn_1.spice -* Created: Fri Aug 28 17:31:45 2020 +* Created: Wed Sep 2 12:07:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_2.lvs.report b/cells/ebufn/sky130_fd_sc_ms__ebufn_2.lvs.report new file mode 100644 index 0000000..6eba195 --- /dev/null +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__ebufn_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__ebufn_2.sp ('sky130_fd_sc_ms__ebufn_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/ebufn/sky130_fd_sc_ms__ebufn_2.spice ('sky130_fd_sc_ms__ebufn_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:07:35 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__ebufn_2 sky130_fd_sc_ms__ebufn_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__ebufn_2 +SOURCE CELL NAME: sky130_fd_sc_ms__ebufn_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 11 11 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB TE_B A Z VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_2.pex.spice b/cells/ebufn/sky130_fd_sc_ms__ebufn_2.pex.spice index 0744878..805c7bb 100644 --- a/cells/ebufn/sky130_fd_sc_ms__ebufn_2.pex.spice +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ebufn_2.pex.spice -* Created: Fri Aug 28 17:31:55 2020 +* Created: Wed Sep 2 12:07:38 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_2.pxi.spice b/cells/ebufn/sky130_fd_sc_ms__ebufn_2.pxi.spice index 1d11a95..4e7a7b5 100644 --- a/cells/ebufn/sky130_fd_sc_ms__ebufn_2.pxi.spice +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ebufn_2.pxi.spice -* Created: Fri Aug 28 17:31:55 2020 +* Created: Wed Sep 2 12:07:38 2020 * x_PM_SKY130_FD_SC_MS__EBUFN_2%A_84_48# N_A_84_48#_M1000_d N_A_84_48#_M1010_d + N_A_84_48#_M1008_g N_A_84_48#_M1005_g N_A_84_48#_M1009_g N_A_84_48#_M1007_g
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_2.spice b/cells/ebufn/sky130_fd_sc_ms__ebufn_2.spice index 34fd3c7..2b3c030 100644 --- a/cells/ebufn/sky130_fd_sc_ms__ebufn_2.spice +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ebufn_2.spice -* Created: Fri Aug 28 17:31:55 2020 +* Created: Wed Sep 2 12:07:38 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_4.lvs.report b/cells/ebufn/sky130_fd_sc_ms__ebufn_4.lvs.report new file mode 100644 index 0000000..4133599 --- /dev/null +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__ebufn_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__ebufn_4.sp ('sky130_fd_sc_ms__ebufn_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/ebufn/sky130_fd_sc_ms__ebufn_4.spice ('sky130_fd_sc_ms__ebufn_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:07:42 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__ebufn_4 sky130_fd_sc_ms__ebufn_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__ebufn_4 +SOURCE CELL NAME: sky130_fd_sc_ms__ebufn_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 11 11 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 4. + 12 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 4. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A TE_B VPWR Z VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_4.pex.spice b/cells/ebufn/sky130_fd_sc_ms__ebufn_4.pex.spice index f9c13ba..f2a2a52 100644 --- a/cells/ebufn/sky130_fd_sc_ms__ebufn_4.pex.spice +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ebufn_4.pex.spice -* Created: Fri Aug 28 17:32:03 2020 +* Created: Wed Sep 2 12:07:45 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_4.pxi.spice b/cells/ebufn/sky130_fd_sc_ms__ebufn_4.pxi.spice index dd5cd15..4c9597e 100644 --- a/cells/ebufn/sky130_fd_sc_ms__ebufn_4.pxi.spice +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ebufn_4.pxi.spice -* Created: Fri Aug 28 17:32:03 2020 +* Created: Wed Sep 2 12:07:45 2020 * x_PM_SKY130_FD_SC_MS__EBUFN_4%A N_A_M1006_g N_A_M1004_g A N_A_c_131_n + PM_SKY130_FD_SC_MS__EBUFN_4%A
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_4.spice b/cells/ebufn/sky130_fd_sc_ms__ebufn_4.spice index dc57df6..857f3fa 100644 --- a/cells/ebufn/sky130_fd_sc_ms__ebufn_4.spice +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ebufn_4.spice -* Created: Fri Aug 28 17:32:03 2020 +* Created: Wed Sep 2 12:07:45 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_8.lvs.report b/cells/ebufn/sky130_fd_sc_ms__ebufn_8.lvs.report new file mode 100644 index 0000000..5442b81 --- /dev/null +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_8.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__ebufn_8.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__ebufn_8.sp ('sky130_fd_sc_ms__ebufn_8') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/ebufn/sky130_fd_sc_ms__ebufn_8.spice ('sky130_fd_sc_ms__ebufn_8') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:07:49 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__ebufn_8 sky130_fd_sc_ms__ebufn_8 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__ebufn_8 +SOURCE CELL NAME: sky130_fd_sc_ms__ebufn_8 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 11 11 + + Instances: 19 19 MN (4 pins) + 19 19 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 39 38 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 36 layout mos transistors were reduced to 6. + 30 mos transistors were deleted by parallel reduction. + 36 source mos transistors were reduced to 6. + 30 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB TE_B A Z VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_8.pex.spice b/cells/ebufn/sky130_fd_sc_ms__ebufn_8.pex.spice index 9c65572..744ad3c 100644 --- a/cells/ebufn/sky130_fd_sc_ms__ebufn_8.pex.spice +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_8.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ebufn_8.pex.spice -* Created: Fri Aug 28 17:32:13 2020 +* Created: Wed Sep 2 12:07:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_8.pxi.spice b/cells/ebufn/sky130_fd_sc_ms__ebufn_8.pxi.spice index 6a8e04d..e0e553c 100644 --- a/cells/ebufn/sky130_fd_sc_ms__ebufn_8.pxi.spice +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_8.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ebufn_8.pxi.spice -* Created: Fri Aug 28 17:32:13 2020 +* Created: Wed Sep 2 12:07:52 2020 * x_PM_SKY130_FD_SC_MS__EBUFN_8%A_84_48# N_A_84_48#_M1011_d N_A_84_48#_M1026_d + N_A_84_48#_M1007_g N_A_84_48#_M1001_g N_A_84_48#_M1013_g N_A_84_48#_M1002_g
diff --git a/cells/ebufn/sky130_fd_sc_ms__ebufn_8.spice b/cells/ebufn/sky130_fd_sc_ms__ebufn_8.spice index 377fb4f..eab5a46 100644 --- a/cells/ebufn/sky130_fd_sc_ms__ebufn_8.spice +++ b/cells/ebufn/sky130_fd_sc_ms__ebufn_8.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ebufn_8.spice -* Created: Fri Aug 28 17:32:13 2020 +* Created: Wed Sep 2 12:07:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.lvs.report b/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.lvs.report new file mode 100644 index 0000000..5858dee --- /dev/null +++ b/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__edfxbp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__edfxbp_1.sp ('sky130_fd_sc_ms__edfxbp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.spice ('sky130_fd_sc_ms__edfxbp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:07:56 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__edfxbp_1 sky130_fd_sc_ms__edfxbp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__edfxbp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__edfxbp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 27 27 + + Instances: 18 18 MN (4 pins) + 18 18 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 37 36 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 17 17 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 5 5 SMN2 (4 pins) + 5 5 SMP2 (4 pins) + ------ ------ + Total Inst: 26 26 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 17 17 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 8 8 0 0 MP(PSHORT) + 5 5 0 0 SMN2 + 5 5 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 26 26 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D DE CLK VPWR Q Q_N VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.pex.spice b/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.pex.spice index b009c10..789fb34 100644 --- a/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.pex.spice +++ b/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__edfxbp_1.pex.spice -* Created: Fri Aug 28 17:32:31 2020 +* Created: Wed Sep 2 12:07:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.pxi.spice b/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.pxi.spice index a576ccb..a7ff7e1 100644 --- a/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.pxi.spice +++ b/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__edfxbp_1.pxi.spice -* Created: Fri Aug 28 17:32:31 2020 +* Created: Wed Sep 2 12:07:59 2020 * x_PM_SKY130_FD_SC_MS__EDFXBP_1%D N_D_c_287_n N_D_M1027_g N_D_M1032_g D D + N_D_c_289_n N_D_c_290_n N_D_c_294_n PM_SKY130_FD_SC_MS__EDFXBP_1%D
diff --git a/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.spice b/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.spice index 4b8cc1e..e4a16b5 100644 --- a/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.spice +++ b/cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__edfxbp_1.spice -* Created: Fri Aug 28 17:32:31 2020 +* Created: Wed Sep 2 12:07:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.lvs.report b/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.lvs.report new file mode 100644 index 0000000..2a64a5d --- /dev/null +++ b/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__edfxtp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__edfxtp_1.sp ('sky130_fd_sc_ms__edfxtp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.spice ('sky130_fd_sc_ms__edfxtp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:08:02 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__edfxtp_1 sky130_fd_sc_ms__edfxtp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__edfxtp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__edfxtp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 26 26 + + Instances: 17 17 MN (4 pins) + 17 17 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 35 34 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 16 16 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 5 5 SMN2 (4 pins) + 5 5 SMP2 (4 pins) + ------ ------ + Total Inst: 24 24 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 16 16 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 7 7 0 0 MP(PSHORT) + 5 5 0 0 SMN2 + 5 5 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 24 24 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D DE CLK VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.pex.spice b/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.pex.spice index 6107d26..7c38759 100644 --- a/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.pex.spice +++ b/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__edfxtp_1.pex.spice -* Created: Fri Aug 28 17:32:51 2020 +* Created: Wed Sep 2 12:08:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.pxi.spice b/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.pxi.spice index bc39ca3..ed0a8af 100644 --- a/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.pxi.spice +++ b/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__edfxtp_1.pxi.spice -* Created: Fri Aug 28 17:32:51 2020 +* Created: Wed Sep 2 12:08:05 2020 * x_PM_SKY130_FD_SC_MS__EDFXTP_1%D N_D_M1008_g N_D_M1009_g D D N_D_c_262_n + N_D_c_263_n N_D_c_264_n N_D_c_268_n PM_SKY130_FD_SC_MS__EDFXTP_1%D
diff --git a/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.spice b/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.spice index 3482d67..6a8006b 100644 --- a/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.spice +++ b/cells/edfxtp/sky130_fd_sc_ms__edfxtp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__edfxtp_1.spice -* Created: Fri Aug 28 17:32:51 2020 +* Created: Wed Sep 2 12:08:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_1.lvs.report b/cells/einvn/sky130_fd_sc_ms__einvn_1.lvs.report new file mode 100644 index 0000000..bf538f9 --- /dev/null +++ b/cells/einvn/sky130_fd_sc_ms__einvn_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__einvn_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__einvn_1.sp ('sky130_fd_sc_ms__einvn_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/einvn/sky130_fd_sc_ms__einvn_1.spice ('sky130_fd_sc_ms__einvn_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:08:09 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__einvn_1 sky130_fd_sc_ms__einvn_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__einvn_1 +SOURCE CELL NAME: sky130_fd_sc_ms__einvn_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB TE_B A VPWR Z VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_1.pex.spice b/cells/einvn/sky130_fd_sc_ms__einvn_1.pex.spice index cd1a15a..66e3ce7 100644 --- a/cells/einvn/sky130_fd_sc_ms__einvn_1.pex.spice +++ b/cells/einvn/sky130_fd_sc_ms__einvn_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvn_1.pex.spice -* Created: Fri Aug 28 17:33:01 2020 +* Created: Wed Sep 2 12:08:12 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_1.pxi.spice b/cells/einvn/sky130_fd_sc_ms__einvn_1.pxi.spice index d980b62..eb1a71b 100644 --- a/cells/einvn/sky130_fd_sc_ms__einvn_1.pxi.spice +++ b/cells/einvn/sky130_fd_sc_ms__einvn_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvn_1.pxi.spice -* Created: Fri Aug 28 17:33:01 2020 +* Created: Wed Sep 2 12:08:12 2020 * x_PM_SKY130_FD_SC_MS__EINVN_1%TE_B N_TE_B_M1004_g N_TE_B_c_44_n N_TE_B_M1005_g + N_TE_B_c_45_n N_TE_B_c_51_n N_TE_B_M1000_g TE_B N_TE_B_c_47_n N_TE_B_c_48_n
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_1.spice b/cells/einvn/sky130_fd_sc_ms__einvn_1.spice index 5ea1ff6..ed46c87 100644 --- a/cells/einvn/sky130_fd_sc_ms__einvn_1.spice +++ b/cells/einvn/sky130_fd_sc_ms__einvn_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvn_1.spice -* Created: Fri Aug 28 17:33:01 2020 +* Created: Wed Sep 2 12:08:12 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_2.lvs.report b/cells/einvn/sky130_fd_sc_ms__einvn_2.lvs.report new file mode 100644 index 0000000..31f513f --- /dev/null +++ b/cells/einvn/sky130_fd_sc_ms__einvn_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__einvn_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__einvn_2.sp ('sky130_fd_sc_ms__einvn_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/einvn/sky130_fd_sc_ms__einvn_2.spice ('sky130_fd_sc_ms__einvn_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:08:16 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__einvn_2 sky130_fd_sc_ms__einvn_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__einvn_2 +SOURCE CELL NAME: sky130_fd_sc_ms__einvn_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB TE_B A VPWR Z VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_2.pex.spice b/cells/einvn/sky130_fd_sc_ms__einvn_2.pex.spice index a6610f2..5bf52e1 100644 --- a/cells/einvn/sky130_fd_sc_ms__einvn_2.pex.spice +++ b/cells/einvn/sky130_fd_sc_ms__einvn_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvn_2.pex.spice -* Created: Fri Aug 28 17:33:10 2020 +* Created: Wed Sep 2 12:08:19 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_2.pxi.spice b/cells/einvn/sky130_fd_sc_ms__einvn_2.pxi.spice index ecaa076..ebb19c3 100644 --- a/cells/einvn/sky130_fd_sc_ms__einvn_2.pxi.spice +++ b/cells/einvn/sky130_fd_sc_ms__einvn_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvn_2.pxi.spice -* Created: Fri Aug 28 17:33:10 2020 +* Created: Wed Sep 2 12:08:19 2020 * x_PM_SKY130_FD_SC_MS__EINVN_2%TE_B N_TE_B_c_68_n N_TE_B_c_73_n N_TE_B_M1006_g + N_TE_B_M1009_g N_TE_B_c_75_n N_TE_B_c_76_n N_TE_B_c_77_n N_TE_B_M1002_g
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_2.spice b/cells/einvn/sky130_fd_sc_ms__einvn_2.spice index e9533fd..959ccf4 100644 --- a/cells/einvn/sky130_fd_sc_ms__einvn_2.spice +++ b/cells/einvn/sky130_fd_sc_ms__einvn_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvn_2.spice -* Created: Fri Aug 28 17:33:10 2020 +* Created: Wed Sep 2 12:08:19 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_4.lvs.report b/cells/einvn/sky130_fd_sc_ms__einvn_4.lvs.report new file mode 100644 index 0000000..90296fe --- /dev/null +++ b/cells/einvn/sky130_fd_sc_ms__einvn_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__einvn_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__einvn_4.sp ('sky130_fd_sc_ms__einvn_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/einvn/sky130_fd_sc_ms__einvn_4.spice ('sky130_fd_sc_ms__einvn_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:08:22 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__einvn_4 sky130_fd_sc_ms__einvn_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__einvn_4 +SOURCE CELL NAME: sky130_fd_sc_ms__einvn_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 10 10 + + Instances: 9 9 MN (4 pins) + 9 9 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 19 18 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 4. + 12 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 4. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB TE_B A VPWR Z VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_4.pex.spice b/cells/einvn/sky130_fd_sc_ms__einvn_4.pex.spice index 01d57dc..ace8622 100644 --- a/cells/einvn/sky130_fd_sc_ms__einvn_4.pex.spice +++ b/cells/einvn/sky130_fd_sc_ms__einvn_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvn_4.pex.spice -* Created: Fri Aug 28 17:33:20 2020 +* Created: Wed Sep 2 12:08:25 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_4.pxi.spice b/cells/einvn/sky130_fd_sc_ms__einvn_4.pxi.spice index 889d0c7..43fd77d 100644 --- a/cells/einvn/sky130_fd_sc_ms__einvn_4.pxi.spice +++ b/cells/einvn/sky130_fd_sc_ms__einvn_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvn_4.pxi.spice -* Created: Fri Aug 28 17:33:20 2020 +* Created: Wed Sep 2 12:08:25 2020 * x_PM_SKY130_FD_SC_MS__EINVN_4%TE_B N_TE_B_M1015_g N_TE_B_c_109_n N_TE_B_M1014_g + N_TE_B_c_100_n N_TE_B_c_111_n N_TE_B_M1000_g N_TE_B_c_101_n N_TE_B_c_113_n
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_4.spice b/cells/einvn/sky130_fd_sc_ms__einvn_4.spice index 9257017..3168f0a 100644 --- a/cells/einvn/sky130_fd_sc_ms__einvn_4.spice +++ b/cells/einvn/sky130_fd_sc_ms__einvn_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvn_4.spice -* Created: Fri Aug 28 17:33:20 2020 +* Created: Wed Sep 2 12:08:25 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_8.lvs.report b/cells/einvn/sky130_fd_sc_ms__einvn_8.lvs.report new file mode 100644 index 0000000..e8fe8af --- /dev/null +++ b/cells/einvn/sky130_fd_sc_ms__einvn_8.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__einvn_8.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__einvn_8.sp ('sky130_fd_sc_ms__einvn_8') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/einvn/sky130_fd_sc_ms__einvn_8.spice ('sky130_fd_sc_ms__einvn_8') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:08:29 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__einvn_8 sky130_fd_sc_ms__einvn_8 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__einvn_8 +SOURCE CELL NAME: sky130_fd_sc_ms__einvn_8 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 10 10 + + Instances: 17 17 MN (4 pins) + 17 17 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 35 34 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 32 layout mos transistors were reduced to 4. + 28 mos transistors were deleted by parallel reduction. + 32 source mos transistors were reduced to 4. + 28 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB TE_B A VPWR Z VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_8.pex.spice b/cells/einvn/sky130_fd_sc_ms__einvn_8.pex.spice index 7667d5f..88cda1b 100644 --- a/cells/einvn/sky130_fd_sc_ms__einvn_8.pex.spice +++ b/cells/einvn/sky130_fd_sc_ms__einvn_8.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvn_8.pex.spice -* Created: Fri Aug 28 17:33:37 2020 +* Created: Wed Sep 2 12:08:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_8.pxi.spice b/cells/einvn/sky130_fd_sc_ms__einvn_8.pxi.spice index 9dbdb63..3f54ead 100644 --- a/cells/einvn/sky130_fd_sc_ms__einvn_8.pxi.spice +++ b/cells/einvn/sky130_fd_sc_ms__einvn_8.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvn_8.pxi.spice -* Created: Fri Aug 28 17:33:37 2020 +* Created: Wed Sep 2 12:08:32 2020 * x_PM_SKY130_FD_SC_MS__EINVN_8%TE_B N_TE_B_c_191_n N_TE_B_M1009_g N_TE_B_M1002_g + N_TE_B_c_174_n N_TE_B_c_193_n N_TE_B_M1017_g N_TE_B_c_175_n N_TE_B_c_195_n
diff --git a/cells/einvn/sky130_fd_sc_ms__einvn_8.spice b/cells/einvn/sky130_fd_sc_ms__einvn_8.spice index 4146b90..8048bd6 100644 --- a/cells/einvn/sky130_fd_sc_ms__einvn_8.spice +++ b/cells/einvn/sky130_fd_sc_ms__einvn_8.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvn_8.spice -* Created: Fri Aug 28 17:33:37 2020 +* Created: Wed Sep 2 12:08:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_1.lvs.report b/cells/einvp/sky130_fd_sc_ms__einvp_1.lvs.report new file mode 100644 index 0000000..e0016c5 --- /dev/null +++ b/cells/einvp/sky130_fd_sc_ms__einvp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__einvp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__einvp_1.sp ('sky130_fd_sc_ms__einvp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/einvp/sky130_fd_sc_ms__einvp_1.spice ('sky130_fd_sc_ms__einvp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:08:36 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__einvp_1 sky130_fd_sc_ms__einvp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__einvp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__einvp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB TE A VPWR Z VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_1.pex.spice b/cells/einvp/sky130_fd_sc_ms__einvp_1.pex.spice index 92999e1..9ace43a 100644 --- a/cells/einvp/sky130_fd_sc_ms__einvp_1.pex.spice +++ b/cells/einvp/sky130_fd_sc_ms__einvp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvp_1.pex.spice -* Created: Fri Aug 28 17:33:57 2020 +* Created: Wed Sep 2 12:08:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_1.pxi.spice b/cells/einvp/sky130_fd_sc_ms__einvp_1.pxi.spice index 27779b6..a7e7571 100644 --- a/cells/einvp/sky130_fd_sc_ms__einvp_1.pxi.spice +++ b/cells/einvp/sky130_fd_sc_ms__einvp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvp_1.pxi.spice -* Created: Fri Aug 28 17:33:57 2020 +* Created: Wed Sep 2 12:08:39 2020 * x_PM_SKY130_FD_SC_MS__EINVP_1%A_44_549# N_A_44_549#_M1003_s N_A_44_549#_M1005_s + N_A_44_549#_c_48_n N_A_44_549#_c_49_n N_A_44_549#_M1000_g N_A_44_549#_c_45_n
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_1.spice b/cells/einvp/sky130_fd_sc_ms__einvp_1.spice index 979d890..2684894 100644 --- a/cells/einvp/sky130_fd_sc_ms__einvp_1.spice +++ b/cells/einvp/sky130_fd_sc_ms__einvp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvp_1.spice -* Created: Fri Aug 28 17:33:57 2020 +* Created: Wed Sep 2 12:08:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_2.lvs.report b/cells/einvp/sky130_fd_sc_ms__einvp_2.lvs.report new file mode 100644 index 0000000..ed50518 --- /dev/null +++ b/cells/einvp/sky130_fd_sc_ms__einvp_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__einvp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__einvp_2.sp ('sky130_fd_sc_ms__einvp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/einvp/sky130_fd_sc_ms__einvp_2.spice ('sky130_fd_sc_ms__einvp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:08:42 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__einvp_2 sky130_fd_sc_ms__einvp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__einvp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__einvp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A TE Z VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_2.pex.spice b/cells/einvp/sky130_fd_sc_ms__einvp_2.pex.spice index 5fe4624..9b0eb41 100644 --- a/cells/einvp/sky130_fd_sc_ms__einvp_2.pex.spice +++ b/cells/einvp/sky130_fd_sc_ms__einvp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvp_2.pex.spice -* Created: Fri Aug 28 17:34:07 2020 +* Created: Wed Sep 2 12:08:45 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_2.pxi.spice b/cells/einvp/sky130_fd_sc_ms__einvp_2.pxi.spice index 51828bc..a94eba3 100644 --- a/cells/einvp/sky130_fd_sc_ms__einvp_2.pxi.spice +++ b/cells/einvp/sky130_fd_sc_ms__einvp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvp_2.pxi.spice -* Created: Fri Aug 28 17:34:07 2020 +* Created: Wed Sep 2 12:08:45 2020 * x_PM_SKY130_FD_SC_MS__EINVP_2%A N_A_M1003_g N_A_c_73_n N_A_M1001_g N_A_M1004_g + N_A_c_75_n N_A_M1009_g A N_A_c_77_n PM_SKY130_FD_SC_MS__EINVP_2%A
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_2.spice b/cells/einvp/sky130_fd_sc_ms__einvp_2.spice index f97a12b..74f6f7f 100644 --- a/cells/einvp/sky130_fd_sc_ms__einvp_2.spice +++ b/cells/einvp/sky130_fd_sc_ms__einvp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvp_2.spice -* Created: Fri Aug 28 17:34:07 2020 +* Created: Wed Sep 2 12:08:45 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_4.lvs.report b/cells/einvp/sky130_fd_sc_ms__einvp_4.lvs.report new file mode 100644 index 0000000..3bf8d7d --- /dev/null +++ b/cells/einvp/sky130_fd_sc_ms__einvp_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__einvp_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__einvp_4.sp ('sky130_fd_sc_ms__einvp_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/einvp/sky130_fd_sc_ms__einvp_4.spice ('sky130_fd_sc_ms__einvp_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:08:49 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__einvp_4 sky130_fd_sc_ms__einvp_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__einvp_4 +SOURCE CELL NAME: sky130_fd_sc_ms__einvp_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 10 10 + + Instances: 9 9 MN (4 pins) + 9 9 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 19 18 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 4. + 12 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 4. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A TE Z VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_4.pex.spice b/cells/einvp/sky130_fd_sc_ms__einvp_4.pex.spice index d81b794..4c71a8c 100644 --- a/cells/einvp/sky130_fd_sc_ms__einvp_4.pex.spice +++ b/cells/einvp/sky130_fd_sc_ms__einvp_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvp_4.pex.spice -* Created: Fri Aug 28 17:34:16 2020 +* Created: Wed Sep 2 12:08:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_4.pxi.spice b/cells/einvp/sky130_fd_sc_ms__einvp_4.pxi.spice index 34f79a4..690e512 100644 --- a/cells/einvp/sky130_fd_sc_ms__einvp_4.pxi.spice +++ b/cells/einvp/sky130_fd_sc_ms__einvp_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvp_4.pxi.spice -* Created: Fri Aug 28 17:34:16 2020 +* Created: Wed Sep 2 12:08:52 2020 * x_PM_SKY130_FD_SC_MS__EINVP_4%A N_A_M1007_g N_A_M1000_g N_A_M1002_g N_A_M1009_g + N_A_M1003_g N_A_M1013_g N_A_c_113_n N_A_M1006_g N_A_M1016_g N_A_c_116_n A A A
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_4.spice b/cells/einvp/sky130_fd_sc_ms__einvp_4.spice index a2da155..2af8852 100644 --- a/cells/einvp/sky130_fd_sc_ms__einvp_4.spice +++ b/cells/einvp/sky130_fd_sc_ms__einvp_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvp_4.spice -* Created: Fri Aug 28 17:34:16 2020 +* Created: Wed Sep 2 12:08:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_8.lvs.report b/cells/einvp/sky130_fd_sc_ms__einvp_8.lvs.report new file mode 100644 index 0000000..867adc1 --- /dev/null +++ b/cells/einvp/sky130_fd_sc_ms__einvp_8.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__einvp_8.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__einvp_8.sp ('sky130_fd_sc_ms__einvp_8') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/einvp/sky130_fd_sc_ms__einvp_8.spice ('sky130_fd_sc_ms__einvp_8') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:08:56 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__einvp_8 sky130_fd_sc_ms__einvp_8 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__einvp_8 +SOURCE CELL NAME: sky130_fd_sc_ms__einvp_8 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 10 10 + + Instances: 17 17 MN (4 pins) + 17 17 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 35 34 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 32 layout mos transistors were reduced to 4. + 28 mos transistors were deleted by parallel reduction. + 32 source mos transistors were reduced to 4. + 28 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A TE Z VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_8.pex.spice b/cells/einvp/sky130_fd_sc_ms__einvp_8.pex.spice index 9d0d813..211f170 100644 --- a/cells/einvp/sky130_fd_sc_ms__einvp_8.pex.spice +++ b/cells/einvp/sky130_fd_sc_ms__einvp_8.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvp_8.pex.spice -* Created: Fri Aug 28 17:34:26 2020 +* Created: Wed Sep 2 12:08:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_8.pxi.spice b/cells/einvp/sky130_fd_sc_ms__einvp_8.pxi.spice index 42f87a2..736eb8b 100644 --- a/cells/einvp/sky130_fd_sc_ms__einvp_8.pxi.spice +++ b/cells/einvp/sky130_fd_sc_ms__einvp_8.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvp_8.pxi.spice -* Created: Fri Aug 28 17:34:26 2020 +* Created: Wed Sep 2 12:08:59 2020 * x_PM_SKY130_FD_SC_MS__EINVP_8%A N_A_M1009_g N_A_c_186_n N_A_M1005_g N_A_c_187_n + N_A_M1006_g N_A_M1012_g N_A_M1016_g N_A_c_190_n N_A_M1008_g N_A_M1017_g
diff --git a/cells/einvp/sky130_fd_sc_ms__einvp_8.spice b/cells/einvp/sky130_fd_sc_ms__einvp_8.spice index 9e977b6..467d878 100644 --- a/cells/einvp/sky130_fd_sc_ms__einvp_8.spice +++ b/cells/einvp/sky130_fd_sc_ms__einvp_8.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__einvp_8.spice -* Created: Fri Aug 28 17:34:26 2020 +* Created: Wed Sep 2 12:08:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/fa/sky130_fd_sc_ms__fa_1.lvs.report b/cells/fa/sky130_fd_sc_ms__fa_1.lvs.report new file mode 100644 index 0000000..2c5c58a --- /dev/null +++ b/cells/fa/sky130_fd_sc_ms__fa_1.lvs.report
@@ -0,0 +1,480 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fa_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fa_1.sp ('sky130_fd_sc_ms__fa_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fa/sky130_fd_sc_ms__fa_1.spice ('sky130_fd_sc_ms__fa_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:09:02 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__fa_1 sky130_fd_sc_ms__fa_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__fa_1 +SOURCE CELL NAME: sky130_fd_sc_ms__fa_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 21 21 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SMP2 (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_2_1 (5 pins) + 1 1 SPMN_3_1 (6 pins) + 1 1 SPMP_2_1 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 12 12 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SMP2 + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_2_1 + 1 1 0 0 SPMN_3_1 + 1 1 0 0 SPMP_2_1 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 12 12 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A CIN B SUM VPWR COUT VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/fa/sky130_fd_sc_ms__fa_1.pex.spice b/cells/fa/sky130_fd_sc_ms__fa_1.pex.spice index 73aae72..6c31f61 100644 --- a/cells/fa/sky130_fd_sc_ms__fa_1.pex.spice +++ b/cells/fa/sky130_fd_sc_ms__fa_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fa_1.pex.spice -* Created: Fri Aug 28 17:34:44 2020 +* Created: Wed Sep 2 12:09:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/fa/sky130_fd_sc_ms__fa_1.pxi.spice b/cells/fa/sky130_fd_sc_ms__fa_1.pxi.spice index 7053282..8c93f70 100644 --- a/cells/fa/sky130_fd_sc_ms__fa_1.pxi.spice +++ b/cells/fa/sky130_fd_sc_ms__fa_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fa_1.pxi.spice -* Created: Fri Aug 28 17:34:44 2020 +* Created: Wed Sep 2 12:09:05 2020 * x_PM_SKY130_FD_SC_MS__FA_1%A_69_260# N_A_69_260#_M1001_d N_A_69_260#_M1004_d + N_A_69_260#_M1021_g N_A_69_260#_M1026_g N_A_69_260#_c_160_n
diff --git a/cells/fa/sky130_fd_sc_ms__fa_1.spice b/cells/fa/sky130_fd_sc_ms__fa_1.spice index 801c1a1..ccc4e98 100644 --- a/cells/fa/sky130_fd_sc_ms__fa_1.spice +++ b/cells/fa/sky130_fd_sc_ms__fa_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fa_1.spice -* Created: Fri Aug 28 17:34:44 2020 +* Created: Wed Sep 2 12:09:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/fa/sky130_fd_sc_ms__fa_2.lvs.report b/cells/fa/sky130_fd_sc_ms__fa_2.lvs.report new file mode 100644 index 0000000..73980b9 --- /dev/null +++ b/cells/fa/sky130_fd_sc_ms__fa_2.lvs.report
@@ -0,0 +1,485 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fa_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fa_2.sp ('sky130_fd_sc_ms__fa_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fa/sky130_fd_sc_ms__fa_2.spice ('sky130_fd_sc_ms__fa_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:09:09 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__fa_2 sky130_fd_sc_ms__fa_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__fa_2 +SOURCE CELL NAME: sky130_fd_sc_ms__fa_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 21 21 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SMP2 (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_2_1 (5 pins) + 1 1 SPMN_3_1 (6 pins) + 1 1 SPMP_2_1 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 12 12 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SMP2 + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_2_1 + 1 1 0 0 SPMN_3_1 + 1 1 0 0 SPMP_2_1 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 12 12 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A CIN B VPWR COUT SUM VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/fa/sky130_fd_sc_ms__fa_2.pex.spice b/cells/fa/sky130_fd_sc_ms__fa_2.pex.spice index 906aaec..e54294b 100644 --- a/cells/fa/sky130_fd_sc_ms__fa_2.pex.spice +++ b/cells/fa/sky130_fd_sc_ms__fa_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fa_2.pex.spice -* Created: Fri Aug 28 17:35:03 2020 +* Created: Wed Sep 2 12:09:12 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/fa/sky130_fd_sc_ms__fa_2.pxi.spice b/cells/fa/sky130_fd_sc_ms__fa_2.pxi.spice index 0f63220..7e76481 100644 --- a/cells/fa/sky130_fd_sc_ms__fa_2.pxi.spice +++ b/cells/fa/sky130_fd_sc_ms__fa_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fa_2.pxi.spice -* Created: Fri Aug 28 17:35:03 2020 +* Created: Wed Sep 2 12:09:12 2020 * x_PM_SKY130_FD_SC_MS__FA_2%A N_A_M1013_g N_A_M1023_g N_A_M1027_g N_A_M1025_g + N_A_M1009_g N_A_M1021_g N_A_M1003_g N_A_M1008_g N_A_c_170_n N_A_c_171_n
diff --git a/cells/fa/sky130_fd_sc_ms__fa_2.spice b/cells/fa/sky130_fd_sc_ms__fa_2.spice index 2443526..7ffbf14 100644 --- a/cells/fa/sky130_fd_sc_ms__fa_2.spice +++ b/cells/fa/sky130_fd_sc_ms__fa_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fa_2.spice -* Created: Fri Aug 28 17:35:03 2020 +* Created: Wed Sep 2 12:09:12 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/fa/sky130_fd_sc_ms__fa_4.lvs.report b/cells/fa/sky130_fd_sc_ms__fa_4.lvs.report new file mode 100644 index 0000000..240b667 --- /dev/null +++ b/cells/fa/sky130_fd_sc_ms__fa_4.lvs.report
@@ -0,0 +1,485 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fa_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fa_4.sp ('sky130_fd_sc_ms__fa_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fa/sky130_fd_sc_ms__fa_4.spice ('sky130_fd_sc_ms__fa_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:09:15 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__fa_4 sky130_fd_sc_ms__fa_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__fa_4 +SOURCE CELL NAME: sky130_fd_sc_ms__fa_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 21 21 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 1 1 SMP2 (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_2_1 (5 pins) + 1 1 SPMN_3_1 (6 pins) + 1 1 SPMP_2_1 (5 pins) + 1 1 SPMP_3_1 (6 pins) + ------ ------ + Total Inst: 12 12 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMN3 + 1 1 0 0 SMP2 + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_2_1 + 1 1 0 0 SPMN_3_1 + 1 1 0 0 SPMP_2_1 + 1 1 0 0 SPMP_3_1 + ------- ------- --------- --------- + Total Inst: 12 12 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 4. + 12 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 4. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B CIN A VPWR SUM COUT VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/fa/sky130_fd_sc_ms__fa_4.pex.spice b/cells/fa/sky130_fd_sc_ms__fa_4.pex.spice index b8c5cf1..c5816e4 100644 --- a/cells/fa/sky130_fd_sc_ms__fa_4.pex.spice +++ b/cells/fa/sky130_fd_sc_ms__fa_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fa_4.pex.spice -* Created: Fri Aug 28 17:35:13 2020 +* Created: Wed Sep 2 12:09:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/fa/sky130_fd_sc_ms__fa_4.pxi.spice b/cells/fa/sky130_fd_sc_ms__fa_4.pxi.spice index 6ff25f7..37404a7 100644 --- a/cells/fa/sky130_fd_sc_ms__fa_4.pxi.spice +++ b/cells/fa/sky130_fd_sc_ms__fa_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fa_4.pxi.spice -* Created: Fri Aug 28 17:35:13 2020 +* Created: Wed Sep 2 12:09:18 2020 * x_PM_SKY130_FD_SC_MS__FA_4%B N_B_M1017_g N_B_M1030_g N_B_M1026_g N_B_M1029_g + N_B_M1033_g N_B_M1012_g N_B_M1031_g N_B_M1039_g N_B_c_193_n N_B_c_204_n
diff --git a/cells/fa/sky130_fd_sc_ms__fa_4.spice b/cells/fa/sky130_fd_sc_ms__fa_4.spice index bbb83fd..ef27106 100644 --- a/cells/fa/sky130_fd_sc_ms__fa_4.spice +++ b/cells/fa/sky130_fd_sc_ms__fa_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fa_4.spice -* Created: Fri Aug 28 17:35:13 2020 +* Created: Wed Sep 2 12:09:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/fah/sky130_fd_sc_ms__fah_1.lvs.report b/cells/fah/sky130_fd_sc_ms__fah_1.lvs.report new file mode 100644 index 0000000..1cda19f --- /dev/null +++ b/cells/fah/sky130_fd_sc_ms__fah_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fah_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fah_1.sp ('sky130_fd_sc_ms__fah_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fah/sky130_fd_sc_ms__fah_1.spice ('sky130_fd_sc_ms__fah_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:09:22 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__fah_1 sky130_fd_sc_ms__fah_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__fah_1 +SOURCE CELL NAME: sky130_fd_sc_ms__fah_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 19 19 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 19 19 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + ------ ------ + Total Inst: 32 32 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 19 19 0 0 + + Instances: 16 16 0 0 MN(NLOWVT) + 16 16 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 32 32 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB CI B A SUM VPWR COUT VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/fah/sky130_fd_sc_ms__fah_1.pex.spice b/cells/fah/sky130_fd_sc_ms__fah_1.pex.spice index 2fda907..35947f4 100644 --- a/cells/fah/sky130_fd_sc_ms__fah_1.pex.spice +++ b/cells/fah/sky130_fd_sc_ms__fah_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fah_1.pex.spice -* Created: Fri Aug 28 17:35:22 2020 +* Created: Wed Sep 2 12:09:25 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/fah/sky130_fd_sc_ms__fah_1.pxi.spice b/cells/fah/sky130_fd_sc_ms__fah_1.pxi.spice index 3226fd7..57b8590 100644 --- a/cells/fah/sky130_fd_sc_ms__fah_1.pxi.spice +++ b/cells/fah/sky130_fd_sc_ms__fah_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fah_1.pxi.spice -* Created: Fri Aug 28 17:35:22 2020 +* Created: Wed Sep 2 12:09:25 2020 * x_PM_SKY130_FD_SC_MS__FAH_1%CI N_CI_M1012_g N_CI_M1000_g CI N_CI_c_272_n + N_CI_c_273_n N_CI_c_274_n PM_SKY130_FD_SC_MS__FAH_1%CI
diff --git a/cells/fah/sky130_fd_sc_ms__fah_1.spice b/cells/fah/sky130_fd_sc_ms__fah_1.spice index f7eaed0..ef43731 100644 --- a/cells/fah/sky130_fd_sc_ms__fah_1.spice +++ b/cells/fah/sky130_fd_sc_ms__fah_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fah_1.spice -* Created: Fri Aug 28 17:35:22 2020 +* Created: Wed Sep 2 12:09:25 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/fah/sky130_fd_sc_ms__fah_2.lvs.report b/cells/fah/sky130_fd_sc_ms__fah_2.lvs.report new file mode 100644 index 0000000..408f122 --- /dev/null +++ b/cells/fah/sky130_fd_sc_ms__fah_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fah_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fah_2.sp ('sky130_fd_sc_ms__fah_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fah/sky130_fd_sc_ms__fah_2.spice ('sky130_fd_sc_ms__fah_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:09:29 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__fah_2 sky130_fd_sc_ms__fah_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__fah_2 +SOURCE CELL NAME: sky130_fd_sc_ms__fah_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 19 19 + + Instances: 18 18 MN (4 pins) + 18 18 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 37 36 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 19 19 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + ------ ------ + Total Inst: 32 32 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 19 19 0 0 + + Instances: 16 16 0 0 MN(NLOWVT) + 16 16 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 32 32 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B CI VPWR COUT SUM VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/fah/sky130_fd_sc_ms__fah_2.pex.spice b/cells/fah/sky130_fd_sc_ms__fah_2.pex.spice index 5594c88..620263e 100644 --- a/cells/fah/sky130_fd_sc_ms__fah_2.pex.spice +++ b/cells/fah/sky130_fd_sc_ms__fah_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fah_2.pex.spice -* Created: Fri Aug 28 17:35:32 2020 +* Created: Wed Sep 2 12:09:33 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/fah/sky130_fd_sc_ms__fah_2.pxi.spice b/cells/fah/sky130_fd_sc_ms__fah_2.pxi.spice index 220c736..10500c2 100644 --- a/cells/fah/sky130_fd_sc_ms__fah_2.pxi.spice +++ b/cells/fah/sky130_fd_sc_ms__fah_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fah_2.pxi.spice -* Created: Fri Aug 28 17:35:32 2020 +* Created: Wed Sep 2 12:09:33 2020 * x_PM_SKY130_FD_SC_MS__FAH_2%A_81_260# N_A_81_260#_M1012_s N_A_81_260#_M1029_s + N_A_81_260#_M1024_g N_A_81_260#_M1034_g N_A_81_260#_c_265_n
diff --git a/cells/fah/sky130_fd_sc_ms__fah_2.spice b/cells/fah/sky130_fd_sc_ms__fah_2.spice index ef928f8..c106b58 100644 --- a/cells/fah/sky130_fd_sc_ms__fah_2.spice +++ b/cells/fah/sky130_fd_sc_ms__fah_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fah_2.spice -* Created: Fri Aug 28 17:35:32 2020 +* Created: Wed Sep 2 12:09:33 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/fah/sky130_fd_sc_ms__fah_4.lvs.report b/cells/fah/sky130_fd_sc_ms__fah_4.lvs.report new file mode 100644 index 0000000..da3d1ab --- /dev/null +++ b/cells/fah/sky130_fd_sc_ms__fah_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fah_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fah_4.sp ('sky130_fd_sc_ms__fah_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fah/sky130_fd_sc_ms__fah_4.spice ('sky130_fd_sc_ms__fah_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:09:36 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__fah_4 sky130_fd_sc_ms__fah_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__fah_4 +SOURCE CELL NAME: sky130_fd_sc_ms__fah_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 19 19 + + Instances: 22 22 MN (4 pins) + 22 22 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 45 44 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 19 19 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + ------ ------ + Total Inst: 32 32 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 19 19 0 0 + + Instances: 16 16 0 0 MN(NLOWVT) + 16 16 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 32 32 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 4. + 12 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 4. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B CI VPWR COUT SUM VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/fah/sky130_fd_sc_ms__fah_4.pex.spice b/cells/fah/sky130_fd_sc_ms__fah_4.pex.spice index ddf18b5..8cfb7d8 100644 --- a/cells/fah/sky130_fd_sc_ms__fah_4.pex.spice +++ b/cells/fah/sky130_fd_sc_ms__fah_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fah_4.pex.spice -* Created: Fri Aug 28 17:35:50 2020 +* Created: Wed Sep 2 12:09:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/fah/sky130_fd_sc_ms__fah_4.pxi.spice b/cells/fah/sky130_fd_sc_ms__fah_4.pxi.spice index 7e6a780..2bf58b4 100644 --- a/cells/fah/sky130_fd_sc_ms__fah_4.pxi.spice +++ b/cells/fah/sky130_fd_sc_ms__fah_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fah_4.pxi.spice -* Created: Fri Aug 28 17:35:50 2020 +* Created: Wed Sep 2 12:09:39 2020 * x_PM_SKY130_FD_SC_MS__FAH_4%A N_A_M1005_g N_A_M1037_g N_A_M1038_g N_A_M1006_g A + N_A_c_298_n N_A_c_299_n PM_SKY130_FD_SC_MS__FAH_4%A
diff --git a/cells/fah/sky130_fd_sc_ms__fah_4.spice b/cells/fah/sky130_fd_sc_ms__fah_4.spice index 1b7d983..725a1a0 100644 --- a/cells/fah/sky130_fd_sc_ms__fah_4.spice +++ b/cells/fah/sky130_fd_sc_ms__fah_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fah_4.spice -* Created: Fri Aug 28 17:35:50 2020 +* Created: Wed Sep 2 12:09:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/fahcin/sky130_fd_sc_ms__fahcin_1.lvs.report b/cells/fahcin/sky130_fd_sc_ms__fahcin_1.lvs.report new file mode 100644 index 0000000..a144e0c --- /dev/null +++ b/cells/fahcin/sky130_fd_sc_ms__fahcin_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fahcin_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fahcin_1.sp ('sky130_fd_sc_ms__fahcin_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fahcin/sky130_fd_sc_ms__fahcin_1.spice ('sky130_fd_sc_ms__fahcin_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:09:43 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__fahcin_1 sky130_fd_sc_ms__fahcin_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__fahcin_1 +SOURCE CELL NAME: sky130_fd_sc_ms__fahcin_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 19 19 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 19 19 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + ------ ------ + Total Inst: 32 32 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 19 19 0 0 + + Instances: 16 16 0 0 MN(NLOWVT) + 16 16 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 32 32 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B CIN VPWR COUT SUM VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/fahcin/sky130_fd_sc_ms__fahcin_1.pex.spice b/cells/fahcin/sky130_fd_sc_ms__fahcin_1.pex.spice index 1a105e9..9659151 100644 --- a/cells/fahcin/sky130_fd_sc_ms__fahcin_1.pex.spice +++ b/cells/fahcin/sky130_fd_sc_ms__fahcin_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fahcin_1.pex.spice -* Created: Fri Aug 28 17:36:10 2020 +* Created: Wed Sep 2 12:09:46 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/fahcin/sky130_fd_sc_ms__fahcin_1.pxi.spice b/cells/fahcin/sky130_fd_sc_ms__fahcin_1.pxi.spice index 493bbff..61a9a45 100644 --- a/cells/fahcin/sky130_fd_sc_ms__fahcin_1.pxi.spice +++ b/cells/fahcin/sky130_fd_sc_ms__fahcin_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fahcin_1.pxi.spice -* Created: Fri Aug 28 17:36:10 2020 +* Created: Wed Sep 2 12:09:46 2020 * x_PM_SKY130_FD_SC_MS__FAHCIN_1%A N_A_M1017_g N_A_M1027_g A N_A_c_243_n + N_A_c_244_n PM_SKY130_FD_SC_MS__FAHCIN_1%A
diff --git a/cells/fahcin/sky130_fd_sc_ms__fahcin_1.spice b/cells/fahcin/sky130_fd_sc_ms__fahcin_1.spice index 45b3af3..22d6e4f 100644 --- a/cells/fahcin/sky130_fd_sc_ms__fahcin_1.spice +++ b/cells/fahcin/sky130_fd_sc_ms__fahcin_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fahcin_1.spice -* Created: Fri Aug 28 17:36:10 2020 +* Created: Wed Sep 2 12:09:46 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/fahcon/sky130_fd_sc_ms__fahcon_1.lvs.report b/cells/fahcon/sky130_fd_sc_ms__fahcon_1.lvs.report new file mode 100644 index 0000000..83ec1e4 --- /dev/null +++ b/cells/fahcon/sky130_fd_sc_ms__fahcon_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fahcon_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fahcon_1.sp ('sky130_fd_sc_ms__fahcon_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fahcon/sky130_fd_sc_ms__fahcon_1.spice ('sky130_fd_sc_ms__fahcon_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:09:50 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__fahcon_1 sky130_fd_sc_ms__fahcon_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__fahcon_1 +SOURCE CELL NAME: sky130_fd_sc_ms__fahcon_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 19 19 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 19 19 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + ------ ------ + Total Inst: 32 32 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 19 19 0 0 + + Instances: 16 16 0 0 MN(NLOWVT) + 16 16 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 32 32 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B CI VPWR COUT_N SUM VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/fahcon/sky130_fd_sc_ms__fahcon_1.pex.spice b/cells/fahcon/sky130_fd_sc_ms__fahcon_1.pex.spice index b1aaf53..36a2456 100644 --- a/cells/fahcon/sky130_fd_sc_ms__fahcon_1.pex.spice +++ b/cells/fahcon/sky130_fd_sc_ms__fahcon_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fahcon_1.pex.spice -* Created: Fri Aug 28 17:36:20 2020 +* Created: Wed Sep 2 12:09:53 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/fahcon/sky130_fd_sc_ms__fahcon_1.pxi.spice b/cells/fahcon/sky130_fd_sc_ms__fahcon_1.pxi.spice index cd2f450..ccb76fa 100644 --- a/cells/fahcon/sky130_fd_sc_ms__fahcon_1.pxi.spice +++ b/cells/fahcon/sky130_fd_sc_ms__fahcon_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fahcon_1.pxi.spice -* Created: Fri Aug 28 17:36:20 2020 +* Created: Wed Sep 2 12:09:53 2020 * x_PM_SKY130_FD_SC_MS__FAHCON_1%A N_A_M1014_g N_A_M1020_g A N_A_c_223_n + N_A_c_224_n PM_SKY130_FD_SC_MS__FAHCON_1%A
diff --git a/cells/fahcon/sky130_fd_sc_ms__fahcon_1.spice b/cells/fahcon/sky130_fd_sc_ms__fahcon_1.spice index 6aa6768..ef89e05 100644 --- a/cells/fahcon/sky130_fd_sc_ms__fahcon_1.spice +++ b/cells/fahcon/sky130_fd_sc_ms__fahcon_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__fahcon_1.spice -* Created: Fri Aug 28 17:36:20 2020 +* Created: Wed Sep 2 12:09:53 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/fill/sky130_fd_sc_ms__fill_1.lvs.report b/cells/fill/sky130_fd_sc_ms__fill_1.lvs.report new file mode 100644 index 0000000..2630dff --- /dev/null +++ b/cells/fill/sky130_fd_sc_ms__fill_1.lvs.report
@@ -0,0 +1,375 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fill_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fill_1.sp ('sky130_fd_sc_ms__fill_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fill/sky130_fd_sc_ms__fill_1.spice ('sky130_fd_sc_ms__fill_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:09:57 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # # ######################## + # # # # + # # NOT COMPARED # + # # # # + # # ######################## + + + Error: Nothing in source. + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/fill/sky130_fd_sc_ms__fill_2.lvs.report b/cells/fill/sky130_fd_sc_ms__fill_2.lvs.report new file mode 100644 index 0000000..8d7113b --- /dev/null +++ b/cells/fill/sky130_fd_sc_ms__fill_2.lvs.report
@@ -0,0 +1,375 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fill_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fill_2.sp ('sky130_fd_sc_ms__fill_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fill/sky130_fd_sc_ms__fill_2.spice ('sky130_fd_sc_ms__fill_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:10:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # # ######################## + # # # # + # # NOT COMPARED # + # # # # + # # ######################## + + + Error: Nothing in source. + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/fill/sky130_fd_sc_ms__fill_4.lvs.report b/cells/fill/sky130_fd_sc_ms__fill_4.lvs.report new file mode 100644 index 0000000..c3c319d --- /dev/null +++ b/cells/fill/sky130_fd_sc_ms__fill_4.lvs.report
@@ -0,0 +1,375 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fill_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fill_4.sp ('sky130_fd_sc_ms__fill_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fill/sky130_fd_sc_ms__fill_4.spice ('sky130_fd_sc_ms__fill_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:10:03 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # # ######################## + # # # # + # # NOT COMPARED # + # # # # + # # ######################## + + + Error: Nothing in source. + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/fill/sky130_fd_sc_ms__fill_8.lvs.report b/cells/fill/sky130_fd_sc_ms__fill_8.lvs.report new file mode 100644 index 0000000..8f8ebb5 --- /dev/null +++ b/cells/fill/sky130_fd_sc_ms__fill_8.lvs.report
@@ -0,0 +1,375 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fill_8.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fill_8.sp ('sky130_fd_sc_ms__fill_8') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fill/sky130_fd_sc_ms__fill_8.spice ('sky130_fd_sc_ms__fill_8') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:10:06 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # # ######################## + # # # # + # # NOT COMPARED # + # # # # + # # ######################## + + + Error: Nothing in source. + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/fill_diode/sky130_fd_sc_ms__fill_diode_2.lvs.report b/cells/fill_diode/sky130_fd_sc_ms__fill_diode_2.lvs.report new file mode 100644 index 0000000..9ce33b1 --- /dev/null +++ b/cells/fill_diode/sky130_fd_sc_ms__fill_diode_2.lvs.report
@@ -0,0 +1,375 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fill_diode_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fill_diode_2.sp ('sky130_fd_sc_ms__fill_diode_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fill_diode/sky130_fd_sc_ms__fill_diode_2.spice ('sky130_fd_sc_ms__fill_diode_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:10:10 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # # ######################## + # # # # + # # NOT COMPARED # + # # # # + # # ######################## + + + Error: Nothing in source. + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/fill_diode/sky130_fd_sc_ms__fill_diode_4.lvs.report b/cells/fill_diode/sky130_fd_sc_ms__fill_diode_4.lvs.report new file mode 100644 index 0000000..69f2b8a --- /dev/null +++ b/cells/fill_diode/sky130_fd_sc_ms__fill_diode_4.lvs.report
@@ -0,0 +1,375 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fill_diode_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fill_diode_4.sp ('sky130_fd_sc_ms__fill_diode_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fill_diode/sky130_fd_sc_ms__fill_diode_4.spice ('sky130_fd_sc_ms__fill_diode_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:10:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # # ######################## + # # # # + # # NOT COMPARED # + # # # # + # # ######################## + + + Error: Nothing in source. + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/fill_diode/sky130_fd_sc_ms__fill_diode_8.lvs.report b/cells/fill_diode/sky130_fd_sc_ms__fill_diode_8.lvs.report new file mode 100644 index 0000000..68c8550 --- /dev/null +++ b/cells/fill_diode/sky130_fd_sc_ms__fill_diode_8.lvs.report
@@ -0,0 +1,375 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__fill_diode_8.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__fill_diode_8.sp ('sky130_fd_sc_ms__fill_diode_8') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/fill_diode/sky130_fd_sc_ms__fill_diode_8.spice ('sky130_fd_sc_ms__fill_diode_8') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:10:16 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # # ######################## + # # # # + # # NOT COMPARED # + # # # # + # # ######################## + + + Error: Nothing in source. + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_ms__ha_1.lvs.report b/cells/ha/sky130_fd_sc_ms__ha_1.lvs.report new file mode 100644 index 0000000..c970a29 --- /dev/null +++ b/cells/ha/sky130_fd_sc_ms__ha_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__ha_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__ha_1.sp ('sky130_fd_sc_ms__ha_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/ha/sky130_fd_sc_ms__ha_1.spice ('sky130_fd_sc_ms__ha_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:10:19 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__ha_1 sky130_fd_sc_ms__ha_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__ha_1 +SOURCE CELL NAME: sky130_fd_sc_ms__ha_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 13 13 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 5 5 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 10 10 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 10 10 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A SUM VPWR COUT VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_ms__ha_1.pex.spice b/cells/ha/sky130_fd_sc_ms__ha_1.pex.spice index 3d22768..6de77c6 100644 --- a/cells/ha/sky130_fd_sc_ms__ha_1.pex.spice +++ b/cells/ha/sky130_fd_sc_ms__ha_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ha_1.pex.spice -* Created: Fri Aug 28 17:37:12 2020 +* Created: Wed Sep 2 12:10:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/ha/sky130_fd_sc_ms__ha_1.pxi.spice b/cells/ha/sky130_fd_sc_ms__ha_1.pxi.spice index 5d73000..9a6bc2a 100644 --- a/cells/ha/sky130_fd_sc_ms__ha_1.pxi.spice +++ b/cells/ha/sky130_fd_sc_ms__ha_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ha_1.pxi.spice -* Created: Fri Aug 28 17:37:12 2020 +* Created: Wed Sep 2 12:10:23 2020 * x_PM_SKY130_FD_SC_MS__HA_1%A_83_260# N_A_83_260#_M1007_s N_A_83_260#_M1006_d + N_A_83_260#_M1005_g N_A_83_260#_M1011_g N_A_83_260#_c_91_n N_A_83_260#_c_92_n
diff --git a/cells/ha/sky130_fd_sc_ms__ha_1.spice b/cells/ha/sky130_fd_sc_ms__ha_1.spice index 7fdbf41..2b4c18c 100644 --- a/cells/ha/sky130_fd_sc_ms__ha_1.spice +++ b/cells/ha/sky130_fd_sc_ms__ha_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ha_1.spice -* Created: Fri Aug 28 17:37:12 2020 +* Created: Wed Sep 2 12:10:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/ha/sky130_fd_sc_ms__ha_2.lvs.report b/cells/ha/sky130_fd_sc_ms__ha_2.lvs.report new file mode 100644 index 0000000..936af79 --- /dev/null +++ b/cells/ha/sky130_fd_sc_ms__ha_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__ha_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__ha_2.sp ('sky130_fd_sc_ms__ha_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/ha/sky130_fd_sc_ms__ha_2.spice ('sky130_fd_sc_ms__ha_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:10:26 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__ha_2 sky130_fd_sc_ms__ha_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__ha_2 +SOURCE CELL NAME: sky130_fd_sc_ms__ha_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 13 13 + + Instances: 9 9 MN (4 pins) + 9 9 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 19 18 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 5 5 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 10 10 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 10 10 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A VPWR SUM COUT VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_ms__ha_2.pex.spice b/cells/ha/sky130_fd_sc_ms__ha_2.pex.spice index 25e4ce0..d5fc0bb 100644 --- a/cells/ha/sky130_fd_sc_ms__ha_2.pex.spice +++ b/cells/ha/sky130_fd_sc_ms__ha_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ha_2.pex.spice -* Created: Fri Aug 28 17:37:22 2020 +* Created: Wed Sep 2 12:10:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/ha/sky130_fd_sc_ms__ha_2.pxi.spice b/cells/ha/sky130_fd_sc_ms__ha_2.pxi.spice index 0309759..8e50fcd 100644 --- a/cells/ha/sky130_fd_sc_ms__ha_2.pxi.spice +++ b/cells/ha/sky130_fd_sc_ms__ha_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ha_2.pxi.spice -* Created: Fri Aug 28 17:37:22 2020 +* Created: Wed Sep 2 12:10:30 2020 * x_PM_SKY130_FD_SC_MS__HA_2%B N_B_c_113_n N_B_M1014_g N_B_M1016_g N_B_c_106_n + N_B_M1007_g N_B_c_107_n N_B_M1010_g N_B_c_108_n N_B_c_109_n N_B_c_110_n
diff --git a/cells/ha/sky130_fd_sc_ms__ha_2.spice b/cells/ha/sky130_fd_sc_ms__ha_2.spice index edec276..e620e68 100644 --- a/cells/ha/sky130_fd_sc_ms__ha_2.spice +++ b/cells/ha/sky130_fd_sc_ms__ha_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ha_2.spice -* Created: Fri Aug 28 17:37:22 2020 +* Created: Wed Sep 2 12:10:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/ha/sky130_fd_sc_ms__ha_4.lvs.report b/cells/ha/sky130_fd_sc_ms__ha_4.lvs.report new file mode 100644 index 0000000..5a812db --- /dev/null +++ b/cells/ha/sky130_fd_sc_ms__ha_4.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__ha_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__ha_4.sp ('sky130_fd_sc_ms__ha_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/ha/sky130_fd_sc_ms__ha_4.spice ('sky130_fd_sc_ms__ha_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:10:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__ha_4 sky130_fd_sc_ms__ha_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__ha_4 +SOURCE CELL NAME: sky130_fd_sc_ms__ha_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 13 13 + + Instances: 18 18 MN (4 pins) + 18 18 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 37 36 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 5 5 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 10 10 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 10 10 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 36 layout mos transistors were reduced to 14. + 22 mos transistors were deleted by parallel reduction. + 36 source mos transistors were reduced to 14. + 22 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A VPWR COUT SUM VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_ms__ha_4.pex.spice b/cells/ha/sky130_fd_sc_ms__ha_4.pex.spice index 4cf4f34..e6d981a 100644 --- a/cells/ha/sky130_fd_sc_ms__ha_4.pex.spice +++ b/cells/ha/sky130_fd_sc_ms__ha_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ha_4.pex.spice -* Created: Fri Aug 28 17:37:31 2020 +* Created: Wed Sep 2 12:10:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/ha/sky130_fd_sc_ms__ha_4.pxi.spice b/cells/ha/sky130_fd_sc_ms__ha_4.pxi.spice index 89f93f0..893ff2d 100644 --- a/cells/ha/sky130_fd_sc_ms__ha_4.pxi.spice +++ b/cells/ha/sky130_fd_sc_ms__ha_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ha_4.pxi.spice -* Created: Fri Aug 28 17:37:31 2020 +* Created: Wed Sep 2 12:10:37 2020 * x_PM_SKY130_FD_SC_MS__HA_4%A_435_99# N_A_435_99#_M1000_d N_A_435_99#_M1008_d + N_A_435_99#_M1029_d N_A_435_99#_c_196_n N_A_435_99#_M1023_g
diff --git a/cells/ha/sky130_fd_sc_ms__ha_4.spice b/cells/ha/sky130_fd_sc_ms__ha_4.spice index ffaaf6b..19e9183 100644 --- a/cells/ha/sky130_fd_sc_ms__ha_4.spice +++ b/cells/ha/sky130_fd_sc_ms__ha_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__ha_4.spice -* Created: Fri Aug 28 17:37:31 2020 +* Created: Wed Sep 2 12:10:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/inv/sky130_fd_sc_ms__inv_1.lvs.report b/cells/inv/sky130_fd_sc_ms__inv_1.lvs.report new file mode 100644 index 0000000..1e167da --- /dev/null +++ b/cells/inv/sky130_fd_sc_ms__inv_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__inv_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__inv_1.sp ('sky130_fd_sc_ms__inv_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/inv/sky130_fd_sc_ms__inv_1.spice ('sky130_fd_sc_ms__inv_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:10:47 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__inv_1 sky130_fd_sc_ms__inv_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__inv_1 +SOURCE CELL NAME: sky130_fd_sc_ms__inv_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 3 2 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + ------ ------ + Total Inst: 2 2 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 6 6 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 2 2 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_ms__inv_1.pex.spice b/cells/inv/sky130_fd_sc_ms__inv_1.pex.spice index 86fc7fe..5042a2b 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_1.pex.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_1.pex.spice -* Created: Fri Aug 28 17:37:49 2020 +* Created: Wed Sep 2 12:10:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_ms__inv_1.pxi.spice b/cells/inv/sky130_fd_sc_ms__inv_1.pxi.spice index edf2cbe..7a1e5ef 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_1.pxi.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_1.pxi.spice -* Created: Fri Aug 28 17:37:49 2020 +* Created: Wed Sep 2 12:10:50 2020 * x_PM_SKY130_FD_SC_MS__INV_1%A N_A_M1001_g N_A_M1000_g N_A_c_23_n N_A_c_24_n A + N_A_c_25_n PM_SKY130_FD_SC_MS__INV_1%A
diff --git a/cells/inv/sky130_fd_sc_ms__inv_1.spice b/cells/inv/sky130_fd_sc_ms__inv_1.spice index cafcb4c..692ad9d 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_1.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_1.spice -* Created: Fri Aug 28 17:37:49 2020 +* Created: Wed Sep 2 12:10:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/inv/sky130_fd_sc_ms__inv_16.lvs.report b/cells/inv/sky130_fd_sc_ms__inv_16.lvs.report new file mode 100644 index 0000000..a34c4c9 --- /dev/null +++ b/cells/inv/sky130_fd_sc_ms__inv_16.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__inv_16.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__inv_16.sp ('sky130_fd_sc_ms__inv_16') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/inv/sky130_fd_sc_ms__inv_16.spice ('sky130_fd_sc_ms__inv_16') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:10:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__inv_16 sky130_fd_sc_ms__inv_16 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__inv_16 +SOURCE CELL NAME: sky130_fd_sc_ms__inv_16 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + ------ ------ + Total Inst: 2 2 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 6 6 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 2 2 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 32 layout mos transistors were reduced to 2. + 30 mos transistors were deleted by parallel reduction. + 32 source mos transistors were reduced to 2. + 30 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_ms__inv_16.pex.spice b/cells/inv/sky130_fd_sc_ms__inv_16.pex.spice index 1ef4d64..05e4c77 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_16.pex.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_16.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_16.pex.spice -* Created: Fri Aug 28 17:37:40 2020 +* Created: Wed Sep 2 12:10:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_ms__inv_16.pxi.spice b/cells/inv/sky130_fd_sc_ms__inv_16.pxi.spice index 0e6d924..fe5698d 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_16.pxi.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_16.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_16.pxi.spice -* Created: Fri Aug 28 17:37:40 2020 +* Created: Wed Sep 2 12:10:43 2020 * x_PM_SKY130_FD_SC_MS__INV_16%A N_A_M1004_g N_A_M1000_g N_A_M1006_g N_A_M1001_g + N_A_M1007_g N_A_M1002_g N_A_M1008_g N_A_M1003_g N_A_M1009_g N_A_M1005_g
diff --git a/cells/inv/sky130_fd_sc_ms__inv_16.spice b/cells/inv/sky130_fd_sc_ms__inv_16.spice index 69776cb..3cc7a38 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_16.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_16.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_16.spice -* Created: Fri Aug 28 17:37:40 2020 +* Created: Wed Sep 2 12:10:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/inv/sky130_fd_sc_ms__inv_2.lvs.report b/cells/inv/sky130_fd_sc_ms__inv_2.lvs.report new file mode 100644 index 0000000..011dbef --- /dev/null +++ b/cells/inv/sky130_fd_sc_ms__inv_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__inv_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__inv_2.sp ('sky130_fd_sc_ms__inv_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/inv/sky130_fd_sc_ms__inv_2.spice ('sky130_fd_sc_ms__inv_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:10:54 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__inv_2 sky130_fd_sc_ms__inv_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__inv_2 +SOURCE CELL NAME: sky130_fd_sc_ms__inv_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 5 4 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + ------ ------ + Total Inst: 2 2 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 6 6 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 2 2 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_ms__inv_2.pex.spice b/cells/inv/sky130_fd_sc_ms__inv_2.pex.spice index 56e9c58..1f829af 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_2.pex.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_2.pex.spice -* Created: Fri Aug 28 17:38:19 2020 +* Created: Wed Sep 2 12:10:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_ms__inv_2.pxi.spice b/cells/inv/sky130_fd_sc_ms__inv_2.pxi.spice index 1dc7382..626a731 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_2.pxi.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_2.pxi.spice -* Created: Fri Aug 28 17:38:19 2020 +* Created: Wed Sep 2 12:10:57 2020 * x_PM_SKY130_FD_SC_MS__INV_2%A N_A_M1000_g N_A_M1002_g N_A_c_31_n N_A_M1001_g + N_A_M1003_g N_A_c_34_n A N_A_c_35_n N_A_c_36_n PM_SKY130_FD_SC_MS__INV_2%A
diff --git a/cells/inv/sky130_fd_sc_ms__inv_2.spice b/cells/inv/sky130_fd_sc_ms__inv_2.spice index ddc9c8a..e1886bd 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_2.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_2.spice -* Created: Fri Aug 28 17:38:19 2020 +* Created: Wed Sep 2 12:10:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/inv/sky130_fd_sc_ms__inv_4.lvs.report b/cells/inv/sky130_fd_sc_ms__inv_4.lvs.report new file mode 100644 index 0000000..0d4bcc3 --- /dev/null +++ b/cells/inv/sky130_fd_sc_ms__inv_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__inv_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__inv_4.sp ('sky130_fd_sc_ms__inv_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/inv/sky130_fd_sc_ms__inv_4.spice ('sky130_fd_sc_ms__inv_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:11:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__inv_4 sky130_fd_sc_ms__inv_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__inv_4 +SOURCE CELL NAME: sky130_fd_sc_ms__inv_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + ------ ------ + Total Inst: 2 2 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 6 6 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 2 2 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 2. + 6 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 2. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_ms__inv_4.pex.spice b/cells/inv/sky130_fd_sc_ms__inv_4.pex.spice index 9c0f599..cf8d07d 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_4.pex.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_4.pex.spice -* Created: Fri Aug 28 17:38:28 2020 +* Created: Wed Sep 2 12:11:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_ms__inv_4.pxi.spice b/cells/inv/sky130_fd_sc_ms__inv_4.pxi.spice index 471c8c5..05615dc 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_4.pxi.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_4.pxi.spice -* Created: Fri Aug 28 17:38:28 2020 +* Created: Wed Sep 2 12:11:04 2020 * x_PM_SKY130_FD_SC_MS__INV_4%A N_A_M1002_g N_A_M1000_g N_A_M1001_g N_A_M1003_g + N_A_M1006_g N_A_M1004_g N_A_M1007_g N_A_M1005_g A A A A N_A_c_48_n
diff --git a/cells/inv/sky130_fd_sc_ms__inv_4.spice b/cells/inv/sky130_fd_sc_ms__inv_4.spice index 79bd5e0..cb4691b 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_4.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_4.spice -* Created: Fri Aug 28 17:38:28 2020 +* Created: Wed Sep 2 12:11:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/inv/sky130_fd_sc_ms__inv_8.lvs.report b/cells/inv/sky130_fd_sc_ms__inv_8.lvs.report new file mode 100644 index 0000000..29600d9 --- /dev/null +++ b/cells/inv/sky130_fd_sc_ms__inv_8.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__inv_8.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__inv_8.sp ('sky130_fd_sc_ms__inv_8') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/inv/sky130_fd_sc_ms__inv_8.spice ('sky130_fd_sc_ms__inv_8') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:11:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__inv_8 sky130_fd_sc_ms__inv_8 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__inv_8 +SOURCE CELL NAME: sky130_fd_sc_ms__inv_8 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 6 6 + + Nets: 6 6 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + ------ ------ + Total Inst: 2 2 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 6 6 0 0 + + Nets: 6 6 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 2 2 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 2. + 14 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 2. + 14 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_ms__inv_8.pex.spice b/cells/inv/sky130_fd_sc_ms__inv_8.pex.spice index cad8cfe..7ffe4c0 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_8.pex.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_8.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_8.pex.spice -* Created: Fri Aug 28 17:38:37 2020 +* Created: Wed Sep 2 12:11:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_ms__inv_8.pxi.spice b/cells/inv/sky130_fd_sc_ms__inv_8.pxi.spice index ca0a99d..0a071f9 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_8.pxi.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_8.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_8.pxi.spice -* Created: Fri Aug 28 17:38:37 2020 +* Created: Wed Sep 2 12:11:10 2020 * x_PM_SKY130_FD_SC_MS__INV_8%A N_A_M1002_g N_A_c_68_n N_A_M1000_g N_A_c_69_n + N_A_M1001_g N_A_M1003_g N_A_M1010_g N_A_M1004_g N_A_M1011_g N_A_M1005_g
diff --git a/cells/inv/sky130_fd_sc_ms__inv_8.spice b/cells/inv/sky130_fd_sc_ms__inv_8.spice index 4f84d7d..b270213 100644 --- a/cells/inv/sky130_fd_sc_ms__inv_8.spice +++ b/cells/inv/sky130_fd_sc_ms__inv_8.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__inv_8.spice -* Created: Fri Aug 28 17:38:37 2020 +* Created: Wed Sep 2 12:11:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/maj3/sky130_fd_sc_ms__maj3_1.lvs.report b/cells/maj3/sky130_fd_sc_ms__maj3_1.lvs.report new file mode 100644 index 0000000..4b1a5d0 --- /dev/null +++ b/cells/maj3/sky130_fd_sc_ms__maj3_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__maj3_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__maj3_1.sp ('sky130_fd_sc_ms__maj3_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/maj3/sky130_fd_sc_ms__maj3_1.spice ('sky130_fd_sc_ms__maj3_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:11:14 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__maj3_1 sky130_fd_sc_ms__maj3_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__maj3_1 +SOURCE CELL NAME: sky130_fd_sc_ms__maj3_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 3 3 SMN2 (4 pins) + 3 3 SMP2 (4 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 3 3 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B C A X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/maj3/sky130_fd_sc_ms__maj3_1.pex.spice b/cells/maj3/sky130_fd_sc_ms__maj3_1.pex.spice index e032969..d1b5be2 100644 --- a/cells/maj3/sky130_fd_sc_ms__maj3_1.pex.spice +++ b/cells/maj3/sky130_fd_sc_ms__maj3_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__maj3_1.pex.spice -* Created: Fri Aug 28 17:38:46 2020 +* Created: Wed Sep 2 12:11:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/maj3/sky130_fd_sc_ms__maj3_1.pxi.spice b/cells/maj3/sky130_fd_sc_ms__maj3_1.pxi.spice index 3c5207d..cd714c1 100644 --- a/cells/maj3/sky130_fd_sc_ms__maj3_1.pxi.spice +++ b/cells/maj3/sky130_fd_sc_ms__maj3_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__maj3_1.pxi.spice -* Created: Fri Aug 28 17:38:46 2020 +* Created: Wed Sep 2 12:11:18 2020 * x_PM_SKY130_FD_SC_MS__MAJ3_1%A_84_74# N_A_84_74#_M1004_d N_A_84_74#_M1008_d + N_A_84_74#_M1010_d N_A_84_74#_M1003_d N_A_84_74#_M1002_g N_A_84_74#_M1001_g
diff --git a/cells/maj3/sky130_fd_sc_ms__maj3_1.spice b/cells/maj3/sky130_fd_sc_ms__maj3_1.spice index 7adbd10..c5bcb08 100644 --- a/cells/maj3/sky130_fd_sc_ms__maj3_1.spice +++ b/cells/maj3/sky130_fd_sc_ms__maj3_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__maj3_1.spice -* Created: Fri Aug 28 17:38:46 2020 +* Created: Wed Sep 2 12:11:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/maj3/sky130_fd_sc_ms__maj3_2.lvs.report b/cells/maj3/sky130_fd_sc_ms__maj3_2.lvs.report new file mode 100644 index 0000000..9fd975b --- /dev/null +++ b/cells/maj3/sky130_fd_sc_ms__maj3_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__maj3_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__maj3_2.sp ('sky130_fd_sc_ms__maj3_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/maj3/sky130_fd_sc_ms__maj3_2.spice ('sky130_fd_sc_ms__maj3_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:11:21 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__maj3_2 sky130_fd_sc_ms__maj3_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__maj3_2 +SOURCE CELL NAME: sky130_fd_sc_ms__maj3_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 3 3 SMN2 (4 pins) + 3 3 SMP2 (4 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 3 3 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B C A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/maj3/sky130_fd_sc_ms__maj3_2.pex.spice b/cells/maj3/sky130_fd_sc_ms__maj3_2.pex.spice index f33bf17..289a81e 100644 --- a/cells/maj3/sky130_fd_sc_ms__maj3_2.pex.spice +++ b/cells/maj3/sky130_fd_sc_ms__maj3_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__maj3_2.pex.spice -* Created: Fri Aug 28 17:38:55 2020 +* Created: Wed Sep 2 12:11:25 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/maj3/sky130_fd_sc_ms__maj3_2.pxi.spice b/cells/maj3/sky130_fd_sc_ms__maj3_2.pxi.spice index a9fc43c..18d1651 100644 --- a/cells/maj3/sky130_fd_sc_ms__maj3_2.pxi.spice +++ b/cells/maj3/sky130_fd_sc_ms__maj3_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__maj3_2.pxi.spice -* Created: Fri Aug 28 17:38:55 2020 +* Created: Wed Sep 2 12:11:25 2020 * x_PM_SKY130_FD_SC_MS__MAJ3_2%A_87_264# N_A_87_264#_M1009_d N_A_87_264#_M1013_d + N_A_87_264#_M1007_d N_A_87_264#_M1015_d N_A_87_264#_M1004_g
diff --git a/cells/maj3/sky130_fd_sc_ms__maj3_2.spice b/cells/maj3/sky130_fd_sc_ms__maj3_2.spice index d904dd3..f4117ab 100644 --- a/cells/maj3/sky130_fd_sc_ms__maj3_2.spice +++ b/cells/maj3/sky130_fd_sc_ms__maj3_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__maj3_2.spice -* Created: Fri Aug 28 17:38:55 2020 +* Created: Wed Sep 2 12:11:25 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/maj3/sky130_fd_sc_ms__maj3_4.lvs.report b/cells/maj3/sky130_fd_sc_ms__maj3_4.lvs.report new file mode 100644 index 0000000..7846eeb --- /dev/null +++ b/cells/maj3/sky130_fd_sc_ms__maj3_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__maj3_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__maj3_4.sp ('sky130_fd_sc_ms__maj3_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/maj3/sky130_fd_sc_ms__maj3_4.spice ('sky130_fd_sc_ms__maj3_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:11:29 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__maj3_4 sky130_fd_sc_ms__maj3_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__maj3_4 +SOURCE CELL NAME: sky130_fd_sc_ms__maj3_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 3 3 SMN2 (4 pins) + 3 3 SMP2 (4 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 3 3 0 0 SMN2 + 3 3 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 32 layout mos transistors were reduced to 14. + 18 mos transistors were deleted by parallel reduction. + 32 source mos transistors were reduced to 14. + 18 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A C VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/maj3/sky130_fd_sc_ms__maj3_4.pex.spice b/cells/maj3/sky130_fd_sc_ms__maj3_4.pex.spice index a4a1c88..5e61ef8 100644 --- a/cells/maj3/sky130_fd_sc_ms__maj3_4.pex.spice +++ b/cells/maj3/sky130_fd_sc_ms__maj3_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__maj3_4.pex.spice -* Created: Fri Aug 28 17:39:25 2020 +* Created: Wed Sep 2 12:11:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/maj3/sky130_fd_sc_ms__maj3_4.pxi.spice b/cells/maj3/sky130_fd_sc_ms__maj3_4.pxi.spice index 4fab9f7..84f1bfe 100644 --- a/cells/maj3/sky130_fd_sc_ms__maj3_4.pxi.spice +++ b/cells/maj3/sky130_fd_sc_ms__maj3_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__maj3_4.pxi.spice -* Created: Fri Aug 28 17:39:25 2020 +* Created: Wed Sep 2 12:11:32 2020 * x_PM_SKY130_FD_SC_MS__MAJ3_4%B N_B_M1004_g N_B_c_144_n N_B_M1017_g N_B_c_145_n + N_B_M1008_g N_B_c_146_n N_B_M1025_g N_B_M1030_g N_B_c_147_n N_B_M1000_g
diff --git a/cells/maj3/sky130_fd_sc_ms__maj3_4.spice b/cells/maj3/sky130_fd_sc_ms__maj3_4.spice index b0b4b88..f43cff6 100644 --- a/cells/maj3/sky130_fd_sc_ms__maj3_4.spice +++ b/cells/maj3/sky130_fd_sc_ms__maj3_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__maj3_4.spice -* Created: Fri Aug 28 17:39:25 2020 +* Created: Wed Sep 2 12:11:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/mux2/sky130_fd_sc_ms__mux2_1.lvs.report b/cells/mux2/sky130_fd_sc_ms__mux2_1.lvs.report new file mode 100644 index 0000000..eaab8cf --- /dev/null +++ b/cells/mux2/sky130_fd_sc_ms__mux2_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__mux2_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__mux2_1.sp ('sky130_fd_sc_ms__mux2_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/mux2/sky130_fd_sc_ms__mux2_1.spice ('sky130_fd_sc_ms__mux2_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:11:36 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__mux2_1 sky130_fd_sc_ms__mux2_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__mux2_1 +SOURCE CELL NAME: sky130_fd_sc_ms__mux2_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 14 14 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB S A1 A0 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_ms__mux2_1.pex.spice b/cells/mux2/sky130_fd_sc_ms__mux2_1.pex.spice index e99f2f6..14ef987 100644 --- a/cells/mux2/sky130_fd_sc_ms__mux2_1.pex.spice +++ b/cells/mux2/sky130_fd_sc_ms__mux2_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2_1.pex.spice -* Created: Fri Aug 28 17:39:35 2020 +* Created: Wed Sep 2 12:11:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_ms__mux2_1.pxi.spice b/cells/mux2/sky130_fd_sc_ms__mux2_1.pxi.spice index d82921a..97c2560 100644 --- a/cells/mux2/sky130_fd_sc_ms__mux2_1.pxi.spice +++ b/cells/mux2/sky130_fd_sc_ms__mux2_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2_1.pxi.spice -* Created: Fri Aug 28 17:39:35 2020 +* Created: Wed Sep 2 12:11:39 2020 * x_PM_SKY130_FD_SC_MS__MUX2_1%S N_S_M1003_g N_S_M1006_g N_S_M1011_g N_S_M1008_g + N_S_c_78_n N_S_c_79_n N_S_c_80_n S N_S_c_81_n PM_SKY130_FD_SC_MS__MUX2_1%S
diff --git a/cells/mux2/sky130_fd_sc_ms__mux2_1.spice b/cells/mux2/sky130_fd_sc_ms__mux2_1.spice index 4a78f9f..a80f81e 100644 --- a/cells/mux2/sky130_fd_sc_ms__mux2_1.spice +++ b/cells/mux2/sky130_fd_sc_ms__mux2_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2_1.spice -* Created: Fri Aug 28 17:39:35 2020 +* Created: Wed Sep 2 12:11:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/mux2/sky130_fd_sc_ms__mux2_2.lvs.report b/cells/mux2/sky130_fd_sc_ms__mux2_2.lvs.report new file mode 100644 index 0000000..463a413 --- /dev/null +++ b/cells/mux2/sky130_fd_sc_ms__mux2_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__mux2_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__mux2_2.sp ('sky130_fd_sc_ms__mux2_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/mux2/sky130_fd_sc_ms__mux2_2.spice ('sky130_fd_sc_ms__mux2_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:11:43 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__mux2_2 sky130_fd_sc_ms__mux2_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__mux2_2 +SOURCE CELL NAME: sky130_fd_sc_ms__mux2_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 14 14 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A0 A1 S VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_ms__mux2_2.pex.spice b/cells/mux2/sky130_fd_sc_ms__mux2_2.pex.spice index 1920be1..4790f69 100644 --- a/cells/mux2/sky130_fd_sc_ms__mux2_2.pex.spice +++ b/cells/mux2/sky130_fd_sc_ms__mux2_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2_2.pex.spice -* Created: Fri Aug 28 17:39:44 2020 +* Created: Wed Sep 2 12:11:46 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_ms__mux2_2.pxi.spice b/cells/mux2/sky130_fd_sc_ms__mux2_2.pxi.spice index 00e356b..b87d522 100644 --- a/cells/mux2/sky130_fd_sc_ms__mux2_2.pxi.spice +++ b/cells/mux2/sky130_fd_sc_ms__mux2_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2_2.pxi.spice -* Created: Fri Aug 28 17:39:44 2020 +* Created: Wed Sep 2 12:11:46 2020 * x_PM_SKY130_FD_SC_MS__MUX2_2%A0 N_A0_M1000_g N_A0_c_96_n N_A0_M1002_g A0 + N_A0_c_98_n PM_SKY130_FD_SC_MS__MUX2_2%A0
diff --git a/cells/mux2/sky130_fd_sc_ms__mux2_2.spice b/cells/mux2/sky130_fd_sc_ms__mux2_2.spice index e88e885..d32b37e 100644 --- a/cells/mux2/sky130_fd_sc_ms__mux2_2.spice +++ b/cells/mux2/sky130_fd_sc_ms__mux2_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2_2.spice -* Created: Fri Aug 28 17:39:44 2020 +* Created: Wed Sep 2 12:11:46 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/mux2/sky130_fd_sc_ms__mux2_4.lvs.report b/cells/mux2/sky130_fd_sc_ms__mux2_4.lvs.report new file mode 100644 index 0000000..52c48ad --- /dev/null +++ b/cells/mux2/sky130_fd_sc_ms__mux2_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__mux2_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__mux2_4.sp ('sky130_fd_sc_ms__mux2_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/mux2/sky130_fd_sc_ms__mux2_4.spice ('sky130_fd_sc_ms__mux2_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:11:49 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__mux2_4 sky130_fd_sc_ms__mux2_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__mux2_4 +SOURCE CELL NAME: sky130_fd_sc_ms__mux2_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 14 14 + + Instances: 13 13 MN (4 pins) + 13 13 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 27 26 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB S A0 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_ms__mux2_4.pex.spice b/cells/mux2/sky130_fd_sc_ms__mux2_4.pex.spice index 9f681cc..b66620a 100644 --- a/cells/mux2/sky130_fd_sc_ms__mux2_4.pex.spice +++ b/cells/mux2/sky130_fd_sc_ms__mux2_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2_4.pex.spice -* Created: Fri Aug 28 17:39:53 2020 +* Created: Wed Sep 2 12:11:53 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_ms__mux2_4.pxi.spice b/cells/mux2/sky130_fd_sc_ms__mux2_4.pxi.spice index 1fb3897..db716a8 100644 --- a/cells/mux2/sky130_fd_sc_ms__mux2_4.pxi.spice +++ b/cells/mux2/sky130_fd_sc_ms__mux2_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2_4.pxi.spice -* Created: Fri Aug 28 17:39:53 2020 +* Created: Wed Sep 2 12:11:53 2020 * x_PM_SKY130_FD_SC_MS__MUX2_4%S N_S_M1009_g N_S_M1002_g N_S_M1001_g N_S_M1010_g + N_S_M1024_g N_S_M1013_g N_S_c_166_n N_S_c_176_p N_S_c_177_p N_S_c_182_p
diff --git a/cells/mux2/sky130_fd_sc_ms__mux2_4.spice b/cells/mux2/sky130_fd_sc_ms__mux2_4.spice index efafd50..8424a32 100644 --- a/cells/mux2/sky130_fd_sc_ms__mux2_4.spice +++ b/cells/mux2/sky130_fd_sc_ms__mux2_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2_4.spice -* Created: Fri Aug 28 17:39:53 2020 +* Created: Wed Sep 2 12:11:53 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/mux2i/sky130_fd_sc_ms__mux2i_1.lvs.report b/cells/mux2i/sky130_fd_sc_ms__mux2i_1.lvs.report new file mode 100644 index 0000000..50fcec8 --- /dev/null +++ b/cells/mux2i/sky130_fd_sc_ms__mux2i_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__mux2i_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__mux2i_1.sp ('sky130_fd_sc_ms__mux2i_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/mux2i/sky130_fd_sc_ms__mux2i_1.spice ('sky130_fd_sc_ms__mux2i_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:11:56 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__mux2i_1 sky130_fd_sc_ms__mux2i_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__mux2i_1 +SOURCE CELL NAME: sky130_fd_sc_ms__mux2i_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB S A0 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/mux2i/sky130_fd_sc_ms__mux2i_1.pex.spice b/cells/mux2i/sky130_fd_sc_ms__mux2i_1.pex.spice index e6d8ae1..ca38ba6 100644 --- a/cells/mux2i/sky130_fd_sc_ms__mux2i_1.pex.spice +++ b/cells/mux2i/sky130_fd_sc_ms__mux2i_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2i_1.pex.spice -* Created: Fri Aug 28 17:40:02 2020 +* Created: Wed Sep 2 12:11:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/mux2i/sky130_fd_sc_ms__mux2i_1.pxi.spice b/cells/mux2i/sky130_fd_sc_ms__mux2i_1.pxi.spice index c6d4c40..adf2d64 100644 --- a/cells/mux2i/sky130_fd_sc_ms__mux2i_1.pxi.spice +++ b/cells/mux2i/sky130_fd_sc_ms__mux2i_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2i_1.pxi.spice -* Created: Fri Aug 28 17:40:02 2020 +* Created: Wed Sep 2 12:11:59 2020 * x_PM_SKY130_FD_SC_MS__MUX2I_1%S N_S_M1009_g N_S_M1007_g N_S_c_70_n N_S_M1002_g + N_S_c_72_n N_S_M1008_g N_S_c_73_n N_S_c_79_n N_S_c_74_n S S N_S_c_76_n
diff --git a/cells/mux2i/sky130_fd_sc_ms__mux2i_1.spice b/cells/mux2i/sky130_fd_sc_ms__mux2i_1.spice index 80c68ff..6aebebe 100644 --- a/cells/mux2i/sky130_fd_sc_ms__mux2i_1.spice +++ b/cells/mux2i/sky130_fd_sc_ms__mux2i_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2i_1.spice -* Created: Fri Aug 28 17:40:02 2020 +* Created: Wed Sep 2 12:11:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/mux2i/sky130_fd_sc_ms__mux2i_2.lvs.report b/cells/mux2i/sky130_fd_sc_ms__mux2i_2.lvs.report new file mode 100644 index 0000000..544c086 --- /dev/null +++ b/cells/mux2i/sky130_fd_sc_ms__mux2i_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__mux2i_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__mux2i_2.sp ('sky130_fd_sc_ms__mux2i_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/mux2i/sky130_fd_sc_ms__mux2i_2.spice ('sky130_fd_sc_ms__mux2i_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:12:03 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__mux2i_2 sky130_fd_sc_ms__mux2i_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__mux2i_2 +SOURCE CELL NAME: sky130_fd_sc_ms__mux2i_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 13 13 + + Instances: 9 9 MN (4 pins) + 9 9 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 19 18 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A0 A1 S Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/mux2i/sky130_fd_sc_ms__mux2i_2.pex.spice b/cells/mux2i/sky130_fd_sc_ms__mux2i_2.pex.spice index d5708b1..42aa1b7 100644 --- a/cells/mux2i/sky130_fd_sc_ms__mux2i_2.pex.spice +++ b/cells/mux2i/sky130_fd_sc_ms__mux2i_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2i_2.pex.spice -* Created: Fri Aug 28 17:40:32 2020 +* Created: Wed Sep 2 12:12:06 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/mux2i/sky130_fd_sc_ms__mux2i_2.pxi.spice b/cells/mux2i/sky130_fd_sc_ms__mux2i_2.pxi.spice index 70ea579..f67b348 100644 --- a/cells/mux2i/sky130_fd_sc_ms__mux2i_2.pxi.spice +++ b/cells/mux2i/sky130_fd_sc_ms__mux2i_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2i_2.pxi.spice -* Created: Fri Aug 28 17:40:32 2020 +* Created: Wed Sep 2 12:12:06 2020 * x_PM_SKY130_FD_SC_MS__MUX2I_2%A0 N_A0_c_92_n N_A0_M1008_g N_A0_M1002_g + N_A0_M1011_g N_A0_c_95_n N_A0_M1016_g A0 A0 N_A0_c_97_n
diff --git a/cells/mux2i/sky130_fd_sc_ms__mux2i_2.spice b/cells/mux2i/sky130_fd_sc_ms__mux2i_2.spice index 3d87c21..5424de0 100644 --- a/cells/mux2i/sky130_fd_sc_ms__mux2i_2.spice +++ b/cells/mux2i/sky130_fd_sc_ms__mux2i_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2i_2.spice -* Created: Fri Aug 28 17:40:32 2020 +* Created: Wed Sep 2 12:12:06 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/mux2i/sky130_fd_sc_ms__mux2i_4.lvs.report b/cells/mux2i/sky130_fd_sc_ms__mux2i_4.lvs.report new file mode 100644 index 0000000..ab6671b --- /dev/null +++ b/cells/mux2i/sky130_fd_sc_ms__mux2i_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__mux2i_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__mux2i_4.sp ('sky130_fd_sc_ms__mux2i_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/mux2i/sky130_fd_sc_ms__mux2i_4.spice ('sky130_fd_sc_ms__mux2i_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:12:10 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__mux2i_4 sky130_fd_sc_ms__mux2i_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__mux2i_4 +SOURCE CELL NAME: sky130_fd_sc_ms__mux2i_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 13 13 + + Instances: 17 17 MN (4 pins) + 18 18 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 36 35 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 34 layout mos transistors were reduced to 9. + 25 mos transistors were deleted by parallel reduction. + 34 source mos transistors were reduced to 9. + 25 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A0 S Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/mux2i/sky130_fd_sc_ms__mux2i_4.pex.spice b/cells/mux2i/sky130_fd_sc_ms__mux2i_4.pex.spice index a7bd370..71af8e9 100644 --- a/cells/mux2i/sky130_fd_sc_ms__mux2i_4.pex.spice +++ b/cells/mux2i/sky130_fd_sc_ms__mux2i_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2i_4.pex.spice -* Created: Fri Aug 28 17:40:42 2020 +* Created: Wed Sep 2 12:12:13 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/mux2i/sky130_fd_sc_ms__mux2i_4.pxi.spice b/cells/mux2i/sky130_fd_sc_ms__mux2i_4.pxi.spice index a46fc2b..a5ddc0b 100644 --- a/cells/mux2i/sky130_fd_sc_ms__mux2i_4.pxi.spice +++ b/cells/mux2i/sky130_fd_sc_ms__mux2i_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2i_4.pxi.spice -* Created: Fri Aug 28 17:40:42 2020 +* Created: Wed Sep 2 12:12:13 2020 * x_PM_SKY130_FD_SC_MS__MUX2I_4%A1 N_A1_M1008_g N_A1_M1000_g N_A1_M1005_g + N_A1_M1009_g N_A1_M1022_g N_A1_M1011_g N_A1_M1015_g N_A1_M1023_g A1 A1 A1
diff --git a/cells/mux2i/sky130_fd_sc_ms__mux2i_4.spice b/cells/mux2i/sky130_fd_sc_ms__mux2i_4.spice index efed995..609b8fa 100644 --- a/cells/mux2i/sky130_fd_sc_ms__mux2i_4.spice +++ b/cells/mux2i/sky130_fd_sc_ms__mux2i_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux2i_4.spice -* Created: Fri Aug 28 17:40:42 2020 +* Created: Wed Sep 2 12:12:13 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/mux4/sky130_fd_sc_ms__mux4_1.lvs.report b/cells/mux4/sky130_fd_sc_ms__mux4_1.lvs.report new file mode 100644 index 0000000..2fee4f9 --- /dev/null +++ b/cells/mux4/sky130_fd_sc_ms__mux4_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__mux4_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__mux4_1.sp ('sky130_fd_sc_ms__mux4_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/mux4/sky130_fd_sc_ms__mux4_1.spice ('sky130_fd_sc_ms__mux4_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:12:17 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__mux4_1 sky130_fd_sc_ms__mux4_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__mux4_1 +SOURCE CELL NAME: sky130_fd_sc_ms__mux4_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 24 24 + + Instances: 13 13 MN (4 pins) + 13 13 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 27 26 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 16 16 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 4 4 SMN2 (4 pins) + 4 4 SMP2 (4 pins) + ------ ------ + Total Inst: 18 18 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 11 11 0 0 + + Nets: 16 16 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 4 4 0 0 SMN2 + 4 4 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 18 18 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A0 A1 A2 S0 A3 S1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/mux4/sky130_fd_sc_ms__mux4_1.pex.spice b/cells/mux4/sky130_fd_sc_ms__mux4_1.pex.spice index 5a5ac4a..2998dd1 100644 --- a/cells/mux4/sky130_fd_sc_ms__mux4_1.pex.spice +++ b/cells/mux4/sky130_fd_sc_ms__mux4_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux4_1.pex.spice -* Created: Fri Aug 28 17:40:51 2020 +* Created: Wed Sep 2 12:12:20 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/mux4/sky130_fd_sc_ms__mux4_1.pxi.spice b/cells/mux4/sky130_fd_sc_ms__mux4_1.pxi.spice index 42547ad..d9401ca 100644 --- a/cells/mux4/sky130_fd_sc_ms__mux4_1.pxi.spice +++ b/cells/mux4/sky130_fd_sc_ms__mux4_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux4_1.pxi.spice -* Created: Fri Aug 28 17:40:51 2020 +* Created: Wed Sep 2 12:12:20 2020 * x_PM_SKY130_FD_SC_MS__MUX4_1%A0 N_A0_M1020_g N_A0_M1014_g A0 N_A0_c_184_n + N_A0_c_185_n PM_SKY130_FD_SC_MS__MUX4_1%A0
diff --git a/cells/mux4/sky130_fd_sc_ms__mux4_1.spice b/cells/mux4/sky130_fd_sc_ms__mux4_1.spice index c677e63..8fbbd8e 100644 --- a/cells/mux4/sky130_fd_sc_ms__mux4_1.spice +++ b/cells/mux4/sky130_fd_sc_ms__mux4_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux4_1.spice -* Created: Fri Aug 28 17:40:51 2020 +* Created: Wed Sep 2 12:12:20 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/mux4/sky130_fd_sc_ms__mux4_2.lvs.report b/cells/mux4/sky130_fd_sc_ms__mux4_2.lvs.report new file mode 100644 index 0000000..d0a5558 --- /dev/null +++ b/cells/mux4/sky130_fd_sc_ms__mux4_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__mux4_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__mux4_2.sp ('sky130_fd_sc_ms__mux4_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/mux4/sky130_fd_sc_ms__mux4_2.spice ('sky130_fd_sc_ms__mux4_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:12:24 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__mux4_2 sky130_fd_sc_ms__mux4_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__mux4_2 +SOURCE CELL NAME: sky130_fd_sc_ms__mux4_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 24 24 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 16 16 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 4 4 SMN2 (4 pins) + 4 4 SMP2 (4 pins) + ------ ------ + Total Inst: 18 18 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 11 11 0 0 + + Nets: 16 16 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 4 4 0 0 SMN2 + 4 4 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 18 18 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB S0 A1 A0 A3 A2 S1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/mux4/sky130_fd_sc_ms__mux4_2.pex.spice b/cells/mux4/sky130_fd_sc_ms__mux4_2.pex.spice index 544e7e7..12d0d10 100644 --- a/cells/mux4/sky130_fd_sc_ms__mux4_2.pex.spice +++ b/cells/mux4/sky130_fd_sc_ms__mux4_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux4_2.pex.spice -* Created: Fri Aug 28 17:40:59 2020 +* Created: Wed Sep 2 12:12:27 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/mux4/sky130_fd_sc_ms__mux4_2.pxi.spice b/cells/mux4/sky130_fd_sc_ms__mux4_2.pxi.spice index 1d71d6b..890966f 100644 --- a/cells/mux4/sky130_fd_sc_ms__mux4_2.pxi.spice +++ b/cells/mux4/sky130_fd_sc_ms__mux4_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux4_2.pxi.spice -* Created: Fri Aug 28 17:40:59 2020 +* Created: Wed Sep 2 12:12:27 2020 * x_PM_SKY130_FD_SC_MS__MUX4_2%S0 N_S0_M1000_g N_S0_M1001_g N_S0_M1011_g + N_S0_M1008_g N_S0_M1016_g N_S0_M1002_g N_S0_c_289_p N_S0_c_208_p N_S0_c_329_p
diff --git a/cells/mux4/sky130_fd_sc_ms__mux4_2.spice b/cells/mux4/sky130_fd_sc_ms__mux4_2.spice index dc525e3..21733c2 100644 --- a/cells/mux4/sky130_fd_sc_ms__mux4_2.spice +++ b/cells/mux4/sky130_fd_sc_ms__mux4_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux4_2.spice -* Created: Fri Aug 28 17:40:59 2020 +* Created: Wed Sep 2 12:12:27 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/mux4/sky130_fd_sc_ms__mux4_4.lvs.report b/cells/mux4/sky130_fd_sc_ms__mux4_4.lvs.report new file mode 100644 index 0000000..735fa30 --- /dev/null +++ b/cells/mux4/sky130_fd_sc_ms__mux4_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__mux4_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__mux4_4.sp ('sky130_fd_sc_ms__mux4_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/mux4/sky130_fd_sc_ms__mux4_4.spice ('sky130_fd_sc_ms__mux4_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:12:31 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__mux4_4 sky130_fd_sc_ms__mux4_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__mux4_4 +SOURCE CELL NAME: sky130_fd_sc_ms__mux4_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 24 24 + + Instances: 26 26 MN (4 pins) + 26 26 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 53 52 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 16 16 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 4 4 SMN2 (4 pins) + 4 4 SMP2 (4 pins) + ------ ------ + Total Inst: 18 18 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 11 11 0 0 + + Nets: 16 16 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 4 4 0 0 SMN2 + 4 4 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 18 18 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 48 layout mos transistors were reduced to 22. + 26 mos transistors were deleted by parallel reduction. + 48 source mos transistors were reduced to 22. + 26 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A0 S0 A2 A3 S1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/mux4/sky130_fd_sc_ms__mux4_4.pex.spice b/cells/mux4/sky130_fd_sc_ms__mux4_4.pex.spice index 0f6e571..3441364 100644 --- a/cells/mux4/sky130_fd_sc_ms__mux4_4.pex.spice +++ b/cells/mux4/sky130_fd_sc_ms__mux4_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux4_4.pex.spice -* Created: Fri Aug 28 17:41:08 2020 +* Created: Wed Sep 2 12:12:34 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/mux4/sky130_fd_sc_ms__mux4_4.pxi.spice b/cells/mux4/sky130_fd_sc_ms__mux4_4.pxi.spice index e9ed019..d4f6680 100644 --- a/cells/mux4/sky130_fd_sc_ms__mux4_4.pxi.spice +++ b/cells/mux4/sky130_fd_sc_ms__mux4_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux4_4.pxi.spice -* Created: Fri Aug 28 17:41:08 2020 +* Created: Wed Sep 2 12:12:34 2020 * x_PM_SKY130_FD_SC_MS__MUX4_4%A1 N_A1_M1003_g N_A1_M1025_g N_A1_M1033_g + N_A1_M1004_g A1 A1 N_A1_c_312_n PM_SKY130_FD_SC_MS__MUX4_4%A1
diff --git a/cells/mux4/sky130_fd_sc_ms__mux4_4.spice b/cells/mux4/sky130_fd_sc_ms__mux4_4.spice index 823d17c..8e87ee6 100644 --- a/cells/mux4/sky130_fd_sc_ms__mux4_4.spice +++ b/cells/mux4/sky130_fd_sc_ms__mux4_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__mux4_4.spice -* Created: Fri Aug 28 17:41:08 2020 +* Created: Wed Sep 2 12:12:34 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_1.lvs.report b/cells/nand2/sky130_fd_sc_ms__nand2_1.lvs.report new file mode 100644 index 0000000..8b47d4a --- /dev/null +++ b/cells/nand2/sky130_fd_sc_ms__nand2_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand2_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand2_1.sp ('sky130_fd_sc_ms__nand2_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand2/sky130_fd_sc_ms__nand2_1.spice ('sky130_fd_sc_ms__nand2_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:12:38 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand2_1 sky130_fd_sc_ms__nand2_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand2_1 +SOURCE CELL NAME: sky130_fd_sc_ms__nand2_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 5 4 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 7 7 + + Instances: 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_1.pex.spice b/cells/nand2/sky130_fd_sc_ms__nand2_1.pex.spice index 034cd7d..ef3d018 100644 --- a/cells/nand2/sky130_fd_sc_ms__nand2_1.pex.spice +++ b/cells/nand2/sky130_fd_sc_ms__nand2_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2_1.pex.spice -* Created: Fri Aug 28 17:41:38 2020 +* Created: Wed Sep 2 12:12:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_1.pxi.spice b/cells/nand2/sky130_fd_sc_ms__nand2_1.pxi.spice index 4a8bfc8..a54542f 100644 --- a/cells/nand2/sky130_fd_sc_ms__nand2_1.pxi.spice +++ b/cells/nand2/sky130_fd_sc_ms__nand2_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2_1.pxi.spice -* Created: Fri Aug 28 17:41:38 2020 +* Created: Wed Sep 2 12:12:41 2020 * x_PM_SKY130_FD_SC_MS__NAND2_1%B N_B_M1001_g N_B_c_28_n N_B_M1003_g B N_B_c_30_n + PM_SKY130_FD_SC_MS__NAND2_1%B
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_1.spice b/cells/nand2/sky130_fd_sc_ms__nand2_1.spice index 1171d78..529f85f 100644 --- a/cells/nand2/sky130_fd_sc_ms__nand2_1.spice +++ b/cells/nand2/sky130_fd_sc_ms__nand2_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2_1.spice -* Created: Fri Aug 28 17:41:38 2020 +* Created: Wed Sep 2 12:12:41 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_2.lvs.report b/cells/nand2/sky130_fd_sc_ms__nand2_2.lvs.report new file mode 100644 index 0000000..fa9456e --- /dev/null +++ b/cells/nand2/sky130_fd_sc_ms__nand2_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand2_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand2_2.sp ('sky130_fd_sc_ms__nand2_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand2/sky130_fd_sc_ms__nand2_2.spice ('sky130_fd_sc_ms__nand2_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:12:45 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand2_2 sky130_fd_sc_ms__nand2_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand2_2 +SOURCE CELL NAME: sky130_fd_sc_ms__nand2_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 7 7 + + Instances: 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_2.pex.spice b/cells/nand2/sky130_fd_sc_ms__nand2_2.pex.spice index 48522d5..bb2b689 100644 --- a/cells/nand2/sky130_fd_sc_ms__nand2_2.pex.spice +++ b/cells/nand2/sky130_fd_sc_ms__nand2_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2_2.pex.spice -* Created: Fri Aug 28 17:41:47 2020 +* Created: Wed Sep 2 12:12:48 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_2.pxi.spice b/cells/nand2/sky130_fd_sc_ms__nand2_2.pxi.spice index 4eb5eab..b5014d5 100644 --- a/cells/nand2/sky130_fd_sc_ms__nand2_2.pxi.spice +++ b/cells/nand2/sky130_fd_sc_ms__nand2_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2_2.pxi.spice -* Created: Fri Aug 28 17:41:47 2020 +* Created: Wed Sep 2 12:12:48 2020 * x_PM_SKY130_FD_SC_MS__NAND2_2%B N_B_M1005_g N_B_M1000_g N_B_M1001_g N_B_M1007_g + B B N_B_c_48_n PM_SKY130_FD_SC_MS__NAND2_2%B
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_2.spice b/cells/nand2/sky130_fd_sc_ms__nand2_2.spice index d2499e7..409901c 100644 --- a/cells/nand2/sky130_fd_sc_ms__nand2_2.spice +++ b/cells/nand2/sky130_fd_sc_ms__nand2_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2_2.spice -* Created: Fri Aug 28 17:41:47 2020 +* Created: Wed Sep 2 12:12:48 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_4.lvs.report b/cells/nand2/sky130_fd_sc_ms__nand2_4.lvs.report new file mode 100644 index 0000000..f3527ba --- /dev/null +++ b/cells/nand2/sky130_fd_sc_ms__nand2_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand2_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand2_4.sp ('sky130_fd_sc_ms__nand2_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand2/sky130_fd_sc_ms__nand2_4.spice ('sky130_fd_sc_ms__nand2_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:12:52 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand2_4 sky130_fd_sc_ms__nand2_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand2_4 +SOURCE CELL NAME: sky130_fd_sc_ms__nand2_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 8 8 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 7 7 + + Instances: 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 4. + 8 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 4. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_4.pex.spice b/cells/nand2/sky130_fd_sc_ms__nand2_4.pex.spice index 7b74855..85db37f 100644 --- a/cells/nand2/sky130_fd_sc_ms__nand2_4.pex.spice +++ b/cells/nand2/sky130_fd_sc_ms__nand2_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2_4.pex.spice -* Created: Fri Aug 28 17:41:56 2020 +* Created: Wed Sep 2 12:12:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_4.pxi.spice b/cells/nand2/sky130_fd_sc_ms__nand2_4.pxi.spice index fcdb8af..e6a70ea 100644 --- a/cells/nand2/sky130_fd_sc_ms__nand2_4.pxi.spice +++ b/cells/nand2/sky130_fd_sc_ms__nand2_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2_4.pxi.spice -* Created: Fri Aug 28 17:41:56 2020 +* Created: Wed Sep 2 12:12:55 2020 * x_PM_SKY130_FD_SC_MS__NAND2_4%B N_B_M1004_g N_B_M1001_g N_B_M1007_g N_B_M1010_g + N_B_M1008_g N_B_M1011_g B B B N_B_c_72_n N_B_c_77_n N_B_c_94_p
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_4.spice b/cells/nand2/sky130_fd_sc_ms__nand2_4.spice index b64eca6..48c7944 100644 --- a/cells/nand2/sky130_fd_sc_ms__nand2_4.spice +++ b/cells/nand2/sky130_fd_sc_ms__nand2_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2_4.spice -* Created: Fri Aug 28 17:41:56 2020 +* Created: Wed Sep 2 12:12:55 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_8.lvs.report b/cells/nand2/sky130_fd_sc_ms__nand2_8.lvs.report new file mode 100644 index 0000000..7f13ac7 --- /dev/null +++ b/cells/nand2/sky130_fd_sc_ms__nand2_8.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand2_8.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand2_8.sp ('sky130_fd_sc_ms__nand2_8') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand2/sky130_fd_sc_ms__nand2_8.spice ('sky130_fd_sc_ms__nand2_8') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:12:59 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand2_8 sky130_fd_sc_ms__nand2_8 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand2_8 +SOURCE CELL NAME: sky130_fd_sc_ms__nand2_8 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 16 16 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 7 7 + + Instances: 2 2 MP (4 pins) + 1 1 SMN2 (4 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 4. + 20 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 4. + 20 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_8.pex.spice b/cells/nand2/sky130_fd_sc_ms__nand2_8.pex.spice index 113e5b0..003aafe 100644 --- a/cells/nand2/sky130_fd_sc_ms__nand2_8.pex.spice +++ b/cells/nand2/sky130_fd_sc_ms__nand2_8.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2_8.pex.spice -* Created: Fri Aug 28 17:42:05 2020 +* Created: Wed Sep 2 12:13:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_8.pxi.spice b/cells/nand2/sky130_fd_sc_ms__nand2_8.pxi.spice index d100265..3e4cb35 100644 --- a/cells/nand2/sky130_fd_sc_ms__nand2_8.pxi.spice +++ b/cells/nand2/sky130_fd_sc_ms__nand2_8.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2_8.pxi.spice -* Created: Fri Aug 28 17:42:05 2020 +* Created: Wed Sep 2 12:13:02 2020 * x_PM_SKY130_FD_SC_MS__NAND2_8%B N_B_c_110_n N_B_M1000_g N_B_c_111_n N_B_c_112_n + N_B_c_113_n N_B_M1001_g N_B_c_114_n N_B_c_115_n N_B_M1002_g N_B_c_116_n
diff --git a/cells/nand2/sky130_fd_sc_ms__nand2_8.spice b/cells/nand2/sky130_fd_sc_ms__nand2_8.spice index 889a725..2a6a605 100644 --- a/cells/nand2/sky130_fd_sc_ms__nand2_8.spice +++ b/cells/nand2/sky130_fd_sc_ms__nand2_8.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2_8.spice -* Created: Fri Aug 28 17:42:05 2020 +* Created: Wed Sep 2 12:13:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand2b/sky130_fd_sc_ms__nand2b_1.lvs.report b/cells/nand2b/sky130_fd_sc_ms__nand2b_1.lvs.report new file mode 100644 index 0000000..9351a9f --- /dev/null +++ b/cells/nand2b/sky130_fd_sc_ms__nand2b_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand2b_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand2b_1.sp ('sky130_fd_sc_ms__nand2b_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand2b/sky130_fd_sc_ms__nand2b_1.spice ('sky130_fd_sc_ms__nand2b_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:13:06 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand2b_1 sky130_fd_sc_ms__nand2b_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand2b_1 +SOURCE CELL NAME: sky130_fd_sc_ms__nand2b_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMN2 (4 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand2b/sky130_fd_sc_ms__nand2b_1.pex.spice b/cells/nand2b/sky130_fd_sc_ms__nand2b_1.pex.spice index a40c0e2..0cc659b 100644 --- a/cells/nand2b/sky130_fd_sc_ms__nand2b_1.pex.spice +++ b/cells/nand2b/sky130_fd_sc_ms__nand2b_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2b_1.pex.spice -* Created: Fri Aug 28 17:42:14 2020 +* Created: Wed Sep 2 12:13:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand2b/sky130_fd_sc_ms__nand2b_1.pxi.spice b/cells/nand2b/sky130_fd_sc_ms__nand2b_1.pxi.spice index 1ac6988..dde8dbe 100644 --- a/cells/nand2b/sky130_fd_sc_ms__nand2b_1.pxi.spice +++ b/cells/nand2b/sky130_fd_sc_ms__nand2b_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2b_1.pxi.spice -* Created: Fri Aug 28 17:42:14 2020 +* Created: Wed Sep 2 12:13:09 2020 * x_PM_SKY130_FD_SC_MS__NAND2B_1%A_N N_A_N_M1002_g N_A_N_M1003_g A_N A_N + N_A_N_c_47_n PM_SKY130_FD_SC_MS__NAND2B_1%A_N
diff --git a/cells/nand2b/sky130_fd_sc_ms__nand2b_1.spice b/cells/nand2b/sky130_fd_sc_ms__nand2b_1.spice index 69a1f44..aaa18e6 100644 --- a/cells/nand2b/sky130_fd_sc_ms__nand2b_1.spice +++ b/cells/nand2b/sky130_fd_sc_ms__nand2b_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2b_1.spice -* Created: Fri Aug 28 17:42:14 2020 +* Created: Wed Sep 2 12:13:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand2b/sky130_fd_sc_ms__nand2b_2.lvs.report b/cells/nand2b/sky130_fd_sc_ms__nand2b_2.lvs.report new file mode 100644 index 0000000..132e961 --- /dev/null +++ b/cells/nand2b/sky130_fd_sc_ms__nand2b_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand2b_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand2b_2.sp ('sky130_fd_sc_ms__nand2b_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand2b/sky130_fd_sc_ms__nand2b_2.spice ('sky130_fd_sc_ms__nand2b_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:13:12 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand2b_2 sky130_fd_sc_ms__nand2b_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand2b_2 +SOURCE CELL NAME: sky130_fd_sc_ms__nand2b_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMN2 (4 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand2b/sky130_fd_sc_ms__nand2b_2.pex.spice b/cells/nand2b/sky130_fd_sc_ms__nand2b_2.pex.spice index f3af684..43650c0 100644 --- a/cells/nand2b/sky130_fd_sc_ms__nand2b_2.pex.spice +++ b/cells/nand2b/sky130_fd_sc_ms__nand2b_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2b_2.pex.spice -* Created: Fri Aug 28 17:42:44 2020 +* Created: Wed Sep 2 12:13:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand2b/sky130_fd_sc_ms__nand2b_2.pxi.spice b/cells/nand2b/sky130_fd_sc_ms__nand2b_2.pxi.spice index 4bebeff..ab8b659 100644 --- a/cells/nand2b/sky130_fd_sc_ms__nand2b_2.pxi.spice +++ b/cells/nand2b/sky130_fd_sc_ms__nand2b_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2b_2.pxi.spice -* Created: Fri Aug 28 17:42:44 2020 +* Created: Wed Sep 2 12:13:16 2020 * x_PM_SKY130_FD_SC_MS__NAND2B_2%A_N N_A_N_c_69_n N_A_N_M1003_g N_A_N_M1008_g A_N + N_A_N_c_71_n PM_SKY130_FD_SC_MS__NAND2B_2%A_N
diff --git a/cells/nand2b/sky130_fd_sc_ms__nand2b_2.spice b/cells/nand2b/sky130_fd_sc_ms__nand2b_2.spice index a990c5e..c9a1900 100644 --- a/cells/nand2b/sky130_fd_sc_ms__nand2b_2.spice +++ b/cells/nand2b/sky130_fd_sc_ms__nand2b_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2b_2.spice -* Created: Fri Aug 28 17:42:44 2020 +* Created: Wed Sep 2 12:13:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand2b/sky130_fd_sc_ms__nand2b_4.lvs.report b/cells/nand2b/sky130_fd_sc_ms__nand2b_4.lvs.report new file mode 100644 index 0000000..3a1cfce --- /dev/null +++ b/cells/nand2b/sky130_fd_sc_ms__nand2b_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand2b_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand2b_4.sp ('sky130_fd_sc_ms__nand2b_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand2b/sky130_fd_sc_ms__nand2b_4.spice ('sky130_fd_sc_ms__nand2b_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:13:19 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand2b_4 sky130_fd_sc_ms__nand2b_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand2b_4 +SOURCE CELL NAME: sky130_fd_sc_ms__nand2b_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 9 9 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 16 15 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 1 1 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMN2 (4 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 14 layout mos transistors were reduced to 5. + 9 mos transistors were deleted by parallel reduction. + 14 source mos transistors were reduced to 5. + 9 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand2b/sky130_fd_sc_ms__nand2b_4.pex.spice b/cells/nand2b/sky130_fd_sc_ms__nand2b_4.pex.spice index e272b8b..39a3bd9 100644 --- a/cells/nand2b/sky130_fd_sc_ms__nand2b_4.pex.spice +++ b/cells/nand2b/sky130_fd_sc_ms__nand2b_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2b_4.pex.spice -* Created: Fri Aug 28 17:42:54 2020 +* Created: Wed Sep 2 12:13:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand2b/sky130_fd_sc_ms__nand2b_4.pxi.spice b/cells/nand2b/sky130_fd_sc_ms__nand2b_4.pxi.spice index d2d4cda..465a155 100644 --- a/cells/nand2b/sky130_fd_sc_ms__nand2b_4.pxi.spice +++ b/cells/nand2b/sky130_fd_sc_ms__nand2b_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2b_4.pxi.spice -* Created: Fri Aug 28 17:42:54 2020 +* Created: Wed Sep 2 12:13:22 2020 * x_PM_SKY130_FD_SC_MS__NAND2B_4%A_N N_A_N_M1010_g N_A_N_c_92_n N_A_N_M1002_g + N_A_N_c_87_n N_A_N_c_94_n N_A_N_M1005_g N_A_N_c_88_n N_A_N_c_89_n A_N A_N
diff --git a/cells/nand2b/sky130_fd_sc_ms__nand2b_4.spice b/cells/nand2b/sky130_fd_sc_ms__nand2b_4.spice index 95cd4ec..6bfcaec 100644 --- a/cells/nand2b/sky130_fd_sc_ms__nand2b_4.spice +++ b/cells/nand2b/sky130_fd_sc_ms__nand2b_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand2b_4.spice -* Created: Fri Aug 28 17:42:54 2020 +* Created: Wed Sep 2 12:13:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand3/sky130_fd_sc_ms__nand3_1.lvs.report b/cells/nand3/sky130_fd_sc_ms__nand3_1.lvs.report new file mode 100644 index 0000000..b782e7e --- /dev/null +++ b/cells/nand3/sky130_fd_sc_ms__nand3_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand3_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand3_1.sp ('sky130_fd_sc_ms__nand3_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand3/sky130_fd_sc_ms__nand3_1.spice ('sky130_fd_sc_ms__nand3_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:13:26 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand3_1 sky130_fd_sc_ms__nand3_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand3_1 +SOURCE CELL NAME: sky130_fd_sc_ms__nand3_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 3 3 MP (4 pins) + 1 1 SMN3 (5 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C B A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand3/sky130_fd_sc_ms__nand3_1.pex.spice b/cells/nand3/sky130_fd_sc_ms__nand3_1.pex.spice index a22e1dc..ff06e41 100644 --- a/cells/nand3/sky130_fd_sc_ms__nand3_1.pex.spice +++ b/cells/nand3/sky130_fd_sc_ms__nand3_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3_1.pex.spice -* Created: Fri Aug 28 17:43:03 2020 +* Created: Wed Sep 2 12:13:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand3/sky130_fd_sc_ms__nand3_1.pxi.spice b/cells/nand3/sky130_fd_sc_ms__nand3_1.pxi.spice index a32cbde..e8a5d13 100644 --- a/cells/nand3/sky130_fd_sc_ms__nand3_1.pxi.spice +++ b/cells/nand3/sky130_fd_sc_ms__nand3_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3_1.pxi.spice -* Created: Fri Aug 28 17:43:03 2020 +* Created: Wed Sep 2 12:13:29 2020 * x_PM_SKY130_FD_SC_MS__NAND3_1%C N_C_M1003_g N_C_c_39_n N_C_M1002_g C C + N_C_c_41_n PM_SKY130_FD_SC_MS__NAND3_1%C
diff --git a/cells/nand3/sky130_fd_sc_ms__nand3_1.spice b/cells/nand3/sky130_fd_sc_ms__nand3_1.spice index 13dfd49..dfa7fe7 100644 --- a/cells/nand3/sky130_fd_sc_ms__nand3_1.spice +++ b/cells/nand3/sky130_fd_sc_ms__nand3_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3_1.spice -* Created: Fri Aug 28 17:43:03 2020 +* Created: Wed Sep 2 12:13:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand3/sky130_fd_sc_ms__nand3_2.lvs.report b/cells/nand3/sky130_fd_sc_ms__nand3_2.lvs.report new file mode 100644 index 0000000..d0d3a30 --- /dev/null +++ b/cells/nand3/sky130_fd_sc_ms__nand3_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand3_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand3_2.sp ('sky130_fd_sc_ms__nand3_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand3/sky130_fd_sc_ms__nand3_2.spice ('sky130_fd_sc_ms__nand3_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:13:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand3_2 sky130_fd_sc_ms__nand3_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand3_2 +SOURCE CELL NAME: sky130_fd_sc_ms__nand3_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 3 3 MP (4 pins) + 1 1 SMN3 (5 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C B A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand3/sky130_fd_sc_ms__nand3_2.pex.spice b/cells/nand3/sky130_fd_sc_ms__nand3_2.pex.spice index 7354e5d..d7399f4 100644 --- a/cells/nand3/sky130_fd_sc_ms__nand3_2.pex.spice +++ b/cells/nand3/sky130_fd_sc_ms__nand3_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3_2.pex.spice -* Created: Fri Aug 28 17:43:12 2020 +* Created: Wed Sep 2 12:13:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand3/sky130_fd_sc_ms__nand3_2.pxi.spice b/cells/nand3/sky130_fd_sc_ms__nand3_2.pxi.spice index 5c97871..76cffff 100644 --- a/cells/nand3/sky130_fd_sc_ms__nand3_2.pxi.spice +++ b/cells/nand3/sky130_fd_sc_ms__nand3_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3_2.pxi.spice -* Created: Fri Aug 28 17:43:12 2020 +* Created: Wed Sep 2 12:13:36 2020 * x_PM_SKY130_FD_SC_MS__NAND3_2%C N_C_c_61_n N_C_M1000_g N_C_M1004_g N_C_c_63_n + N_C_M1010_g N_C_M1005_g C N_C_c_65_n N_C_c_66_n PM_SKY130_FD_SC_MS__NAND3_2%C
diff --git a/cells/nand3/sky130_fd_sc_ms__nand3_2.spice b/cells/nand3/sky130_fd_sc_ms__nand3_2.spice index c1d2ad6..536d6c3 100644 --- a/cells/nand3/sky130_fd_sc_ms__nand3_2.spice +++ b/cells/nand3/sky130_fd_sc_ms__nand3_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3_2.spice -* Created: Fri Aug 28 17:43:12 2020 +* Created: Wed Sep 2 12:13:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand3/sky130_fd_sc_ms__nand3_4.lvs.report b/cells/nand3/sky130_fd_sc_ms__nand3_4.lvs.report new file mode 100644 index 0000000..108c9fc --- /dev/null +++ b/cells/nand3/sky130_fd_sc_ms__nand3_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand3_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand3_4.sp ('sky130_fd_sc_ms__nand3_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand3/sky130_fd_sc_ms__nand3_4.spice ('sky130_fd_sc_ms__nand3_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:13:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand3_4 sky130_fd_sc_ms__nand3_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand3_4 +SOURCE CELL NAME: sky130_fd_sc_ms__nand3_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 12 12 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 19 18 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 3 3 MP (4 pins) + 1 1 SMN3 (5 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 18 layout mos transistors were reduced to 6. + 12 mos transistors were deleted by parallel reduction. + 18 source mos transistors were reduced to 6. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B C VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand3/sky130_fd_sc_ms__nand3_4.pex.spice b/cells/nand3/sky130_fd_sc_ms__nand3_4.pex.spice index 1bfdfd1..8ecc0ca 100644 --- a/cells/nand3/sky130_fd_sc_ms__nand3_4.pex.spice +++ b/cells/nand3/sky130_fd_sc_ms__nand3_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3_4.pex.spice -* Created: Fri Aug 28 17:43:21 2020 +* Created: Wed Sep 2 12:13:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand3/sky130_fd_sc_ms__nand3_4.pxi.spice b/cells/nand3/sky130_fd_sc_ms__nand3_4.pxi.spice index e3b18d3..e012eb3 100644 --- a/cells/nand3/sky130_fd_sc_ms__nand3_4.pxi.spice +++ b/cells/nand3/sky130_fd_sc_ms__nand3_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3_4.pxi.spice -* Created: Fri Aug 28 17:43:21 2020 +* Created: Wed Sep 2 12:13:43 2020 * x_PM_SKY130_FD_SC_MS__NAND3_4%A N_A_c_87_n N_A_M1007_g N_A_M1005_g N_A_c_88_n + N_A_M1014_g N_A_c_89_n N_A_M1015_g N_A_M1006_g N_A_c_90_n N_A_M1017_g A A
diff --git a/cells/nand3/sky130_fd_sc_ms__nand3_4.spice b/cells/nand3/sky130_fd_sc_ms__nand3_4.spice index aaad663..12c5959 100644 --- a/cells/nand3/sky130_fd_sc_ms__nand3_4.spice +++ b/cells/nand3/sky130_fd_sc_ms__nand3_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3_4.spice -* Created: Fri Aug 28 17:43:21 2020 +* Created: Wed Sep 2 12:13:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand3b/sky130_fd_sc_ms__nand3b_1.lvs.report b/cells/nand3b/sky130_fd_sc_ms__nand3b_1.lvs.report new file mode 100644 index 0000000..aadd7ea --- /dev/null +++ b/cells/nand3b/sky130_fd_sc_ms__nand3b_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand3b_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand3b_1.sp ('sky130_fd_sc_ms__nand3b_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand3b/sky130_fd_sc_ms__nand3b_1.spice ('sky130_fd_sc_ms__nand3b_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:13:46 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand3b_1 sky130_fd_sc_ms__nand3b_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand3b_1 +SOURCE CELL NAME: sky130_fd_sc_ms__nand3b_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMN3 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N C B VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand3b/sky130_fd_sc_ms__nand3b_1.pex.spice b/cells/nand3b/sky130_fd_sc_ms__nand3b_1.pex.spice index 9d58850..03731a3 100644 --- a/cells/nand3b/sky130_fd_sc_ms__nand3b_1.pex.spice +++ b/cells/nand3b/sky130_fd_sc_ms__nand3b_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3b_1.pex.spice -* Created: Fri Aug 28 17:43:51 2020 +* Created: Wed Sep 2 12:13:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand3b/sky130_fd_sc_ms__nand3b_1.pxi.spice b/cells/nand3b/sky130_fd_sc_ms__nand3b_1.pxi.spice index abf4bc8..f6a2bc5 100644 --- a/cells/nand3b/sky130_fd_sc_ms__nand3b_1.pxi.spice +++ b/cells/nand3b/sky130_fd_sc_ms__nand3b_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3b_1.pxi.spice -* Created: Fri Aug 28 17:43:51 2020 +* Created: Wed Sep 2 12:13:50 2020 * x_PM_SKY130_FD_SC_MS__NAND3B_1%A_N N_A_N_M1004_g N_A_N_M1005_g A_N N_A_N_c_52_n + N_A_N_c_53_n PM_SKY130_FD_SC_MS__NAND3B_1%A_N
diff --git a/cells/nand3b/sky130_fd_sc_ms__nand3b_1.spice b/cells/nand3b/sky130_fd_sc_ms__nand3b_1.spice index 8288999..68d86d5 100644 --- a/cells/nand3b/sky130_fd_sc_ms__nand3b_1.spice +++ b/cells/nand3b/sky130_fd_sc_ms__nand3b_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3b_1.spice -* Created: Fri Aug 28 17:43:51 2020 +* Created: Wed Sep 2 12:13:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand3b/sky130_fd_sc_ms__nand3b_2.lvs.report b/cells/nand3b/sky130_fd_sc_ms__nand3b_2.lvs.report new file mode 100644 index 0000000..ee39975 --- /dev/null +++ b/cells/nand3b/sky130_fd_sc_ms__nand3b_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand3b_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand3b_2.sp ('sky130_fd_sc_ms__nand3b_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand3b/sky130_fd_sc_ms__nand3b_2.spice ('sky130_fd_sc_ms__nand3b_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:13:53 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand3b_2 sky130_fd_sc_ms__nand3b_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand3b_2 +SOURCE CELL NAME: sky130_fd_sc_ms__nand3b_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMN3 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N C B VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand3b/sky130_fd_sc_ms__nand3b_2.pex.spice b/cells/nand3b/sky130_fd_sc_ms__nand3b_2.pex.spice index 5e194ae..16d3d67 100644 --- a/cells/nand3b/sky130_fd_sc_ms__nand3b_2.pex.spice +++ b/cells/nand3b/sky130_fd_sc_ms__nand3b_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3b_2.pex.spice -* Created: Fri Aug 28 17:44:01 2020 +* Created: Wed Sep 2 12:13:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand3b/sky130_fd_sc_ms__nand3b_2.pxi.spice b/cells/nand3b/sky130_fd_sc_ms__nand3b_2.pxi.spice index b893e5b..e54bb72 100644 --- a/cells/nand3b/sky130_fd_sc_ms__nand3b_2.pxi.spice +++ b/cells/nand3b/sky130_fd_sc_ms__nand3b_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3b_2.pxi.spice -* Created: Fri Aug 28 17:44:01 2020 +* Created: Wed Sep 2 12:13:56 2020 * x_PM_SKY130_FD_SC_MS__NAND3B_2%A_N N_A_N_M1002_g N_A_N_M1000_g A_N N_A_N_c_72_n + N_A_N_c_73_n PM_SKY130_FD_SC_MS__NAND3B_2%A_N
diff --git a/cells/nand3b/sky130_fd_sc_ms__nand3b_2.spice b/cells/nand3b/sky130_fd_sc_ms__nand3b_2.spice index 1aa0b07..4c60031 100644 --- a/cells/nand3b/sky130_fd_sc_ms__nand3b_2.spice +++ b/cells/nand3b/sky130_fd_sc_ms__nand3b_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3b_2.spice -* Created: Fri Aug 28 17:44:01 2020 +* Created: Wed Sep 2 12:13:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand3b/sky130_fd_sc_ms__nand3b_4.lvs.report b/cells/nand3b/sky130_fd_sc_ms__nand3b_4.lvs.report new file mode 100644 index 0000000..a995f6e --- /dev/null +++ b/cells/nand3b/sky130_fd_sc_ms__nand3b_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand3b_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand3b_4.sp ('sky130_fd_sc_ms__nand3b_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand3b/sky130_fd_sc_ms__nand3b_4.spice ('sky130_fd_sc_ms__nand3b_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:14:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand3b_4 sky130_fd_sc_ms__nand3b_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand3b_4 +SOURCE CELL NAME: sky130_fd_sc_ms__nand3b_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 13 13 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 22 21 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMN3 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN3 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 7. + 13 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 7. + 13 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N C B VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand3b/sky130_fd_sc_ms__nand3b_4.pex.spice b/cells/nand3b/sky130_fd_sc_ms__nand3b_4.pex.spice index 2130b24..4d7c5d7 100644 --- a/cells/nand3b/sky130_fd_sc_ms__nand3b_4.pex.spice +++ b/cells/nand3b/sky130_fd_sc_ms__nand3b_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3b_4.pex.spice -* Created: Fri Aug 28 17:44:10 2020 +* Created: Wed Sep 2 12:14:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand3b/sky130_fd_sc_ms__nand3b_4.pxi.spice b/cells/nand3b/sky130_fd_sc_ms__nand3b_4.pxi.spice index 84cc7e0..f53dff5 100644 --- a/cells/nand3b/sky130_fd_sc_ms__nand3b_4.pxi.spice +++ b/cells/nand3b/sky130_fd_sc_ms__nand3b_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3b_4.pxi.spice -* Created: Fri Aug 28 17:44:10 2020 +* Created: Wed Sep 2 12:14:03 2020 * x_PM_SKY130_FD_SC_MS__NAND3B_4%A_N N_A_N_M1000_g N_A_N_c_104_n N_A_N_M1017_g + N_A_N_c_101_n N_A_N_c_106_n N_A_N_M1020_g A_N N_A_N_c_102_n N_A_N_c_103_n
diff --git a/cells/nand3b/sky130_fd_sc_ms__nand3b_4.spice b/cells/nand3b/sky130_fd_sc_ms__nand3b_4.spice index 5e2459d..8bf4e28 100644 --- a/cells/nand3b/sky130_fd_sc_ms__nand3b_4.spice +++ b/cells/nand3b/sky130_fd_sc_ms__nand3b_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand3b_4.spice -* Created: Fri Aug 28 17:44:10 2020 +* Created: Wed Sep 2 12:14:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand4/sky130_fd_sc_ms__nand4_1.lvs.report b/cells/nand4/sky130_fd_sc_ms__nand4_1.lvs.report new file mode 100644 index 0000000..1f19c99 --- /dev/null +++ b/cells/nand4/sky130_fd_sc_ms__nand4_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand4_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand4_1.sp ('sky130_fd_sc_ms__nand4_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand4/sky130_fd_sc_ms__nand4_1.spice ('sky130_fd_sc_ms__nand4_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:14:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand4_1 sky130_fd_sc_ms__nand4_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand4_1 +SOURCE CELL NAME: sky130_fd_sc_ms__nand4_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 4 4 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D C B A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand4/sky130_fd_sc_ms__nand4_1.pex.spice b/cells/nand4/sky130_fd_sc_ms__nand4_1.pex.spice index c95426b..4158aef 100644 --- a/cells/nand4/sky130_fd_sc_ms__nand4_1.pex.spice +++ b/cells/nand4/sky130_fd_sc_ms__nand4_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4_1.pex.spice -* Created: Fri Aug 28 17:44:19 2020 +* Created: Wed Sep 2 12:14:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand4/sky130_fd_sc_ms__nand4_1.pxi.spice b/cells/nand4/sky130_fd_sc_ms__nand4_1.pxi.spice index 6cda5ce..a2b9514 100644 --- a/cells/nand4/sky130_fd_sc_ms__nand4_1.pxi.spice +++ b/cells/nand4/sky130_fd_sc_ms__nand4_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4_1.pxi.spice -* Created: Fri Aug 28 17:44:19 2020 +* Created: Wed Sep 2 12:14:10 2020 * x_PM_SKY130_FD_SC_MS__NAND4_1%D N_D_M1001_g N_D_M1000_g D N_D_c_49_n N_D_c_50_n + PM_SKY130_FD_SC_MS__NAND4_1%D
diff --git a/cells/nand4/sky130_fd_sc_ms__nand4_1.spice b/cells/nand4/sky130_fd_sc_ms__nand4_1.spice index 65e06c4..f54f336 100644 --- a/cells/nand4/sky130_fd_sc_ms__nand4_1.spice +++ b/cells/nand4/sky130_fd_sc_ms__nand4_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4_1.spice -* Created: Fri Aug 28 17:44:19 2020 +* Created: Wed Sep 2 12:14:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand4/sky130_fd_sc_ms__nand4_2.lvs.report b/cells/nand4/sky130_fd_sc_ms__nand4_2.lvs.report new file mode 100644 index 0000000..9fd863d --- /dev/null +++ b/cells/nand4/sky130_fd_sc_ms__nand4_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand4_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand4_2.sp ('sky130_fd_sc_ms__nand4_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand4/sky130_fd_sc_ms__nand4_2.spice ('sky130_fd_sc_ms__nand4_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:14:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand4_2 sky130_fd_sc_ms__nand4_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand4_2 +SOURCE CELL NAME: sky130_fd_sc_ms__nand4_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 4 4 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D C B A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand4/sky130_fd_sc_ms__nand4_2.pex.spice b/cells/nand4/sky130_fd_sc_ms__nand4_2.pex.spice index a231328..c37f329 100644 --- a/cells/nand4/sky130_fd_sc_ms__nand4_2.pex.spice +++ b/cells/nand4/sky130_fd_sc_ms__nand4_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4_2.pex.spice -* Created: Fri Aug 28 17:44:27 2020 +* Created: Wed Sep 2 12:14:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand4/sky130_fd_sc_ms__nand4_2.pxi.spice b/cells/nand4/sky130_fd_sc_ms__nand4_2.pxi.spice index 63272e7..36eaaaf 100644 --- a/cells/nand4/sky130_fd_sc_ms__nand4_2.pxi.spice +++ b/cells/nand4/sky130_fd_sc_ms__nand4_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4_2.pxi.spice -* Created: Fri Aug 28 17:44:27 2020 +* Created: Wed Sep 2 12:14:17 2020 * x_PM_SKY130_FD_SC_MS__NAND4_2%D N_D_M1003_g N_D_M1002_g N_D_M1006_g N_D_M1011_g + D D N_D_c_82_n N_D_c_83_n PM_SKY130_FD_SC_MS__NAND4_2%D
diff --git a/cells/nand4/sky130_fd_sc_ms__nand4_2.spice b/cells/nand4/sky130_fd_sc_ms__nand4_2.spice index 37458c4..90d21c9 100644 --- a/cells/nand4/sky130_fd_sc_ms__nand4_2.spice +++ b/cells/nand4/sky130_fd_sc_ms__nand4_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4_2.spice -* Created: Fri Aug 28 17:44:27 2020 +* Created: Wed Sep 2 12:14:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand4/sky130_fd_sc_ms__nand4_4.lvs.report b/cells/nand4/sky130_fd_sc_ms__nand4_4.lvs.report new file mode 100644 index 0000000..fc1d2ca --- /dev/null +++ b/cells/nand4/sky130_fd_sc_ms__nand4_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand4_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand4_4.sp ('sky130_fd_sc_ms__nand4_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand4/sky130_fd_sc_ms__nand4_4.spice ('sky130_fd_sc_ms__nand4_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:14:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand4_4 sky130_fd_sc_ms__nand4_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand4_4 +SOURCE CELL NAME: sky130_fd_sc_ms__nand4_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 16 16 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 4 4 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 8. + 16 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 8. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D C B A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand4/sky130_fd_sc_ms__nand4_4.pex.spice b/cells/nand4/sky130_fd_sc_ms__nand4_4.pex.spice index 4e269a1..810d3ec 100644 --- a/cells/nand4/sky130_fd_sc_ms__nand4_4.pex.spice +++ b/cells/nand4/sky130_fd_sc_ms__nand4_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4_4.pex.spice -* Created: Fri Aug 28 17:44:57 2020 +* Created: Wed Sep 2 12:14:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand4/sky130_fd_sc_ms__nand4_4.pxi.spice b/cells/nand4/sky130_fd_sc_ms__nand4_4.pxi.spice index 66291e4..bf4a8f4 100644 --- a/cells/nand4/sky130_fd_sc_ms__nand4_4.pxi.spice +++ b/cells/nand4/sky130_fd_sc_ms__nand4_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4_4.pxi.spice -* Created: Fri Aug 28 17:44:57 2020 +* Created: Wed Sep 2 12:14:24 2020 * x_PM_SKY130_FD_SC_MS__NAND4_4%D N_D_M1006_g N_D_M1008_g N_D_c_109_n N_D_M1014_g + N_D_M1005_g N_D_M1019_g N_D_M1007_g N_D_c_112_n N_D_c_113_n N_D_c_114_n D D D
diff --git a/cells/nand4/sky130_fd_sc_ms__nand4_4.spice b/cells/nand4/sky130_fd_sc_ms__nand4_4.spice index 071759b..66b7e31 100644 --- a/cells/nand4/sky130_fd_sc_ms__nand4_4.spice +++ b/cells/nand4/sky130_fd_sc_ms__nand4_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4_4.spice -* Created: Fri Aug 28 17:44:57 2020 +* Created: Wed Sep 2 12:14:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand4b/sky130_fd_sc_ms__nand4b_1.lvs.report b/cells/nand4b/sky130_fd_sc_ms__nand4b_1.lvs.report new file mode 100644 index 0000000..0b63687 --- /dev/null +++ b/cells/nand4b/sky130_fd_sc_ms__nand4b_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand4b_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand4b_1.sp ('sky130_fd_sc_ms__nand4b_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand4b/sky130_fd_sc_ms__nand4b_1.spice ('sky130_fd_sc_ms__nand4b_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:14:27 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand4b_1 sky130_fd_sc_ms__nand4b_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand4b_1 +SOURCE CELL NAME: sky130_fd_sc_ms__nand4b_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 5 5 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N D C B VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand4b/sky130_fd_sc_ms__nand4b_1.pex.spice b/cells/nand4b/sky130_fd_sc_ms__nand4b_1.pex.spice index 25f6cee..3b94eac 100644 --- a/cells/nand4b/sky130_fd_sc_ms__nand4b_1.pex.spice +++ b/cells/nand4b/sky130_fd_sc_ms__nand4b_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4b_1.pex.spice -* Created: Fri Aug 28 17:45:07 2020 +* Created: Wed Sep 2 12:14:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand4b/sky130_fd_sc_ms__nand4b_1.pxi.spice b/cells/nand4b/sky130_fd_sc_ms__nand4b_1.pxi.spice index ee8c6f5..e23ce79 100644 --- a/cells/nand4b/sky130_fd_sc_ms__nand4b_1.pxi.spice +++ b/cells/nand4b/sky130_fd_sc_ms__nand4b_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4b_1.pxi.spice -* Created: Fri Aug 28 17:45:07 2020 +* Created: Wed Sep 2 12:14:31 2020 * x_PM_SKY130_FD_SC_MS__NAND4B_1%A_N N_A_N_M1004_g N_A_N_M1006_g A_N N_A_N_c_59_n + N_A_N_c_60_n PM_SKY130_FD_SC_MS__NAND4B_1%A_N
diff --git a/cells/nand4b/sky130_fd_sc_ms__nand4b_1.spice b/cells/nand4b/sky130_fd_sc_ms__nand4b_1.spice index 0e36925..5e10dc1 100644 --- a/cells/nand4b/sky130_fd_sc_ms__nand4b_1.spice +++ b/cells/nand4b/sky130_fd_sc_ms__nand4b_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4b_1.spice -* Created: Fri Aug 28 17:45:07 2020 +* Created: Wed Sep 2 12:14:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand4b/sky130_fd_sc_ms__nand4b_2.lvs.report b/cells/nand4b/sky130_fd_sc_ms__nand4b_2.lvs.report new file mode 100644 index 0000000..00c3db9 --- /dev/null +++ b/cells/nand4b/sky130_fd_sc_ms__nand4b_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand4b_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand4b_2.sp ('sky130_fd_sc_ms__nand4b_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand4b/sky130_fd_sc_ms__nand4b_2.spice ('sky130_fd_sc_ms__nand4b_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:14:34 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand4b_2 sky130_fd_sc_ms__nand4b_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand4b_2 +SOURCE CELL NAME: sky130_fd_sc_ms__nand4b_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 9 9 MN (4 pins) + 9 9 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 19 18 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 5 5 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B C D VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand4b/sky130_fd_sc_ms__nand4b_2.pex.spice b/cells/nand4b/sky130_fd_sc_ms__nand4b_2.pex.spice index c3de85c..09629a3 100644 --- a/cells/nand4b/sky130_fd_sc_ms__nand4b_2.pex.spice +++ b/cells/nand4b/sky130_fd_sc_ms__nand4b_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4b_2.pex.spice -* Created: Fri Aug 28 17:45:16 2020 +* Created: Wed Sep 2 12:14:38 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand4b/sky130_fd_sc_ms__nand4b_2.pxi.spice b/cells/nand4b/sky130_fd_sc_ms__nand4b_2.pxi.spice index 7435f4a..7d83c92 100644 --- a/cells/nand4b/sky130_fd_sc_ms__nand4b_2.pxi.spice +++ b/cells/nand4b/sky130_fd_sc_ms__nand4b_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4b_2.pxi.spice -* Created: Fri Aug 28 17:45:16 2020 +* Created: Wed Sep 2 12:14:38 2020 * x_PM_SKY130_FD_SC_MS__NAND4B_2%A_N N_A_N_M1010_g N_A_N_M1008_g A_N A_N + N_A_N_c_94_n N_A_N_c_95_n PM_SKY130_FD_SC_MS__NAND4B_2%A_N
diff --git a/cells/nand4b/sky130_fd_sc_ms__nand4b_2.spice b/cells/nand4b/sky130_fd_sc_ms__nand4b_2.spice index 2b81f95..67d1732 100644 --- a/cells/nand4b/sky130_fd_sc_ms__nand4b_2.spice +++ b/cells/nand4b/sky130_fd_sc_ms__nand4b_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4b_2.spice -* Created: Fri Aug 28 17:45:16 2020 +* Created: Wed Sep 2 12:14:38 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand4b/sky130_fd_sc_ms__nand4b_4.lvs.report b/cells/nand4b/sky130_fd_sc_ms__nand4b_4.lvs.report new file mode 100644 index 0000000..9887063 --- /dev/null +++ b/cells/nand4b/sky130_fd_sc_ms__nand4b_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand4b_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand4b_4.sp ('sky130_fd_sc_ms__nand4b_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand4b/sky130_fd_sc_ms__nand4b_4.spice ('sky130_fd_sc_ms__nand4b_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:14:41 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand4b_4 sky130_fd_sc_ms__nand4b_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand4b_4 +SOURCE CELL NAME: sky130_fd_sc_ms__nand4b_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 17 17 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 28 27 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 5 5 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 5 5 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 26 layout mos transistors were reduced to 9. + 17 mos transistors were deleted by parallel reduction. + 26 source mos transistors were reduced to 9. + 17 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B C D VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand4b/sky130_fd_sc_ms__nand4b_4.pex.spice b/cells/nand4b/sky130_fd_sc_ms__nand4b_4.pex.spice index 9350f4c..6ed364d 100644 --- a/cells/nand4b/sky130_fd_sc_ms__nand4b_4.pex.spice +++ b/cells/nand4b/sky130_fd_sc_ms__nand4b_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4b_4.pex.spice -* Created: Fri Aug 28 17:45:25 2020 +* Created: Wed Sep 2 12:14:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand4b/sky130_fd_sc_ms__nand4b_4.pxi.spice b/cells/nand4b/sky130_fd_sc_ms__nand4b_4.pxi.spice index 78b4b44..bce3be3 100644 --- a/cells/nand4b/sky130_fd_sc_ms__nand4b_4.pxi.spice +++ b/cells/nand4b/sky130_fd_sc_ms__nand4b_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4b_4.pxi.spice -* Created: Fri Aug 28 17:45:25 2020 +* Created: Wed Sep 2 12:14:44 2020 * x_PM_SKY130_FD_SC_MS__NAND4B_4%A_N N_A_N_M1023_g N_A_N_c_123_n N_A_N_M1018_g + N_A_N_c_120_n N_A_N_c_125_n N_A_N_M1022_g A_N A_N N_A_N_c_122_n
diff --git a/cells/nand4b/sky130_fd_sc_ms__nand4b_4.spice b/cells/nand4b/sky130_fd_sc_ms__nand4b_4.spice index c35b84f..6ad9f31 100644 --- a/cells/nand4b/sky130_fd_sc_ms__nand4b_4.spice +++ b/cells/nand4b/sky130_fd_sc_ms__nand4b_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4b_4.spice -* Created: Fri Aug 28 17:45:25 2020 +* Created: Wed Sep 2 12:14:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.lvs.report b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.lvs.report new file mode 100644 index 0000000..011b298 --- /dev/null +++ b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand4bb_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand4bb_1.sp ('sky130_fd_sc_ms__nand4bb_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.spice ('sky130_fd_sc_ms__nand4bb_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:14:48 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand4bb_1 sky130_fd_sc_ms__nand4bb_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand4bb_1 +SOURCE CELL NAME: sky130_fd_sc_ms__nand4bb_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 6 6 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 9 9 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 9 9 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B_N C D VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.pex.spice b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.pex.spice index 16766d6..5504c79 100644 --- a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.pex.spice +++ b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4bb_1.pex.spice -* Created: Fri Aug 28 17:45:34 2020 +* Created: Wed Sep 2 12:14:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.pxi.spice b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.pxi.spice index fa41da7..316d184 100644 --- a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.pxi.spice +++ b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4bb_1.pxi.spice -* Created: Fri Aug 28 17:45:34 2020 +* Created: Wed Sep 2 12:14:51 2020 * x_PM_SKY130_FD_SC_MS__NAND4BB_1%A_N N_A_N_c_74_n N_A_N_M1010_g N_A_N_M1002_g A_N + N_A_N_c_77_n N_A_N_c_78_n PM_SKY130_FD_SC_MS__NAND4BB_1%A_N
diff --git a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.spice b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.spice index 1447e33..fc9256c 100644 --- a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.spice +++ b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4bb_1.spice -* Created: Fri Aug 28 17:45:34 2020 +* Created: Wed Sep 2 12:14:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.lvs.report b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.lvs.report new file mode 100644 index 0000000..f664999 --- /dev/null +++ b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand4bb_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand4bb_2.sp ('sky130_fd_sc_ms__nand4bb_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.spice ('sky130_fd_sc_ms__nand4bb_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:14:55 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand4bb_2 sky130_fd_sc_ms__nand4bb_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand4bb_2 +SOURCE CELL NAME: sky130_fd_sc_ms__nand4bb_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 6 6 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 9 9 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 9 9 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B_N C D VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.pex.spice b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.pex.spice index efa513f..c520824 100644 --- a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.pex.spice +++ b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4bb_2.pex.spice -* Created: Fri Aug 28 17:46:04 2020 +* Created: Wed Sep 2 12:14:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.pxi.spice b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.pxi.spice index 834420d..7f12a5f 100644 --- a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.pxi.spice +++ b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4bb_2.pxi.spice -* Created: Fri Aug 28 17:46:04 2020 +* Created: Wed Sep 2 12:14:58 2020 * x_PM_SKY130_FD_SC_MS__NAND4BB_2%A_N N_A_N_M1010_g N_A_N_M1018_g A_N + N_A_N_c_114_n N_A_N_c_115_n PM_SKY130_FD_SC_MS__NAND4BB_2%A_N
diff --git a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.spice b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.spice index a172424..5d92f00 100644 --- a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.spice +++ b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4bb_2.spice -* Created: Fri Aug 28 17:46:04 2020 +* Created: Wed Sep 2 12:14:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.lvs.report b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.lvs.report new file mode 100644 index 0000000..1d451e9 --- /dev/null +++ b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nand4bb_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nand4bb_4.sp ('sky130_fd_sc_ms__nand4bb_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.spice ('sky130_fd_sc_ms__nand4bb_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:15:01 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nand4bb_4 sky130_fd_sc_ms__nand4bb_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nand4bb_4 +SOURCE CELL NAME: sky130_fd_sc_ms__nand4bb_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 18 18 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 39 38 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 2 2 MN (4 pins) + 6 6 MP (4 pins) + 1 1 SMN4 (6 pins) + ------ ------ + Total Inst: 9 9 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 6 6 0 0 MP(PSHORT) + 1 1 0 0 SMN4 + ------- ------- --------- --------- + Total Inst: 9 9 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 36 layout mos transistors were reduced to 10. + 26 mos transistors were deleted by parallel reduction. + 36 source mos transistors were reduced to 10. + 26 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A_N B_N C D VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.pex.spice b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.pex.spice index 932e054..1567dbc 100644 --- a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.pex.spice +++ b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4bb_4.pex.spice -* Created: Fri Aug 28 17:46:14 2020 +* Created: Wed Sep 2 12:15:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.pxi.spice b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.pxi.spice index ba63d2e..56171db 100644 --- a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.pxi.spice +++ b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4bb_4.pxi.spice -* Created: Fri Aug 28 17:46:14 2020 +* Created: Wed Sep 2 12:15:04 2020 * x_PM_SKY130_FD_SC_MS__NAND4BB_4%A_N N_A_N_c_186_n N_A_N_M1015_g N_A_N_M1018_g + N_A_N_c_183_n N_A_N_c_188_n N_A_N_M1016_g A_N N_A_N_c_185_n
diff --git a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.spice b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.spice index d94f8d9..1d9f1b9 100644 --- a/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.spice +++ b/cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nand4bb_4.spice -* Created: Fri Aug 28 17:46:14 2020 +* Created: Wed Sep 2 12:15:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_1.lvs.report b/cells/nor2/sky130_fd_sc_ms__nor2_1.lvs.report new file mode 100644 index 0000000..364ea18 --- /dev/null +++ b/cells/nor2/sky130_fd_sc_ms__nor2_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor2_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor2_1.sp ('sky130_fd_sc_ms__nor2_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor2/sky130_fd_sc_ms__nor2_1.spice ('sky130_fd_sc_ms__nor2_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:15:08 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor2_1 sky130_fd_sc_ms__nor2_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor2_1 +SOURCE CELL NAME: sky130_fd_sc_ms__nor2_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 2 2 MN (4 pins) + 2 2 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 5 4 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_1.pex.spice b/cells/nor2/sky130_fd_sc_ms__nor2_1.pex.spice index dd9bb13..bb6a989 100644 --- a/cells/nor2/sky130_fd_sc_ms__nor2_1.pex.spice +++ b/cells/nor2/sky130_fd_sc_ms__nor2_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2_1.pex.spice -* Created: Fri Aug 28 17:46:23 2020 +* Created: Wed Sep 2 12:15:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_1.pxi.spice b/cells/nor2/sky130_fd_sc_ms__nor2_1.pxi.spice index 718cd59..c02df9b 100644 --- a/cells/nor2/sky130_fd_sc_ms__nor2_1.pxi.spice +++ b/cells/nor2/sky130_fd_sc_ms__nor2_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2_1.pxi.spice -* Created: Fri Aug 28 17:46:23 2020 +* Created: Wed Sep 2 12:15:11 2020 * x_PM_SKY130_FD_SC_MS__NOR2_1%A N_A_M1000_g N_A_M1003_g A N_A_c_31_n N_A_c_32_n + PM_SKY130_FD_SC_MS__NOR2_1%A
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_1.spice b/cells/nor2/sky130_fd_sc_ms__nor2_1.spice index 364fe41..c184586 100644 --- a/cells/nor2/sky130_fd_sc_ms__nor2_1.spice +++ b/cells/nor2/sky130_fd_sc_ms__nor2_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2_1.spice -* Created: Fri Aug 28 17:46:23 2020 +* Created: Wed Sep 2 12:15:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_2.lvs.report b/cells/nor2/sky130_fd_sc_ms__nor2_2.lvs.report new file mode 100644 index 0000000..6c069cd --- /dev/null +++ b/cells/nor2/sky130_fd_sc_ms__nor2_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor2_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor2_2.sp ('sky130_fd_sc_ms__nor2_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor2/sky130_fd_sc_ms__nor2_2.spice ('sky130_fd_sc_ms__nor2_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:15:15 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor2_2 sky130_fd_sc_ms__nor2_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor2_2 +SOURCE CELL NAME: sky130_fd_sc_ms__nor2_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 2 2 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_2.pex.spice b/cells/nor2/sky130_fd_sc_ms__nor2_2.pex.spice index 8ca1058..5e4c430 100644 --- a/cells/nor2/sky130_fd_sc_ms__nor2_2.pex.spice +++ b/cells/nor2/sky130_fd_sc_ms__nor2_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2_2.pex.spice -* Created: Fri Aug 28 17:46:31 2020 +* Created: Wed Sep 2 12:15:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_2.pxi.spice b/cells/nor2/sky130_fd_sc_ms__nor2_2.pxi.spice index ebea37b..fded464 100644 --- a/cells/nor2/sky130_fd_sc_ms__nor2_2.pxi.spice +++ b/cells/nor2/sky130_fd_sc_ms__nor2_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2_2.pxi.spice -* Created: Fri Aug 28 17:46:31 2020 +* Created: Wed Sep 2 12:15:18 2020 * x_PM_SKY130_FD_SC_MS__NOR2_2%B N_B_M1002_g N_B_M1001_g N_B_c_41_n N_B_c_46_n + N_B_M1003_g N_B_c_42_n N_B_c_43_n N_B_c_48_n B PM_SKY130_FD_SC_MS__NOR2_2%B
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_2.spice b/cells/nor2/sky130_fd_sc_ms__nor2_2.spice index 79cf075..27c0deb 100644 --- a/cells/nor2/sky130_fd_sc_ms__nor2_2.spice +++ b/cells/nor2/sky130_fd_sc_ms__nor2_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2_2.spice -* Created: Fri Aug 28 17:46:31 2020 +* Created: Wed Sep 2 12:15:18 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_4.lvs.report b/cells/nor2/sky130_fd_sc_ms__nor2_4.lvs.report new file mode 100644 index 0000000..694dd80 --- /dev/null +++ b/cells/nor2/sky130_fd_sc_ms__nor2_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor2_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor2_4.sp ('sky130_fd_sc_ms__nor2_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor2/sky130_fd_sc_ms__nor2_4.spice ('sky130_fd_sc_ms__nor2_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:15:21 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor2_4 sky130_fd_sc_ms__nor2_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor2_4 +SOURCE CELL NAME: sky130_fd_sc_ms__nor2_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 4 4 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 4. + 8 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 4. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_4.pex.spice b/cells/nor2/sky130_fd_sc_ms__nor2_4.pex.spice index 9868690..6049df7 100644 --- a/cells/nor2/sky130_fd_sc_ms__nor2_4.pex.spice +++ b/cells/nor2/sky130_fd_sc_ms__nor2_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2_4.pex.spice -* Created: Fri Aug 28 17:46:40 2020 +* Created: Wed Sep 2 12:15:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_4.pxi.spice b/cells/nor2/sky130_fd_sc_ms__nor2_4.pxi.spice index 8e3d759..9535f51 100644 --- a/cells/nor2/sky130_fd_sc_ms__nor2_4.pxi.spice +++ b/cells/nor2/sky130_fd_sc_ms__nor2_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2_4.pxi.spice -* Created: Fri Aug 28 17:46:40 2020 +* Created: Wed Sep 2 12:15:24 2020 * x_PM_SKY130_FD_SC_MS__NOR2_4%A N_A_M1000_g N_A_c_57_n N_A_M1002_g N_A_M1001_g + N_A_M1003_g N_A_c_60_n N_A_M1004_g N_A_M1006_g A A A A N_A_c_63_n
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_4.spice b/cells/nor2/sky130_fd_sc_ms__nor2_4.spice index 6df0ac6..0ac0641 100644 --- a/cells/nor2/sky130_fd_sc_ms__nor2_4.spice +++ b/cells/nor2/sky130_fd_sc_ms__nor2_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2_4.spice -* Created: Fri Aug 28 17:46:40 2020 +* Created: Wed Sep 2 12:15:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_8.lvs.report b/cells/nor2/sky130_fd_sc_ms__nor2_8.lvs.report new file mode 100644 index 0000000..dbb5120 --- /dev/null +++ b/cells/nor2/sky130_fd_sc_ms__nor2_8.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor2_8.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor2_8.sp ('sky130_fd_sc_ms__nor2_8') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor2/sky130_fd_sc_ms__nor2_8.spice ('sky130_fd_sc_ms__nor2_8') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:15:28 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor2_8 sky130_fd_sc_ms__nor2_8 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor2_8 +SOURCE CELL NAME: sky130_fd_sc_ms__nor2_8 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 8 8 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 7 7 + + Instances: 2 2 MN (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 7 7 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 4. + 20 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 4. + 20 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_8.pex.spice b/cells/nor2/sky130_fd_sc_ms__nor2_8.pex.spice index b023d7f..a42f5ee 100644 --- a/cells/nor2/sky130_fd_sc_ms__nor2_8.pex.spice +++ b/cells/nor2/sky130_fd_sc_ms__nor2_8.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2_8.pex.spice -* Created: Fri Aug 28 17:47:10 2020 +* Created: Wed Sep 2 12:15:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_8.pxi.spice b/cells/nor2/sky130_fd_sc_ms__nor2_8.pxi.spice index caddc18..bae662e 100644 --- a/cells/nor2/sky130_fd_sc_ms__nor2_8.pxi.spice +++ b/cells/nor2/sky130_fd_sc_ms__nor2_8.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2_8.pxi.spice -* Created: Fri Aug 28 17:47:10 2020 +* Created: Wed Sep 2 12:15:31 2020 * x_PM_SKY130_FD_SC_MS__NOR2_8%A N_A_c_134_n N_A_M1001_g N_A_c_122_n N_A_c_123_n + N_A_c_137_n N_A_M1003_g N_A_c_124_n N_A_c_139_n N_A_M1004_g N_A_c_125_n
diff --git a/cells/nor2/sky130_fd_sc_ms__nor2_8.spice b/cells/nor2/sky130_fd_sc_ms__nor2_8.spice index ed6143c..6090ec4 100644 --- a/cells/nor2/sky130_fd_sc_ms__nor2_8.spice +++ b/cells/nor2/sky130_fd_sc_ms__nor2_8.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2_8.spice -* Created: Fri Aug 28 17:47:10 2020 +* Created: Wed Sep 2 12:15:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor2b/sky130_fd_sc_ms__nor2b_1.lvs.report b/cells/nor2b/sky130_fd_sc_ms__nor2b_1.lvs.report new file mode 100644 index 0000000..86118e8 --- /dev/null +++ b/cells/nor2b/sky130_fd_sc_ms__nor2b_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor2b_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor2b_1.sp ('sky130_fd_sc_ms__nor2b_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor2b/sky130_fd_sc_ms__nor2b_1.spice ('sky130_fd_sc_ms__nor2b_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:15:35 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor2b_1 sky130_fd_sc_ms__nor2b_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor2b_1 +SOURCE CELL NAME: sky130_fd_sc_ms__nor2b_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B_N A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor2b/sky130_fd_sc_ms__nor2b_1.pex.spice b/cells/nor2b/sky130_fd_sc_ms__nor2b_1.pex.spice index eebc73a..97d2f95 100644 --- a/cells/nor2b/sky130_fd_sc_ms__nor2b_1.pex.spice +++ b/cells/nor2b/sky130_fd_sc_ms__nor2b_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2b_1.pex.spice -* Created: Fri Aug 28 17:47:21 2020 +* Created: Wed Sep 2 12:15:38 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor2b/sky130_fd_sc_ms__nor2b_1.pxi.spice b/cells/nor2b/sky130_fd_sc_ms__nor2b_1.pxi.spice index 5b2b129..16b4bcf 100644 --- a/cells/nor2b/sky130_fd_sc_ms__nor2b_1.pxi.spice +++ b/cells/nor2b/sky130_fd_sc_ms__nor2b_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2b_1.pxi.spice -* Created: Fri Aug 28 17:47:21 2020 +* Created: Wed Sep 2 12:15:38 2020 * x_PM_SKY130_FD_SC_MS__NOR2B_1%B_N N_B_N_M1003_g N_B_N_c_43_n N_B_N_M1004_g + N_B_N_c_44_n N_B_N_c_45_n B_N PM_SKY130_FD_SC_MS__NOR2B_1%B_N
diff --git a/cells/nor2b/sky130_fd_sc_ms__nor2b_1.spice b/cells/nor2b/sky130_fd_sc_ms__nor2b_1.spice index ed46ada..5ff897b 100644 --- a/cells/nor2b/sky130_fd_sc_ms__nor2b_1.spice +++ b/cells/nor2b/sky130_fd_sc_ms__nor2b_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2b_1.spice -* Created: Fri Aug 28 17:47:21 2020 +* Created: Wed Sep 2 12:15:38 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor2b/sky130_fd_sc_ms__nor2b_2.lvs.report b/cells/nor2b/sky130_fd_sc_ms__nor2b_2.lvs.report new file mode 100644 index 0000000..deb184d --- /dev/null +++ b/cells/nor2b/sky130_fd_sc_ms__nor2b_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor2b_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor2b_2.sp ('sky130_fd_sc_ms__nor2b_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor2b/sky130_fd_sc_ms__nor2b_2.spice ('sky130_fd_sc_ms__nor2b_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:15:42 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor2b_2 sky130_fd_sc_ms__nor2b_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor2b_2 +SOURCE CELL NAME: sky130_fd_sc_ms__nor2b_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B_N A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor2b/sky130_fd_sc_ms__nor2b_2.pex.spice b/cells/nor2b/sky130_fd_sc_ms__nor2b_2.pex.spice index 6a99f9e..847ed24 100644 --- a/cells/nor2b/sky130_fd_sc_ms__nor2b_2.pex.spice +++ b/cells/nor2b/sky130_fd_sc_ms__nor2b_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2b_2.pex.spice -* Created: Fri Aug 28 17:47:30 2020 +* Created: Wed Sep 2 12:15:45 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor2b/sky130_fd_sc_ms__nor2b_2.pxi.spice b/cells/nor2b/sky130_fd_sc_ms__nor2b_2.pxi.spice index d6c8627..cd383c6 100644 --- a/cells/nor2b/sky130_fd_sc_ms__nor2b_2.pxi.spice +++ b/cells/nor2b/sky130_fd_sc_ms__nor2b_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2b_2.pxi.spice -* Created: Fri Aug 28 17:47:30 2020 +* Created: Wed Sep 2 12:15:45 2020 * x_PM_SKY130_FD_SC_MS__NOR2B_2%B_N N_B_N_M1004_g N_B_N_M1005_g B_N N_B_N_c_63_n + PM_SKY130_FD_SC_MS__NOR2B_2%B_N
diff --git a/cells/nor2b/sky130_fd_sc_ms__nor2b_2.spice b/cells/nor2b/sky130_fd_sc_ms__nor2b_2.spice index 44cc0b4..2c255f3 100644 --- a/cells/nor2b/sky130_fd_sc_ms__nor2b_2.spice +++ b/cells/nor2b/sky130_fd_sc_ms__nor2b_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2b_2.spice -* Created: Fri Aug 28 17:47:30 2020 +* Created: Wed Sep 2 12:15:45 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor2b/sky130_fd_sc_ms__nor2b_4.lvs.report b/cells/nor2b/sky130_fd_sc_ms__nor2b_4.lvs.report new file mode 100644 index 0000000..53a53e5 --- /dev/null +++ b/cells/nor2b/sky130_fd_sc_ms__nor2b_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor2b_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor2b_4.sp ('sky130_fd_sc_ms__nor2b_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor2b/sky130_fd_sc_ms__nor2b_4.spice ('sky130_fd_sc_ms__nor2b_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:15:48 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor2b_4 sky130_fd_sc_ms__nor2b_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor2b_4 +SOURCE CELL NAME: sky130_fd_sc_ms__nor2b_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 5 5 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 16 15 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 14 layout mos transistors were reduced to 5. + 9 mos transistors were deleted by parallel reduction. + 14 source mos transistors were reduced to 5. + 9 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B_N VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor2b/sky130_fd_sc_ms__nor2b_4.pex.spice b/cells/nor2b/sky130_fd_sc_ms__nor2b_4.pex.spice index 7fe466c..2b5047e 100644 --- a/cells/nor2b/sky130_fd_sc_ms__nor2b_4.pex.spice +++ b/cells/nor2b/sky130_fd_sc_ms__nor2b_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2b_4.pex.spice -* Created: Fri Aug 28 17:47:38 2020 +* Created: Wed Sep 2 12:15:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor2b/sky130_fd_sc_ms__nor2b_4.pxi.spice b/cells/nor2b/sky130_fd_sc_ms__nor2b_4.pxi.spice index 10f44c1..21c2f0c 100644 --- a/cells/nor2b/sky130_fd_sc_ms__nor2b_4.pxi.spice +++ b/cells/nor2b/sky130_fd_sc_ms__nor2b_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2b_4.pxi.spice -* Created: Fri Aug 28 17:47:38 2020 +* Created: Wed Sep 2 12:15:51 2020 * x_PM_SKY130_FD_SC_MS__NOR2B_4%A N_A_M1004_g N_A_M1005_g N_A_M1007_g N_A_c_80_n + N_A_M1003_g N_A_M1012_g N_A_c_82_n N_A_M1008_g N_A_c_83_n N_A_c_84_n
diff --git a/cells/nor2b/sky130_fd_sc_ms__nor2b_4.spice b/cells/nor2b/sky130_fd_sc_ms__nor2b_4.spice index 27989fb..ba6057d 100644 --- a/cells/nor2b/sky130_fd_sc_ms__nor2b_4.spice +++ b/cells/nor2b/sky130_fd_sc_ms__nor2b_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor2b_4.spice -* Created: Fri Aug 28 17:47:38 2020 +* Created: Wed Sep 2 12:15:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor3/sky130_fd_sc_ms__nor3_1.lvs.report b/cells/nor3/sky130_fd_sc_ms__nor3_1.lvs.report new file mode 100644 index 0000000..da97445 --- /dev/null +++ b/cells/nor3/sky130_fd_sc_ms__nor3_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor3_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor3_1.sp ('sky130_fd_sc_ms__nor3_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor3/sky130_fd_sc_ms__nor3_1.spice ('sky130_fd_sc_ms__nor3_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:15:55 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor3_1 sky130_fd_sc_ms__nor3_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor3_1 +SOURCE CELL NAME: sky130_fd_sc_ms__nor3_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 1 1 SMP3 (5 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 SMP3 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B C VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor3/sky130_fd_sc_ms__nor3_1.pex.spice b/cells/nor3/sky130_fd_sc_ms__nor3_1.pex.spice index 098b45c..1e55f6f 100644 --- a/cells/nor3/sky130_fd_sc_ms__nor3_1.pex.spice +++ b/cells/nor3/sky130_fd_sc_ms__nor3_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3_1.pex.spice -* Created: Fri Aug 28 17:47:47 2020 +* Created: Wed Sep 2 12:15:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor3/sky130_fd_sc_ms__nor3_1.pxi.spice b/cells/nor3/sky130_fd_sc_ms__nor3_1.pxi.spice index a37bafd..de30f79 100644 --- a/cells/nor3/sky130_fd_sc_ms__nor3_1.pxi.spice +++ b/cells/nor3/sky130_fd_sc_ms__nor3_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3_1.pxi.spice -* Created: Fri Aug 28 17:47:47 2020 +* Created: Wed Sep 2 12:15:58 2020 * x_PM_SKY130_FD_SC_MS__NOR3_1%A N_A_M1001_g N_A_c_42_n N_A_M1003_g A A N_A_c_44_n + PM_SKY130_FD_SC_MS__NOR3_1%A
diff --git a/cells/nor3/sky130_fd_sc_ms__nor3_1.spice b/cells/nor3/sky130_fd_sc_ms__nor3_1.spice index 092b887..4d56d8a 100644 --- a/cells/nor3/sky130_fd_sc_ms__nor3_1.spice +++ b/cells/nor3/sky130_fd_sc_ms__nor3_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3_1.spice -* Created: Fri Aug 28 17:47:47 2020 +* Created: Wed Sep 2 12:15:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor3/sky130_fd_sc_ms__nor3_2.lvs.report b/cells/nor3/sky130_fd_sc_ms__nor3_2.lvs.report new file mode 100644 index 0000000..77a03c4 --- /dev/null +++ b/cells/nor3/sky130_fd_sc_ms__nor3_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor3_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor3_2.sp ('sky130_fd_sc_ms__nor3_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor3/sky130_fd_sc_ms__nor3_2.spice ('sky130_fd_sc_ms__nor3_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:16:01 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor3_2 sky130_fd_sc_ms__nor3_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor3_2 +SOURCE CELL NAME: sky130_fd_sc_ms__nor3_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 10 9 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 1 1 SMP3 (5 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 SMP3 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 6 layout mos transistors were reduced to 3. + 3 mos transistors were deleted by parallel reduction. + 6 source mos transistors were reduced to 3. + 3 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C B A Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor3/sky130_fd_sc_ms__nor3_2.pex.spice b/cells/nor3/sky130_fd_sc_ms__nor3_2.pex.spice index 7683460..02dc525 100644 --- a/cells/nor3/sky130_fd_sc_ms__nor3_2.pex.spice +++ b/cells/nor3/sky130_fd_sc_ms__nor3_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3_2.pex.spice -* Created: Fri Aug 28 17:48:17 2020 +* Created: Wed Sep 2 12:16:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor3/sky130_fd_sc_ms__nor3_2.pxi.spice b/cells/nor3/sky130_fd_sc_ms__nor3_2.pxi.spice index 98001cc..3df47ff 100644 --- a/cells/nor3/sky130_fd_sc_ms__nor3_2.pxi.spice +++ b/cells/nor3/sky130_fd_sc_ms__nor3_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3_2.pxi.spice -* Created: Fri Aug 28 17:48:17 2020 +* Created: Wed Sep 2 12:16:04 2020 * x_PM_SKY130_FD_SC_MS__NOR3_2%C N_C_c_59_n N_C_M1000_g N_C_c_56_n N_C_M1006_g + N_C_c_60_n N_C_M1002_g C N_C_c_58_n PM_SKY130_FD_SC_MS__NOR3_2%C
diff --git a/cells/nor3/sky130_fd_sc_ms__nor3_2.spice b/cells/nor3/sky130_fd_sc_ms__nor3_2.spice index dcd3fdf..4e2939d 100644 --- a/cells/nor3/sky130_fd_sc_ms__nor3_2.spice +++ b/cells/nor3/sky130_fd_sc_ms__nor3_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3_2.spice -* Created: Fri Aug 28 17:48:17 2020 +* Created: Wed Sep 2 12:16:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor3/sky130_fd_sc_ms__nor3_4.lvs.report b/cells/nor3/sky130_fd_sc_ms__nor3_4.lvs.report new file mode 100644 index 0000000..a8483d3 --- /dev/null +++ b/cells/nor3/sky130_fd_sc_ms__nor3_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor3_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor3_4.sp ('sky130_fd_sc_ms__nor3_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor3/sky130_fd_sc_ms__nor3_4.spice ('sky130_fd_sc_ms__nor3_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:16:08 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor3_4 sky130_fd_sc_ms__nor3_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor3_4 +SOURCE CELL NAME: sky130_fd_sc_ms__nor3_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 6 6 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 19 18 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 1 1 SMP3 (5 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 SMP3 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 18 layout mos transistors were reduced to 6. + 12 mos transistors were deleted by parallel reduction. + 18 source mos transistors were reduced to 6. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B C VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor3/sky130_fd_sc_ms__nor3_4.pex.spice b/cells/nor3/sky130_fd_sc_ms__nor3_4.pex.spice index a6953bb..569e0b1 100644 --- a/cells/nor3/sky130_fd_sc_ms__nor3_4.pex.spice +++ b/cells/nor3/sky130_fd_sc_ms__nor3_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3_4.pex.spice -* Created: Fri Aug 28 17:48:28 2020 +* Created: Wed Sep 2 12:16:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor3/sky130_fd_sc_ms__nor3_4.pxi.spice b/cells/nor3/sky130_fd_sc_ms__nor3_4.pxi.spice index 517db52..05e2fae 100644 --- a/cells/nor3/sky130_fd_sc_ms__nor3_4.pxi.spice +++ b/cells/nor3/sky130_fd_sc_ms__nor3_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3_4.pxi.spice -* Created: Fri Aug 28 17:48:28 2020 +* Created: Wed Sep 2 12:16:11 2020 * x_PM_SKY130_FD_SC_MS__NOR3_4%A N_A_M1008_g N_A_M1004_g N_A_M1016_g N_A_M1009_g + N_A_c_115_n N_A_M1012_g N_A_c_116_n N_A_M1014_g N_A_c_163_p N_A_c_108_n
diff --git a/cells/nor3/sky130_fd_sc_ms__nor3_4.spice b/cells/nor3/sky130_fd_sc_ms__nor3_4.spice index 3b32272..ee21518 100644 --- a/cells/nor3/sky130_fd_sc_ms__nor3_4.spice +++ b/cells/nor3/sky130_fd_sc_ms__nor3_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3_4.spice -* Created: Fri Aug 28 17:48:28 2020 +* Created: Wed Sep 2 12:16:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor3b/sky130_fd_sc_ms__nor3b_1.lvs.report b/cells/nor3b/sky130_fd_sc_ms__nor3b_1.lvs.report new file mode 100644 index 0000000..98ee524 --- /dev/null +++ b/cells/nor3b/sky130_fd_sc_ms__nor3b_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor3b_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor3b_1.sp ('sky130_fd_sc_ms__nor3b_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor3b/sky130_fd_sc_ms__nor3b_1.spice ('sky130_fd_sc_ms__nor3b_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:16:14 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor3b_1 sky130_fd_sc_ms__nor3b_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor3b_1 +SOURCE CELL NAME: sky130_fd_sc_ms__nor3b_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP3 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C_N A B VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor3b/sky130_fd_sc_ms__nor3b_1.pex.spice b/cells/nor3b/sky130_fd_sc_ms__nor3b_1.pex.spice index 61e071a..0595132 100644 --- a/cells/nor3b/sky130_fd_sc_ms__nor3b_1.pex.spice +++ b/cells/nor3b/sky130_fd_sc_ms__nor3b_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3b_1.pex.spice -* Created: Fri Aug 28 17:48:36 2020 +* Created: Wed Sep 2 12:16:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor3b/sky130_fd_sc_ms__nor3b_1.pxi.spice b/cells/nor3b/sky130_fd_sc_ms__nor3b_1.pxi.spice index ec29c9e..1f45675 100644 --- a/cells/nor3b/sky130_fd_sc_ms__nor3b_1.pxi.spice +++ b/cells/nor3b/sky130_fd_sc_ms__nor3b_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3b_1.pxi.spice -* Created: Fri Aug 28 17:48:36 2020 +* Created: Wed Sep 2 12:16:17 2020 * x_PM_SKY130_FD_SC_MS__NOR3B_1%C_N N_C_N_M1006_g N_C_N_M1004_g C_N N_C_N_c_53_n + N_C_N_c_54_n PM_SKY130_FD_SC_MS__NOR3B_1%C_N
diff --git a/cells/nor3b/sky130_fd_sc_ms__nor3b_1.spice b/cells/nor3b/sky130_fd_sc_ms__nor3b_1.spice index a672126..eaabd83 100644 --- a/cells/nor3b/sky130_fd_sc_ms__nor3b_1.spice +++ b/cells/nor3b/sky130_fd_sc_ms__nor3b_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3b_1.spice -* Created: Fri Aug 28 17:48:36 2020 +* Created: Wed Sep 2 12:16:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor3b/sky130_fd_sc_ms__nor3b_2.lvs.report b/cells/nor3b/sky130_fd_sc_ms__nor3b_2.lvs.report new file mode 100644 index 0000000..69495f6 --- /dev/null +++ b/cells/nor3b/sky130_fd_sc_ms__nor3b_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor3b_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor3b_2.sp ('sky130_fd_sc_ms__nor3b_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor3b/sky130_fd_sc_ms__nor3b_2.spice ('sky130_fd_sc_ms__nor3b_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:16:21 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor3b_2 sky130_fd_sc_ms__nor3b_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor3b_2 +SOURCE CELL NAME: sky130_fd_sc_ms__nor3b_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP3 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C_N B A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor3b/sky130_fd_sc_ms__nor3b_2.pex.spice b/cells/nor3b/sky130_fd_sc_ms__nor3b_2.pex.spice index 69659bd..855d9e2 100644 --- a/cells/nor3b/sky130_fd_sc_ms__nor3b_2.pex.spice +++ b/cells/nor3b/sky130_fd_sc_ms__nor3b_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3b_2.pex.spice -* Created: Fri Aug 28 17:48:45 2020 +* Created: Wed Sep 2 12:16:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor3b/sky130_fd_sc_ms__nor3b_2.pxi.spice b/cells/nor3b/sky130_fd_sc_ms__nor3b_2.pxi.spice index 4253dc3..9e6b16a 100644 --- a/cells/nor3b/sky130_fd_sc_ms__nor3b_2.pxi.spice +++ b/cells/nor3b/sky130_fd_sc_ms__nor3b_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3b_2.pxi.spice -* Created: Fri Aug 28 17:48:45 2020 +* Created: Wed Sep 2 12:16:24 2020 * x_PM_SKY130_FD_SC_MS__NOR3B_2%C_N N_C_N_M1003_g N_C_N_M1008_g C_N N_C_N_c_82_n + PM_SKY130_FD_SC_MS__NOR3B_2%C_N
diff --git a/cells/nor3b/sky130_fd_sc_ms__nor3b_2.spice b/cells/nor3b/sky130_fd_sc_ms__nor3b_2.spice index 045ba4b..ad9d245 100644 --- a/cells/nor3b/sky130_fd_sc_ms__nor3b_2.spice +++ b/cells/nor3b/sky130_fd_sc_ms__nor3b_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3b_2.spice -* Created: Fri Aug 28 17:48:45 2020 +* Created: Wed Sep 2 12:16:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor3b/sky130_fd_sc_ms__nor3b_4.lvs.report b/cells/nor3b/sky130_fd_sc_ms__nor3b_4.lvs.report new file mode 100644 index 0000000..4fc943e --- /dev/null +++ b/cells/nor3b/sky130_fd_sc_ms__nor3b_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor3b_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor3b_4.sp ('sky130_fd_sc_ms__nor3b_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor3b/sky130_fd_sc_ms__nor3b_4.spice ('sky130_fd_sc_ms__nor3b_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:16:27 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor3b_4 sky130_fd_sc_ms__nor3b_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor3b_4 +SOURCE CELL NAME: sky130_fd_sc_ms__nor3b_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 13 13 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 28 27 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP3 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 26 layout mos transistors were reduced to 7. + 19 mos transistors were deleted by parallel reduction. + 26 source mos transistors were reduced to 7. + 19 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A C_N Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor3b/sky130_fd_sc_ms__nor3b_4.pex.spice b/cells/nor3b/sky130_fd_sc_ms__nor3b_4.pex.spice index 7dd3d6d..560377b 100644 --- a/cells/nor3b/sky130_fd_sc_ms__nor3b_4.pex.spice +++ b/cells/nor3b/sky130_fd_sc_ms__nor3b_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3b_4.pex.spice -* Created: Fri Aug 28 17:48:54 2020 +* Created: Wed Sep 2 12:16:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor3b/sky130_fd_sc_ms__nor3b_4.pxi.spice b/cells/nor3b/sky130_fd_sc_ms__nor3b_4.pxi.spice index 7da6e77..9edb4f6 100644 --- a/cells/nor3b/sky130_fd_sc_ms__nor3b_4.pxi.spice +++ b/cells/nor3b/sky130_fd_sc_ms__nor3b_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3b_4.pxi.spice -* Created: Fri Aug 28 17:48:54 2020 +* Created: Wed Sep 2 12:16:30 2020 * x_PM_SKY130_FD_SC_MS__NOR3B_4%B N_B_M1010_g N_B_M1001_g N_B_M1006_g N_B_M1015_g + N_B_M1007_g N_B_M1025_g N_B_M1011_g N_B_M1026_g B B B B N_B_c_123_n
diff --git a/cells/nor3b/sky130_fd_sc_ms__nor3b_4.spice b/cells/nor3b/sky130_fd_sc_ms__nor3b_4.spice index 095b581..45dae92 100644 --- a/cells/nor3b/sky130_fd_sc_ms__nor3b_4.spice +++ b/cells/nor3b/sky130_fd_sc_ms__nor3b_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor3b_4.spice -* Created: Fri Aug 28 17:48:54 2020 +* Created: Wed Sep 2 12:16:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor4/sky130_fd_sc_ms__nor4_1.lvs.report b/cells/nor4/sky130_fd_sc_ms__nor4_1.lvs.report new file mode 100644 index 0000000..f7e8665 --- /dev/null +++ b/cells/nor4/sky130_fd_sc_ms__nor4_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor4_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor4_1.sp ('sky130_fd_sc_ms__nor4_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor4/sky130_fd_sc_ms__nor4_1.spice ('sky130_fd_sc_ms__nor4_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:16:34 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor4_1 sky130_fd_sc_ms__nor4_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor4_1 +SOURCE CELL NAME: sky130_fd_sc_ms__nor4_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B C D VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor4/sky130_fd_sc_ms__nor4_1.pex.spice b/cells/nor4/sky130_fd_sc_ms__nor4_1.pex.spice index ef27c69..5ef0cf4 100644 --- a/cells/nor4/sky130_fd_sc_ms__nor4_1.pex.spice +++ b/cells/nor4/sky130_fd_sc_ms__nor4_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4_1.pex.spice -* Created: Fri Aug 28 17:49:24 2020 +* Created: Wed Sep 2 12:16:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor4/sky130_fd_sc_ms__nor4_1.pxi.spice b/cells/nor4/sky130_fd_sc_ms__nor4_1.pxi.spice index 4f54fa6..916c6b2 100644 --- a/cells/nor4/sky130_fd_sc_ms__nor4_1.pxi.spice +++ b/cells/nor4/sky130_fd_sc_ms__nor4_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4_1.pxi.spice -* Created: Fri Aug 28 17:49:24 2020 +* Created: Wed Sep 2 12:16:37 2020 * x_PM_SKY130_FD_SC_MS__NOR4_1%A N_A_M1001_g N_A_c_50_n N_A_M1000_g N_A_c_51_n + N_A_c_52_n A N_A_c_53_n PM_SKY130_FD_SC_MS__NOR4_1%A
diff --git a/cells/nor4/sky130_fd_sc_ms__nor4_1.spice b/cells/nor4/sky130_fd_sc_ms__nor4_1.spice index 7e6423f..ba39678 100644 --- a/cells/nor4/sky130_fd_sc_ms__nor4_1.spice +++ b/cells/nor4/sky130_fd_sc_ms__nor4_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4_1.spice -* Created: Fri Aug 28 17:49:24 2020 +* Created: Wed Sep 2 12:16:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor4/sky130_fd_sc_ms__nor4_2.lvs.report b/cells/nor4/sky130_fd_sc_ms__nor4_2.lvs.report new file mode 100644 index 0000000..41f5fad --- /dev/null +++ b/cells/nor4/sky130_fd_sc_ms__nor4_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor4_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor4_2.sp ('sky130_fd_sc_ms__nor4_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor4/sky130_fd_sc_ms__nor4_2.spice ('sky130_fd_sc_ms__nor4_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:16:41 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor4_2 sky130_fd_sc_ms__nor4_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor4_2 +SOURCE CELL NAME: sky130_fd_sc_ms__nor4_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C D B A Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor4/sky130_fd_sc_ms__nor4_2.pex.spice b/cells/nor4/sky130_fd_sc_ms__nor4_2.pex.spice index b454cf6..675332a 100644 --- a/cells/nor4/sky130_fd_sc_ms__nor4_2.pex.spice +++ b/cells/nor4/sky130_fd_sc_ms__nor4_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4_2.pex.spice -* Created: Fri Aug 28 17:49:34 2020 +* Created: Wed Sep 2 12:16:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor4/sky130_fd_sc_ms__nor4_2.pxi.spice b/cells/nor4/sky130_fd_sc_ms__nor4_2.pxi.spice index 4afe995..f901984 100644 --- a/cells/nor4/sky130_fd_sc_ms__nor4_2.pxi.spice +++ b/cells/nor4/sky130_fd_sc_ms__nor4_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4_2.pxi.spice -* Created: Fri Aug 28 17:49:34 2020 +* Created: Wed Sep 2 12:16:44 2020 * x_PM_SKY130_FD_SC_MS__NOR4_2%C N_C_M1001_g N_C_M1008_g N_C_M1002_g N_C_c_83_n + N_C_c_84_n C C N_C_c_85_n N_C_c_86_n C N_C_c_88_n PM_SKY130_FD_SC_MS__NOR4_2%C
diff --git a/cells/nor4/sky130_fd_sc_ms__nor4_2.spice b/cells/nor4/sky130_fd_sc_ms__nor4_2.spice index 70cedb7..651ecd0 100644 --- a/cells/nor4/sky130_fd_sc_ms__nor4_2.spice +++ b/cells/nor4/sky130_fd_sc_ms__nor4_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4_2.spice -* Created: Fri Aug 28 17:49:34 2020 +* Created: Wed Sep 2 12:16:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor4/sky130_fd_sc_ms__nor4_4.lvs.report b/cells/nor4/sky130_fd_sc_ms__nor4_4.lvs.report new file mode 100644 index 0000000..49de027 --- /dev/null +++ b/cells/nor4/sky130_fd_sc_ms__nor4_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor4_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor4_4.sp ('sky130_fd_sc_ms__nor4_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor4/sky130_fd_sc_ms__nor4_4.spice ('sky130_fd_sc_ms__nor4_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:16:47 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor4_4 sky130_fd_sc_ms__nor4_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor4_4 +SOURCE CELL NAME: sky130_fd_sc_ms__nor4_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 8 8 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 8. + 16 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 8. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D C B A Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor4/sky130_fd_sc_ms__nor4_4.pex.spice b/cells/nor4/sky130_fd_sc_ms__nor4_4.pex.spice index cc283c4..e9626fb 100644 --- a/cells/nor4/sky130_fd_sc_ms__nor4_4.pex.spice +++ b/cells/nor4/sky130_fd_sc_ms__nor4_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4_4.pex.spice -* Created: Fri Aug 28 17:49:43 2020 +* Created: Wed Sep 2 12:16:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor4/sky130_fd_sc_ms__nor4_4.pxi.spice b/cells/nor4/sky130_fd_sc_ms__nor4_4.pxi.spice index 22c75bd..c050e6a 100644 --- a/cells/nor4/sky130_fd_sc_ms__nor4_4.pxi.spice +++ b/cells/nor4/sky130_fd_sc_ms__nor4_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4_4.pxi.spice -* Created: Fri Aug 28 17:49:43 2020 +* Created: Wed Sep 2 12:16:50 2020 * x_PM_SKY130_FD_SC_MS__NOR4_4%D N_D_M1001_g N_D_M1002_g N_D_M1003_g N_D_M1004_g + N_D_M1022_g N_D_M1006_g D D D N_D_c_111_n N_D_c_106_n
diff --git a/cells/nor4/sky130_fd_sc_ms__nor4_4.spice b/cells/nor4/sky130_fd_sc_ms__nor4_4.spice index 66ebc85..491009c 100644 --- a/cells/nor4/sky130_fd_sc_ms__nor4_4.spice +++ b/cells/nor4/sky130_fd_sc_ms__nor4_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4_4.spice -* Created: Fri Aug 28 17:49:43 2020 +* Created: Wed Sep 2 12:16:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor4b/sky130_fd_sc_ms__nor4b_1.lvs.report b/cells/nor4b/sky130_fd_sc_ms__nor4b_1.lvs.report new file mode 100644 index 0000000..a69ffcb --- /dev/null +++ b/cells/nor4b/sky130_fd_sc_ms__nor4b_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor4b_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor4b_1.sp ('sky130_fd_sc_ms__nor4b_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor4b/sky130_fd_sc_ms__nor4b_1.spice ('sky130_fd_sc_ms__nor4b_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:16:54 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor4b_1 sky130_fd_sc_ms__nor4b_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor4b_1 +SOURCE CELL NAME: sky130_fd_sc_ms__nor4b_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D_N A B C VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor4b/sky130_fd_sc_ms__nor4b_1.pex.spice b/cells/nor4b/sky130_fd_sc_ms__nor4b_1.pex.spice index 9bc2c8d..4ad3834 100644 --- a/cells/nor4b/sky130_fd_sc_ms__nor4b_1.pex.spice +++ b/cells/nor4b/sky130_fd_sc_ms__nor4b_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4b_1.pex.spice -* Created: Fri Aug 28 17:49:52 2020 +* Created: Wed Sep 2 12:16:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor4b/sky130_fd_sc_ms__nor4b_1.pxi.spice b/cells/nor4b/sky130_fd_sc_ms__nor4b_1.pxi.spice index 2671422..81a90b8 100644 --- a/cells/nor4b/sky130_fd_sc_ms__nor4b_1.pxi.spice +++ b/cells/nor4b/sky130_fd_sc_ms__nor4b_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4b_1.pxi.spice -* Created: Fri Aug 28 17:49:52 2020 +* Created: Wed Sep 2 12:16:57 2020 * x_PM_SKY130_FD_SC_MS__NOR4B_1%D_N N_D_N_M1008_g N_D_N_M1004_g D_N N_D_N_c_64_n + PM_SKY130_FD_SC_MS__NOR4B_1%D_N
diff --git a/cells/nor4b/sky130_fd_sc_ms__nor4b_1.spice b/cells/nor4b/sky130_fd_sc_ms__nor4b_1.spice index 1a9df66..cb669a5 100644 --- a/cells/nor4b/sky130_fd_sc_ms__nor4b_1.spice +++ b/cells/nor4b/sky130_fd_sc_ms__nor4b_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4b_1.spice -* Created: Fri Aug 28 17:49:52 2020 +* Created: Wed Sep 2 12:16:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor4b/sky130_fd_sc_ms__nor4b_2.lvs.report b/cells/nor4b/sky130_fd_sc_ms__nor4b_2.lvs.report new file mode 100644 index 0000000..f49adad --- /dev/null +++ b/cells/nor4b/sky130_fd_sc_ms__nor4b_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor4b_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor4b_2.sp ('sky130_fd_sc_ms__nor4b_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor4b/sky130_fd_sc_ms__nor4b_2.spice ('sky130_fd_sc_ms__nor4b_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:17:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor4b_2 sky130_fd_sc_ms__nor4b_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor4b_2 +SOURCE CELL NAME: sky130_fd_sc_ms__nor4b_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 9 9 MN (4 pins) + 9 9 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 19 18 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D_N C B A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor4b/sky130_fd_sc_ms__nor4b_2.pex.spice b/cells/nor4b/sky130_fd_sc_ms__nor4b_2.pex.spice index 30e42ae..e66ba24 100644 --- a/cells/nor4b/sky130_fd_sc_ms__nor4b_2.pex.spice +++ b/cells/nor4b/sky130_fd_sc_ms__nor4b_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4b_2.pex.spice -* Created: Fri Aug 28 17:50:00 2020 +* Created: Wed Sep 2 12:17:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor4b/sky130_fd_sc_ms__nor4b_2.pxi.spice b/cells/nor4b/sky130_fd_sc_ms__nor4b_2.pxi.spice index 7e6e4cf..62a9056 100644 --- a/cells/nor4b/sky130_fd_sc_ms__nor4b_2.pxi.spice +++ b/cells/nor4b/sky130_fd_sc_ms__nor4b_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4b_2.pxi.spice -* Created: Fri Aug 28 17:50:00 2020 +* Created: Wed Sep 2 12:17:03 2020 * x_PM_SKY130_FD_SC_MS__NOR4B_2%D_N N_D_N_M1001_g N_D_N_M1000_g D_N N_D_N_c_97_n + PM_SKY130_FD_SC_MS__NOR4B_2%D_N
diff --git a/cells/nor4b/sky130_fd_sc_ms__nor4b_2.spice b/cells/nor4b/sky130_fd_sc_ms__nor4b_2.spice index 711bd85..ff59e4b 100644 --- a/cells/nor4b/sky130_fd_sc_ms__nor4b_2.spice +++ b/cells/nor4b/sky130_fd_sc_ms__nor4b_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4b_2.spice -* Created: Fri Aug 28 17:50:00 2020 +* Created: Wed Sep 2 12:17:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor4b/sky130_fd_sc_ms__nor4b_4.lvs.report b/cells/nor4b/sky130_fd_sc_ms__nor4b_4.lvs.report new file mode 100644 index 0000000..cfe5daf --- /dev/null +++ b/cells/nor4b/sky130_fd_sc_ms__nor4b_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor4b_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor4b_4.sp ('sky130_fd_sc_ms__nor4b_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor4b/sky130_fd_sc_ms__nor4b_4.spice ('sky130_fd_sc_ms__nor4b_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:17:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor4b_4 sky130_fd_sc_ms__nor4b_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor4b_4 +SOURCE CELL NAME: sky130_fd_sc_ms__nor4b_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 17 17 MN (4 pins) + 18 18 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 36 35 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 34 layout mos transistors were reduced to 9. + 25 mos transistors were deleted by parallel reduction. + 34 source mos transistors were reduced to 9. + 25 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D_N C B A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor4b/sky130_fd_sc_ms__nor4b_4.pex.spice b/cells/nor4b/sky130_fd_sc_ms__nor4b_4.pex.spice index 9138450..737e3d2 100644 --- a/cells/nor4b/sky130_fd_sc_ms__nor4b_4.pex.spice +++ b/cells/nor4b/sky130_fd_sc_ms__nor4b_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4b_4.pex.spice -* Created: Fri Aug 28 17:50:30 2020 +* Created: Wed Sep 2 12:17:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor4b/sky130_fd_sc_ms__nor4b_4.pxi.spice b/cells/nor4b/sky130_fd_sc_ms__nor4b_4.pxi.spice index ca30206..d989b58 100644 --- a/cells/nor4b/sky130_fd_sc_ms__nor4b_4.pxi.spice +++ b/cells/nor4b/sky130_fd_sc_ms__nor4b_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4b_4.pxi.spice -* Created: Fri Aug 28 17:50:30 2020 +* Created: Wed Sep 2 12:17:10 2020 * x_PM_SKY130_FD_SC_MS__NOR4B_4%D_N N_D_N_c_149_n N_D_N_M1012_g N_D_N_M1013_g + N_D_N_c_150_n N_D_N_M1010_g D_N D_N N_D_N_c_151_n
diff --git a/cells/nor4b/sky130_fd_sc_ms__nor4b_4.spice b/cells/nor4b/sky130_fd_sc_ms__nor4b_4.spice index bc6569e..b39ad77 100644 --- a/cells/nor4b/sky130_fd_sc_ms__nor4b_4.spice +++ b/cells/nor4b/sky130_fd_sc_ms__nor4b_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4b_4.spice -* Created: Fri Aug 28 17:50:30 2020 +* Created: Wed Sep 2 12:17:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.lvs.report b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.lvs.report new file mode 100644 index 0000000..3294114 --- /dev/null +++ b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor4bb_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor4bb_1.sp ('sky130_fd_sc_ms__nor4bb_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.spice ('sky130_fd_sc_ms__nor4bb_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:17:14 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor4bb_1 sky130_fd_sc_ms__nor4bb_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor4bb_1 +SOURCE CELL NAME: sky130_fd_sc_ms__nor4bb_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 6 6 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 9 9 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 6 6 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 9 9 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C_N A B D_N VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.pex.spice b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.pex.spice index 9008784..ae35b85 100644 --- a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.pex.spice +++ b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4bb_1.pex.spice -* Created: Fri Aug 28 17:50:41 2020 +* Created: Wed Sep 2 12:17:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.pxi.spice b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.pxi.spice index 773460b..6d0743b 100644 --- a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.pxi.spice +++ b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4bb_1.pxi.spice -* Created: Fri Aug 28 17:50:41 2020 +* Created: Wed Sep 2 12:17:17 2020 * x_PM_SKY130_FD_SC_MS__NOR4BB_1%C_N N_C_N_M1006_g N_C_N_c_77_n N_C_N_M1003_g C_N + N_C_N_c_79_n PM_SKY130_FD_SC_MS__NOR4BB_1%C_N
diff --git a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.spice b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.spice index 966f4fb..31badb6 100644 --- a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.spice +++ b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4bb_1.spice -* Created: Fri Aug 28 17:50:41 2020 +* Created: Wed Sep 2 12:17:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.lvs.report b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.lvs.report new file mode 100644 index 0000000..4610ac9 --- /dev/null +++ b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor4bb_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor4bb_2.sp ('sky130_fd_sc_ms__nor4bb_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.spice ('sky130_fd_sc_ms__nor4bb_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:17:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor4bb_2 sky130_fd_sc_ms__nor4bb_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor4bb_2 +SOURCE CELL NAME: sky130_fd_sc_ms__nor4bb_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 6 6 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 9 9 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 6 6 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 9 9 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C_N D_N B A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.pex.spice b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.pex.spice index 8e62cbe..e2d47ff 100644 --- a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.pex.spice +++ b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4bb_2.pex.spice -* Created: Fri Aug 28 17:50:50 2020 +* Created: Wed Sep 2 12:17:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.pxi.spice b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.pxi.spice index f4ccf89..c213e5d 100644 --- a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.pxi.spice +++ b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4bb_2.pxi.spice -* Created: Fri Aug 28 17:50:50 2020 +* Created: Wed Sep 2 12:17:23 2020 * x_PM_SKY130_FD_SC_MS__NOR4BB_2%C_N N_C_N_M1003_g N_C_N_M1019_g C_N C_N + N_C_N_c_109_n PM_SKY130_FD_SC_MS__NOR4BB_2%C_N
diff --git a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.spice b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.spice index 27abbf6..c6adc9a 100644 --- a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.spice +++ b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4bb_2.spice -* Created: Fri Aug 28 17:50:50 2020 +* Created: Wed Sep 2 12:17:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.lvs.report b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.lvs.report new file mode 100644 index 0000000..8794390 --- /dev/null +++ b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__nor4bb_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__nor4bb_4.sp ('sky130_fd_sc_ms__nor4bb_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.spice ('sky130_fd_sc_ms__nor4bb_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:17:27 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__nor4bb_4 sky130_fd_sc_ms__nor4bb_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__nor4bb_4 +SOURCE CELL NAME: sky130_fd_sc_ms__nor4bb_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 18 18 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 39 38 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 6 6 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 9 9 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 6 6 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 9 9 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 36 layout mos transistors were reduced to 10. + 26 mos transistors were deleted by parallel reduction. + 36 source mos transistors were reduced to 10. + 26 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A C_N D_N VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.pex.spice b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.pex.spice index 13ee6c6..a68a9ea 100644 --- a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.pex.spice +++ b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4bb_4.pex.spice -* Created: Fri Aug 28 17:50:59 2020 +* Created: Wed Sep 2 12:17:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.pxi.spice b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.pxi.spice index c004b10..26ff638 100644 --- a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.pxi.spice +++ b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4bb_4.pxi.spice -* Created: Fri Aug 28 17:50:59 2020 +* Created: Wed Sep 2 12:17:30 2020 * x_PM_SKY130_FD_SC_MS__NOR4BB_4%B N_B_c_187_n N_B_M1001_g N_B_M1000_g N_B_M1018_g + N_B_M1002_g N_B_M1013_g N_B_M1025_g N_B_M1037_g N_B_M1034_g N_B_c_193_n
diff --git a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.spice b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.spice index de2087f..85e3635 100644 --- a/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.spice +++ b/cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__nor4bb_4.spice -* Created: Fri Aug 28 17:50:59 2020 +* Created: Wed Sep 2 12:17:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o2111a/sky130_fd_sc_ms__o2111a_1.lvs.report b/cells/o2111a/sky130_fd_sc_ms__o2111a_1.lvs.report new file mode 100644 index 0000000..71de963 --- /dev/null +++ b/cells/o2111a/sky130_fd_sc_ms__o2111a_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o2111a_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o2111a_1.sp ('sky130_fd_sc_ms__o2111a_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o2111a/sky130_fd_sc_ms__o2111a_1.spice ('sky130_fd_sc_ms__o2111a_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:17:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o2111a_1 sky130_fd_sc_ms__o2111a_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o2111a_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o2111a_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A2 A1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o2111a/sky130_fd_sc_ms__o2111a_1.pex.spice b/cells/o2111a/sky130_fd_sc_ms__o2111a_1.pex.spice index 2f693bd..20ccbab 100644 --- a/cells/o2111a/sky130_fd_sc_ms__o2111a_1.pex.spice +++ b/cells/o2111a/sky130_fd_sc_ms__o2111a_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111a_1.pex.spice -* Created: Fri Aug 28 17:51:08 2020 +* Created: Wed Sep 2 12:17:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o2111a/sky130_fd_sc_ms__o2111a_1.pxi.spice b/cells/o2111a/sky130_fd_sc_ms__o2111a_1.pxi.spice index 1c430a7..fc6d982 100644 --- a/cells/o2111a/sky130_fd_sc_ms__o2111a_1.pxi.spice +++ b/cells/o2111a/sky130_fd_sc_ms__o2111a_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111a_1.pxi.spice -* Created: Fri Aug 28 17:51:08 2020 +* Created: Wed Sep 2 12:17:36 2020 * x_PM_SKY130_FD_SC_MS__O2111A_1%A_82_48# N_A_82_48#_M1011_s N_A_82_48#_M1008_d + N_A_82_48#_M1002_d N_A_82_48#_M1007_g N_A_82_48#_M1003_g N_A_82_48#_c_74_n
diff --git a/cells/o2111a/sky130_fd_sc_ms__o2111a_1.spice b/cells/o2111a/sky130_fd_sc_ms__o2111a_1.spice index 0c9d2aa..275f131 100644 --- a/cells/o2111a/sky130_fd_sc_ms__o2111a_1.spice +++ b/cells/o2111a/sky130_fd_sc_ms__o2111a_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111a_1.spice -* Created: Fri Aug 28 17:51:08 2020 +* Created: Wed Sep 2 12:17:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o2111a/sky130_fd_sc_ms__o2111a_2.lvs.report b/cells/o2111a/sky130_fd_sc_ms__o2111a_2.lvs.report new file mode 100644 index 0000000..6ca84b7 --- /dev/null +++ b/cells/o2111a/sky130_fd_sc_ms__o2111a_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o2111a_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o2111a_2.sp ('sky130_fd_sc_ms__o2111a_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o2111a/sky130_fd_sc_ms__o2111a_2.spice ('sky130_fd_sc_ms__o2111a_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:17:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o2111a_2 sky130_fd_sc_ms__o2111a_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o2111a_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o2111a_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1 C1 D1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o2111a/sky130_fd_sc_ms__o2111a_2.pex.spice b/cells/o2111a/sky130_fd_sc_ms__o2111a_2.pex.spice index d62ecaa..cf4ad7a 100644 --- a/cells/o2111a/sky130_fd_sc_ms__o2111a_2.pex.spice +++ b/cells/o2111a/sky130_fd_sc_ms__o2111a_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111a_2.pex.spice -* Created: Fri Aug 28 17:51:37 2020 +* Created: Wed Sep 2 12:17:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o2111a/sky130_fd_sc_ms__o2111a_2.pxi.spice b/cells/o2111a/sky130_fd_sc_ms__o2111a_2.pxi.spice index cb77c96..5fcfac9 100644 --- a/cells/o2111a/sky130_fd_sc_ms__o2111a_2.pxi.spice +++ b/cells/o2111a/sky130_fd_sc_ms__o2111a_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111a_2.pxi.spice -* Created: Fri Aug 28 17:51:37 2020 +* Created: Wed Sep 2 12:17:43 2020 * x_PM_SKY130_FD_SC_MS__O2111A_2%A1 N_A1_M1006_g N_A1_c_78_n N_A1_M1007_g A1 A1 + N_A1_c_80_n PM_SKY130_FD_SC_MS__O2111A_2%A1
diff --git a/cells/o2111a/sky130_fd_sc_ms__o2111a_2.spice b/cells/o2111a/sky130_fd_sc_ms__o2111a_2.spice index a645cf5..8827af1 100644 --- a/cells/o2111a/sky130_fd_sc_ms__o2111a_2.spice +++ b/cells/o2111a/sky130_fd_sc_ms__o2111a_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111a_2.spice -* Created: Fri Aug 28 17:51:37 2020 +* Created: Wed Sep 2 12:17:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o2111a/sky130_fd_sc_ms__o2111a_4.lvs.report b/cells/o2111a/sky130_fd_sc_ms__o2111a_4.lvs.report new file mode 100644 index 0000000..d010b65 --- /dev/null +++ b/cells/o2111a/sky130_fd_sc_ms__o2111a_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o2111a_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o2111a_4.sp ('sky130_fd_sc_ms__o2111a_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o2111a/sky130_fd_sc_ms__o2111a_4.spice ('sky130_fd_sc_ms__o2111a_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:17:46 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o2111a_4 sky130_fd_sc_ms__o2111a_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o2111a_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o2111a_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o2111a/sky130_fd_sc_ms__o2111a_4.pex.spice b/cells/o2111a/sky130_fd_sc_ms__o2111a_4.pex.spice index ba56ff3..988a587 100644 --- a/cells/o2111a/sky130_fd_sc_ms__o2111a_4.pex.spice +++ b/cells/o2111a/sky130_fd_sc_ms__o2111a_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111a_4.pex.spice -* Created: Fri Aug 28 17:51:48 2020 +* Created: Wed Sep 2 12:17:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o2111a/sky130_fd_sc_ms__o2111a_4.pxi.spice b/cells/o2111a/sky130_fd_sc_ms__o2111a_4.pxi.spice index c72a053..80c7a50 100644 --- a/cells/o2111a/sky130_fd_sc_ms__o2111a_4.pxi.spice +++ b/cells/o2111a/sky130_fd_sc_ms__o2111a_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111a_4.pxi.spice -* Created: Fri Aug 28 17:51:48 2020 +* Created: Wed Sep 2 12:17:50 2020 * x_PM_SKY130_FD_SC_MS__O2111A_4%D1 N_D1_M1000_g N_D1_M1010_g N_D1_c_150_n + N_D1_M1011_g N_D1_M1023_g N_D1_c_152_n D1 N_D1_c_153_n N_D1_c_154_n
diff --git a/cells/o2111a/sky130_fd_sc_ms__o2111a_4.spice b/cells/o2111a/sky130_fd_sc_ms__o2111a_4.spice index f0e5fef..06c527f 100644 --- a/cells/o2111a/sky130_fd_sc_ms__o2111a_4.spice +++ b/cells/o2111a/sky130_fd_sc_ms__o2111a_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111a_4.spice -* Created: Fri Aug 28 17:51:48 2020 +* Created: Wed Sep 2 12:17:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.lvs.report b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.lvs.report new file mode 100644 index 0000000..e14cae5 --- /dev/null +++ b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o2111ai_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o2111ai_1.sp ('sky130_fd_sc_ms__o2111ai_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.spice ('sky130_fd_sc_ms__o2111ai_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:17:53 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o2111ai_1 sky130_fd_sc_ms__o2111ai_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o2111ai_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o2111ai_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 3 3 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A2 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.pex.spice b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.pex.spice index 363769b..a3d6d5f 100644 --- a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.pex.spice +++ b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111ai_1.pex.spice -* Created: Fri Aug 28 17:51:57 2020 +* Created: Wed Sep 2 12:17:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.pxi.spice b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.pxi.spice index cb36144..d4050fc 100644 --- a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.pxi.spice +++ b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111ai_1.pxi.spice -* Created: Fri Aug 28 17:51:57 2020 +* Created: Wed Sep 2 12:17:56 2020 * x_PM_SKY130_FD_SC_MS__O2111AI_1%D1 N_D1_M1008_g N_D1_M1006_g D1 N_D1_c_56_n + N_D1_c_57_n PM_SKY130_FD_SC_MS__O2111AI_1%D1
diff --git a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.spice b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.spice index e220c3b..81e2dec 100644 --- a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.spice +++ b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111ai_1.spice -* Created: Fri Aug 28 17:51:57 2020 +* Created: Wed Sep 2 12:17:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.lvs.report b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.lvs.report new file mode 100644 index 0000000..e58df46 --- /dev/null +++ b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o2111ai_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o2111ai_2.sp ('sky130_fd_sc_ms__o2111ai_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.spice ('sky130_fd_sc_ms__o2111ai_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:18:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o2111ai_2 sky130_fd_sc_ms__o2111ai_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o2111ai_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o2111ai_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 3 3 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A2 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.pex.spice b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.pex.spice index 4756542..b1ca70d 100644 --- a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.pex.spice +++ b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111ai_2.pex.spice -* Created: Fri Aug 28 17:52:06 2020 +* Created: Wed Sep 2 12:18:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.pxi.spice b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.pxi.spice index 230e314..35943be 100644 --- a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.pxi.spice +++ b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111ai_2.pxi.spice -* Created: Fri Aug 28 17:52:06 2020 +* Created: Wed Sep 2 12:18:03 2020 * x_PM_SKY130_FD_SC_MS__O2111AI_2%D1 N_D1_M1011_g N_D1_c_103_n N_D1_M1014_g + N_D1_M1012_g N_D1_c_105_n N_D1_M1016_g N_D1_c_106_n N_D1_c_107_n D1
diff --git a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.spice b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.spice index 8f42b8e..fe6cf64 100644 --- a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.spice +++ b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111ai_2.spice -* Created: Fri Aug 28 17:52:06 2020 +* Created: Wed Sep 2 12:18:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.lvs.report b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.lvs.report new file mode 100644 index 0000000..20c9f3a --- /dev/null +++ b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o2111ai_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o2111ai_4.sp ('sky130_fd_sc_ms__o2111ai_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.spice ('sky130_fd_sc_ms__o2111ai_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:18:06 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o2111ai_4 sky130_fd_sc_ms__o2111ai_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o2111ai_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o2111ai_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 20 20 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 35 34 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 3 3 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1_1_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1_1_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 34 layout mos transistors were reduced to 10. + 24 mos transistors were deleted by parallel reduction. + 34 source mos transistors were reduced to 10. + 24 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.pex.spice b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.pex.spice index 6a81f1c..08bd9df 100644 --- a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.pex.spice +++ b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111ai_4.pex.spice -* Created: Fri Aug 28 17:52:15 2020 +* Created: Wed Sep 2 12:18:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.pxi.spice b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.pxi.spice index 6d42ceb..eebb2a1 100644 --- a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.pxi.spice +++ b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111ai_4.pxi.spice -* Created: Fri Aug 28 17:52:15 2020 +* Created: Wed Sep 2 12:18:10 2020 * x_PM_SKY130_FD_SC_MS__O2111AI_4%D1 N_D1_c_141_n N_D1_M1010_g N_D1_c_142_n + N_D1_M1013_g N_D1_M1004_g N_D1_c_143_n N_D1_M1027_g N_D1_c_144_n N_D1_M1012_g
diff --git a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.spice b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.spice index 7f00cf3..fb52c88 100644 --- a/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.spice +++ b/cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2111ai_4.spice -* Created: Fri Aug 28 17:52:15 2020 +* Created: Wed Sep 2 12:18:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o211a/sky130_fd_sc_ms__o211a_1.lvs.report b/cells/o211a/sky130_fd_sc_ms__o211a_1.lvs.report new file mode 100644 index 0000000..9298a1a --- /dev/null +++ b/cells/o211a/sky130_fd_sc_ms__o211a_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o211a_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o211a_1.sp ('sky130_fd_sc_ms__o211a_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o211a/sky130_fd_sc_ms__o211a_1.spice ('sky130_fd_sc_ms__o211a_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:18:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o211a_1 sky130_fd_sc_ms__o211a_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o211a_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o211a_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1_1 (6 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o211a/sky130_fd_sc_ms__o211a_1.pex.spice b/cells/o211a/sky130_fd_sc_ms__o211a_1.pex.spice index a430b84..4077ea0 100644 --- a/cells/o211a/sky130_fd_sc_ms__o211a_1.pex.spice +++ b/cells/o211a/sky130_fd_sc_ms__o211a_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211a_1.pex.spice -* Created: Fri Aug 28 17:52:45 2020 +* Created: Wed Sep 2 12:18:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o211a/sky130_fd_sc_ms__o211a_1.pxi.spice b/cells/o211a/sky130_fd_sc_ms__o211a_1.pxi.spice index a12e661..42a2df8 100644 --- a/cells/o211a/sky130_fd_sc_ms__o211a_1.pxi.spice +++ b/cells/o211a/sky130_fd_sc_ms__o211a_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211a_1.pxi.spice -* Created: Fri Aug 28 17:52:45 2020 +* Created: Wed Sep 2 12:18:16 2020 * x_PM_SKY130_FD_SC_MS__O211A_1%A_83_264# N_A_83_264#_M1001_d N_A_83_264#_M1007_d + N_A_83_264#_M1006_d N_A_83_264#_M1000_g N_A_83_264#_M1009_g N_A_83_264#_c_66_n
diff --git a/cells/o211a/sky130_fd_sc_ms__o211a_1.spice b/cells/o211a/sky130_fd_sc_ms__o211a_1.spice index 97385e9..db7101f 100644 --- a/cells/o211a/sky130_fd_sc_ms__o211a_1.spice +++ b/cells/o211a/sky130_fd_sc_ms__o211a_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211a_1.spice -* Created: Fri Aug 28 17:52:45 2020 +* Created: Wed Sep 2 12:18:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o211a/sky130_fd_sc_ms__o211a_2.lvs.report b/cells/o211a/sky130_fd_sc_ms__o211a_2.lvs.report new file mode 100644 index 0000000..875da33 --- /dev/null +++ b/cells/o211a/sky130_fd_sc_ms__o211a_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o211a_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o211a_2.sp ('sky130_fd_sc_ms__o211a_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o211a/sky130_fd_sc_ms__o211a_2.spice ('sky130_fd_sc_ms__o211a_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:18:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o211a_2 sky130_fd_sc_ms__o211a_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o211a_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o211a_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1_1 (6 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o211a/sky130_fd_sc_ms__o211a_2.pex.spice b/cells/o211a/sky130_fd_sc_ms__o211a_2.pex.spice index a684969..d438acb 100644 --- a/cells/o211a/sky130_fd_sc_ms__o211a_2.pex.spice +++ b/cells/o211a/sky130_fd_sc_ms__o211a_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211a_2.pex.spice -* Created: Fri Aug 28 17:52:55 2020 +* Created: Wed Sep 2 12:20:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o211a/sky130_fd_sc_ms__o211a_2.pxi.spice b/cells/o211a/sky130_fd_sc_ms__o211a_2.pxi.spice index 0742249..e507757 100644 --- a/cells/o211a/sky130_fd_sc_ms__o211a_2.pxi.spice +++ b/cells/o211a/sky130_fd_sc_ms__o211a_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211a_2.pxi.spice -* Created: Fri Aug 28 17:52:55 2020 +* Created: Wed Sep 2 12:20:08 2020 * x_PM_SKY130_FD_SC_MS__O211A_2%C1 N_C1_M1007_g N_C1_c_69_n N_C1_M1011_g C1 + N_C1_c_71_n PM_SKY130_FD_SC_MS__O211A_2%C1
diff --git a/cells/o211a/sky130_fd_sc_ms__o211a_2.spice b/cells/o211a/sky130_fd_sc_ms__o211a_2.spice index 5df2b54..3a28e93 100644 --- a/cells/o211a/sky130_fd_sc_ms__o211a_2.spice +++ b/cells/o211a/sky130_fd_sc_ms__o211a_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211a_2.spice -* Created: Fri Aug 28 17:52:55 2020 +* Created: Wed Sep 2 12:20:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o211a/sky130_fd_sc_ms__o211a_4.lvs.report b/cells/o211a/sky130_fd_sc_ms__o211a_4.lvs.report new file mode 100644 index 0000000..da56c63 --- /dev/null +++ b/cells/o211a/sky130_fd_sc_ms__o211a_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o211a_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o211a_4.sp ('sky130_fd_sc_ms__o211a_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o211a/sky130_fd_sc_ms__o211a_4.spice ('sky130_fd_sc_ms__o211a_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:20:22 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o211a_4 sky130_fd_sc_ms__o211a_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o211a_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o211a_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1_1 (6 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o211a/sky130_fd_sc_ms__o211a_4.pex.spice b/cells/o211a/sky130_fd_sc_ms__o211a_4.pex.spice index e243601..2cead2f 100644 --- a/cells/o211a/sky130_fd_sc_ms__o211a_4.pex.spice +++ b/cells/o211a/sky130_fd_sc_ms__o211a_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211a_4.pex.spice -* Created: Fri Aug 28 17:53:04 2020 +* Created: Wed Sep 2 12:20:26 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o211a/sky130_fd_sc_ms__o211a_4.pxi.spice b/cells/o211a/sky130_fd_sc_ms__o211a_4.pxi.spice index 366d74a..d152a68 100644 --- a/cells/o211a/sky130_fd_sc_ms__o211a_4.pxi.spice +++ b/cells/o211a/sky130_fd_sc_ms__o211a_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211a_4.pxi.spice -* Created: Fri Aug 28 17:53:04 2020 +* Created: Wed Sep 2 12:20:26 2020 * x_PM_SKY130_FD_SC_MS__O211A_4%A_91_48# N_A_91_48#_M1015_s N_A_91_48#_M1010_s + N_A_91_48#_M1007_s N_A_91_48#_M1001_s N_A_91_48#_M1002_g N_A_91_48#_M1004_g
diff --git a/cells/o211a/sky130_fd_sc_ms__o211a_4.spice b/cells/o211a/sky130_fd_sc_ms__o211a_4.spice index de7a467..6d34106 100644 --- a/cells/o211a/sky130_fd_sc_ms__o211a_4.spice +++ b/cells/o211a/sky130_fd_sc_ms__o211a_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211a_4.spice -* Created: Fri Aug 28 17:53:04 2020 +* Created: Wed Sep 2 12:20:26 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o211ai/sky130_fd_sc_ms__o211ai_1.lvs.report b/cells/o211ai/sky130_fd_sc_ms__o211ai_1.lvs.report new file mode 100644 index 0000000..02bddac --- /dev/null +++ b/cells/o211ai/sky130_fd_sc_ms__o211ai_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o211ai_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o211ai_1.sp ('sky130_fd_sc_ms__o211ai_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o211ai/sky130_fd_sc_ms__o211ai_1.spice ('sky130_fd_sc_ms__o211ai_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:20:29 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o211ai_1 sky130_fd_sc_ms__o211ai_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o211ai_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o211ai_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1_1 (6 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o211ai/sky130_fd_sc_ms__o211ai_1.pex.spice b/cells/o211ai/sky130_fd_sc_ms__o211ai_1.pex.spice index 93bf58b..e387ca4 100644 --- a/cells/o211ai/sky130_fd_sc_ms__o211ai_1.pex.spice +++ b/cells/o211ai/sky130_fd_sc_ms__o211ai_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211ai_1.pex.spice -* Created: Fri Aug 28 17:53:13 2020 +* Created: Wed Sep 2 12:20:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o211ai/sky130_fd_sc_ms__o211ai_1.pxi.spice b/cells/o211ai/sky130_fd_sc_ms__o211ai_1.pxi.spice index 7fd4333..3e7e70b 100644 --- a/cells/o211ai/sky130_fd_sc_ms__o211ai_1.pxi.spice +++ b/cells/o211ai/sky130_fd_sc_ms__o211ai_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211ai_1.pxi.spice -* Created: Fri Aug 28 17:53:13 2020 +* Created: Wed Sep 2 12:20:32 2020 * x_PM_SKY130_FD_SC_MS__O211AI_1%A1 N_A1_M1004_g N_A1_M1006_g A1 N_A1_c_52_n + N_A1_c_53_n PM_SKY130_FD_SC_MS__O211AI_1%A1
diff --git a/cells/o211ai/sky130_fd_sc_ms__o211ai_1.spice b/cells/o211ai/sky130_fd_sc_ms__o211ai_1.spice index d89ad38..d010636 100644 --- a/cells/o211ai/sky130_fd_sc_ms__o211ai_1.spice +++ b/cells/o211ai/sky130_fd_sc_ms__o211ai_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211ai_1.spice -* Created: Fri Aug 28 17:53:13 2020 +* Created: Wed Sep 2 12:20:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o211ai/sky130_fd_sc_ms__o211ai_2.lvs.report b/cells/o211ai/sky130_fd_sc_ms__o211ai_2.lvs.report new file mode 100644 index 0000000..3b0d724 --- /dev/null +++ b/cells/o211ai/sky130_fd_sc_ms__o211ai_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o211ai_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o211ai_2.sp ('sky130_fd_sc_ms__o211ai_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o211ai/sky130_fd_sc_ms__o211ai_2.spice ('sky130_fd_sc_ms__o211ai_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:20:36 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o211ai_2 sky130_fd_sc_ms__o211ai_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o211ai_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o211ai_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1_1 (6 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 A2 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o211ai/sky130_fd_sc_ms__o211ai_2.pex.spice b/cells/o211ai/sky130_fd_sc_ms__o211ai_2.pex.spice index 97a8c87..7f92532 100644 --- a/cells/o211ai/sky130_fd_sc_ms__o211ai_2.pex.spice +++ b/cells/o211ai/sky130_fd_sc_ms__o211ai_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211ai_2.pex.spice -* Created: Fri Aug 28 17:53:22 2020 +* Created: Wed Sep 2 12:20:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o211ai/sky130_fd_sc_ms__o211ai_2.pxi.spice b/cells/o211ai/sky130_fd_sc_ms__o211ai_2.pxi.spice index 753417c..cf9ae22 100644 --- a/cells/o211ai/sky130_fd_sc_ms__o211ai_2.pxi.spice +++ b/cells/o211ai/sky130_fd_sc_ms__o211ai_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211ai_2.pxi.spice -* Created: Fri Aug 28 17:53:22 2020 +* Created: Wed Sep 2 12:20:39 2020 * x_PM_SKY130_FD_SC_MS__O211AI_2%C1 N_C1_M1001_g N_C1_M1008_g N_C1_M1002_g + N_C1_M1009_g C1 N_C1_c_90_n N_C1_c_91_n PM_SKY130_FD_SC_MS__O211AI_2%C1
diff --git a/cells/o211ai/sky130_fd_sc_ms__o211ai_2.spice b/cells/o211ai/sky130_fd_sc_ms__o211ai_2.spice index fd69edf..41e383f 100644 --- a/cells/o211ai/sky130_fd_sc_ms__o211ai_2.spice +++ b/cells/o211ai/sky130_fd_sc_ms__o211ai_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211ai_2.spice -* Created: Fri Aug 28 17:53:22 2020 +* Created: Wed Sep 2 12:20:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o211ai/sky130_fd_sc_ms__o211ai_4.lvs.report b/cells/o211ai/sky130_fd_sc_ms__o211ai_4.lvs.report new file mode 100644 index 0000000..acaec79 --- /dev/null +++ b/cells/o211ai/sky130_fd_sc_ms__o211ai_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o211ai_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o211ai_4.sp ('sky130_fd_sc_ms__o211ai_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o211ai/sky130_fd_sc_ms__o211ai_4.spice ('sky130_fd_sc_ms__o211ai_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:20:42 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o211ai_4 sky130_fd_sc_ms__o211ai_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o211ai_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o211ai_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 16 16 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1_1 (6 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 8. + 20 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 8. + 20 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o211ai/sky130_fd_sc_ms__o211ai_4.pex.spice b/cells/o211ai/sky130_fd_sc_ms__o211ai_4.pex.spice index 7319191..7c7bcab 100644 --- a/cells/o211ai/sky130_fd_sc_ms__o211ai_4.pex.spice +++ b/cells/o211ai/sky130_fd_sc_ms__o211ai_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211ai_4.pex.spice -* Created: Fri Aug 28 17:53:52 2020 +* Created: Wed Sep 2 12:21:20 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o211ai/sky130_fd_sc_ms__o211ai_4.pxi.spice b/cells/o211ai/sky130_fd_sc_ms__o211ai_4.pxi.spice index c198a5d..e7632c3 100644 --- a/cells/o211ai/sky130_fd_sc_ms__o211ai_4.pxi.spice +++ b/cells/o211ai/sky130_fd_sc_ms__o211ai_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211ai_4.pxi.spice -* Created: Fri Aug 28 17:53:52 2020 +* Created: Wed Sep 2 12:21:20 2020 * x_PM_SKY130_FD_SC_MS__O211AI_4%A1 N_A1_M1009_g N_A1_M1011_g N_A1_M1012_g + N_A1_M1017_g N_A1_M1013_g N_A1_M1024_g N_A1_M1019_g N_A1_M1027_g A1 A1 A1 A1
diff --git a/cells/o211ai/sky130_fd_sc_ms__o211ai_4.spice b/cells/o211ai/sky130_fd_sc_ms__o211ai_4.spice index e2dbe02..93ade49 100644 --- a/cells/o211ai/sky130_fd_sc_ms__o211ai_4.spice +++ b/cells/o211ai/sky130_fd_sc_ms__o211ai_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o211ai_4.spice -* Created: Fri Aug 28 17:53:52 2020 +* Created: Wed Sep 2 12:21:20 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o21a/sky130_fd_sc_ms__o21a_1.lvs.report b/cells/o21a/sky130_fd_sc_ms__o21a_1.lvs.report new file mode 100644 index 0000000..1336c6c --- /dev/null +++ b/cells/o21a/sky130_fd_sc_ms__o21a_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o21a_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o21a_1.sp ('sky130_fd_sc_ms__o21a_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o21a/sky130_fd_sc_ms__o21a_1.spice ('sky130_fd_sc_ms__o21a_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:21:27 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o21a_1 sky130_fd_sc_ms__o21a_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o21a_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o21a_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A2 A1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o21a/sky130_fd_sc_ms__o21a_1.pex.spice b/cells/o21a/sky130_fd_sc_ms__o21a_1.pex.spice index 979733a..a78f615 100644 --- a/cells/o21a/sky130_fd_sc_ms__o21a_1.pex.spice +++ b/cells/o21a/sky130_fd_sc_ms__o21a_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21a_1.pex.spice -* Created: Fri Aug 28 17:54:02 2020 +* Created: Wed Sep 2 12:21:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o21a/sky130_fd_sc_ms__o21a_1.pxi.spice b/cells/o21a/sky130_fd_sc_ms__o21a_1.pxi.spice index c94b4fb..4344db6 100644 --- a/cells/o21a/sky130_fd_sc_ms__o21a_1.pxi.spice +++ b/cells/o21a/sky130_fd_sc_ms__o21a_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21a_1.pxi.spice -* Created: Fri Aug 28 17:54:02 2020 +* Created: Wed Sep 2 12:21:30 2020 * x_PM_SKY130_FD_SC_MS__O21A_1%A_83_244# N_A_83_244#_M1002_s N_A_83_244#_M1000_d + N_A_83_244#_M1003_g N_A_83_244#_c_55_n N_A_83_244#_M1005_g N_A_83_244#_c_56_n
diff --git a/cells/o21a/sky130_fd_sc_ms__o21a_1.spice b/cells/o21a/sky130_fd_sc_ms__o21a_1.spice index cc1342e..f1b2ebd 100644 --- a/cells/o21a/sky130_fd_sc_ms__o21a_1.spice +++ b/cells/o21a/sky130_fd_sc_ms__o21a_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21a_1.spice -* Created: Fri Aug 28 17:54:02 2020 +* Created: Wed Sep 2 12:21:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o21a/sky130_fd_sc_ms__o21a_2.lvs.report b/cells/o21a/sky130_fd_sc_ms__o21a_2.lvs.report new file mode 100644 index 0000000..2742630 --- /dev/null +++ b/cells/o21a/sky130_fd_sc_ms__o21a_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o21a_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o21a_2.sp ('sky130_fd_sc_ms__o21a_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o21a/sky130_fd_sc_ms__o21a_2.spice ('sky130_fd_sc_ms__o21a_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:21:34 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o21a_2 sky130_fd_sc_ms__o21a_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o21a_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o21a_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 1 sec
diff --git a/cells/o21a/sky130_fd_sc_ms__o21a_2.pex.spice b/cells/o21a/sky130_fd_sc_ms__o21a_2.pex.spice index 772b14f..ec3f474 100644 --- a/cells/o21a/sky130_fd_sc_ms__o21a_2.pex.spice +++ b/cells/o21a/sky130_fd_sc_ms__o21a_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21a_2.pex.spice -* Created: Fri Aug 28 17:54:11 2020 +* Created: Wed Sep 2 12:21:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o21a/sky130_fd_sc_ms__o21a_2.pxi.spice b/cells/o21a/sky130_fd_sc_ms__o21a_2.pxi.spice index 53fe390..d3ecf46 100644 --- a/cells/o21a/sky130_fd_sc_ms__o21a_2.pxi.spice +++ b/cells/o21a/sky130_fd_sc_ms__o21a_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21a_2.pxi.spice -* Created: Fri Aug 28 17:54:11 2020 +* Created: Wed Sep 2 12:21:37 2020 * x_PM_SKY130_FD_SC_MS__O21A_2%A1 N_A1_c_63_n N_A1_M1006_g N_A1_M1008_g + N_A1_c_65_n N_A1_c_66_n A1 A1 PM_SKY130_FD_SC_MS__O21A_2%A1
diff --git a/cells/o21a/sky130_fd_sc_ms__o21a_2.spice b/cells/o21a/sky130_fd_sc_ms__o21a_2.spice index 0faba4a..edbd175 100644 --- a/cells/o21a/sky130_fd_sc_ms__o21a_2.spice +++ b/cells/o21a/sky130_fd_sc_ms__o21a_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21a_2.spice -* Created: Fri Aug 28 17:54:11 2020 +* Created: Wed Sep 2 12:21:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o21a/sky130_fd_sc_ms__o21a_4.lvs.report b/cells/o21a/sky130_fd_sc_ms__o21a_4.lvs.report new file mode 100644 index 0000000..e08547b --- /dev/null +++ b/cells/o21a/sky130_fd_sc_ms__o21a_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o21a_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o21a_4.sp ('sky130_fd_sc_ms__o21a_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o21a/sky130_fd_sc_ms__o21a_4.spice ('sky130_fd_sc_ms__o21a_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:21:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o21a_4 sky130_fd_sc_ms__o21a_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o21a_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o21a_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o21a/sky130_fd_sc_ms__o21a_4.pex.spice b/cells/o21a/sky130_fd_sc_ms__o21a_4.pex.spice index da658e3..39f227f 100644 --- a/cells/o21a/sky130_fd_sc_ms__o21a_4.pex.spice +++ b/cells/o21a/sky130_fd_sc_ms__o21a_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21a_4.pex.spice -* Created: Fri Aug 28 17:54:20 2020 +* Created: Wed Sep 2 12:21:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o21a/sky130_fd_sc_ms__o21a_4.pxi.spice b/cells/o21a/sky130_fd_sc_ms__o21a_4.pxi.spice index 1abb1ce..78b9356 100644 --- a/cells/o21a/sky130_fd_sc_ms__o21a_4.pxi.spice +++ b/cells/o21a/sky130_fd_sc_ms__o21a_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21a_4.pxi.spice -* Created: Fri Aug 28 17:54:20 2020 +* Created: Wed Sep 2 12:21:43 2020 * x_PM_SKY130_FD_SC_MS__O21A_4%A2 N_A2_M1011_g N_A2_M1003_g N_A2_M1004_g + N_A2_M1013_g A2 N_A2_c_104_n N_A2_c_105_n PM_SKY130_FD_SC_MS__O21A_4%A2
diff --git a/cells/o21a/sky130_fd_sc_ms__o21a_4.spice b/cells/o21a/sky130_fd_sc_ms__o21a_4.spice index fd703e2..6dc99e5 100644 --- a/cells/o21a/sky130_fd_sc_ms__o21a_4.spice +++ b/cells/o21a/sky130_fd_sc_ms__o21a_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21a_4.spice -* Created: Fri Aug 28 17:54:20 2020 +* Created: Wed Sep 2 12:21:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o21ai/sky130_fd_sc_ms__o21ai_1.lvs.report b/cells/o21ai/sky130_fd_sc_ms__o21ai_1.lvs.report new file mode 100644 index 0000000..7555299 --- /dev/null +++ b/cells/o21ai/sky130_fd_sc_ms__o21ai_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o21ai_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o21ai_1.sp ('sky130_fd_sc_ms__o21ai_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o21ai/sky130_fd_sc_ms__o21ai_1.spice ('sky130_fd_sc_ms__o21ai_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:21:47 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o21ai_1 sky130_fd_sc_ms__o21ai_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o21ai_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o21ai_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 1 1 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o21ai/sky130_fd_sc_ms__o21ai_1.pex.spice b/cells/o21ai/sky130_fd_sc_ms__o21ai_1.pex.spice index 268498b..846b1d7 100644 --- a/cells/o21ai/sky130_fd_sc_ms__o21ai_1.pex.spice +++ b/cells/o21ai/sky130_fd_sc_ms__o21ai_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ai_1.pex.spice -* Created: Fri Aug 28 17:54:29 2020 +* Created: Wed Sep 2 12:21:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o21ai/sky130_fd_sc_ms__o21ai_1.pxi.spice b/cells/o21ai/sky130_fd_sc_ms__o21ai_1.pxi.spice index 93b3adb..f86b070 100644 --- a/cells/o21ai/sky130_fd_sc_ms__o21ai_1.pxi.spice +++ b/cells/o21ai/sky130_fd_sc_ms__o21ai_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ai_1.pxi.spice -* Created: Fri Aug 28 17:54:29 2020 +* Created: Wed Sep 2 12:21:50 2020 * x_PM_SKY130_FD_SC_MS__O21AI_1%A1 N_A1_c_39_n N_A1_M1005_g N_A1_M1001_g A1 + N_A1_c_41_n N_A1_c_42_n PM_SKY130_FD_SC_MS__O21AI_1%A1
diff --git a/cells/o21ai/sky130_fd_sc_ms__o21ai_1.spice b/cells/o21ai/sky130_fd_sc_ms__o21ai_1.spice index be6d628..26850a4 100644 --- a/cells/o21ai/sky130_fd_sc_ms__o21ai_1.spice +++ b/cells/o21ai/sky130_fd_sc_ms__o21ai_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ai_1.spice -* Created: Fri Aug 28 17:54:29 2020 +* Created: Wed Sep 2 12:21:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o21ai/sky130_fd_sc_ms__o21ai_2.lvs.report b/cells/o21ai/sky130_fd_sc_ms__o21ai_2.lvs.report new file mode 100644 index 0000000..6785aed --- /dev/null +++ b/cells/o21ai/sky130_fd_sc_ms__o21ai_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o21ai_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o21ai_2.sp ('sky130_fd_sc_ms__o21ai_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o21ai/sky130_fd_sc_ms__o21ai_2.spice ('sky130_fd_sc_ms__o21ai_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:21:54 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o21ai_2 sky130_fd_sc_ms__o21ai_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o21ai_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o21ai_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 1 1 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o21ai/sky130_fd_sc_ms__o21ai_2.pex.spice b/cells/o21ai/sky130_fd_sc_ms__o21ai_2.pex.spice index 1577a21..cbc70f3 100644 --- a/cells/o21ai/sky130_fd_sc_ms__o21ai_2.pex.spice +++ b/cells/o21ai/sky130_fd_sc_ms__o21ai_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ai_2.pex.spice -* Created: Fri Aug 28 17:54:59 2020 +* Created: Wed Sep 2 12:21:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o21ai/sky130_fd_sc_ms__o21ai_2.pxi.spice b/cells/o21ai/sky130_fd_sc_ms__o21ai_2.pxi.spice index ab54c04..e0468b8 100644 --- a/cells/o21ai/sky130_fd_sc_ms__o21ai_2.pxi.spice +++ b/cells/o21ai/sky130_fd_sc_ms__o21ai_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ai_2.pxi.spice -* Created: Fri Aug 28 17:54:59 2020 +* Created: Wed Sep 2 12:21:57 2020 * x_PM_SKY130_FD_SC_MS__O21AI_2%A1 N_A1_M1000_g N_A1_M1009_g N_A1_M1010_g + N_A1_M1002_g N_A1_c_68_n N_A1_c_69_n N_A1_c_80_p N_A1_c_104_p A1 N_A1_c_70_n
diff --git a/cells/o21ai/sky130_fd_sc_ms__o21ai_2.spice b/cells/o21ai/sky130_fd_sc_ms__o21ai_2.spice index 0f4ebdf..86d885e 100644 --- a/cells/o21ai/sky130_fd_sc_ms__o21ai_2.spice +++ b/cells/o21ai/sky130_fd_sc_ms__o21ai_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ai_2.spice -* Created: Fri Aug 28 17:54:59 2020 +* Created: Wed Sep 2 12:21:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o21ai/sky130_fd_sc_ms__o21ai_4.lvs.report b/cells/o21ai/sky130_fd_sc_ms__o21ai_4.lvs.report new file mode 100644 index 0000000..4340dfa --- /dev/null +++ b/cells/o21ai/sky130_fd_sc_ms__o21ai_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o21ai_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o21ai_4.sp ('sky130_fd_sc_ms__o21ai_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o21ai/sky130_fd_sc_ms__o21ai_4.spice ('sky130_fd_sc_ms__o21ai_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:22:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o21ai_4 sky130_fd_sc_ms__o21ai_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o21ai_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o21ai_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 12 12 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 8 8 + + Instances: 1 1 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 8 8 0 0 + + Instances: 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 22 layout mos transistors were reduced to 6. + 16 mos transistors were deleted by parallel reduction. + 22 source mos transistors were reduced to 6. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 B1 A2 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o21ai/sky130_fd_sc_ms__o21ai_4.pex.spice b/cells/o21ai/sky130_fd_sc_ms__o21ai_4.pex.spice index adf40e3..0de9e43 100644 --- a/cells/o21ai/sky130_fd_sc_ms__o21ai_4.pex.spice +++ b/cells/o21ai/sky130_fd_sc_ms__o21ai_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ai_4.pex.spice -* Created: Fri Aug 28 17:55:09 2020 +* Created: Wed Sep 2 12:22:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o21ai/sky130_fd_sc_ms__o21ai_4.pxi.spice b/cells/o21ai/sky130_fd_sc_ms__o21ai_4.pxi.spice index 051d6a1..41dda46 100644 --- a/cells/o21ai/sky130_fd_sc_ms__o21ai_4.pxi.spice +++ b/cells/o21ai/sky130_fd_sc_ms__o21ai_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ai_4.pxi.spice -* Created: Fri Aug 28 17:55:09 2020 +* Created: Wed Sep 2 12:22:03 2020 * x_PM_SKY130_FD_SC_MS__O21AI_4%A1 N_A1_M1004_g N_A1_M1009_g N_A1_M1018_g + N_A1_M1005_g N_A1_M1019_g N_A1_M1006_g N_A1_M1021_g N_A1_M1007_g A1 A1
diff --git a/cells/o21ai/sky130_fd_sc_ms__o21ai_4.spice b/cells/o21ai/sky130_fd_sc_ms__o21ai_4.spice index e9717ae..276c5dd 100644 --- a/cells/o21ai/sky130_fd_sc_ms__o21ai_4.spice +++ b/cells/o21ai/sky130_fd_sc_ms__o21ai_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ai_4.spice -* Created: Fri Aug 28 17:55:09 2020 +* Created: Wed Sep 2 12:22:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o21ba/sky130_fd_sc_ms__o21ba_1.lvs.report b/cells/o21ba/sky130_fd_sc_ms__o21ba_1.lvs.report new file mode 100644 index 0000000..1fccb8a --- /dev/null +++ b/cells/o21ba/sky130_fd_sc_ms__o21ba_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o21ba_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o21ba_1.sp ('sky130_fd_sc_ms__o21ba_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o21ba/sky130_fd_sc_ms__o21ba_1.spice ('sky130_fd_sc_ms__o21ba_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:22:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o21ba_1 sky130_fd_sc_ms__o21ba_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o21ba_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o21ba_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1_N VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o21ba/sky130_fd_sc_ms__o21ba_1.pex.spice b/cells/o21ba/sky130_fd_sc_ms__o21ba_1.pex.spice index 989e8ef..8ad06f6 100644 --- a/cells/o21ba/sky130_fd_sc_ms__o21ba_1.pex.spice +++ b/cells/o21ba/sky130_fd_sc_ms__o21ba_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ba_1.pex.spice -* Created: Fri Aug 28 17:55:18 2020 +* Created: Wed Sep 2 12:22:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o21ba/sky130_fd_sc_ms__o21ba_1.pxi.spice b/cells/o21ba/sky130_fd_sc_ms__o21ba_1.pxi.spice index bd3b66e..d109a99 100644 --- a/cells/o21ba/sky130_fd_sc_ms__o21ba_1.pxi.spice +++ b/cells/o21ba/sky130_fd_sc_ms__o21ba_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ba_1.pxi.spice -* Created: Fri Aug 28 17:55:18 2020 +* Created: Wed Sep 2 12:22:10 2020 * x_PM_SKY130_FD_SC_MS__O21BA_1%A1 N_A1_c_75_n N_A1_c_80_n N_A1_M1002_g + N_A1_M1008_g A1 A1 N_A1_c_77_n N_A1_c_78_n PM_SKY130_FD_SC_MS__O21BA_1%A1
diff --git a/cells/o21ba/sky130_fd_sc_ms__o21ba_1.spice b/cells/o21ba/sky130_fd_sc_ms__o21ba_1.spice index ec5a01a..55cbbd2 100644 --- a/cells/o21ba/sky130_fd_sc_ms__o21ba_1.spice +++ b/cells/o21ba/sky130_fd_sc_ms__o21ba_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ba_1.spice -* Created: Fri Aug 28 17:55:18 2020 +* Created: Wed Sep 2 12:22:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o21ba/sky130_fd_sc_ms__o21ba_2.lvs.report b/cells/o21ba/sky130_fd_sc_ms__o21ba_2.lvs.report new file mode 100644 index 0000000..12dcb00 --- /dev/null +++ b/cells/o21ba/sky130_fd_sc_ms__o21ba_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o21ba_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o21ba_2.sp ('sky130_fd_sc_ms__o21ba_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o21ba/sky130_fd_sc_ms__o21ba_2.spice ('sky130_fd_sc_ms__o21ba_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:22:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o21ba_2 sky130_fd_sc_ms__o21ba_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o21ba_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o21ba_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o21ba/sky130_fd_sc_ms__o21ba_2.pex.spice b/cells/o21ba/sky130_fd_sc_ms__o21ba_2.pex.spice index 4780db1..45c9548 100644 --- a/cells/o21ba/sky130_fd_sc_ms__o21ba_2.pex.spice +++ b/cells/o21ba/sky130_fd_sc_ms__o21ba_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ba_2.pex.spice -* Created: Fri Aug 28 17:55:27 2020 +* Created: Wed Sep 2 12:22:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o21ba/sky130_fd_sc_ms__o21ba_2.pxi.spice b/cells/o21ba/sky130_fd_sc_ms__o21ba_2.pxi.spice index 1115f14..8099b0c 100644 --- a/cells/o21ba/sky130_fd_sc_ms__o21ba_2.pxi.spice +++ b/cells/o21ba/sky130_fd_sc_ms__o21ba_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ba_2.pxi.spice -* Created: Fri Aug 28 17:55:27 2020 +* Created: Wed Sep 2 12:22:16 2020 * x_PM_SKY130_FD_SC_MS__O21BA_2%B1_N N_B1_N_M1006_g N_B1_N_M1002_g B1_N + N_B1_N_c_75_n N_B1_N_c_76_n PM_SKY130_FD_SC_MS__O21BA_2%B1_N
diff --git a/cells/o21ba/sky130_fd_sc_ms__o21ba_2.spice b/cells/o21ba/sky130_fd_sc_ms__o21ba_2.spice index 3855acc..aaa7183 100644 --- a/cells/o21ba/sky130_fd_sc_ms__o21ba_2.spice +++ b/cells/o21ba/sky130_fd_sc_ms__o21ba_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ba_2.spice -* Created: Fri Aug 28 17:55:27 2020 +* Created: Wed Sep 2 12:22:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o21ba/sky130_fd_sc_ms__o21ba_4.lvs.report b/cells/o21ba/sky130_fd_sc_ms__o21ba_4.lvs.report new file mode 100644 index 0000000..911488b --- /dev/null +++ b/cells/o21ba/sky130_fd_sc_ms__o21ba_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o21ba_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o21ba_4.sp ('sky130_fd_sc_ms__o21ba_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o21ba/sky130_fd_sc_ms__o21ba_4.spice ('sky130_fd_sc_ms__o21ba_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:22:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o21ba_4 sky130_fd_sc_ms__o21ba_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o21ba_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o21ba_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 2 2 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o21ba/sky130_fd_sc_ms__o21ba_4.pex.spice b/cells/o21ba/sky130_fd_sc_ms__o21ba_4.pex.spice index 0cb1b61..dbab820 100644 --- a/cells/o21ba/sky130_fd_sc_ms__o21ba_4.pex.spice +++ b/cells/o21ba/sky130_fd_sc_ms__o21ba_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ba_4.pex.spice -* Created: Fri Aug 28 17:55:36 2020 +* Created: Wed Sep 2 12:22:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o21ba/sky130_fd_sc_ms__o21ba_4.pxi.spice b/cells/o21ba/sky130_fd_sc_ms__o21ba_4.pxi.spice index e307c4b..999d9ad 100644 --- a/cells/o21ba/sky130_fd_sc_ms__o21ba_4.pxi.spice +++ b/cells/o21ba/sky130_fd_sc_ms__o21ba_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ba_4.pxi.spice -* Created: Fri Aug 28 17:55:36 2020 +* Created: Wed Sep 2 12:22:23 2020 * x_PM_SKY130_FD_SC_MS__O21BA_4%B1_N N_B1_N_M1010_g N_B1_N_M1020_g B1_N + N_B1_N_c_121_n N_B1_N_c_122_n PM_SKY130_FD_SC_MS__O21BA_4%B1_N
diff --git a/cells/o21ba/sky130_fd_sc_ms__o21ba_4.spice b/cells/o21ba/sky130_fd_sc_ms__o21ba_4.spice index bb832b3..8e542e2 100644 --- a/cells/o21ba/sky130_fd_sc_ms__o21ba_4.spice +++ b/cells/o21ba/sky130_fd_sc_ms__o21ba_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21ba_4.spice -* Created: Fri Aug 28 17:55:36 2020 +* Created: Wed Sep 2 12:22:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o21bai/sky130_fd_sc_ms__o21bai_1.lvs.report b/cells/o21bai/sky130_fd_sc_ms__o21bai_1.lvs.report new file mode 100644 index 0000000..9b62ede --- /dev/null +++ b/cells/o21bai/sky130_fd_sc_ms__o21bai_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o21bai_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o21bai_1.sp ('sky130_fd_sc_ms__o21bai_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o21bai/sky130_fd_sc_ms__o21bai_1.spice ('sky130_fd_sc_ms__o21bai_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:22:26 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o21bai_1 sky130_fd_sc_ms__o21bai_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o21bai_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o21bai_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A2 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o21bai/sky130_fd_sc_ms__o21bai_1.pex.spice b/cells/o21bai/sky130_fd_sc_ms__o21bai_1.pex.spice index 2efd443..6616aec 100644 --- a/cells/o21bai/sky130_fd_sc_ms__o21bai_1.pex.spice +++ b/cells/o21bai/sky130_fd_sc_ms__o21bai_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21bai_1.pex.spice -* Created: Fri Aug 28 17:56:05 2020 +* Created: Wed Sep 2 12:22:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o21bai/sky130_fd_sc_ms__o21bai_1.pxi.spice b/cells/o21bai/sky130_fd_sc_ms__o21bai_1.pxi.spice index b9e1a52..33a27b0 100644 --- a/cells/o21bai/sky130_fd_sc_ms__o21bai_1.pxi.spice +++ b/cells/o21bai/sky130_fd_sc_ms__o21bai_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21bai_1.pxi.spice -* Created: Fri Aug 28 17:56:05 2020 +* Created: Wed Sep 2 12:22:29 2020 * x_PM_SKY130_FD_SC_MS__O21BAI_1%B1_N N_B1_N_M1001_g N_B1_N_c_61_n N_B1_N_M1005_g + B1_N N_B1_N_c_62_n PM_SKY130_FD_SC_MS__O21BAI_1%B1_N
diff --git a/cells/o21bai/sky130_fd_sc_ms__o21bai_1.spice b/cells/o21bai/sky130_fd_sc_ms__o21bai_1.spice index b7ff880..141bcdc 100644 --- a/cells/o21bai/sky130_fd_sc_ms__o21bai_1.spice +++ b/cells/o21bai/sky130_fd_sc_ms__o21bai_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21bai_1.spice -* Created: Fri Aug 28 17:56:05 2020 +* Created: Wed Sep 2 12:22:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o21bai/sky130_fd_sc_ms__o21bai_2.lvs.report b/cells/o21bai/sky130_fd_sc_ms__o21bai_2.lvs.report new file mode 100644 index 0000000..7fc8f17 --- /dev/null +++ b/cells/o21bai/sky130_fd_sc_ms__o21bai_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o21bai_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o21bai_2.sp ('sky130_fd_sc_ms__o21bai_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o21bai/sky130_fd_sc_ms__o21bai_2.spice ('sky130_fd_sc_ms__o21bai_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:22:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o21bai_2 sky130_fd_sc_ms__o21bai_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o21bai_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o21bai_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1_N A1 A2 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o21bai/sky130_fd_sc_ms__o21bai_2.pex.spice b/cells/o21bai/sky130_fd_sc_ms__o21bai_2.pex.spice index 6592e16..711c51c 100644 --- a/cells/o21bai/sky130_fd_sc_ms__o21bai_2.pex.spice +++ b/cells/o21bai/sky130_fd_sc_ms__o21bai_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21bai_2.pex.spice -* Created: Fri Aug 28 17:56:16 2020 +* Created: Wed Sep 2 12:22:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o21bai/sky130_fd_sc_ms__o21bai_2.pxi.spice b/cells/o21bai/sky130_fd_sc_ms__o21bai_2.pxi.spice index f05485d..5b1d6b4 100644 --- a/cells/o21bai/sky130_fd_sc_ms__o21bai_2.pxi.spice +++ b/cells/o21bai/sky130_fd_sc_ms__o21bai_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21bai_2.pxi.spice -* Created: Fri Aug 28 17:56:16 2020 +* Created: Wed Sep 2 12:22:36 2020 * x_PM_SKY130_FD_SC_MS__O21BAI_2%B1_N N_B1_N_M1011_g N_B1_N_M1000_g B1_N + N_B1_N_c_81_n N_B1_N_c_82_n PM_SKY130_FD_SC_MS__O21BAI_2%B1_N
diff --git a/cells/o21bai/sky130_fd_sc_ms__o21bai_2.spice b/cells/o21bai/sky130_fd_sc_ms__o21bai_2.spice index f9d2001..209e081 100644 --- a/cells/o21bai/sky130_fd_sc_ms__o21bai_2.spice +++ b/cells/o21bai/sky130_fd_sc_ms__o21bai_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21bai_2.spice -* Created: Fri Aug 28 17:56:16 2020 +* Created: Wed Sep 2 12:22:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o21bai/sky130_fd_sc_ms__o21bai_4.lvs.report b/cells/o21bai/sky130_fd_sc_ms__o21bai_4.lvs.report new file mode 100644 index 0000000..63ea410 --- /dev/null +++ b/cells/o21bai/sky130_fd_sc_ms__o21bai_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o21bai_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o21bai_4.sp ('sky130_fd_sc_ms__o21bai_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o21bai/sky130_fd_sc_ms__o21bai_4.spice ('sky130_fd_sc_ms__o21bai_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:22:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o21bai_4 sky130_fd_sc_ms__o21bai_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o21bai_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o21bai_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 13 13 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 26 25 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 7. + 17 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 7. + 17 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1_N VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o21bai/sky130_fd_sc_ms__o21bai_4.pex.spice b/cells/o21bai/sky130_fd_sc_ms__o21bai_4.pex.spice index 09b7dcb..003de68 100644 --- a/cells/o21bai/sky130_fd_sc_ms__o21bai_4.pex.spice +++ b/cells/o21bai/sky130_fd_sc_ms__o21bai_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21bai_4.pex.spice -* Created: Fri Aug 28 17:56:25 2020 +* Created: Wed Sep 2 12:22:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o21bai/sky130_fd_sc_ms__o21bai_4.pxi.spice b/cells/o21bai/sky130_fd_sc_ms__o21bai_4.pxi.spice index 36ede34..6e8ebc2 100644 --- a/cells/o21bai/sky130_fd_sc_ms__o21bai_4.pxi.spice +++ b/cells/o21bai/sky130_fd_sc_ms__o21bai_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21bai_4.pxi.spice -* Created: Fri Aug 28 17:56:25 2020 +* Created: Wed Sep 2 12:22:43 2020 * x_PM_SKY130_FD_SC_MS__O21BAI_4%A1 N_A1_M1009_g N_A1_M1002_g N_A1_M1003_g + N_A1_M1020_g N_A1_M1004_g N_A1_M1021_g N_A1_c_126_n N_A1_M1023_g N_A1_M1008_g
diff --git a/cells/o21bai/sky130_fd_sc_ms__o21bai_4.spice b/cells/o21bai/sky130_fd_sc_ms__o21bai_4.spice index 02912e7..b7072ce 100644 --- a/cells/o21bai/sky130_fd_sc_ms__o21bai_4.spice +++ b/cells/o21bai/sky130_fd_sc_ms__o21bai_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o21bai_4.spice -* Created: Fri Aug 28 17:56:25 2020 +* Created: Wed Sep 2 12:22:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o221a/sky130_fd_sc_ms__o221a_1.lvs.report b/cells/o221a/sky130_fd_sc_ms__o221a_1.lvs.report new file mode 100644 index 0000000..97e10e3 --- /dev/null +++ b/cells/o221a/sky130_fd_sc_ms__o221a_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o221a_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o221a_1.sp ('sky130_fd_sc_ms__o221a_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o221a/sky130_fd_sc_ms__o221a_1.spice ('sky130_fd_sc_ms__o221a_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:22:47 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o221a_1 sky130_fd_sc_ms__o221a_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o221a_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o221a_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 2 2 SMP2 (4 pins) + 1 1 SPMN_2_2_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 2 2 0 0 SMP2 + 1 1 0 0 SPMN_2_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B2 B1 C1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o221a/sky130_fd_sc_ms__o221a_1.pex.spice b/cells/o221a/sky130_fd_sc_ms__o221a_1.pex.spice index fd0cc8e..20aff42 100644 --- a/cells/o221a/sky130_fd_sc_ms__o221a_1.pex.spice +++ b/cells/o221a/sky130_fd_sc_ms__o221a_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221a_1.pex.spice -* Created: Fri Aug 28 17:56:34 2020 +* Created: Wed Sep 2 12:22:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o221a/sky130_fd_sc_ms__o221a_1.pxi.spice b/cells/o221a/sky130_fd_sc_ms__o221a_1.pxi.spice index ea7b4e0..b2c5386 100644 --- a/cells/o221a/sky130_fd_sc_ms__o221a_1.pxi.spice +++ b/cells/o221a/sky130_fd_sc_ms__o221a_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221a_1.pxi.spice -* Created: Fri Aug 28 17:56:34 2020 +* Created: Wed Sep 2 12:22:50 2020 * x_PM_SKY130_FD_SC_MS__O221A_1%A_83_264# N_A_83_264#_M1006_d N_A_83_264#_M1002_d + N_A_83_264#_M1009_d N_A_83_264#_M1007_g N_A_83_264#_M1004_g N_A_83_264#_c_85_n
diff --git a/cells/o221a/sky130_fd_sc_ms__o221a_1.spice b/cells/o221a/sky130_fd_sc_ms__o221a_1.spice index c3b7585..ba4e2bf 100644 --- a/cells/o221a/sky130_fd_sc_ms__o221a_1.spice +++ b/cells/o221a/sky130_fd_sc_ms__o221a_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221a_1.spice -* Created: Fri Aug 28 17:56:34 2020 +* Created: Wed Sep 2 12:22:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o221a/sky130_fd_sc_ms__o221a_2.lvs.report b/cells/o221a/sky130_fd_sc_ms__o221a_2.lvs.report new file mode 100644 index 0000000..ab834c5 --- /dev/null +++ b/cells/o221a/sky130_fd_sc_ms__o221a_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o221a_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o221a_2.sp ('sky130_fd_sc_ms__o221a_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o221a/sky130_fd_sc_ms__o221a_2.spice ('sky130_fd_sc_ms__o221a_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:22:53 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o221a_2 sky130_fd_sc_ms__o221a_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o221a_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o221a_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 2 2 SMP2 (4 pins) + 1 1 SPMN_2_2_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 2 2 0 0 SMP2 + 1 1 0 0 SPMN_2_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 B2 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o221a/sky130_fd_sc_ms__o221a_2.pex.spice b/cells/o221a/sky130_fd_sc_ms__o221a_2.pex.spice index b985338..bc6e1b1 100644 --- a/cells/o221a/sky130_fd_sc_ms__o221a_2.pex.spice +++ b/cells/o221a/sky130_fd_sc_ms__o221a_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221a_2.pex.spice -* Created: Fri Aug 28 17:56:43 2020 +* Created: Wed Sep 2 12:22:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o221a/sky130_fd_sc_ms__o221a_2.pxi.spice b/cells/o221a/sky130_fd_sc_ms__o221a_2.pxi.spice index 1fcaf95..92c0392 100644 --- a/cells/o221a/sky130_fd_sc_ms__o221a_2.pxi.spice +++ b/cells/o221a/sky130_fd_sc_ms__o221a_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221a_2.pxi.spice -* Created: Fri Aug 28 17:56:43 2020 +* Created: Wed Sep 2 12:22:56 2020 * x_PM_SKY130_FD_SC_MS__O221A_2%C1 N_C1_M1006_g N_C1_c_85_n N_C1_M1007_g C1 + N_C1_c_87_n PM_SKY130_FD_SC_MS__O221A_2%C1
diff --git a/cells/o221a/sky130_fd_sc_ms__o221a_2.spice b/cells/o221a/sky130_fd_sc_ms__o221a_2.spice index 963765d..a072ac2 100644 --- a/cells/o221a/sky130_fd_sc_ms__o221a_2.spice +++ b/cells/o221a/sky130_fd_sc_ms__o221a_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221a_2.spice -* Created: Fri Aug 28 17:56:43 2020 +* Created: Wed Sep 2 12:22:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o221a/sky130_fd_sc_ms__o221a_4.lvs.report b/cells/o221a/sky130_fd_sc_ms__o221a_4.lvs.report new file mode 100644 index 0000000..2fb0a8c --- /dev/null +++ b/cells/o221a/sky130_fd_sc_ms__o221a_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o221a_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o221a_4.sp ('sky130_fd_sc_ms__o221a_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o221a/sky130_fd_sc_ms__o221a_4.spice ('sky130_fd_sc_ms__o221a_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:23:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o221a_4 sky130_fd_sc_ms__o221a_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o221a_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o221a_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 2 2 SMP2 (4 pins) + 1 1 SPMN_2_2_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 2 2 0 0 SMP2 + 1 1 0 0 SPMN_2_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B2 B1 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o221a/sky130_fd_sc_ms__o221a_4.pex.spice b/cells/o221a/sky130_fd_sc_ms__o221a_4.pex.spice index f528e59..503ecfb 100644 --- a/cells/o221a/sky130_fd_sc_ms__o221a_4.pex.spice +++ b/cells/o221a/sky130_fd_sc_ms__o221a_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221a_4.pex.spice -* Created: Fri Aug 28 17:57:13 2020 +* Created: Wed Sep 2 12:23:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o221a/sky130_fd_sc_ms__o221a_4.pxi.spice b/cells/o221a/sky130_fd_sc_ms__o221a_4.pxi.spice index 23217d8..592bf6a 100644 --- a/cells/o221a/sky130_fd_sc_ms__o221a_4.pxi.spice +++ b/cells/o221a/sky130_fd_sc_ms__o221a_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221a_4.pxi.spice -* Created: Fri Aug 28 17:57:13 2020 +* Created: Wed Sep 2 12:23:03 2020 * x_PM_SKY130_FD_SC_MS__O221A_4%C1 N_C1_M1015_g N_C1_M1012_g N_C1_M1014_g + N_C1_M1016_g C1 C1 N_C1_c_144_n PM_SKY130_FD_SC_MS__O221A_4%C1
diff --git a/cells/o221a/sky130_fd_sc_ms__o221a_4.spice b/cells/o221a/sky130_fd_sc_ms__o221a_4.spice index c2fd509..7548819 100644 --- a/cells/o221a/sky130_fd_sc_ms__o221a_4.spice +++ b/cells/o221a/sky130_fd_sc_ms__o221a_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221a_4.spice -* Created: Fri Aug 28 17:57:13 2020 +* Created: Wed Sep 2 12:23:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o221ai/sky130_fd_sc_ms__o221ai_1.lvs.report b/cells/o221ai/sky130_fd_sc_ms__o221ai_1.lvs.report new file mode 100644 index 0000000..6c79242 --- /dev/null +++ b/cells/o221ai/sky130_fd_sc_ms__o221ai_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o221ai_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o221ai_1.sp ('sky130_fd_sc_ms__o221ai_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o221ai/sky130_fd_sc_ms__o221ai_1.spice ('sky130_fd_sc_ms__o221ai_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:23:06 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o221ai_1 sky130_fd_sc_ms__o221ai_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o221ai_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o221ai_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MP (4 pins) + 2 2 SMP2 (4 pins) + 1 1 SPMN_2_2_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMP2 + 1 1 0 0 SPMN_2_2_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 B2 A2 A1 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o221ai/sky130_fd_sc_ms__o221ai_1.pex.spice b/cells/o221ai/sky130_fd_sc_ms__o221ai_1.pex.spice index 6f239fc..efc6611 100644 --- a/cells/o221ai/sky130_fd_sc_ms__o221ai_1.pex.spice +++ b/cells/o221ai/sky130_fd_sc_ms__o221ai_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221ai_1.pex.spice -* Created: Fri Aug 28 17:57:23 2020 +* Created: Wed Sep 2 12:23:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o221ai/sky130_fd_sc_ms__o221ai_1.pxi.spice b/cells/o221ai/sky130_fd_sc_ms__o221ai_1.pxi.spice index dcc6040..a7fb545 100644 --- a/cells/o221ai/sky130_fd_sc_ms__o221ai_1.pxi.spice +++ b/cells/o221ai/sky130_fd_sc_ms__o221ai_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221ai_1.pxi.spice -* Created: Fri Aug 28 17:57:23 2020 +* Created: Wed Sep 2 12:23:09 2020 * x_PM_SKY130_FD_SC_MS__O221AI_1%C1 N_C1_M1009_g N_C1_M1002_g C1 N_C1_c_62_n + N_C1_c_63_n PM_SKY130_FD_SC_MS__O221AI_1%C1
diff --git a/cells/o221ai/sky130_fd_sc_ms__o221ai_1.spice b/cells/o221ai/sky130_fd_sc_ms__o221ai_1.spice index 136781c..add1ae9 100644 --- a/cells/o221ai/sky130_fd_sc_ms__o221ai_1.spice +++ b/cells/o221ai/sky130_fd_sc_ms__o221ai_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221ai_1.spice -* Created: Fri Aug 28 17:57:23 2020 +* Created: Wed Sep 2 12:23:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o221ai/sky130_fd_sc_ms__o221ai_2.lvs.report b/cells/o221ai/sky130_fd_sc_ms__o221ai_2.lvs.report new file mode 100644 index 0000000..b7a6787 --- /dev/null +++ b/cells/o221ai/sky130_fd_sc_ms__o221ai_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o221ai_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o221ai_2.sp ('sky130_fd_sc_ms__o221ai_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o221ai/sky130_fd_sc_ms__o221ai_2.spice ('sky130_fd_sc_ms__o221ai_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:23:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o221ai_2 sky130_fd_sc_ms__o221ai_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o221ai_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o221ai_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MP (4 pins) + 2 2 SMP2 (4 pins) + 1 1 SPMN_2_2_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMP2 + 1 1 0 0 SPMN_2_2_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 B2 A1 A2 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o221ai/sky130_fd_sc_ms__o221ai_2.pex.spice b/cells/o221ai/sky130_fd_sc_ms__o221ai_2.pex.spice index 95d6d63..9847d22 100644 --- a/cells/o221ai/sky130_fd_sc_ms__o221ai_2.pex.spice +++ b/cells/o221ai/sky130_fd_sc_ms__o221ai_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221ai_2.pex.spice -* Created: Fri Aug 28 17:57:32 2020 +* Created: Wed Sep 2 12:23:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o221ai/sky130_fd_sc_ms__o221ai_2.pxi.spice b/cells/o221ai/sky130_fd_sc_ms__o221ai_2.pxi.spice index 99eb073..038158c 100644 --- a/cells/o221ai/sky130_fd_sc_ms__o221ai_2.pxi.spice +++ b/cells/o221ai/sky130_fd_sc_ms__o221ai_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221ai_2.pxi.spice -* Created: Fri Aug 28 17:57:32 2020 +* Created: Wed Sep 2 12:23:16 2020 * x_PM_SKY130_FD_SC_MS__O221AI_2%C1 N_C1_M1017_g N_C1_M1013_g N_C1_M1018_g + N_C1_M1014_g C1 N_C1_c_101_n N_C1_c_102_n PM_SKY130_FD_SC_MS__O221AI_2%C1
diff --git a/cells/o221ai/sky130_fd_sc_ms__o221ai_2.spice b/cells/o221ai/sky130_fd_sc_ms__o221ai_2.spice index 04c1760..878e846 100644 --- a/cells/o221ai/sky130_fd_sc_ms__o221ai_2.spice +++ b/cells/o221ai/sky130_fd_sc_ms__o221ai_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221ai_2.spice -* Created: Fri Aug 28 17:57:32 2020 +* Created: Wed Sep 2 12:23:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o221ai/sky130_fd_sc_ms__o221ai_4.lvs.report b/cells/o221ai/sky130_fd_sc_ms__o221ai_4.lvs.report new file mode 100644 index 0000000..72e73c4 --- /dev/null +++ b/cells/o221ai/sky130_fd_sc_ms__o221ai_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o221ai_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o221ai_4.sp ('sky130_fd_sc_ms__o221ai_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o221ai/sky130_fd_sc_ms__o221ai_4.spice ('sky130_fd_sc_ms__o221ai_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:23:19 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o221ai_4 sky130_fd_sc_ms__o221ai_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o221ai_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o221ai_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MP (4 pins) + 2 2 SMP2 (4 pins) + 1 1 SPMN_2_2_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMP2 + 1 1 0 0 SPMN_2_2_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 40 layout mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + 40 source mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 B2 A1 A2 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o221ai/sky130_fd_sc_ms__o221ai_4.pex.spice b/cells/o221ai/sky130_fd_sc_ms__o221ai_4.pex.spice index 19ff12c..7d3dbdf 100644 --- a/cells/o221ai/sky130_fd_sc_ms__o221ai_4.pex.spice +++ b/cells/o221ai/sky130_fd_sc_ms__o221ai_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221ai_4.pex.spice -* Created: Fri Aug 28 17:57:41 2020 +* Created: Wed Sep 2 12:23:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o221ai/sky130_fd_sc_ms__o221ai_4.pxi.spice b/cells/o221ai/sky130_fd_sc_ms__o221ai_4.pxi.spice index d95a0a5..b329f46 100644 --- a/cells/o221ai/sky130_fd_sc_ms__o221ai_4.pxi.spice +++ b/cells/o221ai/sky130_fd_sc_ms__o221ai_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221ai_4.pxi.spice -* Created: Fri Aug 28 17:57:41 2020 +* Created: Wed Sep 2 12:23:22 2020 * x_PM_SKY130_FD_SC_MS__O221AI_4%C1 N_C1_M1013_g N_C1_M1000_g N_C1_M1002_g + N_C1_M1014_g N_C1_M1004_g N_C1_M1024_g N_C1_M1018_g N_C1_M1035_g C1 C1 C1
diff --git a/cells/o221ai/sky130_fd_sc_ms__o221ai_4.spice b/cells/o221ai/sky130_fd_sc_ms__o221ai_4.spice index 43cde56..95fdf5c 100644 --- a/cells/o221ai/sky130_fd_sc_ms__o221ai_4.spice +++ b/cells/o221ai/sky130_fd_sc_ms__o221ai_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o221ai_4.spice -* Created: Fri Aug 28 17:57:41 2020 +* Created: Wed Sep 2 12:23:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o22a/sky130_fd_sc_ms__o22a_1.lvs.report b/cells/o22a/sky130_fd_sc_ms__o22a_1.lvs.report new file mode 100644 index 0000000..9300be7 --- /dev/null +++ b/cells/o22a/sky130_fd_sc_ms__o22a_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o22a_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o22a_1.sp ('sky130_fd_sc_ms__o22a_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o22a/sky130_fd_sc_ms__o22a_1.spice ('sky130_fd_sc_ms__o22a_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:23:26 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o22a_1 sky130_fd_sc_ms__o22a_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o22a_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o22a_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMP2 (4 pins) + 1 1 SPMN_2_2 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMP2 + 1 1 0 0 SPMN_2_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 B2 A2 A1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o22a/sky130_fd_sc_ms__o22a_1.pex.spice b/cells/o22a/sky130_fd_sc_ms__o22a_1.pex.spice index 5f307a5..fcab36e 100644 --- a/cells/o22a/sky130_fd_sc_ms__o22a_1.pex.spice +++ b/cells/o22a/sky130_fd_sc_ms__o22a_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22a_1.pex.spice -* Created: Fri Aug 28 17:57:50 2020 +* Created: Wed Sep 2 12:23:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o22a/sky130_fd_sc_ms__o22a_1.pxi.spice b/cells/o22a/sky130_fd_sc_ms__o22a_1.pxi.spice index bfbfda3..28c8500 100644 --- a/cells/o22a/sky130_fd_sc_ms__o22a_1.pxi.spice +++ b/cells/o22a/sky130_fd_sc_ms__o22a_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22a_1.pxi.spice -* Created: Fri Aug 28 17:57:50 2020 +* Created: Wed Sep 2 12:23:29 2020 * x_PM_SKY130_FD_SC_MS__O22A_1%A_83_260# N_A_83_260#_M1003_d N_A_83_260#_M1007_d + N_A_83_260#_M1002_g N_A_83_260#_M1009_g N_A_83_260#_c_63_n N_A_83_260#_c_108_p
diff --git a/cells/o22a/sky130_fd_sc_ms__o22a_1.spice b/cells/o22a/sky130_fd_sc_ms__o22a_1.spice index d82779b..6937468 100644 --- a/cells/o22a/sky130_fd_sc_ms__o22a_1.spice +++ b/cells/o22a/sky130_fd_sc_ms__o22a_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22a_1.spice -* Created: Fri Aug 28 17:57:50 2020 +* Created: Wed Sep 2 12:23:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o22a/sky130_fd_sc_ms__o22a_2.lvs.report b/cells/o22a/sky130_fd_sc_ms__o22a_2.lvs.report new file mode 100644 index 0000000..130eda1 --- /dev/null +++ b/cells/o22a/sky130_fd_sc_ms__o22a_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o22a_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o22a_2.sp ('sky130_fd_sc_ms__o22a_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o22a/sky130_fd_sc_ms__o22a_2.spice ('sky130_fd_sc_ms__o22a_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:23:32 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o22a_2 sky130_fd_sc_ms__o22a_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o22a_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o22a_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMP2 (4 pins) + 1 1 SPMN_2_2 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMP2 + 1 1 0 0 SPMN_2_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 B2 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o22a/sky130_fd_sc_ms__o22a_2.pex.spice b/cells/o22a/sky130_fd_sc_ms__o22a_2.pex.spice index 8377f85..a997308 100644 --- a/cells/o22a/sky130_fd_sc_ms__o22a_2.pex.spice +++ b/cells/o22a/sky130_fd_sc_ms__o22a_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22a_2.pex.spice -* Created: Fri Aug 28 17:58:20 2020 +* Created: Wed Sep 2 12:23:35 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o22a/sky130_fd_sc_ms__o22a_2.pxi.spice b/cells/o22a/sky130_fd_sc_ms__o22a_2.pxi.spice index bdb2005..a58c661 100644 --- a/cells/o22a/sky130_fd_sc_ms__o22a_2.pxi.spice +++ b/cells/o22a/sky130_fd_sc_ms__o22a_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22a_2.pxi.spice -* Created: Fri Aug 28 17:58:20 2020 +* Created: Wed Sep 2 12:23:35 2020 * x_PM_SKY130_FD_SC_MS__O22A_2%A_82_48# N_A_82_48#_M1003_d N_A_82_48#_M1008_d + N_A_82_48#_M1004_g N_A_82_48#_M1001_g N_A_82_48#_M1009_g N_A_82_48#_M1002_g
diff --git a/cells/o22a/sky130_fd_sc_ms__o22a_2.spice b/cells/o22a/sky130_fd_sc_ms__o22a_2.spice index bad5393..85fbf8b 100644 --- a/cells/o22a/sky130_fd_sc_ms__o22a_2.spice +++ b/cells/o22a/sky130_fd_sc_ms__o22a_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22a_2.spice -* Created: Fri Aug 28 17:58:20 2020 +* Created: Wed Sep 2 12:23:35 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o22a/sky130_fd_sc_ms__o22a_4.lvs.report b/cells/o22a/sky130_fd_sc_ms__o22a_4.lvs.report new file mode 100644 index 0000000..6218531 --- /dev/null +++ b/cells/o22a/sky130_fd_sc_ms__o22a_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o22a_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o22a_4.sp ('sky130_fd_sc_ms__o22a_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o22a/sky130_fd_sc_ms__o22a_4.spice ('sky130_fd_sc_ms__o22a_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:23:39 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o22a_4 sky130_fd_sc_ms__o22a_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o22a_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o22a_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 2 2 SMP2 (4 pins) + 1 1 SPMN_2_2 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 2 2 0 0 SMP2 + 1 1 0 0 SPMN_2_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A2 A1 B2 B1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o22a/sky130_fd_sc_ms__o22a_4.pex.spice b/cells/o22a/sky130_fd_sc_ms__o22a_4.pex.spice index 5313b31..70860f9 100644 --- a/cells/o22a/sky130_fd_sc_ms__o22a_4.pex.spice +++ b/cells/o22a/sky130_fd_sc_ms__o22a_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22a_4.pex.spice -* Created: Fri Aug 28 17:58:31 2020 +* Created: Wed Sep 2 12:23:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o22a/sky130_fd_sc_ms__o22a_4.pxi.spice b/cells/o22a/sky130_fd_sc_ms__o22a_4.pxi.spice index 8fcd5d0..66c82f4 100644 --- a/cells/o22a/sky130_fd_sc_ms__o22a_4.pxi.spice +++ b/cells/o22a/sky130_fd_sc_ms__o22a_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22a_4.pxi.spice -* Created: Fri Aug 28 17:58:31 2020 +* Created: Wed Sep 2 12:23:42 2020 * x_PM_SKY130_FD_SC_MS__O22A_4%A2 N_A2_M1001_g N_A2_M1013_g N_A2_c_114_n + N_A2_M1014_g N_A2_M1003_g A2 N_A2_c_115_n N_A2_c_116_n
diff --git a/cells/o22a/sky130_fd_sc_ms__o22a_4.spice b/cells/o22a/sky130_fd_sc_ms__o22a_4.spice index 69e0d28..01c4154 100644 --- a/cells/o22a/sky130_fd_sc_ms__o22a_4.spice +++ b/cells/o22a/sky130_fd_sc_ms__o22a_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22a_4.spice -* Created: Fri Aug 28 17:58:31 2020 +* Created: Wed Sep 2 12:23:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o22ai/sky130_fd_sc_ms__o22ai_1.lvs.report b/cells/o22ai/sky130_fd_sc_ms__o22ai_1.lvs.report new file mode 100644 index 0000000..5857d5c --- /dev/null +++ b/cells/o22ai/sky130_fd_sc_ms__o22ai_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o22ai_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o22ai_1.sp ('sky130_fd_sc_ms__o22ai_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o22ai/sky130_fd_sc_ms__o22ai_1.spice ('sky130_fd_sc_ms__o22ai_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:23:46 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o22ai_1 sky130_fd_sc_ms__o22ai_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o22ai_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o22ai_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 SMP2 (4 pins) + 1 1 SPMN_2_2 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 SMP2 + 1 1 0 0 SPMN_2_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 B2 A2 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o22ai/sky130_fd_sc_ms__o22ai_1.pex.spice b/cells/o22ai/sky130_fd_sc_ms__o22ai_1.pex.spice index 86e6ab5..259a046 100644 --- a/cells/o22ai/sky130_fd_sc_ms__o22ai_1.pex.spice +++ b/cells/o22ai/sky130_fd_sc_ms__o22ai_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22ai_1.pex.spice -* Created: Fri Aug 28 17:58:40 2020 +* Created: Wed Sep 2 12:23:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o22ai/sky130_fd_sc_ms__o22ai_1.pxi.spice b/cells/o22ai/sky130_fd_sc_ms__o22ai_1.pxi.spice index 2cf4892..edac091 100644 --- a/cells/o22ai/sky130_fd_sc_ms__o22ai_1.pxi.spice +++ b/cells/o22ai/sky130_fd_sc_ms__o22ai_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22ai_1.pxi.spice -* Created: Fri Aug 28 17:58:40 2020 +* Created: Wed Sep 2 12:23:49 2020 * x_PM_SKY130_FD_SC_MS__O22AI_1%B1 N_B1_c_48_n N_B1_M1006_g N_B1_M1005_g B1 + N_B1_c_51_n PM_SKY130_FD_SC_MS__O22AI_1%B1
diff --git a/cells/o22ai/sky130_fd_sc_ms__o22ai_1.spice b/cells/o22ai/sky130_fd_sc_ms__o22ai_1.spice index 8b60ce6..27b01dd 100644 --- a/cells/o22ai/sky130_fd_sc_ms__o22ai_1.spice +++ b/cells/o22ai/sky130_fd_sc_ms__o22ai_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22ai_1.spice -* Created: Fri Aug 28 17:58:40 2020 +* Created: Wed Sep 2 12:23:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o22ai/sky130_fd_sc_ms__o22ai_2.lvs.report b/cells/o22ai/sky130_fd_sc_ms__o22ai_2.lvs.report new file mode 100644 index 0000000..396c566 --- /dev/null +++ b/cells/o22ai/sky130_fd_sc_ms__o22ai_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o22ai_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o22ai_2.sp ('sky130_fd_sc_ms__o22ai_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o22ai/sky130_fd_sc_ms__o22ai_2.spice ('sky130_fd_sc_ms__o22ai_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:23:53 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o22ai_2 sky130_fd_sc_ms__o22ai_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o22ai_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o22ai_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 SMP2 (4 pins) + 1 1 SPMN_2_2 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 SMP2 + 1 1 0 0 SPMN_2_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 B2 A2 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o22ai/sky130_fd_sc_ms__o22ai_2.pex.spice b/cells/o22ai/sky130_fd_sc_ms__o22ai_2.pex.spice index b438b4c..d8b2fc4 100644 --- a/cells/o22ai/sky130_fd_sc_ms__o22ai_2.pex.spice +++ b/cells/o22ai/sky130_fd_sc_ms__o22ai_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22ai_2.pex.spice -* Created: Fri Aug 28 17:58:49 2020 +* Created: Wed Sep 2 12:23:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o22ai/sky130_fd_sc_ms__o22ai_2.pxi.spice b/cells/o22ai/sky130_fd_sc_ms__o22ai_2.pxi.spice index 268bdf4..91960fd 100644 --- a/cells/o22ai/sky130_fd_sc_ms__o22ai_2.pxi.spice +++ b/cells/o22ai/sky130_fd_sc_ms__o22ai_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22ai_2.pxi.spice -* Created: Fri Aug 28 17:58:49 2020 +* Created: Wed Sep 2 12:23:56 2020 * x_PM_SKY130_FD_SC_MS__O22AI_2%B1 N_B1_M1007_g N_B1_M1001_g N_B1_M1015_g + N_B1_M1013_g B1 B1 B1 N_B1_c_83_n PM_SKY130_FD_SC_MS__O22AI_2%B1
diff --git a/cells/o22ai/sky130_fd_sc_ms__o22ai_2.spice b/cells/o22ai/sky130_fd_sc_ms__o22ai_2.spice index bf0b0fa..8b50b6f 100644 --- a/cells/o22ai/sky130_fd_sc_ms__o22ai_2.spice +++ b/cells/o22ai/sky130_fd_sc_ms__o22ai_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22ai_2.spice -* Created: Fri Aug 28 17:58:49 2020 +* Created: Wed Sep 2 12:23:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o22ai/sky130_fd_sc_ms__o22ai_4.lvs.report b/cells/o22ai/sky130_fd_sc_ms__o22ai_4.lvs.report new file mode 100644 index 0000000..618367e --- /dev/null +++ b/cells/o22ai/sky130_fd_sc_ms__o22ai_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o22ai_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o22ai_4.sp ('sky130_fd_sc_ms__o22ai_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o22ai/sky130_fd_sc_ms__o22ai_4.spice ('sky130_fd_sc_ms__o22ai_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:23:59 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o22ai_4 sky130_fd_sc_ms__o22ai_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o22ai_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o22ai_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 2 2 SMP2 (4 pins) + 1 1 SPMN_2_2 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 2 2 0 0 SMP2 + 1 1 0 0 SPMN_2_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 32 layout mos transistors were reduced to 8. + 24 mos transistors were deleted by parallel reduction. + 32 source mos transistors were reduced to 8. + 24 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 B1 B2 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o22ai/sky130_fd_sc_ms__o22ai_4.pex.spice b/cells/o22ai/sky130_fd_sc_ms__o22ai_4.pex.spice index 0a4e439..13e12a1 100644 --- a/cells/o22ai/sky130_fd_sc_ms__o22ai_4.pex.spice +++ b/cells/o22ai/sky130_fd_sc_ms__o22ai_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22ai_4.pex.spice -* Created: Fri Aug 28 17:58:58 2020 +* Created: Wed Sep 2 12:24:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o22ai/sky130_fd_sc_ms__o22ai_4.pxi.spice b/cells/o22ai/sky130_fd_sc_ms__o22ai_4.pxi.spice index 1003c25..d11ee68 100644 --- a/cells/o22ai/sky130_fd_sc_ms__o22ai_4.pxi.spice +++ b/cells/o22ai/sky130_fd_sc_ms__o22ai_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22ai_4.pxi.spice -* Created: Fri Aug 28 17:58:58 2020 +* Created: Wed Sep 2 12:24:02 2020 * x_PM_SKY130_FD_SC_MS__O22AI_4%A1 N_A1_M1000_g N_A1_M1001_g N_A1_M1002_g + N_A1_M1015_g N_A1_M1027_g N_A1_M1003_g N_A1_M1012_g N_A1_M1030_g N_A1_c_132_n
diff --git a/cells/o22ai/sky130_fd_sc_ms__o22ai_4.spice b/cells/o22ai/sky130_fd_sc_ms__o22ai_4.spice index 9f30e69..5d232f7 100644 --- a/cells/o22ai/sky130_fd_sc_ms__o22ai_4.spice +++ b/cells/o22ai/sky130_fd_sc_ms__o22ai_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o22ai_4.spice -* Created: Fri Aug 28 17:58:58 2020 +* Created: Wed Sep 2 12:24:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.lvs.report b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.lvs.report new file mode 100644 index 0000000..4f71b11 --- /dev/null +++ b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o2bb2a_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o2bb2a_1.sp ('sky130_fd_sc_ms__o2bb2a_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.spice ('sky130_fd_sc_ms__o2bb2a_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:24:06 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o2bb2a_1 sky130_fd_sc_ms__o2bb2a_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o2bb2a_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o2bb2a_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1_N A2_N B2 B1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.pex.spice b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.pex.spice index ad16a8c..bdba335 100644 --- a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.pex.spice +++ b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2a_1.pex.spice -* Created: Fri Aug 28 17:59:28 2020 +* Created: Wed Sep 2 12:24:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.pxi.spice b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.pxi.spice index 279c5d8..332d456 100644 --- a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.pxi.spice +++ b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2a_1.pxi.spice -* Created: Fri Aug 28 17:59:28 2020 +* Created: Wed Sep 2 12:24:09 2020 * x_PM_SKY130_FD_SC_MS__O2BB2A_1%A_83_260# N_A_83_260#_M1006_s N_A_83_260#_M1007_d + N_A_83_260#_M1002_g N_A_83_260#_M1001_g N_A_83_260#_c_81_n N_A_83_260#_c_82_n
diff --git a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.spice b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.spice index b28b6f1..1a9a829 100644 --- a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.spice +++ b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2a_1.spice -* Created: Fri Aug 28 17:59:28 2020 +* Created: Wed Sep 2 12:24:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.lvs.report b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.lvs.report new file mode 100644 index 0000000..4f23a6d --- /dev/null +++ b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o2bb2a_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o2bb2a_2.sp ('sky130_fd_sc_ms__o2bb2a_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.spice ('sky130_fd_sc_ms__o2bb2a_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:24:12 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o2bb2a_2 sky130_fd_sc_ms__o2bb2a_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o2bb2a_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o2bb2a_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 B2 A2_N A1_N VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.pex.spice b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.pex.spice index 5f2ac52..e43258f 100644 --- a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.pex.spice +++ b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2a_2.pex.spice -* Created: Fri Aug 28 17:59:38 2020 +* Created: Wed Sep 2 12:24:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.pxi.spice b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.pxi.spice index 5f94807..57af890 100644 --- a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.pxi.spice +++ b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2a_2.pxi.spice -* Created: Fri Aug 28 17:59:38 2020 +* Created: Wed Sep 2 12:24:15 2020 * x_PM_SKY130_FD_SC_MS__O2BB2A_2%B1 N_B1_M1009_g N_B1_c_90_n N_B1_M1006_g B1 + N_B1_c_91_n PM_SKY130_FD_SC_MS__O2BB2A_2%B1
diff --git a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.spice b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.spice index edef67e..a351216 100644 --- a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.spice +++ b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2a_2.spice -* Created: Fri Aug 28 17:59:38 2020 +* Created: Wed Sep 2 12:24:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.lvs.report b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.lvs.report new file mode 100644 index 0000000..a939904 --- /dev/null +++ b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o2bb2a_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o2bb2a_4.sp ('sky130_fd_sc_ms__o2bb2a_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.spice ('sky130_fd_sc_ms__o2bb2a_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:24:19 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o2bb2a_4 sky130_fd_sc_ms__o2bb2a_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o2bb2a_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o2bb2a_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 4 4 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 4 4 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 8. + 12 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 B2 A2_N A1_N VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.pex.spice b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.pex.spice index 6adfc97..dce6c26 100644 --- a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.pex.spice +++ b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2a_4.pex.spice -* Created: Fri Aug 28 17:59:47 2020 +* Created: Wed Sep 2 12:24:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.pxi.spice b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.pxi.spice index 2bb3229..6c5039f 100644 --- a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.pxi.spice +++ b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2a_4.pxi.spice -* Created: Fri Aug 28 17:59:47 2020 +* Created: Wed Sep 2 12:24:22 2020 * x_PM_SKY130_FD_SC_MS__O2BB2A_4%B1 N_B1_M1022_g N_B1_M1000_g N_B1_M1001_g + N_B1_M1023_g B1 B1 N_B1_c_131_n N_B1_c_132_n PM_SKY130_FD_SC_MS__O2BB2A_4%B1
diff --git a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.spice b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.spice index e64657b..db4c74e 100644 --- a/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.spice +++ b/cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2a_4.spice -* Created: Fri Aug 28 17:59:47 2020 +* Created: Wed Sep 2 12:24:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.lvs.report b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.lvs.report new file mode 100644 index 0000000..0938e6b --- /dev/null +++ b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o2bb2ai_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o2bb2ai_1.sp ('sky130_fd_sc_ms__o2bb2ai_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.spice ('sky130_fd_sc_ms__o2bb2ai_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:24:26 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o2bb2ai_1 sky130_fd_sc_ms__o2bb2ai_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o2bb2ai_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o2bb2ai_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.pex.spice b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.pex.spice index 0b8d95e..744ee62 100644 --- a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.pex.spice +++ b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2ai_1.pex.spice -* Created: Fri Aug 28 17:59:56 2020 +* Created: Wed Sep 2 12:24:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.pxi.spice index ccb1665..7fcbd02 100644 --- a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.pxi.spice +++ b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2ai_1.pxi.spice -* Created: Fri Aug 28 17:59:56 2020 +* Created: Wed Sep 2 12:24:29 2020 * x_PM_SKY130_FD_SC_MS__O2BB2AI_1%A1_N N_A1_N_M1009_g N_A1_N_M1005_g N_A1_N_c_65_n + N_A1_N_c_69_n A1_N N_A1_N_c_67_n PM_SKY130_FD_SC_MS__O2BB2AI_1%A1_N
diff --git a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.spice b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.spice index 5772870..bac1cca 100644 --- a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.spice +++ b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2ai_1.spice -* Created: Fri Aug 28 17:59:56 2020 +* Created: Wed Sep 2 12:24:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.lvs.report b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.lvs.report new file mode 100644 index 0000000..e1e2791 --- /dev/null +++ b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o2bb2ai_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o2bb2ai_2.sp ('sky130_fd_sc_ms__o2bb2ai_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.spice ('sky130_fd_sc_ms__o2bb2ai_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:24:32 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o2bb2ai_2 sky130_fd_sc_ms__o2bb2ai_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o2bb2ai_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o2bb2ai_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1_N A2_N B1 B2 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.pex.spice b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.pex.spice index 068072b..23f4584 100644 --- a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.pex.spice +++ b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2ai_2.pex.spice -* Created: Fri Aug 28 18:00:05 2020 +* Created: Wed Sep 2 12:24:35 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.pxi.spice index 9f09445..c0c6efe 100644 --- a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.pxi.spice +++ b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2ai_2.pxi.spice -* Created: Fri Aug 28 18:00:05 2020 +* Created: Wed Sep 2 12:24:35 2020 * x_PM_SKY130_FD_SC_MS__O2BB2AI_2%A1_N N_A1_N_M1001_g N_A1_N_M1007_g + N_A1_N_c_104_n N_A1_N_M1012_g N_A1_N_c_105_n N_A1_N_M1014_g N_A1_N_c_106_n
diff --git a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.spice b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.spice index 00341d9..28bd0f0 100644 --- a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.spice +++ b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2ai_2.spice -* Created: Fri Aug 28 18:00:05 2020 +* Created: Wed Sep 2 12:24:35 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.lvs.report b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.lvs.report new file mode 100644 index 0000000..ac65136 --- /dev/null +++ b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o2bb2ai_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o2bb2ai_4.sp ('sky130_fd_sc_ms__o2bb2ai_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.spice ('sky130_fd_sc_ms__o2bb2ai_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:24:39 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o2bb2ai_4 sky130_fd_sc_ms__o2bb2ai_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o2bb2ai_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o2bb2ai_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 3 3 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 40 layout mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + 40 source mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.pex.spice b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.pex.spice index 7b3cf3a..da0ecbd 100644 --- a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.pex.spice +++ b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2ai_4.pex.spice -* Created: Fri Aug 28 18:00:35 2020 +* Created: Wed Sep 2 12:24:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.pxi.spice index 1734beb..f10ad3c 100644 --- a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.pxi.spice +++ b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2ai_4.pxi.spice -* Created: Fri Aug 28 18:00:35 2020 +* Created: Wed Sep 2 12:24:42 2020 * x_PM_SKY130_FD_SC_MS__O2BB2AI_4%A1_N N_A1_N_M1026_g N_A1_N_M1012_g + N_A1_N_M1032_g N_A1_N_M1027_g N_A1_N_M1033_g N_A1_N_M1030_g N_A1_N_M1034_g
diff --git a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.spice b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.spice index 9198758..085ee34 100644 --- a/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.spice +++ b/cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o2bb2ai_4.spice -* Created: Fri Aug 28 18:00:35 2020 +* Created: Wed Sep 2 12:24:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o311a/sky130_fd_sc_ms__o311a_1.lvs.report b/cells/o311a/sky130_fd_sc_ms__o311a_1.lvs.report new file mode 100644 index 0000000..0cd213c --- /dev/null +++ b/cells/o311a/sky130_fd_sc_ms__o311a_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o311a_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o311a_1.sp ('sky130_fd_sc_ms__o311a_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o311a/sky130_fd_sc_ms__o311a_1.spice ('sky130_fd_sc_ms__o311a_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:24:45 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o311a_1 sky130_fd_sc_ms__o311a_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o311a_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o311a_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_1_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 A2 A3 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o311a/sky130_fd_sc_ms__o311a_1.pex.spice b/cells/o311a/sky130_fd_sc_ms__o311a_1.pex.spice index 6aa2d7a..00c7b13 100644 --- a/cells/o311a/sky130_fd_sc_ms__o311a_1.pex.spice +++ b/cells/o311a/sky130_fd_sc_ms__o311a_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311a_1.pex.spice -* Created: Fri Aug 28 18:00:45 2020 +* Created: Wed Sep 2 12:24:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o311a/sky130_fd_sc_ms__o311a_1.pxi.spice b/cells/o311a/sky130_fd_sc_ms__o311a_1.pxi.spice index 691d14c..98909c8 100644 --- a/cells/o311a/sky130_fd_sc_ms__o311a_1.pxi.spice +++ b/cells/o311a/sky130_fd_sc_ms__o311a_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311a_1.pxi.spice -* Created: Fri Aug 28 18:00:45 2020 +* Created: Wed Sep 2 12:24:49 2020 * x_PM_SKY130_FD_SC_MS__O311A_1%C1 N_C1_M1010_g N_C1_M1004_g C1 N_C1_c_81_n + PM_SKY130_FD_SC_MS__O311A_1%C1
diff --git a/cells/o311a/sky130_fd_sc_ms__o311a_1.spice b/cells/o311a/sky130_fd_sc_ms__o311a_1.spice index 0fe4ea7..43c5a04 100644 --- a/cells/o311a/sky130_fd_sc_ms__o311a_1.spice +++ b/cells/o311a/sky130_fd_sc_ms__o311a_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311a_1.spice -* Created: Fri Aug 28 18:00:45 2020 +* Created: Wed Sep 2 12:24:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o311a/sky130_fd_sc_ms__o311a_2.lvs.report b/cells/o311a/sky130_fd_sc_ms__o311a_2.lvs.report new file mode 100644 index 0000000..97fdcf8 --- /dev/null +++ b/cells/o311a/sky130_fd_sc_ms__o311a_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o311a_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o311a_2.sp ('sky130_fd_sc_ms__o311a_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o311a/sky130_fd_sc_ms__o311a_2.spice ('sky130_fd_sc_ms__o311a_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:24:53 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o311a_2 sky130_fd_sc_ms__o311a_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o311a_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o311a_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_1_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 A3 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o311a/sky130_fd_sc_ms__o311a_2.pex.spice b/cells/o311a/sky130_fd_sc_ms__o311a_2.pex.spice index 6f13f0e..6e67927 100644 --- a/cells/o311a/sky130_fd_sc_ms__o311a_2.pex.spice +++ b/cells/o311a/sky130_fd_sc_ms__o311a_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311a_2.pex.spice -* Created: Fri Aug 28 18:00:54 2020 +* Created: Wed Sep 2 12:24:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o311a/sky130_fd_sc_ms__o311a_2.pxi.spice b/cells/o311a/sky130_fd_sc_ms__o311a_2.pxi.spice index 90b0c8c..c485800 100644 --- a/cells/o311a/sky130_fd_sc_ms__o311a_2.pxi.spice +++ b/cells/o311a/sky130_fd_sc_ms__o311a_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311a_2.pxi.spice -* Created: Fri Aug 28 18:00:54 2020 +* Created: Wed Sep 2 12:24:56 2020 * x_PM_SKY130_FD_SC_MS__O311A_2%C1 N_C1_c_75_n N_C1_M1001_g N_C1_M1007_g + N_C1_c_77_n N_C1_c_78_n C1 PM_SKY130_FD_SC_MS__O311A_2%C1
diff --git a/cells/o311a/sky130_fd_sc_ms__o311a_2.spice b/cells/o311a/sky130_fd_sc_ms__o311a_2.spice index 8914638..8a809ec 100644 --- a/cells/o311a/sky130_fd_sc_ms__o311a_2.spice +++ b/cells/o311a/sky130_fd_sc_ms__o311a_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311a_2.spice -* Created: Fri Aug 28 18:00:54 2020 +* Created: Wed Sep 2 12:24:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o311a/sky130_fd_sc_ms__o311a_4.lvs.report b/cells/o311a/sky130_fd_sc_ms__o311a_4.lvs.report new file mode 100644 index 0000000..e32d43f --- /dev/null +++ b/cells/o311a/sky130_fd_sc_ms__o311a_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o311a_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o311a_4.sp ('sky130_fd_sc_ms__o311a_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o311a/sky130_fd_sc_ms__o311a_4.spice ('sky130_fd_sc_ms__o311a_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:24:59 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o311a_4 sky130_fd_sc_ms__o311a_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o311a_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o311a_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_1_1 (7 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_1_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 C1 A3 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o311a/sky130_fd_sc_ms__o311a_4.pex.spice b/cells/o311a/sky130_fd_sc_ms__o311a_4.pex.spice index 19b7064..e1b96fb 100644 --- a/cells/o311a/sky130_fd_sc_ms__o311a_4.pex.spice +++ b/cells/o311a/sky130_fd_sc_ms__o311a_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311a_4.pex.spice -* Created: Fri Aug 28 18:01:03 2020 +* Created: Wed Sep 2 12:25:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o311a/sky130_fd_sc_ms__o311a_4.pxi.spice b/cells/o311a/sky130_fd_sc_ms__o311a_4.pxi.spice index 680e472..9d483fb 100644 --- a/cells/o311a/sky130_fd_sc_ms__o311a_4.pxi.spice +++ b/cells/o311a/sky130_fd_sc_ms__o311a_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311a_4.pxi.spice -* Created: Fri Aug 28 18:01:03 2020 +* Created: Wed Sep 2 12:25:02 2020 * x_PM_SKY130_FD_SC_MS__O311A_4%A_83_244# N_A_83_244#_M1017_d N_A_83_244#_M1003_d + N_A_83_244#_M1019_s N_A_83_244#_M1008_d N_A_83_244#_M1009_g
diff --git a/cells/o311a/sky130_fd_sc_ms__o311a_4.spice b/cells/o311a/sky130_fd_sc_ms__o311a_4.spice index 5f80034..895eb6f 100644 --- a/cells/o311a/sky130_fd_sc_ms__o311a_4.spice +++ b/cells/o311a/sky130_fd_sc_ms__o311a_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311a_4.spice -* Created: Fri Aug 28 18:01:03 2020 +* Created: Wed Sep 2 12:25:02 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o311ai/sky130_fd_sc_ms__o311ai_1.lvs.report b/cells/o311ai/sky130_fd_sc_ms__o311ai_1.lvs.report new file mode 100644 index 0000000..e370dd8 --- /dev/null +++ b/cells/o311ai/sky130_fd_sc_ms__o311ai_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o311ai_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o311ai_1.sp ('sky130_fd_sc_ms__o311ai_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o311ai/sky130_fd_sc_ms__o311ai_1.spice ('sky130_fd_sc_ms__o311ai_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:25:06 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o311ai_1 sky130_fd_sc_ms__o311ai_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o311ai_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o311ai_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 2 2 MP (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_1_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 A3 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o311ai/sky130_fd_sc_ms__o311ai_1.pex.spice b/cells/o311ai/sky130_fd_sc_ms__o311ai_1.pex.spice index 39b2972..0ccb19a 100644 --- a/cells/o311ai/sky130_fd_sc_ms__o311ai_1.pex.spice +++ b/cells/o311ai/sky130_fd_sc_ms__o311ai_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311ai_1.pex.spice -* Created: Fri Aug 28 18:01:12 2020 +* Created: Wed Sep 2 12:25:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o311ai/sky130_fd_sc_ms__o311ai_1.pxi.spice b/cells/o311ai/sky130_fd_sc_ms__o311ai_1.pxi.spice index caa8873..82c7597 100644 --- a/cells/o311ai/sky130_fd_sc_ms__o311ai_1.pxi.spice +++ b/cells/o311ai/sky130_fd_sc_ms__o311ai_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311ai_1.pxi.spice -* Created: Fri Aug 28 18:01:12 2020 +* Created: Wed Sep 2 12:25:09 2020 * x_PM_SKY130_FD_SC_MS__O311AI_1%A1 N_A1_M1003_g N_A1_M1002_g A1 N_A1_c_55_n + N_A1_c_56_n PM_SKY130_FD_SC_MS__O311AI_1%A1
diff --git a/cells/o311ai/sky130_fd_sc_ms__o311ai_1.spice b/cells/o311ai/sky130_fd_sc_ms__o311ai_1.spice index c857b12..2cc8954 100644 --- a/cells/o311ai/sky130_fd_sc_ms__o311ai_1.spice +++ b/cells/o311ai/sky130_fd_sc_ms__o311ai_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311ai_1.spice -* Created: Fri Aug 28 18:01:12 2020 +* Created: Wed Sep 2 12:25:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o311ai/sky130_fd_sc_ms__o311ai_2.lvs.report b/cells/o311ai/sky130_fd_sc_ms__o311ai_2.lvs.report new file mode 100644 index 0000000..b86bfd0 --- /dev/null +++ b/cells/o311ai/sky130_fd_sc_ms__o311ai_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o311ai_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o311ai_2.sp ('sky130_fd_sc_ms__o311ai_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o311ai/sky130_fd_sc_ms__o311ai_2.spice ('sky130_fd_sc_ms__o311ai_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:25:12 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o311ai_2 sky130_fd_sc_ms__o311ai_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o311ai_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o311ai_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 2 2 MP (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_1_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 A3 B1 C1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o311ai/sky130_fd_sc_ms__o311ai_2.pex.spice b/cells/o311ai/sky130_fd_sc_ms__o311ai_2.pex.spice index f92d10b..f912d97 100644 --- a/cells/o311ai/sky130_fd_sc_ms__o311ai_2.pex.spice +++ b/cells/o311ai/sky130_fd_sc_ms__o311ai_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311ai_2.pex.spice -* Created: Fri Aug 28 18:01:42 2020 +* Created: Wed Sep 2 12:25:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o311ai/sky130_fd_sc_ms__o311ai_2.pxi.spice b/cells/o311ai/sky130_fd_sc_ms__o311ai_2.pxi.spice index a25bc44..94b77c3 100644 --- a/cells/o311ai/sky130_fd_sc_ms__o311ai_2.pxi.spice +++ b/cells/o311ai/sky130_fd_sc_ms__o311ai_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311ai_2.pxi.spice -* Created: Fri Aug 28 18:01:42 2020 +* Created: Wed Sep 2 12:25:15 2020 * x_PM_SKY130_FD_SC_MS__O311AI_2%A1 N_A1_M1003_g N_A1_M1005_g N_A1_M1014_g + N_A1_M1018_g A1 A1 N_A1_c_103_n PM_SKY130_FD_SC_MS__O311AI_2%A1
diff --git a/cells/o311ai/sky130_fd_sc_ms__o311ai_2.spice b/cells/o311ai/sky130_fd_sc_ms__o311ai_2.spice index fb53cfa..cc78354 100644 --- a/cells/o311ai/sky130_fd_sc_ms__o311ai_2.spice +++ b/cells/o311ai/sky130_fd_sc_ms__o311ai_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311ai_2.spice -* Created: Fri Aug 28 18:01:42 2020 +* Created: Wed Sep 2 12:25:15 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o311ai/sky130_fd_sc_ms__o311ai_4.lvs.report b/cells/o311ai/sky130_fd_sc_ms__o311ai_4.lvs.report new file mode 100644 index 0000000..48ab55a --- /dev/null +++ b/cells/o311ai/sky130_fd_sc_ms__o311ai_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o311ai_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o311ai_4.sp ('sky130_fd_sc_ms__o311ai_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o311ai/sky130_fd_sc_ms__o311ai_4.spice ('sky130_fd_sc_ms__o311ai_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:25:19 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o311ai_4 sky130_fd_sc_ms__o311ai_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o311ai_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o311ai_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 20 20 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 37 36 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 2 2 MP (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_1_1 (7 pins) + ------ ------ + Total Inst: 4 4 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_1_1 + ------- ------- --------- --------- + Total Inst: 4 4 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 36 layout mos transistors were reduced to 10. + 26 mos transistors were deleted by parallel reduction. + 36 source mos transistors were reduced to 10. + 26 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C1 B1 A3 A2 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o311ai/sky130_fd_sc_ms__o311ai_4.pex.spice b/cells/o311ai/sky130_fd_sc_ms__o311ai_4.pex.spice index 9f90cba..b1b4a26 100644 --- a/cells/o311ai/sky130_fd_sc_ms__o311ai_4.pex.spice +++ b/cells/o311ai/sky130_fd_sc_ms__o311ai_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311ai_4.pex.spice -* Created: Fri Aug 28 18:01:52 2020 +* Created: Wed Sep 2 12:25:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o311ai/sky130_fd_sc_ms__o311ai_4.pxi.spice b/cells/o311ai/sky130_fd_sc_ms__o311ai_4.pxi.spice index 64ce8a8..ab9f2a7 100644 --- a/cells/o311ai/sky130_fd_sc_ms__o311ai_4.pxi.spice +++ b/cells/o311ai/sky130_fd_sc_ms__o311ai_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311ai_4.pxi.spice -* Created: Fri Aug 28 18:01:52 2020 +* Created: Wed Sep 2 12:25:22 2020 * x_PM_SKY130_FD_SC_MS__O311AI_4%C1 N_C1_M1010_g N_C1_c_149_n N_C1_M1005_g + N_C1_c_150_n N_C1_M1019_g N_C1_M1021_g N_C1_c_152_n N_C1_M1020_g N_C1_c_153_n
diff --git a/cells/o311ai/sky130_fd_sc_ms__o311ai_4.spice b/cells/o311ai/sky130_fd_sc_ms__o311ai_4.spice index b23601a..f2379fd 100644 --- a/cells/o311ai/sky130_fd_sc_ms__o311ai_4.spice +++ b/cells/o311ai/sky130_fd_sc_ms__o311ai_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o311ai_4.spice -* Created: Fri Aug 28 18:01:52 2020 +* Created: Wed Sep 2 12:25:22 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o31a/sky130_fd_sc_ms__o31a_1.lvs.report b/cells/o31a/sky130_fd_sc_ms__o31a_1.lvs.report new file mode 100644 index 0000000..55e3396 --- /dev/null +++ b/cells/o31a/sky130_fd_sc_ms__o31a_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o31a_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o31a_1.sp ('sky130_fd_sc_ms__o31a_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o31a/sky130_fd_sc_ms__o31a_1.spice ('sky130_fd_sc_ms__o31a_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:25:26 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o31a_1 sky130_fd_sc_ms__o31a_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o31a_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o31a_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_1 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 A3 B1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o31a/sky130_fd_sc_ms__o31a_1.pex.spice b/cells/o31a/sky130_fd_sc_ms__o31a_1.pex.spice index 10c8a16..eb7d058 100644 --- a/cells/o31a/sky130_fd_sc_ms__o31a_1.pex.spice +++ b/cells/o31a/sky130_fd_sc_ms__o31a_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31a_1.pex.spice -* Created: Fri Aug 28 18:02:01 2020 +* Created: Wed Sep 2 12:25:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o31a/sky130_fd_sc_ms__o31a_1.pxi.spice b/cells/o31a/sky130_fd_sc_ms__o31a_1.pxi.spice index b00a4aa..8615dd9 100644 --- a/cells/o31a/sky130_fd_sc_ms__o31a_1.pxi.spice +++ b/cells/o31a/sky130_fd_sc_ms__o31a_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31a_1.pxi.spice -* Created: Fri Aug 28 18:02:01 2020 +* Created: Wed Sep 2 12:25:29 2020 * x_PM_SKY130_FD_SC_MS__O31A_1%A_84_48# N_A_84_48#_M1001_d N_A_84_48#_M1002_d + N_A_84_48#_M1008_g N_A_84_48#_M1006_g N_A_84_48#_c_67_n N_A_84_48#_c_83_p
diff --git a/cells/o31a/sky130_fd_sc_ms__o31a_1.spice b/cells/o31a/sky130_fd_sc_ms__o31a_1.spice index 8812942..8a0747a 100644 --- a/cells/o31a/sky130_fd_sc_ms__o31a_1.spice +++ b/cells/o31a/sky130_fd_sc_ms__o31a_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31a_1.spice -* Created: Fri Aug 28 18:02:01 2020 +* Created: Wed Sep 2 12:25:29 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o31a/sky130_fd_sc_ms__o31a_2.lvs.report b/cells/o31a/sky130_fd_sc_ms__o31a_2.lvs.report new file mode 100644 index 0000000..333c056 --- /dev/null +++ b/cells/o31a/sky130_fd_sc_ms__o31a_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o31a_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o31a_2.sp ('sky130_fd_sc_ms__o31a_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o31a/sky130_fd_sc_ms__o31a_2.spice ('sky130_fd_sc_ms__o31a_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:25:32 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o31a_2 sky130_fd_sc_ms__o31a_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o31a_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o31a_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_1 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 A3 B1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o31a/sky130_fd_sc_ms__o31a_2.pex.spice b/cells/o31a/sky130_fd_sc_ms__o31a_2.pex.spice index 23fa28d..1d55f9d 100644 --- a/cells/o31a/sky130_fd_sc_ms__o31a_2.pex.spice +++ b/cells/o31a/sky130_fd_sc_ms__o31a_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31a_2.pex.spice -* Created: Fri Aug 28 18:02:10 2020 +* Created: Wed Sep 2 12:25:35 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o31a/sky130_fd_sc_ms__o31a_2.pxi.spice b/cells/o31a/sky130_fd_sc_ms__o31a_2.pxi.spice index a435f05..488f354 100644 --- a/cells/o31a/sky130_fd_sc_ms__o31a_2.pxi.spice +++ b/cells/o31a/sky130_fd_sc_ms__o31a_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31a_2.pxi.spice -* Created: Fri Aug 28 18:02:10 2020 +* Created: Wed Sep 2 12:25:35 2020 * x_PM_SKY130_FD_SC_MS__O31A_2%A_55_264# N_A_55_264#_M1003_d N_A_55_264#_M1000_d + N_A_55_264#_M1004_g N_A_55_264#_M1005_g N_A_55_264#_c_72_n N_A_55_264#_M1006_g
diff --git a/cells/o31a/sky130_fd_sc_ms__o31a_2.spice b/cells/o31a/sky130_fd_sc_ms__o31a_2.spice index 31f131a..95b23df 100644 --- a/cells/o31a/sky130_fd_sc_ms__o31a_2.spice +++ b/cells/o31a/sky130_fd_sc_ms__o31a_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31a_2.spice -* Created: Fri Aug 28 18:02:10 2020 +* Created: Wed Sep 2 12:25:35 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o31a/sky130_fd_sc_ms__o31a_4.lvs.report b/cells/o31a/sky130_fd_sc_ms__o31a_4.lvs.report new file mode 100644 index 0000000..9256924 --- /dev/null +++ b/cells/o31a/sky130_fd_sc_ms__o31a_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o31a_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o31a_4.sp ('sky130_fd_sc_ms__o31a_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o31a/sky130_fd_sc_ms__o31a_4.spice ('sky130_fd_sc_ms__o31a_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:25:39 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o31a_4 sky130_fd_sc_ms__o31a_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o31a_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o31a_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_1 (6 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 24 layout mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + 24 source mos transistors were reduced to 10. + 14 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A3 A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o31a/sky130_fd_sc_ms__o31a_4.pex.spice b/cells/o31a/sky130_fd_sc_ms__o31a_4.pex.spice index ccb7786..0b4d0d6 100644 --- a/cells/o31a/sky130_fd_sc_ms__o31a_4.pex.spice +++ b/cells/o31a/sky130_fd_sc_ms__o31a_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31a_4.pex.spice -* Created: Fri Aug 28 18:02:19 2020 +* Created: Wed Sep 2 12:25:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o31a/sky130_fd_sc_ms__o31a_4.pxi.spice b/cells/o31a/sky130_fd_sc_ms__o31a_4.pxi.spice index beabcdc..104a44c 100644 --- a/cells/o31a/sky130_fd_sc_ms__o31a_4.pxi.spice +++ b/cells/o31a/sky130_fd_sc_ms__o31a_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31a_4.pxi.spice -* Created: Fri Aug 28 18:02:19 2020 +* Created: Wed Sep 2 12:25:42 2020 * x_PM_SKY130_FD_SC_MS__O31A_4%A_86_260# N_A_86_260#_M1009_s N_A_86_260#_M1002_d + N_A_86_260#_M1012_d N_A_86_260#_M1007_g N_A_86_260#_M1003_g
diff --git a/cells/o31a/sky130_fd_sc_ms__o31a_4.spice b/cells/o31a/sky130_fd_sc_ms__o31a_4.spice index 7a2c2c8..6215fb3 100644 --- a/cells/o31a/sky130_fd_sc_ms__o31a_4.spice +++ b/cells/o31a/sky130_fd_sc_ms__o31a_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31a_4.spice -* Created: Fri Aug 28 18:02:19 2020 +* Created: Wed Sep 2 12:25:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o31ai/sky130_fd_sc_ms__o31ai_1.lvs.report b/cells/o31ai/sky130_fd_sc_ms__o31ai_1.lvs.report new file mode 100644 index 0000000..f8ee0e3 --- /dev/null +++ b/cells/o31ai/sky130_fd_sc_ms__o31ai_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o31ai_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o31ai_1.sp ('sky130_fd_sc_ms__o31ai_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o31ai/sky130_fd_sc_ms__o31ai_1.spice ('sky130_fd_sc_ms__o31ai_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:25:46 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o31ai_1 sky130_fd_sc_ms__o31ai_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o31ai_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o31ai_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 1 1 MP (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_1 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 A3 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o31ai/sky130_fd_sc_ms__o31ai_1.pex.spice b/cells/o31ai/sky130_fd_sc_ms__o31ai_1.pex.spice index a56003c..fc550d1 100644 --- a/cells/o31ai/sky130_fd_sc_ms__o31ai_1.pex.spice +++ b/cells/o31ai/sky130_fd_sc_ms__o31ai_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31ai_1.pex.spice -* Created: Fri Aug 28 18:02:49 2020 +* Created: Wed Sep 2 12:25:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o31ai/sky130_fd_sc_ms__o31ai_1.pxi.spice b/cells/o31ai/sky130_fd_sc_ms__o31ai_1.pxi.spice index 7a97354..5924476 100644 --- a/cells/o31ai/sky130_fd_sc_ms__o31ai_1.pxi.spice +++ b/cells/o31ai/sky130_fd_sc_ms__o31ai_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31ai_1.pxi.spice -* Created: Fri Aug 28 18:02:49 2020 +* Created: Wed Sep 2 12:25:49 2020 * x_PM_SKY130_FD_SC_MS__O31AI_1%A1 N_A1_c_46_n N_A1_M1005_g N_A1_M1003_g A1 + N_A1_c_49_n PM_SKY130_FD_SC_MS__O31AI_1%A1
diff --git a/cells/o31ai/sky130_fd_sc_ms__o31ai_1.spice b/cells/o31ai/sky130_fd_sc_ms__o31ai_1.spice index cc69d23..e9dd008 100644 --- a/cells/o31ai/sky130_fd_sc_ms__o31ai_1.spice +++ b/cells/o31ai/sky130_fd_sc_ms__o31ai_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31ai_1.spice -* Created: Fri Aug 28 18:02:49 2020 +* Created: Wed Sep 2 12:25:49 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o31ai/sky130_fd_sc_ms__o31ai_2.lvs.report b/cells/o31ai/sky130_fd_sc_ms__o31ai_2.lvs.report new file mode 100644 index 0000000..a75a64f --- /dev/null +++ b/cells/o31ai/sky130_fd_sc_ms__o31ai_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o31ai_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o31ai_2.sp ('sky130_fd_sc_ms__o31ai_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o31ai/sky130_fd_sc_ms__o31ai_2.spice ('sky130_fd_sc_ms__o31ai_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:25:53 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o31ai_2 sky130_fd_sc_ms__o31ai_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o31ai_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o31ai_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 1 1 MP (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_1 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 A3 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o31ai/sky130_fd_sc_ms__o31ai_2.pex.spice b/cells/o31ai/sky130_fd_sc_ms__o31ai_2.pex.spice index a55a9c3..af26b14 100644 --- a/cells/o31ai/sky130_fd_sc_ms__o31ai_2.pex.spice +++ b/cells/o31ai/sky130_fd_sc_ms__o31ai_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31ai_2.pex.spice -* Created: Fri Aug 28 18:03:00 2020 +* Created: Wed Sep 2 12:25:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o31ai/sky130_fd_sc_ms__o31ai_2.pxi.spice b/cells/o31ai/sky130_fd_sc_ms__o31ai_2.pxi.spice index 800c6b7..b8921c2 100644 --- a/cells/o31ai/sky130_fd_sc_ms__o31ai_2.pxi.spice +++ b/cells/o31ai/sky130_fd_sc_ms__o31ai_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31ai_2.pxi.spice -* Created: Fri Aug 28 18:03:00 2020 +* Created: Wed Sep 2 12:25:56 2020 * x_PM_SKY130_FD_SC_MS__O31AI_2%A1 N_A1_M1013_g N_A1_M1000_g N_A1_M1001_g + N_A1_c_82_n N_A1_M1015_g A1 A1 A1 N_A1_c_84_n PM_SKY130_FD_SC_MS__O31AI_2%A1
diff --git a/cells/o31ai/sky130_fd_sc_ms__o31ai_2.spice b/cells/o31ai/sky130_fd_sc_ms__o31ai_2.spice index 21ccdae..56c539b 100644 --- a/cells/o31ai/sky130_fd_sc_ms__o31ai_2.spice +++ b/cells/o31ai/sky130_fd_sc_ms__o31ai_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31ai_2.spice -* Created: Fri Aug 28 18:03:00 2020 +* Created: Wed Sep 2 12:25:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o31ai/sky130_fd_sc_ms__o31ai_4.lvs.report b/cells/o31ai/sky130_fd_sc_ms__o31ai_4.lvs.report new file mode 100644 index 0000000..281cd68 --- /dev/null +++ b/cells/o31ai/sky130_fd_sc_ms__o31ai_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o31ai_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o31ai_4.sp ('sky130_fd_sc_ms__o31ai_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o31ai/sky130_fd_sc_ms__o31ai_4.spice ('sky130_fd_sc_ms__o31ai_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:25:59 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o31ai_4 sky130_fd_sc_ms__o31ai_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o31ai_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o31ai_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 16 16 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 31 30 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 9 9 + + Instances: 1 1 MP (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_1 (6 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 9 9 0 0 + + Instances: 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 30 layout mos transistors were reduced to 8. + 22 mos transistors were deleted by parallel reduction. + 30 source mos transistors were reduced to 8. + 22 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 A3 B1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o31ai/sky130_fd_sc_ms__o31ai_4.pex.spice b/cells/o31ai/sky130_fd_sc_ms__o31ai_4.pex.spice index e4b14b7..3a64230 100644 --- a/cells/o31ai/sky130_fd_sc_ms__o31ai_4.pex.spice +++ b/cells/o31ai/sky130_fd_sc_ms__o31ai_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31ai_4.pex.spice -* Created: Fri Aug 28 18:03:09 2020 +* Created: Wed Sep 2 12:26:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o31ai/sky130_fd_sc_ms__o31ai_4.pxi.spice b/cells/o31ai/sky130_fd_sc_ms__o31ai_4.pxi.spice index 760a04a..507176d 100644 --- a/cells/o31ai/sky130_fd_sc_ms__o31ai_4.pxi.spice +++ b/cells/o31ai/sky130_fd_sc_ms__o31ai_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31ai_4.pxi.spice -* Created: Fri Aug 28 18:03:09 2020 +* Created: Wed Sep 2 12:26:03 2020 * x_PM_SKY130_FD_SC_MS__O31AI_4%A1 N_A1_M1000_g N_A1_M1001_g N_A1_M1002_g + N_A1_M1007_g N_A1_M1005_g N_A1_M1018_g N_A1_c_135_n N_A1_M1006_g N_A1_M1027_g
diff --git a/cells/o31ai/sky130_fd_sc_ms__o31ai_4.spice b/cells/o31ai/sky130_fd_sc_ms__o31ai_4.spice index 949fadb..701a3f7 100644 --- a/cells/o31ai/sky130_fd_sc_ms__o31ai_4.spice +++ b/cells/o31ai/sky130_fd_sc_ms__o31ai_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o31ai_4.spice -* Created: Fri Aug 28 18:03:09 2020 +* Created: Wed Sep 2 12:26:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o32a/sky130_fd_sc_ms__o32a_1.lvs.report b/cells/o32a/sky130_fd_sc_ms__o32a_1.lvs.report new file mode 100644 index 0000000..3daa42b --- /dev/null +++ b/cells/o32a/sky130_fd_sc_ms__o32a_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o32a_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o32a_1.sp ('sky130_fd_sc_ms__o32a_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o32a/sky130_fd_sc_ms__o32a_1.spice ('sky130_fd_sc_ms__o32a_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:26:06 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o32a_1 sky130_fd_sc_ms__o32a_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o32a_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o32a_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_2 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 A3 B2 B1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o32a/sky130_fd_sc_ms__o32a_1.pex.spice b/cells/o32a/sky130_fd_sc_ms__o32a_1.pex.spice index 0858f1e..0adcef8 100644 --- a/cells/o32a/sky130_fd_sc_ms__o32a_1.pex.spice +++ b/cells/o32a/sky130_fd_sc_ms__o32a_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32a_1.pex.spice -* Created: Fri Aug 28 18:03:18 2020 +* Created: Wed Sep 2 12:26:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o32a/sky130_fd_sc_ms__o32a_1.pxi.spice b/cells/o32a/sky130_fd_sc_ms__o32a_1.pxi.spice index b1872b5..2909743 100644 --- a/cells/o32a/sky130_fd_sc_ms__o32a_1.pxi.spice +++ b/cells/o32a/sky130_fd_sc_ms__o32a_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32a_1.pxi.spice -* Created: Fri Aug 28 18:03:18 2020 +* Created: Wed Sep 2 12:26:10 2020 * x_PM_SKY130_FD_SC_MS__O32A_1%A_83_264# N_A_83_264#_M1006_d N_A_83_264#_M1011_d + N_A_83_264#_M1003_g N_A_83_264#_M1007_g N_A_83_264#_c_74_n N_A_83_264#_c_85_p
diff --git a/cells/o32a/sky130_fd_sc_ms__o32a_1.spice b/cells/o32a/sky130_fd_sc_ms__o32a_1.spice index d2444bb..c69c2d7 100644 --- a/cells/o32a/sky130_fd_sc_ms__o32a_1.spice +++ b/cells/o32a/sky130_fd_sc_ms__o32a_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32a_1.spice -* Created: Fri Aug 28 18:03:18 2020 +* Created: Wed Sep 2 12:26:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o32a/sky130_fd_sc_ms__o32a_2.lvs.report b/cells/o32a/sky130_fd_sc_ms__o32a_2.lvs.report new file mode 100644 index 0000000..ba0d7d7 --- /dev/null +++ b/cells/o32a/sky130_fd_sc_ms__o32a_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o32a_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o32a_2.sp ('sky130_fd_sc_ms__o32a_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o32a/sky130_fd_sc_ms__o32a_2.spice ('sky130_fd_sc_ms__o32a_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:26:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o32a_2 sky130_fd_sc_ms__o32a_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o32a_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o32a_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_2 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 A3 B2 B1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 1 sec
diff --git a/cells/o32a/sky130_fd_sc_ms__o32a_2.pex.spice b/cells/o32a/sky130_fd_sc_ms__o32a_2.pex.spice index d33614f..759e638 100644 --- a/cells/o32a/sky130_fd_sc_ms__o32a_2.pex.spice +++ b/cells/o32a/sky130_fd_sc_ms__o32a_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32a_2.pex.spice -* Created: Fri Aug 28 18:03:27 2020 +* Created: Wed Sep 2 12:26:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o32a/sky130_fd_sc_ms__o32a_2.pxi.spice b/cells/o32a/sky130_fd_sc_ms__o32a_2.pxi.spice index 27cf8f3..a57b44b 100644 --- a/cells/o32a/sky130_fd_sc_ms__o32a_2.pxi.spice +++ b/cells/o32a/sky130_fd_sc_ms__o32a_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32a_2.pxi.spice -* Created: Fri Aug 28 18:03:27 2020 +* Created: Wed Sep 2 12:26:16 2020 * x_PM_SKY130_FD_SC_MS__O32A_2%A_83_264# N_A_83_264#_M1001_d N_A_83_264#_M1006_d + N_A_83_264#_M1004_g N_A_83_264#_M1010_g N_A_83_264#_M1005_g
diff --git a/cells/o32a/sky130_fd_sc_ms__o32a_2.spice b/cells/o32a/sky130_fd_sc_ms__o32a_2.spice index 5c197ac..928c2ee 100644 --- a/cells/o32a/sky130_fd_sc_ms__o32a_2.spice +++ b/cells/o32a/sky130_fd_sc_ms__o32a_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32a_2.spice -* Created: Fri Aug 28 18:03:27 2020 +* Created: Wed Sep 2 12:26:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o32a/sky130_fd_sc_ms__o32a_4.lvs.report b/cells/o32a/sky130_fd_sc_ms__o32a_4.lvs.report new file mode 100644 index 0000000..156b180 --- /dev/null +++ b/cells/o32a/sky130_fd_sc_ms__o32a_4.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o32a_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o32a_4.sp ('sky130_fd_sc_ms__o32a_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o32a/sky130_fd_sc_ms__o32a_4.spice ('sky130_fd_sc_ms__o32a_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:26:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o32a_4 sky130_fd_sc_ms__o32a_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o32a_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o32a_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_2 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 B2 A3 A2 A1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o32a/sky130_fd_sc_ms__o32a_4.pex.spice b/cells/o32a/sky130_fd_sc_ms__o32a_4.pex.spice index 820266e..e458ba3 100644 --- a/cells/o32a/sky130_fd_sc_ms__o32a_4.pex.spice +++ b/cells/o32a/sky130_fd_sc_ms__o32a_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32a_4.pex.spice -* Created: Fri Aug 28 18:03:57 2020 +* Created: Wed Sep 2 12:26:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o32a/sky130_fd_sc_ms__o32a_4.pxi.spice b/cells/o32a/sky130_fd_sc_ms__o32a_4.pxi.spice index 294deee..23e2c25 100644 --- a/cells/o32a/sky130_fd_sc_ms__o32a_4.pxi.spice +++ b/cells/o32a/sky130_fd_sc_ms__o32a_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32a_4.pxi.spice -* Created: Fri Aug 28 18:03:57 2020 +* Created: Wed Sep 2 12:26:23 2020 * x_PM_SKY130_FD_SC_MS__O32A_4%A_83_256# N_A_83_256#_M1010_d N_A_83_256#_M1021_s + N_A_83_256#_M1016_d N_A_83_256#_M1000_s N_A_83_256#_M1003_g
diff --git a/cells/o32a/sky130_fd_sc_ms__o32a_4.spice b/cells/o32a/sky130_fd_sc_ms__o32a_4.spice index 44c953c..89aa306 100644 --- a/cells/o32a/sky130_fd_sc_ms__o32a_4.spice +++ b/cells/o32a/sky130_fd_sc_ms__o32a_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32a_4.spice -* Created: Fri Aug 28 18:03:57 2020 +* Created: Wed Sep 2 12:26:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o32ai/sky130_fd_sc_ms__o32ai_1.lvs.report b/cells/o32ai/sky130_fd_sc_ms__o32ai_1.lvs.report new file mode 100644 index 0000000..18ef153 --- /dev/null +++ b/cells/o32ai/sky130_fd_sc_ms__o32ai_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o32ai_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o32ai_1.sp ('sky130_fd_sc_ms__o32ai_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o32ai/sky130_fd_sc_ms__o32ai_1.spice ('sky130_fd_sc_ms__o32ai_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:26:26 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o32ai_1 sky130_fd_sc_ms__o32ai_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o32ai_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o32ai_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 SMP2 (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_2 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 SMP2 + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 B2 A3 A2 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o32ai/sky130_fd_sc_ms__o32ai_1.pex.spice b/cells/o32ai/sky130_fd_sc_ms__o32ai_1.pex.spice index 877518f..c26a451 100644 --- a/cells/o32ai/sky130_fd_sc_ms__o32ai_1.pex.spice +++ b/cells/o32ai/sky130_fd_sc_ms__o32ai_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32ai_1.pex.spice -* Created: Fri Aug 28 18:04:07 2020 +* Created: Wed Sep 2 12:26:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o32ai/sky130_fd_sc_ms__o32ai_1.pxi.spice b/cells/o32ai/sky130_fd_sc_ms__o32ai_1.pxi.spice index 404232d..ad1fc12 100644 --- a/cells/o32ai/sky130_fd_sc_ms__o32ai_1.pxi.spice +++ b/cells/o32ai/sky130_fd_sc_ms__o32ai_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32ai_1.pxi.spice -* Created: Fri Aug 28 18:04:07 2020 +* Created: Wed Sep 2 12:26:30 2020 * x_PM_SKY130_FD_SC_MS__O32AI_1%B1 N_B1_c_53_n N_B1_M1009_g N_B1_M1006_g B1 + N_B1_c_56_n PM_SKY130_FD_SC_MS__O32AI_1%B1
diff --git a/cells/o32ai/sky130_fd_sc_ms__o32ai_1.spice b/cells/o32ai/sky130_fd_sc_ms__o32ai_1.spice index 7915c42..c6f4652 100644 --- a/cells/o32ai/sky130_fd_sc_ms__o32ai_1.spice +++ b/cells/o32ai/sky130_fd_sc_ms__o32ai_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32ai_1.spice -* Created: Fri Aug 28 18:04:07 2020 +* Created: Wed Sep 2 12:26:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o32ai/sky130_fd_sc_ms__o32ai_2.lvs.report b/cells/o32ai/sky130_fd_sc_ms__o32ai_2.lvs.report new file mode 100644 index 0000000..a74697b --- /dev/null +++ b/cells/o32ai/sky130_fd_sc_ms__o32ai_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o32ai_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o32ai_2.sp ('sky130_fd_sc_ms__o32ai_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o32ai/sky130_fd_sc_ms__o32ai_2.spice ('sky130_fd_sc_ms__o32ai_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:26:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o32ai_2 sky130_fd_sc_ms__o32ai_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o32ai_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o32ai_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 SMP2 (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_2 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 SMP2 + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A3 A2 A1 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o32ai/sky130_fd_sc_ms__o32ai_2.pex.spice b/cells/o32ai/sky130_fd_sc_ms__o32ai_2.pex.spice index 049d7ef..c2f5b86 100644 --- a/cells/o32ai/sky130_fd_sc_ms__o32ai_2.pex.spice +++ b/cells/o32ai/sky130_fd_sc_ms__o32ai_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32ai_2.pex.spice -* Created: Fri Aug 28 18:04:16 2020 +* Created: Wed Sep 2 12:26:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o32ai/sky130_fd_sc_ms__o32ai_2.pxi.spice b/cells/o32ai/sky130_fd_sc_ms__o32ai_2.pxi.spice index 27b9420..1655912 100644 --- a/cells/o32ai/sky130_fd_sc_ms__o32ai_2.pxi.spice +++ b/cells/o32ai/sky130_fd_sc_ms__o32ai_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32ai_2.pxi.spice -* Created: Fri Aug 28 18:04:16 2020 +* Created: Wed Sep 2 12:26:36 2020 * x_PM_SKY130_FD_SC_MS__O32AI_2%B2 N_B2_M1002_g N_B2_M1015_g N_B2_M1016_g + N_B2_M1003_g B2 B2 B2 N_B2_c_100_n PM_SKY130_FD_SC_MS__O32AI_2%B2
diff --git a/cells/o32ai/sky130_fd_sc_ms__o32ai_2.spice b/cells/o32ai/sky130_fd_sc_ms__o32ai_2.spice index 5d50ec4..f294115 100644 --- a/cells/o32ai/sky130_fd_sc_ms__o32ai_2.spice +++ b/cells/o32ai/sky130_fd_sc_ms__o32ai_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32ai_2.spice -* Created: Fri Aug 28 18:04:16 2020 +* Created: Wed Sep 2 12:26:36 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o32ai/sky130_fd_sc_ms__o32ai_4.lvs.report b/cells/o32ai/sky130_fd_sc_ms__o32ai_4.lvs.report new file mode 100644 index 0000000..d4781e8 --- /dev/null +++ b/cells/o32ai/sky130_fd_sc_ms__o32ai_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o32ai_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o32ai_4.sp ('sky130_fd_sc_ms__o32ai_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o32ai/sky130_fd_sc_ms__o32ai_4.spice ('sky130_fd_sc_ms__o32ai_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:26:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o32ai_4 sky130_fd_sc_ms__o32ai_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o32ai_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o32ai_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 SMP2 (4 pins) + 1 1 SMP3 (5 pins) + 1 1 SPMN_3_2 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 SMP2 + 1 1 0 0 SMP3 + 1 1 0 0 SPMN_3_2 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 40 layout mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + 40 source mos transistors were reduced to 10. + 30 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B2 B1 A3 A2 A1 Y VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o32ai/sky130_fd_sc_ms__o32ai_4.pex.spice b/cells/o32ai/sky130_fd_sc_ms__o32ai_4.pex.spice index 78c5ffc..e3f8695 100644 --- a/cells/o32ai/sky130_fd_sc_ms__o32ai_4.pex.spice +++ b/cells/o32ai/sky130_fd_sc_ms__o32ai_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32ai_4.pex.spice -* Created: Fri Aug 28 18:04:25 2020 +* Created: Wed Sep 2 12:26:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o32ai/sky130_fd_sc_ms__o32ai_4.pxi.spice b/cells/o32ai/sky130_fd_sc_ms__o32ai_4.pxi.spice index 31f1443..85a7f22 100644 --- a/cells/o32ai/sky130_fd_sc_ms__o32ai_4.pxi.spice +++ b/cells/o32ai/sky130_fd_sc_ms__o32ai_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32ai_4.pxi.spice -* Created: Fri Aug 28 18:04:25 2020 +* Created: Wed Sep 2 12:26:43 2020 * x_PM_SKY130_FD_SC_MS__O32AI_4%B2 N_B2_M1015_g N_B2_M1022_g N_B2_M1030_g + N_B2_M1016_g N_B2_M1019_g N_B2_M1031_g N_B2_M1020_g N_B2_M1032_g B2 B2 B2 B2
diff --git a/cells/o32ai/sky130_fd_sc_ms__o32ai_4.spice b/cells/o32ai/sky130_fd_sc_ms__o32ai_4.spice index 88b82d4..9d1e10f 100644 --- a/cells/o32ai/sky130_fd_sc_ms__o32ai_4.spice +++ b/cells/o32ai/sky130_fd_sc_ms__o32ai_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o32ai_4.spice -* Created: Fri Aug 28 18:04:25 2020 +* Created: Wed Sep 2 12:26:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o41a/sky130_fd_sc_ms__o41a_1.lvs.report b/cells/o41a/sky130_fd_sc_ms__o41a_1.lvs.report new file mode 100644 index 0000000..890236e --- /dev/null +++ b/cells/o41a/sky130_fd_sc_ms__o41a_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o41a_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o41a_1.sp ('sky130_fd_sc_ms__o41a_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o41a/sky130_fd_sc_ms__o41a_1.spice ('sky130_fd_sc_ms__o41a_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:26:46 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o41a_1 sky130_fd_sc_ms__o41a_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o41a_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o41a_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP4 (6 pins) + 1 1 SPMN_4_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + 1 1 0 0 SPMN_4_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A4 A3 A2 A1 X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o41a/sky130_fd_sc_ms__o41a_1.pex.spice b/cells/o41a/sky130_fd_sc_ms__o41a_1.pex.spice index 590a91b..6eb97fe 100644 --- a/cells/o41a/sky130_fd_sc_ms__o41a_1.pex.spice +++ b/cells/o41a/sky130_fd_sc_ms__o41a_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41a_1.pex.spice -* Created: Fri Aug 28 18:04:34 2020 +* Created: Wed Sep 2 12:26:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o41a/sky130_fd_sc_ms__o41a_1.pxi.spice b/cells/o41a/sky130_fd_sc_ms__o41a_1.pxi.spice index 9a2f1b1..14e8475 100644 --- a/cells/o41a/sky130_fd_sc_ms__o41a_1.pxi.spice +++ b/cells/o41a/sky130_fd_sc_ms__o41a_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41a_1.pxi.spice -* Created: Fri Aug 28 18:04:34 2020 +* Created: Wed Sep 2 12:26:50 2020 * x_PM_SKY130_FD_SC_MS__O41A_1%A_83_270# N_A_83_270#_M1004_s N_A_83_270#_M1002_d + N_A_83_270#_M1000_g N_A_83_270#_M1010_g N_A_83_270#_c_78_n N_A_83_270#_c_73_n
diff --git a/cells/o41a/sky130_fd_sc_ms__o41a_1.spice b/cells/o41a/sky130_fd_sc_ms__o41a_1.spice index 3e97555..5bf240b 100644 --- a/cells/o41a/sky130_fd_sc_ms__o41a_1.spice +++ b/cells/o41a/sky130_fd_sc_ms__o41a_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41a_1.spice -* Created: Fri Aug 28 18:04:34 2020 +* Created: Wed Sep 2 12:26:50 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o41a/sky130_fd_sc_ms__o41a_2.lvs.report b/cells/o41a/sky130_fd_sc_ms__o41a_2.lvs.report new file mode 100644 index 0000000..999328a --- /dev/null +++ b/cells/o41a/sky130_fd_sc_ms__o41a_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o41a_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o41a_2.sp ('sky130_fd_sc_ms__o41a_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o41a/sky130_fd_sc_ms__o41a_2.spice ('sky130_fd_sc_ms__o41a_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:26:54 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o41a_2 sky130_fd_sc_ms__o41a_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o41a_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o41a_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP4 (6 pins) + 1 1 SPMN_4_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + 1 1 0 0 SPMN_4_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A1 A2 A3 A4 B1 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o41a/sky130_fd_sc_ms__o41a_2.pex.spice b/cells/o41a/sky130_fd_sc_ms__o41a_2.pex.spice index f55bbd8..bd27fb9 100644 --- a/cells/o41a/sky130_fd_sc_ms__o41a_2.pex.spice +++ b/cells/o41a/sky130_fd_sc_ms__o41a_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41a_2.pex.spice -* Created: Fri Aug 28 18:05:04 2020 +* Created: Wed Sep 2 12:26:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o41a/sky130_fd_sc_ms__o41a_2.pxi.spice b/cells/o41a/sky130_fd_sc_ms__o41a_2.pxi.spice index e4624e2..29455f8 100644 --- a/cells/o41a/sky130_fd_sc_ms__o41a_2.pxi.spice +++ b/cells/o41a/sky130_fd_sc_ms__o41a_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41a_2.pxi.spice -* Created: Fri Aug 28 18:05:04 2020 +* Created: Wed Sep 2 12:26:57 2020 * x_PM_SKY130_FD_SC_MS__O41A_2%A1 N_A1_M1002_g N_A1_M1011_g A1 N_A1_c_79_n + N_A1_c_80_n PM_SKY130_FD_SC_MS__O41A_2%A1
diff --git a/cells/o41a/sky130_fd_sc_ms__o41a_2.spice b/cells/o41a/sky130_fd_sc_ms__o41a_2.spice index f836595..2ae0d13 100644 --- a/cells/o41a/sky130_fd_sc_ms__o41a_2.spice +++ b/cells/o41a/sky130_fd_sc_ms__o41a_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41a_2.spice -* Created: Fri Aug 28 18:05:04 2020 +* Created: Wed Sep 2 12:26:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o41a/sky130_fd_sc_ms__o41a_4.lvs.report b/cells/o41a/sky130_fd_sc_ms__o41a_4.lvs.report new file mode 100644 index 0000000..9ec67ce --- /dev/null +++ b/cells/o41a/sky130_fd_sc_ms__o41a_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o41a_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o41a_4.sp ('sky130_fd_sc_ms__o41a_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o41a/sky130_fd_sc_ms__o41a_4.spice ('sky130_fd_sc_ms__o41a_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:27:00 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o41a_4 sky130_fd_sc_ms__o41a_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o41a_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o41a_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 11 11 + + Instances: 1 1 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP4 (6 pins) + 1 1 SPMN_4_1 (7 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 11 11 0 0 + + Instances: 1 1 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + 1 1 0 0 SPMN_4_1 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 28 layout mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + 28 source mos transistors were reduced to 12. + 16 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A4 A3 A1 A2 VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o41a/sky130_fd_sc_ms__o41a_4.pex.spice b/cells/o41a/sky130_fd_sc_ms__o41a_4.pex.spice index bd0195a..69f7a23 100644 --- a/cells/o41a/sky130_fd_sc_ms__o41a_4.pex.spice +++ b/cells/o41a/sky130_fd_sc_ms__o41a_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41a_4.pex.spice -* Created: Fri Aug 28 18:05:15 2020 +* Created: Wed Sep 2 12:27:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o41a/sky130_fd_sc_ms__o41a_4.pxi.spice b/cells/o41a/sky130_fd_sc_ms__o41a_4.pxi.spice index 8768282..28d863e 100644 --- a/cells/o41a/sky130_fd_sc_ms__o41a_4.pxi.spice +++ b/cells/o41a/sky130_fd_sc_ms__o41a_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41a_4.pxi.spice -* Created: Fri Aug 28 18:05:15 2020 +* Created: Wed Sep 2 12:27:03 2020 * x_PM_SKY130_FD_SC_MS__O41A_4%A_110_48# N_A_110_48#_M1005_s N_A_110_48#_M1011_d + N_A_110_48#_M1019_d N_A_110_48#_M1010_g N_A_110_48#_M1003_g
diff --git a/cells/o41a/sky130_fd_sc_ms__o41a_4.spice b/cells/o41a/sky130_fd_sc_ms__o41a_4.spice index 937a258..1550b75 100644 --- a/cells/o41a/sky130_fd_sc_ms__o41a_4.spice +++ b/cells/o41a/sky130_fd_sc_ms__o41a_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41a_4.spice -* Created: Fri Aug 28 18:05:15 2020 +* Created: Wed Sep 2 12:27:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o41ai/sky130_fd_sc_ms__o41ai_1.lvs.report b/cells/o41ai/sky130_fd_sc_ms__o41ai_1.lvs.report new file mode 100644 index 0000000..cbb348e --- /dev/null +++ b/cells/o41ai/sky130_fd_sc_ms__o41ai_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o41ai_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o41ai_1.sp ('sky130_fd_sc_ms__o41ai_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o41ai/sky130_fd_sc_ms__o41ai_1.spice ('sky130_fd_sc_ms__o41ai_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:27:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o41ai_1 sky130_fd_sc_ms__o41ai_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o41ai_1 +SOURCE CELL NAME: sky130_fd_sc_ms__o41ai_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MP (4 pins) + 1 1 SMP4 (6 pins) + 1 1 SPMN_4_1 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + 1 1 0 0 SPMN_4_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o41ai/sky130_fd_sc_ms__o41ai_1.pex.spice b/cells/o41ai/sky130_fd_sc_ms__o41ai_1.pex.spice index 16e69e5..3d40e43 100644 --- a/cells/o41ai/sky130_fd_sc_ms__o41ai_1.pex.spice +++ b/cells/o41ai/sky130_fd_sc_ms__o41ai_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41ai_1.pex.spice -* Created: Fri Aug 28 18:05:24 2020 +* Created: Wed Sep 2 12:27:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o41ai/sky130_fd_sc_ms__o41ai_1.pxi.spice b/cells/o41ai/sky130_fd_sc_ms__o41ai_1.pxi.spice index 14ff175..47298ba 100644 --- a/cells/o41ai/sky130_fd_sc_ms__o41ai_1.pxi.spice +++ b/cells/o41ai/sky130_fd_sc_ms__o41ai_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41ai_1.pxi.spice -* Created: Fri Aug 28 18:05:24 2020 +* Created: Wed Sep 2 12:27:10 2020 * x_PM_SKY130_FD_SC_MS__O41AI_1%B1 N_B1_c_62_n N_B1_M1009_g N_B1_M1006_g + N_B1_c_64_n N_B1_c_65_n B1 PM_SKY130_FD_SC_MS__O41AI_1%B1
diff --git a/cells/o41ai/sky130_fd_sc_ms__o41ai_1.spice b/cells/o41ai/sky130_fd_sc_ms__o41ai_1.spice index 7fc65a9..8f29c46 100644 --- a/cells/o41ai/sky130_fd_sc_ms__o41ai_1.spice +++ b/cells/o41ai/sky130_fd_sc_ms__o41ai_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41ai_1.spice -* Created: Fri Aug 28 18:05:24 2020 +* Created: Wed Sep 2 12:27:10 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o41ai/sky130_fd_sc_ms__o41ai_2.lvs.report b/cells/o41ai/sky130_fd_sc_ms__o41ai_2.lvs.report new file mode 100644 index 0000000..5fec48b --- /dev/null +++ b/cells/o41ai/sky130_fd_sc_ms__o41ai_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o41ai_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o41ai_2.sp ('sky130_fd_sc_ms__o41ai_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o41ai/sky130_fd_sc_ms__o41ai_2.spice ('sky130_fd_sc_ms__o41ai_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:27:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o41ai_2 sky130_fd_sc_ms__o41ai_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o41ai_2 +SOURCE CELL NAME: sky130_fd_sc_ms__o41ai_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MP (4 pins) + 1 1 SMP4 (6 pins) + 1 1 SPMN_4_1 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + 1 1 0 0 SPMN_4_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 20 layout mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + 20 source mos transistors were reduced to 10. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o41ai/sky130_fd_sc_ms__o41ai_2.pex.spice b/cells/o41ai/sky130_fd_sc_ms__o41ai_2.pex.spice index 929a793..cbbd857 100644 --- a/cells/o41ai/sky130_fd_sc_ms__o41ai_2.pex.spice +++ b/cells/o41ai/sky130_fd_sc_ms__o41ai_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41ai_2.pex.spice -* Created: Fri Aug 28 18:05:33 2020 +* Created: Wed Sep 2 12:27:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o41ai/sky130_fd_sc_ms__o41ai_2.pxi.spice b/cells/o41ai/sky130_fd_sc_ms__o41ai_2.pxi.spice index 38510ac..ef995a4 100644 --- a/cells/o41ai/sky130_fd_sc_ms__o41ai_2.pxi.spice +++ b/cells/o41ai/sky130_fd_sc_ms__o41ai_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41ai_2.pxi.spice -* Created: Fri Aug 28 18:05:33 2020 +* Created: Wed Sep 2 12:27:17 2020 * x_PM_SKY130_FD_SC_MS__O41AI_2%B1 N_B1_M1014_g N_B1_M1015_g N_B1_c_116_n + N_B1_M1005_g N_B1_c_117_n N_B1_c_118_n N_B1_c_119_n N_B1_M1018_g N_B1_c_120_n
diff --git a/cells/o41ai/sky130_fd_sc_ms__o41ai_2.spice b/cells/o41ai/sky130_fd_sc_ms__o41ai_2.spice index 7d37cde..2c58cf0 100644 --- a/cells/o41ai/sky130_fd_sc_ms__o41ai_2.spice +++ b/cells/o41ai/sky130_fd_sc_ms__o41ai_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41ai_2.spice -* Created: Fri Aug 28 18:05:33 2020 +* Created: Wed Sep 2 12:27:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/o41ai/sky130_fd_sc_ms__o41ai_4.lvs.report b/cells/o41ai/sky130_fd_sc_ms__o41ai_4.lvs.report new file mode 100644 index 0000000..6438b28 --- /dev/null +++ b/cells/o41ai/sky130_fd_sc_ms__o41ai_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__o41ai_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__o41ai_4.sp ('sky130_fd_sc_ms__o41ai_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/o41ai/sky130_fd_sc_ms__o41ai_4.spice ('sky130_fd_sc_ms__o41ai_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:27:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__o41ai_4 sky130_fd_sc_ms__o41ai_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__o41ai_4 +SOURCE CELL NAME: sky130_fd_sc_ms__o41ai_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 14 14 + + Instances: 20 20 MN (4 pins) + 18 18 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 39 38 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 10 10 + + Instances: 1 1 MP (4 pins) + 1 1 SMP4 (6 pins) + 1 1 SPMN_4_1 (7 pins) + ------ ------ + Total Inst: 3 3 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 10 10 0 0 + + Instances: 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + 1 1 0 0 SPMN_4_1 + ------- ------- --------- --------- + Total Inst: 3 3 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 38 layout mos transistors were reduced to 10. + 28 mos transistors were deleted by parallel reduction. + 38 source mos transistors were reduced to 10. + 28 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/o41ai/sky130_fd_sc_ms__o41ai_4.pex.spice b/cells/o41ai/sky130_fd_sc_ms__o41ai_4.pex.spice index dd844e9..24b8d2a 100644 --- a/cells/o41ai/sky130_fd_sc_ms__o41ai_4.pex.spice +++ b/cells/o41ai/sky130_fd_sc_ms__o41ai_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41ai_4.pex.spice -* Created: Fri Aug 28 18:05:42 2020 +* Created: Wed Sep 2 12:27:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/o41ai/sky130_fd_sc_ms__o41ai_4.pxi.spice b/cells/o41ai/sky130_fd_sc_ms__o41ai_4.pxi.spice index afb325c..9b7b300 100644 --- a/cells/o41ai/sky130_fd_sc_ms__o41ai_4.pxi.spice +++ b/cells/o41ai/sky130_fd_sc_ms__o41ai_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41ai_4.pxi.spice -* Created: Fri Aug 28 18:05:42 2020 +* Created: Wed Sep 2 12:27:23 2020 * x_PM_SKY130_FD_SC_MS__O41AI_4%B1 N_B1_M1004_g N_B1_c_156_n N_B1_M1009_g + N_B1_c_157_n N_B1_M1010_g N_B1_M1008_g N_B1_c_159_n N_B1_M1029_g N_B1_c_160_n
diff --git a/cells/o41ai/sky130_fd_sc_ms__o41ai_4.spice b/cells/o41ai/sky130_fd_sc_ms__o41ai_4.spice index f1dabdc..d860060 100644 --- a/cells/o41ai/sky130_fd_sc_ms__o41ai_4.spice +++ b/cells/o41ai/sky130_fd_sc_ms__o41ai_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__o41ai_4.spice -* Created: Fri Aug 28 18:05:42 2020 +* Created: Wed Sep 2 12:27:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or2/sky130_fd_sc_ms__or2_1.lvs.report b/cells/or2/sky130_fd_sc_ms__or2_1.lvs.report new file mode 100644 index 0000000..1be705c --- /dev/null +++ b/cells/or2/sky130_fd_sc_ms__or2_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or2_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or2_1.sp ('sky130_fd_sc_ms__or2_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or2/sky130_fd_sc_ms__or2_1.spice ('sky130_fd_sc_ms__or2_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:27:27 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or2_1 sky130_fd_sc_ms__or2_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or2_1 +SOURCE CELL NAME: sky130_fd_sc_ms__or2_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 3 3 MN (4 pins) + 3 3 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 7 6 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or2/sky130_fd_sc_ms__or2_1.pex.spice b/cells/or2/sky130_fd_sc_ms__or2_1.pex.spice index 1307955..bb7a380 100644 --- a/cells/or2/sky130_fd_sc_ms__or2_1.pex.spice +++ b/cells/or2/sky130_fd_sc_ms__or2_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2_1.pex.spice -* Created: Fri Aug 28 18:06:12 2020 +* Created: Wed Sep 2 12:27:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or2/sky130_fd_sc_ms__or2_1.pxi.spice b/cells/or2/sky130_fd_sc_ms__or2_1.pxi.spice index 9665c94..933f89a 100644 --- a/cells/or2/sky130_fd_sc_ms__or2_1.pxi.spice +++ b/cells/or2/sky130_fd_sc_ms__or2_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2_1.pxi.spice -* Created: Fri Aug 28 18:06:12 2020 +* Created: Wed Sep 2 12:27:30 2020 * x_PM_SKY130_FD_SC_MS__OR2_1%B N_B_M1001_g N_B_c_44_n N_B_M1003_g B N_B_c_45_n + N_B_c_46_n PM_SKY130_FD_SC_MS__OR2_1%B
diff --git a/cells/or2/sky130_fd_sc_ms__or2_1.spice b/cells/or2/sky130_fd_sc_ms__or2_1.spice index 7f81438..212d2b1 100644 --- a/cells/or2/sky130_fd_sc_ms__or2_1.spice +++ b/cells/or2/sky130_fd_sc_ms__or2_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2_1.spice -* Created: Fri Aug 28 18:06:12 2020 +* Created: Wed Sep 2 12:27:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or2/sky130_fd_sc_ms__or2_2.lvs.report b/cells/or2/sky130_fd_sc_ms__or2_2.lvs.report new file mode 100644 index 0000000..f8e2ac7 --- /dev/null +++ b/cells/or2/sky130_fd_sc_ms__or2_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or2_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or2_2.sp ('sky130_fd_sc_ms__or2_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or2/sky130_fd_sc_ms__or2_2.spice ('sky130_fd_sc_ms__or2_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:27:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or2_2 sky130_fd_sc_ms__or2_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or2_2 +SOURCE CELL NAME: sky130_fd_sc_ms__or2_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or2/sky130_fd_sc_ms__or2_2.pex.spice b/cells/or2/sky130_fd_sc_ms__or2_2.pex.spice index ecdf4ea..476a94a 100644 --- a/cells/or2/sky130_fd_sc_ms__or2_2.pex.spice +++ b/cells/or2/sky130_fd_sc_ms__or2_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2_2.pex.spice -* Created: Fri Aug 28 18:06:22 2020 +* Created: Wed Sep 2 12:27:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or2/sky130_fd_sc_ms__or2_2.pxi.spice b/cells/or2/sky130_fd_sc_ms__or2_2.pxi.spice index 5fb24a3..b1e82f5 100644 --- a/cells/or2/sky130_fd_sc_ms__or2_2.pxi.spice +++ b/cells/or2/sky130_fd_sc_ms__or2_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2_2.pxi.spice -* Created: Fri Aug 28 18:06:22 2020 +* Created: Wed Sep 2 12:27:37 2020 * x_PM_SKY130_FD_SC_MS__OR2_2%B N_B_M1004_g N_B_c_52_n N_B_M1003_g B N_B_c_54_n + PM_SKY130_FD_SC_MS__OR2_2%B
diff --git a/cells/or2/sky130_fd_sc_ms__or2_2.spice b/cells/or2/sky130_fd_sc_ms__or2_2.spice index 37c2e50..0b12b22 100644 --- a/cells/or2/sky130_fd_sc_ms__or2_2.spice +++ b/cells/or2/sky130_fd_sc_ms__or2_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2_2.spice -* Created: Fri Aug 28 18:06:22 2020 +* Created: Wed Sep 2 12:27:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or2/sky130_fd_sc_ms__or2_4.lvs.report b/cells/or2/sky130_fd_sc_ms__or2_4.lvs.report new file mode 100644 index 0000000..5bb5268 --- /dev/null +++ b/cells/or2/sky130_fd_sc_ms__or2_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or2_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or2_4.sp ('sky130_fd_sc_ms__or2_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or2/sky130_fd_sc_ms__or2_4.spice ('sky130_fd_sc_ms__or2_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:27:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or2_4 sky130_fd_sc_ms__or2_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or2_4 +SOURCE CELL NAME: sky130_fd_sc_ms__or2_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 6 6 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 5 5 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 5 5 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 4. + 8 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 4. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or2/sky130_fd_sc_ms__or2_4.pex.spice b/cells/or2/sky130_fd_sc_ms__or2_4.pex.spice index 0291d04..f8f1d62 100644 --- a/cells/or2/sky130_fd_sc_ms__or2_4.pex.spice +++ b/cells/or2/sky130_fd_sc_ms__or2_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2_4.pex.spice -* Created: Fri Aug 28 18:06:31 2020 +* Created: Wed Sep 2 12:27:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or2/sky130_fd_sc_ms__or2_4.pxi.spice b/cells/or2/sky130_fd_sc_ms__or2_4.pxi.spice index c3b3491..d21e3db 100644 --- a/cells/or2/sky130_fd_sc_ms__or2_4.pxi.spice +++ b/cells/or2/sky130_fd_sc_ms__or2_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2_4.pxi.spice -* Created: Fri Aug 28 18:06:31 2020 +* Created: Wed Sep 2 12:27:43 2020 * x_PM_SKY130_FD_SC_MS__OR2_4%A_83_260# N_A_83_260#_M1004_d N_A_83_260#_M1007_d + N_A_83_260#_M1001_g N_A_83_260#_M1008_g N_A_83_260#_M1009_g
diff --git a/cells/or2/sky130_fd_sc_ms__or2_4.spice b/cells/or2/sky130_fd_sc_ms__or2_4.spice index 2d292d8..3a15523 100644 --- a/cells/or2/sky130_fd_sc_ms__or2_4.spice +++ b/cells/or2/sky130_fd_sc_ms__or2_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2_4.spice -* Created: Fri Aug 28 18:06:31 2020 +* Created: Wed Sep 2 12:27:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or2b/sky130_fd_sc_ms__or2b_1.lvs.report b/cells/or2b/sky130_fd_sc_ms__or2b_1.lvs.report new file mode 100644 index 0000000..2d4ad89 --- /dev/null +++ b/cells/or2b/sky130_fd_sc_ms__or2b_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or2b_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or2b_1.sp ('sky130_fd_sc_ms__or2b_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or2b/sky130_fd_sc_ms__or2b_1.spice ('sky130_fd_sc_ms__or2b_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:27:47 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or2b_1 sky130_fd_sc_ms__or2b_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or2b_1 +SOURCE CELL NAME: sky130_fd_sc_ms__or2b_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 10 10 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B_N A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or2b/sky130_fd_sc_ms__or2b_1.pex.spice b/cells/or2b/sky130_fd_sc_ms__or2b_1.pex.spice index c893927..637adf7 100644 --- a/cells/or2b/sky130_fd_sc_ms__or2b_1.pex.spice +++ b/cells/or2b/sky130_fd_sc_ms__or2b_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2b_1.pex.spice -* Created: Fri Aug 28 18:06:40 2020 +* Created: Wed Sep 2 12:27:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or2b/sky130_fd_sc_ms__or2b_1.pxi.spice b/cells/or2b/sky130_fd_sc_ms__or2b_1.pxi.spice index e6aae92..e9bb115 100644 --- a/cells/or2b/sky130_fd_sc_ms__or2b_1.pxi.spice +++ b/cells/or2b/sky130_fd_sc_ms__or2b_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2b_1.pxi.spice -* Created: Fri Aug 28 18:06:40 2020 +* Created: Wed Sep 2 12:27:51 2020 * x_PM_SKY130_FD_SC_MS__OR2B_1%B_N N_B_N_c_60_n N_B_N_M1005_g N_B_N_c_61_n + N_B_N_c_62_n N_B_N_M1003_g B_N PM_SKY130_FD_SC_MS__OR2B_1%B_N
diff --git a/cells/or2b/sky130_fd_sc_ms__or2b_1.spice b/cells/or2b/sky130_fd_sc_ms__or2b_1.spice index c47e188..421da57 100644 --- a/cells/or2b/sky130_fd_sc_ms__or2b_1.spice +++ b/cells/or2b/sky130_fd_sc_ms__or2b_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2b_1.spice -* Created: Fri Aug 28 18:06:40 2020 +* Created: Wed Sep 2 12:27:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or2b/sky130_fd_sc_ms__or2b_2.lvs.report b/cells/or2b/sky130_fd_sc_ms__or2b_2.lvs.report new file mode 100644 index 0000000..9180359 --- /dev/null +++ b/cells/or2b/sky130_fd_sc_ms__or2b_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or2b_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or2b_2.sp ('sky130_fd_sc_ms__or2b_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or2b/sky130_fd_sc_ms__or2b_2.spice ('sky130_fd_sc_ms__or2b_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:27:54 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or2b_2 sky130_fd_sc_ms__or2b_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or2b_2 +SOURCE CELL NAME: sky130_fd_sc_ms__or2b_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B_N A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or2b/sky130_fd_sc_ms__or2b_2.pex.spice b/cells/or2b/sky130_fd_sc_ms__or2b_2.pex.spice index 0d5486f..a74f6d1 100644 --- a/cells/or2b/sky130_fd_sc_ms__or2b_2.pex.spice +++ b/cells/or2b/sky130_fd_sc_ms__or2b_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2b_2.pex.spice -* Created: Fri Aug 28 18:06:49 2020 +* Created: Wed Sep 2 12:27:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or2b/sky130_fd_sc_ms__or2b_2.pxi.spice b/cells/or2b/sky130_fd_sc_ms__or2b_2.pxi.spice index 3c62638..bcaf8ef 100644 --- a/cells/or2b/sky130_fd_sc_ms__or2b_2.pxi.spice +++ b/cells/or2b/sky130_fd_sc_ms__or2b_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2b_2.pxi.spice -* Created: Fri Aug 28 18:06:49 2020 +* Created: Wed Sep 2 12:27:57 2020 * x_PM_SKY130_FD_SC_MS__OR2B_2%B_N N_B_N_M1001_g N_B_N_M1002_g B_N N_B_N_c_68_n + N_B_N_c_69_n PM_SKY130_FD_SC_MS__OR2B_2%B_N
diff --git a/cells/or2b/sky130_fd_sc_ms__or2b_2.spice b/cells/or2b/sky130_fd_sc_ms__or2b_2.spice index 35dae10..ebe2a05 100644 --- a/cells/or2b/sky130_fd_sc_ms__or2b_2.spice +++ b/cells/or2b/sky130_fd_sc_ms__or2b_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2b_2.spice -* Created: Fri Aug 28 18:06:49 2020 +* Created: Wed Sep 2 12:27:57 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or2b/sky130_fd_sc_ms__or2b_4.lvs.report b/cells/or2b/sky130_fd_sc_ms__or2b_4.lvs.report new file mode 100644 index 0000000..1dbb6f0 --- /dev/null +++ b/cells/or2b/sky130_fd_sc_ms__or2b_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or2b_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or2b_4.sp ('sky130_fd_sc_ms__or2b_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or2b/sky130_fd_sc_ms__or2b_4.spice ('sky130_fd_sc_ms__or2b_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:28:01 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or2b_4 sky130_fd_sc_ms__or2b_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or2b_4 +SOURCE CELL NAME: sky130_fd_sc_ms__or2b_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 10 10 + + Instances: 9 9 MN (4 pins) + 9 9 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 19 18 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP2 (4 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B_N VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or2b/sky130_fd_sc_ms__or2b_4.pex.spice b/cells/or2b/sky130_fd_sc_ms__or2b_4.pex.spice index bd56385..2ec3f8e 100644 --- a/cells/or2b/sky130_fd_sc_ms__or2b_4.pex.spice +++ b/cells/or2b/sky130_fd_sc_ms__or2b_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2b_4.pex.spice -* Created: Fri Aug 28 18:07:19 2020 +* Created: Wed Sep 2 12:28:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or2b/sky130_fd_sc_ms__or2b_4.pxi.spice b/cells/or2b/sky130_fd_sc_ms__or2b_4.pxi.spice index e2d1159..4ce0e6f 100644 --- a/cells/or2b/sky130_fd_sc_ms__or2b_4.pxi.spice +++ b/cells/or2b/sky130_fd_sc_ms__or2b_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2b_4.pxi.spice -* Created: Fri Aug 28 18:07:19 2020 +* Created: Wed Sep 2 12:28:04 2020 * x_PM_SKY130_FD_SC_MS__OR2B_4%A_81_296# N_A_81_296#_M1000_d N_A_81_296#_M1006_d + N_A_81_296#_M1001_d N_A_81_296#_M1008_g N_A_81_296#_M1005_g
diff --git a/cells/or2b/sky130_fd_sc_ms__or2b_4.spice b/cells/or2b/sky130_fd_sc_ms__or2b_4.spice index dfa8768..a6446d9 100644 --- a/cells/or2b/sky130_fd_sc_ms__or2b_4.spice +++ b/cells/or2b/sky130_fd_sc_ms__or2b_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or2b_4.spice -* Created: Fri Aug 28 18:07:19 2020 +* Created: Wed Sep 2 12:28:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or3/sky130_fd_sc_ms__or3_1.lvs.report b/cells/or3/sky130_fd_sc_ms__or3_1.lvs.report new file mode 100644 index 0000000..ab90a76 --- /dev/null +++ b/cells/or3/sky130_fd_sc_ms__or3_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or3_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or3_1.sp ('sky130_fd_sc_ms__or3_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or3/sky130_fd_sc_ms__or3_1.spice ('sky130_fd_sc_ms__or3_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:28:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or3_1 sky130_fd_sc_ms__or3_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or3_1 +SOURCE CELL NAME: sky130_fd_sc_ms__or3_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 4 4 MN (4 pins) + 4 4 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 9 8 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP3 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C B A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or3/sky130_fd_sc_ms__or3_1.pex.spice b/cells/or3/sky130_fd_sc_ms__or3_1.pex.spice index 63bcd12..6435da6 100644 --- a/cells/or3/sky130_fd_sc_ms__or3_1.pex.spice +++ b/cells/or3/sky130_fd_sc_ms__or3_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3_1.pex.spice -* Created: Fri Aug 28 18:07:29 2020 +* Created: Wed Sep 2 12:28:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or3/sky130_fd_sc_ms__or3_1.pxi.spice b/cells/or3/sky130_fd_sc_ms__or3_1.pxi.spice index c8036a5..3a32f4c 100644 --- a/cells/or3/sky130_fd_sc_ms__or3_1.pxi.spice +++ b/cells/or3/sky130_fd_sc_ms__or3_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3_1.pxi.spice -* Created: Fri Aug 28 18:07:29 2020 +* Created: Wed Sep 2 12:28:11 2020 * x_PM_SKY130_FD_SC_MS__OR3_1%C N_C_c_51_n N_C_M1000_g N_C_M1007_g C N_C_c_53_n + PM_SKY130_FD_SC_MS__OR3_1%C
diff --git a/cells/or3/sky130_fd_sc_ms__or3_1.spice b/cells/or3/sky130_fd_sc_ms__or3_1.spice index 89179f6..74f74a2 100644 --- a/cells/or3/sky130_fd_sc_ms__or3_1.spice +++ b/cells/or3/sky130_fd_sc_ms__or3_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3_1.spice -* Created: Fri Aug 28 18:07:29 2020 +* Created: Wed Sep 2 12:28:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or3/sky130_fd_sc_ms__or3_2.lvs.report b/cells/or3/sky130_fd_sc_ms__or3_2.lvs.report new file mode 100644 index 0000000..436ce1d --- /dev/null +++ b/cells/or3/sky130_fd_sc_ms__or3_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or3_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or3_2.sp ('sky130_fd_sc_ms__or3_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or3/sky130_fd_sc_ms__or3_2.spice ('sky130_fd_sc_ms__or3_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:28:14 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or3_2 sky130_fd_sc_ms__or3_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or3_2 +SOURCE CELL NAME: sky130_fd_sc_ms__or3_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP3 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C B A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or3/sky130_fd_sc_ms__or3_2.pex.spice b/cells/or3/sky130_fd_sc_ms__or3_2.pex.spice index 4eb48c9..cae0fff 100644 --- a/cells/or3/sky130_fd_sc_ms__or3_2.pex.spice +++ b/cells/or3/sky130_fd_sc_ms__or3_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3_2.pex.spice -* Created: Fri Aug 28 18:07:38 2020 +* Created: Wed Sep 2 12:28:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or3/sky130_fd_sc_ms__or3_2.pxi.spice b/cells/or3/sky130_fd_sc_ms__or3_2.pxi.spice index cc20449..8a824e8 100644 --- a/cells/or3/sky130_fd_sc_ms__or3_2.pxi.spice +++ b/cells/or3/sky130_fd_sc_ms__or3_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3_2.pxi.spice -* Created: Fri Aug 28 18:07:38 2020 +* Created: Wed Sep 2 12:28:17 2020 * x_PM_SKY130_FD_SC_MS__OR3_2%C N_C_M1009_g N_C_c_63_n N_C_M1003_g N_C_c_64_n C C + N_C_c_65_n N_C_c_66_n N_C_c_67_n PM_SKY130_FD_SC_MS__OR3_2%C
diff --git a/cells/or3/sky130_fd_sc_ms__or3_2.spice b/cells/or3/sky130_fd_sc_ms__or3_2.spice index 6732aa8..222fd1a 100644 --- a/cells/or3/sky130_fd_sc_ms__or3_2.spice +++ b/cells/or3/sky130_fd_sc_ms__or3_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3_2.spice -* Created: Fri Aug 28 18:07:38 2020 +* Created: Wed Sep 2 12:28:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or3/sky130_fd_sc_ms__or3_4.lvs.report b/cells/or3/sky130_fd_sc_ms__or3_4.lvs.report new file mode 100644 index 0000000..8de9acd --- /dev/null +++ b/cells/or3/sky130_fd_sc_ms__or3_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or3_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or3_4.sp ('sky130_fd_sc_ms__or3_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or3/sky130_fd_sc_ms__or3_4.spice ('sky130_fd_sc_ms__or3_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:28:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or3_4 sky130_fd_sc_ms__or3_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or3_4 +SOURCE CELL NAME: sky130_fd_sc_ms__or3_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 11 11 + + Instances: 7 7 MN (4 pins) + 10 10 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 18 17 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 9 9 + + Instances: 4 4 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP3 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 9 9 0 0 + + Instances: 4 4 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 14 layout mos transistors were reduced to 5. + 9 mos transistors were deleted by parallel reduction. + 14 source mos transistors were reduced to 5. + 9 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B C VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or3/sky130_fd_sc_ms__or3_4.pex.spice b/cells/or3/sky130_fd_sc_ms__or3_4.pex.spice index b881d3e..8dc0dee 100644 --- a/cells/or3/sky130_fd_sc_ms__or3_4.pex.spice +++ b/cells/or3/sky130_fd_sc_ms__or3_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3_4.pex.spice -* Created: Fri Aug 28 18:07:48 2020 +* Created: Wed Sep 2 12:28:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or3/sky130_fd_sc_ms__or3_4.pxi.spice b/cells/or3/sky130_fd_sc_ms__or3_4.pxi.spice index a6c7ce4..e3a3dca 100644 --- a/cells/or3/sky130_fd_sc_ms__or3_4.pxi.spice +++ b/cells/or3/sky130_fd_sc_ms__or3_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3_4.pxi.spice -* Created: Fri Aug 28 18:07:48 2020 +* Created: Wed Sep 2 12:28:24 2020 * x_PM_SKY130_FD_SC_MS__OR3_4%A N_A_M1006_g N_A_M1013_g N_A_M1001_g N_A_c_96_n + N_A_c_97_n N_A_c_98_n N_A_c_99_n N_A_c_100_n A N_A_c_102_n N_A_c_103_n A
diff --git a/cells/or3/sky130_fd_sc_ms__or3_4.spice b/cells/or3/sky130_fd_sc_ms__or3_4.spice index 0b225ae..66df2ca 100644 --- a/cells/or3/sky130_fd_sc_ms__or3_4.spice +++ b/cells/or3/sky130_fd_sc_ms__or3_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3_4.spice -* Created: Fri Aug 28 18:07:48 2020 +* Created: Wed Sep 2 12:28:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or3b/sky130_fd_sc_ms__or3b_1.lvs.report b/cells/or3b/sky130_fd_sc_ms__or3b_1.lvs.report new file mode 100644 index 0000000..afdf701 --- /dev/null +++ b/cells/or3b/sky130_fd_sc_ms__or3b_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or3b_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or3b_1.sp ('sky130_fd_sc_ms__or3b_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or3b/sky130_fd_sc_ms__or3b_1.spice ('sky130_fd_sc_ms__or3b_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:28:27 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or3b_1 sky130_fd_sc_ms__or3b_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or3b_1 +SOURCE CELL NAME: sky130_fd_sc_ms__or3b_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP3 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C_N B A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or3b/sky130_fd_sc_ms__or3b_1.pex.spice b/cells/or3b/sky130_fd_sc_ms__or3b_1.pex.spice index 86edbf7..3ebf5d4 100644 --- a/cells/or3b/sky130_fd_sc_ms__or3b_1.pex.spice +++ b/cells/or3b/sky130_fd_sc_ms__or3b_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3b_1.pex.spice -* Created: Fri Aug 28 18:07:57 2020 +* Created: Wed Sep 2 12:28:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or3b/sky130_fd_sc_ms__or3b_1.pxi.spice b/cells/or3b/sky130_fd_sc_ms__or3b_1.pxi.spice index 5435d39..c337718 100644 --- a/cells/or3b/sky130_fd_sc_ms__or3b_1.pxi.spice +++ b/cells/or3b/sky130_fd_sc_ms__or3b_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3b_1.pxi.spice -* Created: Fri Aug 28 18:07:57 2020 +* Created: Wed Sep 2 12:28:30 2020 * x_PM_SKY130_FD_SC_MS__OR3B_1%C_N N_C_N_c_75_n N_C_N_M1008_g N_C_N_M1007_g + N_C_N_c_77_n C_N C_N N_C_N_c_78_n N_C_N_c_79_n PM_SKY130_FD_SC_MS__OR3B_1%C_N
diff --git a/cells/or3b/sky130_fd_sc_ms__or3b_1.spice b/cells/or3b/sky130_fd_sc_ms__or3b_1.spice index 7cabd24..a75a7a7 100644 --- a/cells/or3b/sky130_fd_sc_ms__or3b_1.spice +++ b/cells/or3b/sky130_fd_sc_ms__or3b_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3b_1.spice -* Created: Fri Aug 28 18:07:57 2020 +* Created: Wed Sep 2 12:28:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or3b/sky130_fd_sc_ms__or3b_2.lvs.report b/cells/or3b/sky130_fd_sc_ms__or3b_2.lvs.report new file mode 100644 index 0000000..96ec880 --- /dev/null +++ b/cells/or3b/sky130_fd_sc_ms__or3b_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or3b_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or3b_2.sp ('sky130_fd_sc_ms__or3b_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or3b/sky130_fd_sc_ms__or3b_2.spice ('sky130_fd_sc_ms__or3b_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:28:34 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or3b_2 sky130_fd_sc_ms__or3b_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or3b_2 +SOURCE CELL NAME: sky130_fd_sc_ms__or3b_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP3 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C_N A B VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or3b/sky130_fd_sc_ms__or3b_2.pex.spice b/cells/or3b/sky130_fd_sc_ms__or3b_2.pex.spice index 6488b63..ab93ec4 100644 --- a/cells/or3b/sky130_fd_sc_ms__or3b_2.pex.spice +++ b/cells/or3b/sky130_fd_sc_ms__or3b_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3b_2.pex.spice -* Created: Fri Aug 28 18:08:27 2020 +* Created: Wed Sep 2 12:28:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or3b/sky130_fd_sc_ms__or3b_2.pxi.spice b/cells/or3b/sky130_fd_sc_ms__or3b_2.pxi.spice index 555144b..77ff52f 100644 --- a/cells/or3b/sky130_fd_sc_ms__or3b_2.pxi.spice +++ b/cells/or3b/sky130_fd_sc_ms__or3b_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3b_2.pxi.spice -* Created: Fri Aug 28 18:08:27 2020 +* Created: Wed Sep 2 12:28:37 2020 * x_PM_SKY130_FD_SC_MS__OR3B_2%C_N N_C_N_c_70_n N_C_N_M1002_g N_C_N_M1005_g C_N + N_C_N_c_72_n PM_SKY130_FD_SC_MS__OR3B_2%C_N
diff --git a/cells/or3b/sky130_fd_sc_ms__or3b_2.spice b/cells/or3b/sky130_fd_sc_ms__or3b_2.spice index b0559ca..e779dd6 100644 --- a/cells/or3b/sky130_fd_sc_ms__or3b_2.spice +++ b/cells/or3b/sky130_fd_sc_ms__or3b_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3b_2.spice -* Created: Fri Aug 28 18:08:27 2020 +* Created: Wed Sep 2 12:28:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or3b/sky130_fd_sc_ms__or3b_4.lvs.report b/cells/or3b/sky130_fd_sc_ms__or3b_4.lvs.report new file mode 100644 index 0000000..eabb631 --- /dev/null +++ b/cells/or3b/sky130_fd_sc_ms__or3b_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or3b_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or3b_4.sp ('sky130_fd_sc_ms__or3b_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or3b/sky130_fd_sc_ms__or3b_4.spice ('sky130_fd_sc_ms__or3b_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:28:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or3b_4 sky130_fd_sc_ms__or3b_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or3b_4 +SOURCE CELL NAME: sky130_fd_sc_ms__or3b_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 12 12 + + Instances: 8 8 MN (4 pins) + 11 11 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 20 19 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP3 (5 pins) + ------ ------ + Total Inst: 8 8 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 10 10 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP3 + ------- ------- --------- --------- + Total Inst: 8 8 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 14 layout mos transistors were reduced to 5. + 9 mos transistors were deleted by parallel reduction. + 14 source mos transistors were reduced to 5. + 9 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB C_N A B VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or3b/sky130_fd_sc_ms__or3b_4.pex.spice b/cells/or3b/sky130_fd_sc_ms__or3b_4.pex.spice index 75ccbcf..fad1de7 100644 --- a/cells/or3b/sky130_fd_sc_ms__or3b_4.pex.spice +++ b/cells/or3b/sky130_fd_sc_ms__or3b_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3b_4.pex.spice -* Created: Fri Aug 28 18:08:37 2020 +* Created: Wed Sep 2 12:28:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or3b/sky130_fd_sc_ms__or3b_4.pxi.spice b/cells/or3b/sky130_fd_sc_ms__or3b_4.pxi.spice index 638b26f..fa101f1 100644 --- a/cells/or3b/sky130_fd_sc_ms__or3b_4.pxi.spice +++ b/cells/or3b/sky130_fd_sc_ms__or3b_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3b_4.pxi.spice -* Created: Fri Aug 28 18:08:37 2020 +* Created: Wed Sep 2 12:28:44 2020 * x_PM_SKY130_FD_SC_MS__OR3B_4%C_N N_C_N_c_114_n N_C_N_M1005_g N_C_N_M1015_g C_N + N_C_N_c_117_n N_C_N_c_118_n N_C_N_c_119_n PM_SKY130_FD_SC_MS__OR3B_4%C_N
diff --git a/cells/or3b/sky130_fd_sc_ms__or3b_4.spice b/cells/or3b/sky130_fd_sc_ms__or3b_4.spice index e865f82..a7c46a6 100644 --- a/cells/or3b/sky130_fd_sc_ms__or3b_4.spice +++ b/cells/or3b/sky130_fd_sc_ms__or3b_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or3b_4.spice -* Created: Fri Aug 28 18:08:37 2020 +* Created: Wed Sep 2 12:28:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or4/sky130_fd_sc_ms__or4_1.lvs.report b/cells/or4/sky130_fd_sc_ms__or4_1.lvs.report new file mode 100644 index 0000000..1f53417 --- /dev/null +++ b/cells/or4/sky130_fd_sc_ms__or4_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or4_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or4_1.sp ('sky130_fd_sc_ms__or4_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or4/sky130_fd_sc_ms__or4_1.spice ('sky130_fd_sc_ms__or4_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:28:47 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or4_1 sky130_fd_sc_ms__or4_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or4_1 +SOURCE CELL NAME: sky130_fd_sc_ms__or4_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D C B A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or4/sky130_fd_sc_ms__or4_1.pex.spice b/cells/or4/sky130_fd_sc_ms__or4_1.pex.spice index d6faff6..0a3d690 100644 --- a/cells/or4/sky130_fd_sc_ms__or4_1.pex.spice +++ b/cells/or4/sky130_fd_sc_ms__or4_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4_1.pex.spice -* Created: Fri Aug 28 18:08:47 2020 +* Created: Wed Sep 2 12:28:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or4/sky130_fd_sc_ms__or4_1.pxi.spice b/cells/or4/sky130_fd_sc_ms__or4_1.pxi.spice index 1e7a8dd..bdfbccb 100644 --- a/cells/or4/sky130_fd_sc_ms__or4_1.pxi.spice +++ b/cells/or4/sky130_fd_sc_ms__or4_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4_1.pxi.spice -* Created: Fri Aug 28 18:08:47 2020 +* Created: Wed Sep 2 12:28:51 2020 * x_PM_SKY130_FD_SC_MS__OR4_1%D N_D_M1003_g N_D_c_63_n N_D_M1001_g D N_D_c_64_n + PM_SKY130_FD_SC_MS__OR4_1%D
diff --git a/cells/or4/sky130_fd_sc_ms__or4_1.spice b/cells/or4/sky130_fd_sc_ms__or4_1.spice index a9527d2..fbbcf7e 100644 --- a/cells/or4/sky130_fd_sc_ms__or4_1.spice +++ b/cells/or4/sky130_fd_sc_ms__or4_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4_1.spice -* Created: Fri Aug 28 18:08:47 2020 +* Created: Wed Sep 2 12:28:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or4/sky130_fd_sc_ms__or4_2.lvs.report b/cells/or4/sky130_fd_sc_ms__or4_2.lvs.report new file mode 100644 index 0000000..a75fbd4 --- /dev/null +++ b/cells/or4/sky130_fd_sc_ms__or4_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or4_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or4_2.sp ('sky130_fd_sc_ms__or4_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or4/sky130_fd_sc_ms__or4_2.spice ('sky130_fd_sc_ms__or4_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:28:54 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or4_2 sky130_fd_sc_ms__or4_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or4_2 +SOURCE CELL NAME: sky130_fd_sc_ms__or4_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D C B A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or4/sky130_fd_sc_ms__or4_2.pex.spice b/cells/or4/sky130_fd_sc_ms__or4_2.pex.spice index 5848b9e..69623aa 100644 --- a/cells/or4/sky130_fd_sc_ms__or4_2.pex.spice +++ b/cells/or4/sky130_fd_sc_ms__or4_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4_2.pex.spice -* Created: Fri Aug 28 18:08:56 2020 +* Created: Wed Sep 2 12:28:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or4/sky130_fd_sc_ms__or4_2.pxi.spice b/cells/or4/sky130_fd_sc_ms__or4_2.pxi.spice index 3d7d3a4..3c619ee 100644 --- a/cells/or4/sky130_fd_sc_ms__or4_2.pxi.spice +++ b/cells/or4/sky130_fd_sc_ms__or4_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4_2.pxi.spice -* Created: Fri Aug 28 18:08:56 2020 +* Created: Wed Sep 2 12:28:58 2020 * x_PM_SKY130_FD_SC_MS__OR4_2%D N_D_M1004_g N_D_c_69_n N_D_M1010_g D + PM_SKY130_FD_SC_MS__OR4_2%D
diff --git a/cells/or4/sky130_fd_sc_ms__or4_2.spice b/cells/or4/sky130_fd_sc_ms__or4_2.spice index 57499cc..1eece23 100644 --- a/cells/or4/sky130_fd_sc_ms__or4_2.spice +++ b/cells/or4/sky130_fd_sc_ms__or4_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4_2.spice -* Created: Fri Aug 28 18:08:56 2020 +* Created: Wed Sep 2 12:28:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or4/sky130_fd_sc_ms__or4_4.lvs.report b/cells/or4/sky130_fd_sc_ms__or4_4.lvs.report new file mode 100644 index 0000000..9a64be6 --- /dev/null +++ b/cells/or4/sky130_fd_sc_ms__or4_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or4_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or4_4.sp ('sky130_fd_sc_ms__or4_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or4/sky130_fd_sc_ms__or4_4.spice ('sky130_fd_sc_ms__or4_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:29:01 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or4_4 sky130_fd_sc_ms__or4_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or4_4 +SOURCE CELL NAME: sky130_fd_sc_ms__or4_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 13 13 + + Instances: 8 8 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 21 20 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 10 10 + + Instances: 5 5 MN (4 pins) + 1 1 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 7 7 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 10 10 0 0 + + Instances: 5 5 0 0 MN(NLOWVT) + 1 1 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 7 7 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A C D VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or4/sky130_fd_sc_ms__or4_4.pex.spice b/cells/or4/sky130_fd_sc_ms__or4_4.pex.spice index af78c62..d361b77 100644 --- a/cells/or4/sky130_fd_sc_ms__or4_4.pex.spice +++ b/cells/or4/sky130_fd_sc_ms__or4_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4_4.pex.spice -* Created: Fri Aug 28 18:09:05 2020 +* Created: Wed Sep 2 12:29:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or4/sky130_fd_sc_ms__or4_4.pxi.spice b/cells/or4/sky130_fd_sc_ms__or4_4.pxi.spice index 10f2a65..9593ed7 100644 --- a/cells/or4/sky130_fd_sc_ms__or4_4.pxi.spice +++ b/cells/or4/sky130_fd_sc_ms__or4_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4_4.pxi.spice -* Created: Fri Aug 28 18:09:05 2020 +* Created: Wed Sep 2 12:29:04 2020 * x_PM_SKY130_FD_SC_MS__OR4_4%A_83_264# N_A_83_264#_M1004_d N_A_83_264#_M1015_d + N_A_83_264#_M1000_d N_A_83_264#_M1005_g N_A_83_264#_M1001_g
diff --git a/cells/or4/sky130_fd_sc_ms__or4_4.spice b/cells/or4/sky130_fd_sc_ms__or4_4.spice index ec2ddbf..65782cc 100644 --- a/cells/or4/sky130_fd_sc_ms__or4_4.spice +++ b/cells/or4/sky130_fd_sc_ms__or4_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4_4.spice -* Created: Fri Aug 28 18:09:05 2020 +* Created: Wed Sep 2 12:29:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or4b/sky130_fd_sc_ms__or4b_1.lvs.report b/cells/or4b/sky130_fd_sc_ms__or4b_1.lvs.report new file mode 100644 index 0000000..d3f61b5 --- /dev/null +++ b/cells/or4b/sky130_fd_sc_ms__or4b_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or4b_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or4b_1.sp ('sky130_fd_sc_ms__or4b_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or4b/sky130_fd_sc_ms__or4b_1.spice ('sky130_fd_sc_ms__or4b_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:29:08 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or4b_1 sky130_fd_sc_ms__or4b_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or4b_1 +SOURCE CELL NAME: sky130_fd_sc_ms__or4b_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 6 6 MN (4 pins) + 6 6 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 13 12 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 6 6 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 9 9 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 6 6 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 9 9 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D_N C B A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or4b/sky130_fd_sc_ms__or4b_1.pex.spice b/cells/or4b/sky130_fd_sc_ms__or4b_1.pex.spice index 97c26b9..1566d7f 100644 --- a/cells/or4b/sky130_fd_sc_ms__or4b_1.pex.spice +++ b/cells/or4b/sky130_fd_sc_ms__or4b_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4b_1.pex.spice -* Created: Fri Aug 28 18:09:35 2020 +* Created: Wed Sep 2 12:29:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or4b/sky130_fd_sc_ms__or4b_1.pxi.spice b/cells/or4b/sky130_fd_sc_ms__or4b_1.pxi.spice index aab2c04..877e299 100644 --- a/cells/or4b/sky130_fd_sc_ms__or4b_1.pxi.spice +++ b/cells/or4b/sky130_fd_sc_ms__or4b_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4b_1.pxi.spice -* Created: Fri Aug 28 18:09:35 2020 +* Created: Wed Sep 2 12:29:11 2020 * x_PM_SKY130_FD_SC_MS__OR4B_1%D_N N_D_N_M1008_g N_D_N_c_80_n N_D_N_M1001_g D_N + N_D_N_c_81_n PM_SKY130_FD_SC_MS__OR4B_1%D_N
diff --git a/cells/or4b/sky130_fd_sc_ms__or4b_1.spice b/cells/or4b/sky130_fd_sc_ms__or4b_1.spice index e0d8e7e..e060ff2 100644 --- a/cells/or4b/sky130_fd_sc_ms__or4b_1.spice +++ b/cells/or4b/sky130_fd_sc_ms__or4b_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4b_1.spice -* Created: Fri Aug 28 18:09:35 2020 +* Created: Wed Sep 2 12:29:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or4b/sky130_fd_sc_ms__or4b_2.lvs.report b/cells/or4b/sky130_fd_sc_ms__or4b_2.lvs.report new file mode 100644 index 0000000..7977cb6 --- /dev/null +++ b/cells/or4b/sky130_fd_sc_ms__or4b_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or4b_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or4b_2.sp ('sky130_fd_sc_ms__or4b_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or4b/sky130_fd_sc_ms__or4b_2.spice ('sky130_fd_sc_ms__or4b_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:29:14 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or4b_2 sky130_fd_sc_ms__or4b_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or4b_2 +SOURCE CELL NAME: sky130_fd_sc_ms__or4b_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 6 6 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 9 9 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 6 6 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 9 9 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D_N A B C VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or4b/sky130_fd_sc_ms__or4b_2.pex.spice b/cells/or4b/sky130_fd_sc_ms__or4b_2.pex.spice index ba0c839..dd3b8b0 100644 --- a/cells/or4b/sky130_fd_sc_ms__or4b_2.pex.spice +++ b/cells/or4b/sky130_fd_sc_ms__or4b_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4b_2.pex.spice -* Created: Fri Aug 28 18:09:45 2020 +* Created: Wed Sep 2 12:29:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or4b/sky130_fd_sc_ms__or4b_2.pxi.spice b/cells/or4b/sky130_fd_sc_ms__or4b_2.pxi.spice index a360212..6ab8429 100644 --- a/cells/or4b/sky130_fd_sc_ms__or4b_2.pxi.spice +++ b/cells/or4b/sky130_fd_sc_ms__or4b_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4b_2.pxi.spice -* Created: Fri Aug 28 18:09:45 2020 +* Created: Wed Sep 2 12:29:17 2020 * x_PM_SKY130_FD_SC_MS__OR4B_2%D_N N_D_N_c_84_n N_D_N_M1003_g N_D_N_M1010_g D_N + N_D_N_c_86_n PM_SKY130_FD_SC_MS__OR4B_2%D_N
diff --git a/cells/or4b/sky130_fd_sc_ms__or4b_2.spice b/cells/or4b/sky130_fd_sc_ms__or4b_2.spice index b93e262..efbf33f 100644 --- a/cells/or4b/sky130_fd_sc_ms__or4b_2.spice +++ b/cells/or4b/sky130_fd_sc_ms__or4b_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4b_2.spice -* Created: Fri Aug 28 18:09:45 2020 +* Created: Wed Sep 2 12:29:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or4b/sky130_fd_sc_ms__or4b_4.lvs.report b/cells/or4b/sky130_fd_sc_ms__or4b_4.lvs.report new file mode 100644 index 0000000..384149b --- /dev/null +++ b/cells/or4b/sky130_fd_sc_ms__or4b_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or4b_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or4b_4.sp ('sky130_fd_sc_ms__or4b_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or4b/sky130_fd_sc_ms__or4b_4.spice ('sky130_fd_sc_ms__or4b_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:29:21 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or4b_4 sky130_fd_sc_ms__or4b_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or4b_4 +SOURCE CELL NAME: sky130_fd_sc_ms__or4b_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 14 14 + + Instances: 9 9 MN (4 pins) + 13 13 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 11 11 + + Instances: 6 6 MN (4 pins) + 2 2 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 9 9 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 11 11 0 0 + + Instances: 6 6 0 0 MN(NLOWVT) + 2 2 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 9 9 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A C D_N VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or4b/sky130_fd_sc_ms__or4b_4.pex.spice b/cells/or4b/sky130_fd_sc_ms__or4b_4.pex.spice index b73b774..f5bb35f 100644 --- a/cells/or4b/sky130_fd_sc_ms__or4b_4.pex.spice +++ b/cells/or4b/sky130_fd_sc_ms__or4b_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4b_4.pex.spice -* Created: Fri Aug 28 18:09:54 2020 +* Created: Wed Sep 2 12:29:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or4b/sky130_fd_sc_ms__or4b_4.pxi.spice b/cells/or4b/sky130_fd_sc_ms__or4b_4.pxi.spice index 474c313..7671cfc 100644 --- a/cells/or4b/sky130_fd_sc_ms__or4b_4.pxi.spice +++ b/cells/or4b/sky130_fd_sc_ms__or4b_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4b_4.pxi.spice -* Created: Fri Aug 28 18:09:54 2020 +* Created: Wed Sep 2 12:29:24 2020 * x_PM_SKY130_FD_SC_MS__OR4B_4%B N_B_M1001_g N_B_M1018_g N_B_M1005_g N_B_c_132_n + N_B_c_133_n N_B_c_134_n B B N_B_c_135_n N_B_c_136_n N_B_c_137_n N_B_c_138_n
diff --git a/cells/or4b/sky130_fd_sc_ms__or4b_4.spice b/cells/or4b/sky130_fd_sc_ms__or4b_4.spice index 4159f4a..54916e7 100644 --- a/cells/or4b/sky130_fd_sc_ms__or4b_4.spice +++ b/cells/or4b/sky130_fd_sc_ms__or4b_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4b_4.spice -* Created: Fri Aug 28 18:09:54 2020 +* Created: Wed Sep 2 12:29:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or4bb/sky130_fd_sc_ms__or4bb_1.lvs.report b/cells/or4bb/sky130_fd_sc_ms__or4bb_1.lvs.report new file mode 100644 index 0000000..0a142e0 --- /dev/null +++ b/cells/or4bb/sky130_fd_sc_ms__or4bb_1.lvs.report
@@ -0,0 +1,466 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or4bb_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or4bb_1.sp ('sky130_fd_sc_ms__or4bb_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or4bb/sky130_fd_sc_ms__or4bb_1.spice ('sky130_fd_sc_ms__or4bb_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:29:28 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or4bb_1 sky130_fd_sc_ms__or4bb_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or4bb_1 +SOURCE CELL NAME: sky130_fd_sc_ms__or4bb_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 15 15 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 15 14 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 7 7 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 11 11 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 12 12 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 11 11 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C_N D_N B A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or4bb/sky130_fd_sc_ms__or4bb_1.pex.spice b/cells/or4bb/sky130_fd_sc_ms__or4bb_1.pex.spice index 8009b18..72a31ac 100644 --- a/cells/or4bb/sky130_fd_sc_ms__or4bb_1.pex.spice +++ b/cells/or4bb/sky130_fd_sc_ms__or4bb_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4bb_1.pex.spice -* Created: Fri Aug 28 18:10:03 2020 +* Created: Wed Sep 2 12:29:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or4bb/sky130_fd_sc_ms__or4bb_1.pxi.spice b/cells/or4bb/sky130_fd_sc_ms__or4bb_1.pxi.spice index aad37bc..661b5f7 100644 --- a/cells/or4bb/sky130_fd_sc_ms__or4bb_1.pxi.spice +++ b/cells/or4bb/sky130_fd_sc_ms__or4bb_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4bb_1.pxi.spice -* Created: Fri Aug 28 18:10:03 2020 +* Created: Wed Sep 2 12:29:31 2020 * x_PM_SKY130_FD_SC_MS__OR4BB_1%C_N N_C_N_M1005_g N_C_N_M1004_g C_N N_C_N_c_95_n + N_C_N_c_96_n PM_SKY130_FD_SC_MS__OR4BB_1%C_N
diff --git a/cells/or4bb/sky130_fd_sc_ms__or4bb_1.spice b/cells/or4bb/sky130_fd_sc_ms__or4bb_1.spice index 00b4b67..0097dc5 100644 --- a/cells/or4bb/sky130_fd_sc_ms__or4bb_1.spice +++ b/cells/or4bb/sky130_fd_sc_ms__or4bb_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4bb_1.spice -* Created: Fri Aug 28 18:10:03 2020 +* Created: Wed Sep 2 12:29:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or4bb/sky130_fd_sc_ms__or4bb_2.lvs.report b/cells/or4bb/sky130_fd_sc_ms__or4bb_2.lvs.report new file mode 100644 index 0000000..c01c0b9 --- /dev/null +++ b/cells/or4bb/sky130_fd_sc_ms__or4bb_2.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or4bb_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or4bb_2.sp ('sky130_fd_sc_ms__or4bb_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or4bb/sky130_fd_sc_ms__or4bb_2.spice ('sky130_fd_sc_ms__or4bb_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:29:34 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or4bb_2 sky130_fd_sc_ms__or4bb_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or4bb_2 +SOURCE CELL NAME: sky130_fd_sc_ms__or4bb_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 15 15 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 7 7 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 11 11 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 12 12 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 11 11 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D_N B A C_N VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or4bb/sky130_fd_sc_ms__or4bb_2.pex.spice b/cells/or4bb/sky130_fd_sc_ms__or4bb_2.pex.spice index 88e3be2..f728d21 100644 --- a/cells/or4bb/sky130_fd_sc_ms__or4bb_2.pex.spice +++ b/cells/or4bb/sky130_fd_sc_ms__or4bb_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4bb_2.pex.spice -* Created: Fri Aug 28 18:10:12 2020 +* Created: Wed Sep 2 12:29:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or4bb/sky130_fd_sc_ms__or4bb_2.pxi.spice b/cells/or4bb/sky130_fd_sc_ms__or4bb_2.pxi.spice index df55546..9f1982a 100644 --- a/cells/or4bb/sky130_fd_sc_ms__or4bb_2.pxi.spice +++ b/cells/or4bb/sky130_fd_sc_ms__or4bb_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4bb_2.pxi.spice -* Created: Fri Aug 28 18:10:12 2020 +* Created: Wed Sep 2 12:29:37 2020 * x_PM_SKY130_FD_SC_MS__OR4BB_2%D_N N_D_N_c_96_n N_D_N_M1015_g N_D_N_c_97_n + N_D_N_M1008_g D_N N_D_N_c_98_n PM_SKY130_FD_SC_MS__OR4BB_2%D_N
diff --git a/cells/or4bb/sky130_fd_sc_ms__or4bb_2.spice b/cells/or4bb/sky130_fd_sc_ms__or4bb_2.spice index 42196f6..19d0100 100644 --- a/cells/or4bb/sky130_fd_sc_ms__or4bb_2.spice +++ b/cells/or4bb/sky130_fd_sc_ms__or4bb_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4bb_2.spice -* Created: Fri Aug 28 18:10:12 2020 +* Created: Wed Sep 2 12:29:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/or4bb/sky130_fd_sc_ms__or4bb_4.lvs.report b/cells/or4bb/sky130_fd_sc_ms__or4bb_4.lvs.report new file mode 100644 index 0000000..a14938d --- /dev/null +++ b/cells/or4bb/sky130_fd_sc_ms__or4bb_4.lvs.report
@@ -0,0 +1,471 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__or4bb_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__or4bb_4.sp ('sky130_fd_sc_ms__or4bb_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/or4bb/sky130_fd_sc_ms__or4bb_4.spice ('sky130_fd_sc_ms__or4bb_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:29:41 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__or4bb_4 sky130_fd_sc_ms__or4bb_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__or4bb_4 +SOURCE CELL NAME: sky130_fd_sc_ms__or4bb_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 15 15 + + Instances: 10 10 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 12 12 + + Instances: 7 7 MN (4 pins) + 3 3 MP (4 pins) + 1 1 SMP4 (6 pins) + ------ ------ + Total Inst: 11 11 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 12 12 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMP4 + ------- ------- --------- --------- + Total Inst: 11 11 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 6. + 10 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D_N C_N B A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/or4bb/sky130_fd_sc_ms__or4bb_4.pex.spice b/cells/or4bb/sky130_fd_sc_ms__or4bb_4.pex.spice index c076f68..b47a68a 100644 --- a/cells/or4bb/sky130_fd_sc_ms__or4bb_4.pex.spice +++ b/cells/or4bb/sky130_fd_sc_ms__or4bb_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4bb_4.pex.spice -* Created: Fri Aug 28 18:10:42 2020 +* Created: Wed Sep 2 12:29:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/or4bb/sky130_fd_sc_ms__or4bb_4.pxi.spice b/cells/or4bb/sky130_fd_sc_ms__or4bb_4.pxi.spice index 5dde7dd..99c4bc4 100644 --- a/cells/or4bb/sky130_fd_sc_ms__or4bb_4.pxi.spice +++ b/cells/or4bb/sky130_fd_sc_ms__or4bb_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4bb_4.pxi.spice -* Created: Fri Aug 28 18:10:42 2020 +* Created: Wed Sep 2 12:29:44 2020 * x_PM_SKY130_FD_SC_MS__OR4BB_4%D_N N_D_N_M1011_g N_D_N_M1008_g D_N N_D_N_c_138_n + N_D_N_c_139_n PM_SKY130_FD_SC_MS__OR4BB_4%D_N
diff --git a/cells/or4bb/sky130_fd_sc_ms__or4bb_4.spice b/cells/or4bb/sky130_fd_sc_ms__or4bb_4.spice index 57b9e88..27901ef 100644 --- a/cells/or4bb/sky130_fd_sc_ms__or4bb_4.spice +++ b/cells/or4bb/sky130_fd_sc_ms__or4bb_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__or4bb_4.spice -* Created: Fri Aug 28 18:10:42 2020 +* Created: Wed Sep 2 12:29:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.lvs.report b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.lvs.report new file mode 100644 index 0000000..e0145c8 --- /dev/null +++ b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfbbn_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfbbn_1.sp ('sky130_fd_sc_ms__sdfbbn_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.spice ('sky130_fd_sc_ms__sdfbbn_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:29:48 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfbbn_1 sky130_fd_sc_ms__sdfbbn_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfbbn_1 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfbbn_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 12 12 + + Nets: 36 36 + + Instances: 24 24 MN (4 pins) + 24 24 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 49 48 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 12 12 + + Nets: 22 22 + + Instances: 8 8 MN (4 pins) + 10 10 MP (4 pins) + 5 5 SMN2 (4 pins) + 7 7 SMP2 (4 pins) + 2 2 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 32 32 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 12 12 0 0 + + Nets: 22 22 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 5 5 0 0 SMN2 + 7 7 0 0 SMP2 + 2 2 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 32 32 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCD D SCE CLK_N SET_B RESET_B VPWR Q_N Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.pex.spice b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.pex.spice index 1f6a3d9..8c68694 100644 --- a/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.pex.spice +++ b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfbbn_1.pex.spice -* Created: Fri Aug 28 18:10:52 2020 +* Created: Wed Sep 2 12:29:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.pxi.spice b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.pxi.spice index bcdb286..e99701e 100644 --- a/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.pxi.spice +++ b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfbbn_1.pxi.spice -* Created: Fri Aug 28 18:10:52 2020 +* Created: Wed Sep 2 12:29:52 2020 * x_PM_SKY130_FD_SC_MS__SDFBBN_1%SCD N_SCD_c_377_n N_SCD_M1008_g N_SCD_M1006_g + N_SCD_c_383_n SCD N_SCD_c_379_n N_SCD_c_380_n PM_SKY130_FD_SC_MS__SDFBBN_1%SCD
diff --git a/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.spice b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.spice index 73feb42..178759f 100644 --- a/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.spice +++ b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfbbn_1.spice -* Created: Fri Aug 28 18:10:52 2020 +* Created: Wed Sep 2 12:29:52 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.lvs.report b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.lvs.report new file mode 100644 index 0000000..e2f3f72 --- /dev/null +++ b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfbbn_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfbbn_2.sp ('sky130_fd_sc_ms__sdfbbn_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.spice ('sky130_fd_sc_ms__sdfbbn_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:29:55 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfbbn_2 sky130_fd_sc_ms__sdfbbn_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfbbn_2 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfbbn_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 12 12 + + Nets: 36 36 + + Instances: 26 26 MN (4 pins) + 26 26 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 53 52 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 12 12 + + Nets: 22 22 + + Instances: 8 8 MN (4 pins) + 10 10 MP (4 pins) + 5 5 SMN2 (4 pins) + 7 7 SMP2 (4 pins) + 2 2 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 32 32 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 12 12 0 0 + + Nets: 22 22 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 5 5 0 0 SMN2 + 7 7 0 0 SMP2 + 2 2 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 32 32 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCD D SCE CLK_N SET_B RESET_B VPWR Q_N Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.pex.spice b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.pex.spice index facdea2..9b2648a 100644 --- a/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.pex.spice +++ b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfbbn_2.pex.spice -* Created: Fri Aug 28 18:11:01 2020 +* Created: Wed Sep 2 12:29:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.pxi.spice b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.pxi.spice index 68906b5..c70db6a 100644 --- a/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.pxi.spice +++ b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfbbn_2.pxi.spice -* Created: Fri Aug 28 18:11:01 2020 +* Created: Wed Sep 2 12:29:59 2020 * x_PM_SKY130_FD_SC_MS__SDFBBN_2%SCD N_SCD_c_379_n N_SCD_M1012_g N_SCD_M1008_g SCD + SCD N_SCD_c_380_n N_SCD_c_381_n N_SCD_c_382_n N_SCD_c_386_n
diff --git a/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.spice b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.spice index 08578d9..741382e 100644 --- a/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.spice +++ b/cells/sdfbbn/sky130_fd_sc_ms__sdfbbn_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfbbn_2.spice -* Created: Fri Aug 28 18:11:01 2020 +* Created: Wed Sep 2 12:29:59 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.lvs.report b/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.lvs.report new file mode 100644 index 0000000..8327a64 --- /dev/null +++ b/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfbbp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfbbp_1.sp ('sky130_fd_sc_ms__sdfbbp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.spice ('sky130_fd_sc_ms__sdfbbp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:30:02 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfbbp_1 sky130_fd_sc_ms__sdfbbp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfbbp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfbbp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 12 12 + + Nets: 36 36 + + Instances: 24 24 MN (4 pins) + 24 24 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 49 48 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 12 12 + + Nets: 22 22 + + Instances: 8 8 MN (4 pins) + 10 10 MP (4 pins) + 5 5 SMN2 (4 pins) + 7 7 SMP2 (4 pins) + 2 2 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 32 32 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 12 12 0 0 + + Nets: 22 22 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 5 5 0 0 SMN2 + 7 7 0 0 SMP2 + 2 2 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 32 32 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCD D SCE CLK SET_B RESET_B VPWR Q_N Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.pex.spice b/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.pex.spice index 509270e..a8fee5c 100644 --- a/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.pex.spice +++ b/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfbbp_1.pex.spice -* Created: Fri Aug 28 18:11:11 2020 +* Created: Wed Sep 2 12:30:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.pxi.spice b/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.pxi.spice index 75c1070..61932b5 100644 --- a/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.pxi.spice +++ b/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfbbp_1.pxi.spice -* Created: Fri Aug 28 18:11:11 2020 +* Created: Wed Sep 2 12:30:05 2020 * x_PM_SKY130_FD_SC_MS__SDFBBP_1%SCD N_SCD_c_331_n N_SCD_M1010_g N_SCD_M1006_g SCD + SCD N_SCD_c_332_n N_SCD_c_333_n N_SCD_c_334_n N_SCD_c_338_n
diff --git a/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.spice b/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.spice index 3f26d70..46fab25 100644 --- a/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.spice +++ b/cells/sdfbbp/sky130_fd_sc_ms__sdfbbp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfbbp_1.spice -* Created: Fri Aug 28 18:11:11 2020 +* Created: Wed Sep 2 12:30:05 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.lvs.report b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.lvs.report new file mode 100644 index 0000000..58aac95 --- /dev/null +++ b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.lvs.report
@@ -0,0 +1,472 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfrbp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfrbp_1.sp ('sky130_fd_sc_ms__sdfrbp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.spice ('sky130_fd_sc_ms__sdfrbp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:30:09 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfrbp_1 sky130_fd_sc_ms__sdfrbp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfrbp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfrbp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 31 31 + + Instances: 21 21 MN (4 pins) + 21 21 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 43 42 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 20 20 + + Instances: 9 9 MN (4 pins) + 13 13 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 4 4 SMP2 (4 pins) + 1 1 SPMN((2+2)*1) (7 pins) + ------ ------ + Total Inst: 30 30 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 11 11 0 0 + + Nets: 20 20 0 0 + + Instances: 9 9 0 0 MN(NLOWVT) + 13 13 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SMN3 + 4 4 0 0 SMP2 + 1 1 0 0 SPMN((2+2)*1) + ------- ------- --------- --------- + Total Inst: 30 30 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK RESET_B VPWR Q_N Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.pex.spice b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.pex.spice index 9539f16..64fa1f9 100644 --- a/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.pex.spice +++ b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrbp_1.pex.spice -* Created: Fri Aug 28 18:11:20 2020 +* Created: Wed Sep 2 12:30:12 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.pxi.spice b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.pxi.spice index 031813e..ea3b41c 100644 --- a/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.pxi.spice +++ b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrbp_1.pxi.spice -* Created: Fri Aug 28 18:11:20 2020 +* Created: Wed Sep 2 12:30:12 2020 * x_PM_SKY130_FD_SC_MS__SDFRBP_1%A_27_74# N_A_27_74#_M1038_s N_A_27_74#_M1018_s + N_A_27_74#_c_289_n N_A_27_74#_M1023_g N_A_27_74#_M1030_g N_A_27_74#_c_290_n
diff --git a/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.spice b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.spice index 7a5d7f1..739d526 100644 --- a/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.spice +++ b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrbp_1.spice -* Created: Fri Aug 28 18:11:20 2020 +* Created: Wed Sep 2 12:30:12 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.lvs.report b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.lvs.report new file mode 100644 index 0000000..c7b4b02 --- /dev/null +++ b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.lvs.report
@@ -0,0 +1,477 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfrbp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfrbp_2.sp ('sky130_fd_sc_ms__sdfrbp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.spice ('sky130_fd_sc_ms__sdfrbp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:30:16 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfrbp_2 sky130_fd_sc_ms__sdfrbp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfrbp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfrbp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 31 31 + + Instances: 23 23 MN (4 pins) + 23 23 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 47 46 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 20 20 + + Instances: 9 9 MN (4 pins) + 13 13 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 4 4 SMP2 (4 pins) + 1 1 SPMN((2+2)*1) (7 pins) + ------ ------ + Total Inst: 30 30 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 11 11 0 0 + + Nets: 20 20 0 0 + + Instances: 9 9 0 0 MN(NLOWVT) + 13 13 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SMN3 + 4 4 0 0 SMP2 + 1 1 0 0 SPMN((2+2)*1) + ------- ------- --------- --------- + Total Inst: 30 30 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK RESET_B VPWR Q_N Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.pex.spice b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.pex.spice index 064f3fb..1673313 100644 --- a/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.pex.spice +++ b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrbp_2.pex.spice -* Created: Fri Aug 28 18:11:50 2020 +* Created: Wed Sep 2 12:30:19 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.pxi.spice b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.pxi.spice index e6a6b64..1d6460d 100644 --- a/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.pxi.spice +++ b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrbp_2.pxi.spice -* Created: Fri Aug 28 18:11:50 2020 +* Created: Wed Sep 2 12:30:19 2020 * x_PM_SKY130_FD_SC_MS__SDFRBP_2%SCE N_SCE_c_285_n N_SCE_M1009_g N_SCE_c_286_n + N_SCE_M1030_g N_SCE_c_295_n N_SCE_M1039_g N_SCE_M1031_g N_SCE_c_288_n
diff --git a/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.spice b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.spice index a7a3782..3f46987 100644 --- a/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.spice +++ b/cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrbp_2.spice -* Created: Fri Aug 28 18:11:50 2020 +* Created: Wed Sep 2 12:30:19 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.lvs.report b/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.lvs.report new file mode 100644 index 0000000..1a3138f --- /dev/null +++ b/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.lvs.report
@@ -0,0 +1,472 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfrtn_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfrtn_1.sp ('sky130_fd_sc_ms__sdfrtn_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.spice ('sky130_fd_sc_ms__sdfrtn_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:30:22 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfrtn_1 sky130_fd_sc_ms__sdfrtn_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfrtn_1 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfrtn_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 30 30 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 19 19 + + Instances: 8 8 MN (4 pins) + 12 12 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 4 4 SMP2 (4 pins) + 1 1 SPMN((2+2)*1) (7 pins) + ------ ------ + Total Inst: 28 28 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 19 19 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 12 12 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SMN3 + 4 4 0 0 SMP2 + 1 1 0 0 SPMN((2+2)*1) + ------- ------- --------- --------- + Total Inst: 28 28 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK_N RESET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.pex.spice b/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.pex.spice index a811248..8377db5 100644 --- a/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.pex.spice +++ b/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrtn_1.pex.spice -* Created: Fri Aug 28 18:12:01 2020 +* Created: Wed Sep 2 12:30:26 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.pxi.spice b/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.pxi.spice index 0c79cb7..a1c7cda 100644 --- a/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.pxi.spice +++ b/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrtn_1.pxi.spice -* Created: Fri Aug 28 18:12:01 2020 +* Created: Wed Sep 2 12:30:26 2020 * x_PM_SKY130_FD_SC_MS__SDFRTN_1%SCE N_SCE_M1011_g N_SCE_M1037_g N_SCE_c_269_n + N_SCE_M1012_g N_SCE_M1006_g N_SCE_c_271_n N_SCE_c_272_n N_SCE_c_273_n
diff --git a/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.spice b/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.spice index 8b1560d..2c43a29 100644 --- a/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.spice +++ b/cells/sdfrtn/sky130_fd_sc_ms__sdfrtn_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrtn_1.spice -* Created: Fri Aug 28 18:12:01 2020 +* Created: Wed Sep 2 12:30:26 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.lvs.report b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.lvs.report new file mode 100644 index 0000000..ffb522b --- /dev/null +++ b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.lvs.report
@@ -0,0 +1,472 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfrtp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfrtp_1.sp ('sky130_fd_sc_ms__sdfrtp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.spice ('sky130_fd_sc_ms__sdfrtp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:30:29 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfrtp_1 sky130_fd_sc_ms__sdfrtp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfrtp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfrtp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 30 30 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 19 19 + + Instances: 8 8 MN (4 pins) + 12 12 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 4 4 SMP2 (4 pins) + 1 1 SPMN((2+2)*1) (7 pins) + ------ ------ + Total Inst: 28 28 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 19 19 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 12 12 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SMN3 + 4 4 0 0 SMP2 + 1 1 0 0 SPMN((2+2)*1) + ------- ------- --------- --------- + Total Inst: 28 28 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK RESET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.pex.spice b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.pex.spice index 026c4d9..1893a01 100644 --- a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.pex.spice +++ b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrtp_1.pex.spice -* Created: Fri Aug 28 18:12:10 2020 +* Created: Wed Sep 2 12:30:33 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.pxi.spice b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.pxi.spice index 8bd0273..cb1b9e6 100644 --- a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.pxi.spice +++ b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrtp_1.pxi.spice -* Created: Fri Aug 28 18:12:10 2020 +* Created: Wed Sep 2 12:30:33 2020 * x_PM_SKY130_FD_SC_MS__SDFRTP_1%SCE N_SCE_M1005_g N_SCE_M1034_g N_SCE_M1002_g + N_SCE_M1025_g N_SCE_c_285_n N_SCE_c_286_n N_SCE_c_287_n N_SCE_c_288_n
diff --git a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.spice b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.spice index 79425e2..4068e5f 100644 --- a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.spice +++ b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrtp_1.spice -* Created: Fri Aug 28 18:12:10 2020 +* Created: Wed Sep 2 12:30:33 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.lvs.report b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.lvs.report new file mode 100644 index 0000000..e5dfbc5 --- /dev/null +++ b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.lvs.report
@@ -0,0 +1,477 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfrtp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfrtp_2.sp ('sky130_fd_sc_ms__sdfrtp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.spice ('sky130_fd_sc_ms__sdfrtp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:30:36 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfrtp_2 sky130_fd_sc_ms__sdfrtp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfrtp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfrtp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 30 30 + + Instances: 21 21 MN (4 pins) + 21 21 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 43 42 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 19 19 + + Instances: 8 8 MN (4 pins) + 12 12 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 4 4 SMP2 (4 pins) + 1 1 SPMN((2+2)*1) (7 pins) + ------ ------ + Total Inst: 28 28 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 19 19 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 12 12 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SMN3 + 4 4 0 0 SMP2 + 1 1 0 0 SPMN((2+2)*1) + ------- ------- --------- --------- + Total Inst: 28 28 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK RESET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.pex.spice b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.pex.spice index c4c835c..35148c3 100644 --- a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.pex.spice +++ b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrtp_2.pex.spice -* Created: Fri Aug 28 18:12:19 2020 +* Created: Wed Sep 2 12:30:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.pxi.spice b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.pxi.spice index 95b8905..cba52d1 100644 --- a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.pxi.spice +++ b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrtp_2.pxi.spice -* Created: Fri Aug 28 18:12:19 2020 +* Created: Wed Sep 2 12:30:39 2020 * x_PM_SKY130_FD_SC_MS__SDFRTP_2%A_27_74# N_A_27_74#_M1036_s N_A_27_74#_M1011_s + N_A_27_74#_c_291_n N_A_27_74#_c_292_n N_A_27_74#_M1014_g N_A_27_74#_M1038_g
diff --git a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.spice b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.spice index 5ed7d31..a1aeea1 100644 --- a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.spice +++ b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrtp_2.spice -* Created: Fri Aug 28 18:12:19 2020 +* Created: Wed Sep 2 12:30:39 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.lvs.report b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.lvs.report new file mode 100644 index 0000000..9b28ce9 --- /dev/null +++ b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.lvs.report
@@ -0,0 +1,477 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfrtp_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfrtp_4.sp ('sky130_fd_sc_ms__sdfrtp_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.spice ('sky130_fd_sc_ms__sdfrtp_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:30:43 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfrtp_4 sky130_fd_sc_ms__sdfrtp_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfrtp_4 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfrtp_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 30 30 + + Instances: 23 23 MN (4 pins) + 24 24 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 48 47 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 19 19 + + Instances: 8 8 MN (4 pins) + 12 12 MP (4 pins) + 2 2 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 4 4 SMP2 (4 pins) + 1 1 SPMN((2+2)*1) (7 pins) + ------ ------ + Total Inst: 28 28 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 19 19 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 12 12 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 1 1 0 0 SMN3 + 4 4 0 0 SMP2 + 1 1 0 0 SPMN((2+2)*1) + ------- ------- --------- --------- + Total Inst: 28 28 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 10 layout mos transistors were reduced to 3. + 7 mos transistors were deleted by parallel reduction. + 10 source mos transistors were reduced to 3. + 7 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK RESET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.pex.spice b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.pex.spice index 44d07d4..4bfb1fc 100644 --- a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.pex.spice +++ b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrtp_4.pex.spice -* Created: Fri Aug 28 18:12:28 2020 +* Created: Wed Sep 2 12:30:46 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.pxi.spice b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.pxi.spice index 69ad4df..43cc517 100644 --- a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.pxi.spice +++ b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrtp_4.pxi.spice -* Created: Fri Aug 28 18:12:28 2020 +* Created: Wed Sep 2 12:30:46 2020 * x_PM_SKY130_FD_SC_MS__SDFRTP_4%A_27_74# N_A_27_74#_M1042_s N_A_27_74#_M1004_s + N_A_27_74#_c_294_n N_A_27_74#_c_295_n N_A_27_74#_M1007_g N_A_27_74#_M1024_g
diff --git a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.spice b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.spice index 98e07c5..5321401 100644 --- a/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.spice +++ b/cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfrtp_4.spice -* Created: Fri Aug 28 18:12:28 2020 +* Created: Wed Sep 2 12:30:46 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.lvs.report b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.lvs.report new file mode 100644 index 0000000..f0aeef1 --- /dev/null +++ b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfsbp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfsbp_1.sp ('sky130_fd_sc_ms__sdfsbp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.spice ('sky130_fd_sc_ms__sdfsbp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:30:50 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfsbp_1 sky130_fd_sc_ms__sdfsbp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfsbp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfsbp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 32 32 + + Instances: 21 21 MN (4 pins) + 21 21 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 43 42 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 20 20 + + Instances: 8 8 MN (4 pins) + 11 11 MP (4 pins) + 5 5 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 5 5 SMP2 (4 pins) + ------ ------ + Total Inst: 30 30 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 11 11 0 0 + + Nets: 20 20 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 11 11 0 0 MP(PSHORT) + 5 5 0 0 SMN2 + 1 1 0 0 SMN3 + 5 5 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 30 30 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q_N Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.pex.spice b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.pex.spice index 7129290..57cf655 100644 --- a/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.pex.spice +++ b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfsbp_1.pex.spice -* Created: Fri Aug 28 18:12:58 2020 +* Created: Wed Sep 2 12:30:54 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.pxi.spice b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.pxi.spice index 20cc43a..7a1b48d 100644 --- a/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.pxi.spice +++ b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfsbp_1.pxi.spice -* Created: Fri Aug 28 18:12:58 2020 +* Created: Wed Sep 2 12:30:54 2020 * x_PM_SKY130_FD_SC_MS__SDFSBP_1%SCE N_SCE_M1010_g N_SCE_M1036_g N_SCE_c_302_n + N_SCE_M1011_g N_SCE_M1015_g N_SCE_c_304_n N_SCE_c_296_n N_SCE_c_297_n
diff --git a/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.spice b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.spice index 49543cc..f8df83b 100644 --- a/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.spice +++ b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfsbp_1.spice -* Created: Fri Aug 28 18:12:58 2020 +* Created: Wed Sep 2 12:30:54 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.lvs.report b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.lvs.report new file mode 100644 index 0000000..8315fdd --- /dev/null +++ b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfsbp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfsbp_2.sp ('sky130_fd_sc_ms__sdfsbp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.spice ('sky130_fd_sc_ms__sdfsbp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:30:57 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfsbp_2 sky130_fd_sc_ms__sdfsbp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfsbp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfsbp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 32 32 + + Instances: 25 25 MN (4 pins) + 25 25 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 51 50 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 20 20 + + Instances: 8 8 MN (4 pins) + 11 11 MP (4 pins) + 5 5 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 5 5 SMP2 (4 pins) + ------ ------ + Total Inst: 30 30 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 11 11 0 0 + + Nets: 20 20 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 11 11 0 0 MP(PSHORT) + 5 5 0 0 SMN2 + 1 1 0 0 SMN3 + 5 5 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 30 30 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 16 layout mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + 16 source mos transistors were reduced to 8. + 8 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q_N Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.pex.spice b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.pex.spice index 509d972..a99af14 100644 --- a/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.pex.spice +++ b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfsbp_2.pex.spice -* Created: Fri Aug 28 18:13:08 2020 +* Created: Wed Sep 2 12:31:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.pxi.spice b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.pxi.spice index 346a910..fd69da0 100644 --- a/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.pxi.spice +++ b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfsbp_2.pxi.spice -* Created: Fri Aug 28 18:13:08 2020 +* Created: Wed Sep 2 12:31:01 2020 * x_PM_SKY130_FD_SC_MS__SDFSBP_2%A_27_74# N_A_27_74#_M1044_s N_A_27_74#_M1009_s + N_A_27_74#_M1037_g N_A_27_74#_M1027_g N_A_27_74#_c_357_n N_A_27_74#_c_358_n
diff --git a/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.spice b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.spice index 1c3ca6c..07c9f45 100644 --- a/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.spice +++ b/cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfsbp_2.spice -* Created: Fri Aug 28 18:13:08 2020 +* Created: Wed Sep 2 12:31:01 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.lvs.report b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.lvs.report new file mode 100644 index 0000000..897e00c --- /dev/null +++ b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.lvs.report
@@ -0,0 +1,470 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfstp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfstp_1.sp ('sky130_fd_sc_ms__sdfstp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.spice ('sky130_fd_sc_ms__sdfstp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:31:04 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfstp_1 sky130_fd_sc_ms__sdfstp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfstp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfstp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 31 31 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 19 19 + + Instances: 7 7 MN (4 pins) + 10 10 MP (4 pins) + 5 5 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 5 5 SMP2 (4 pins) + ------ ------ + Total Inst: 28 28 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 19 19 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 5 5 0 0 SMN2 + 1 1 0 0 SMN3 + 5 5 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 28 28 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.pex.spice b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.pex.spice index 7245464..4728a1b 100644 --- a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.pex.spice +++ b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfstp_1.pex.spice -* Created: Fri Aug 28 18:13:17 2020 +* Created: Wed Sep 2 12:31:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.pxi.spice b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.pxi.spice index e6f2caf..da5bd40 100644 --- a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.pxi.spice +++ b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfstp_1.pxi.spice -* Created: Fri Aug 28 18:13:17 2020 +* Created: Wed Sep 2 12:31:08 2020 * x_PM_SKY130_FD_SC_MS__SDFSTP_1%SCE N_SCE_M1017_g N_SCE_M1025_g N_SCE_c_300_n + N_SCE_M1018_g N_SCE_M1005_g N_SCE_c_293_n N_SCE_c_303_n N_SCE_c_294_n
diff --git a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.spice b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.spice index a937e8a..9b7e0cd 100644 --- a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.spice +++ b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfstp_1.spice -* Created: Fri Aug 28 18:13:17 2020 +* Created: Wed Sep 2 12:31:08 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.lvs.report b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.lvs.report new file mode 100644 index 0000000..358a371 --- /dev/null +++ b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfstp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfstp_2.sp ('sky130_fd_sc_ms__sdfstp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.spice ('sky130_fd_sc_ms__sdfstp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:31:11 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfstp_2 sky130_fd_sc_ms__sdfstp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfstp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfstp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 31 31 + + Instances: 23 23 MN (4 pins) + 23 23 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 47 46 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 19 19 + + Instances: 7 7 MN (4 pins) + 10 10 MP (4 pins) + 5 5 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 5 5 SMP2 (4 pins) + ------ ------ + Total Inst: 28 28 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 19 19 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 5 5 0 0 SMN2 + 1 1 0 0 SMN3 + 5 5 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 28 28 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.pex.spice b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.pex.spice index 19406ae..f420c49 100644 --- a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.pex.spice +++ b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfstp_2.pex.spice -* Created: Fri Aug 28 18:13:26 2020 +* Created: Wed Sep 2 12:31:14 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.pxi.spice b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.pxi.spice index ee62977..70683b3 100644 --- a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.pxi.spice +++ b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfstp_2.pxi.spice -* Created: Fri Aug 28 18:13:26 2020 +* Created: Wed Sep 2 12:31:14 2020 * x_PM_SKY130_FD_SC_MS__SDFSTP_2%SCE N_SCE_c_320_n N_SCE_M1015_g N_SCE_M1043_g + N_SCE_c_322_n N_SCE_M1016_g N_SCE_M1039_g N_SCE_c_315_n N_SCE_c_316_n
diff --git a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.spice b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.spice index ee31db0..dc260f0 100644 --- a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.spice +++ b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfstp_2.spice -* Created: Fri Aug 28 18:13:26 2020 +* Created: Wed Sep 2 12:31:14 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.lvs.report b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.lvs.report new file mode 100644 index 0000000..ee82b55 --- /dev/null +++ b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.lvs.report
@@ -0,0 +1,475 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfstp_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfstp_4.sp ('sky130_fd_sc_ms__sdfstp_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.spice ('sky130_fd_sc_ms__sdfstp_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:31:18 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfstp_4 sky130_fd_sc_ms__sdfstp_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfstp_4 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfstp_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 31 31 + + Instances: 25 25 MN (4 pins) + 26 26 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 52 51 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 19 19 + + Instances: 7 7 MN (4 pins) + 10 10 MP (4 pins) + 5 5 SMN2 (4 pins) + 1 1 SMN3 (5 pins) + 5 5 SMP2 (4 pins) + ------ ------ + Total Inst: 28 28 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 19 19 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 5 5 0 0 SMN2 + 1 1 0 0 SMN3 + 5 5 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 28 28 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 18 layout mos transistors were reduced to 7. + 11 mos transistors were deleted by parallel reduction. + 18 source mos transistors were reduced to 7. + 11 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.pex.spice b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.pex.spice index a993c8e..6d868c4 100644 --- a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.pex.spice +++ b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfstp_4.pex.spice -* Created: Fri Aug 28 18:13:36 2020 +* Created: Wed Sep 2 12:31:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.pxi.spice b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.pxi.spice index cfe9237..3e96854 100644 --- a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.pxi.spice +++ b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfstp_4.pxi.spice -* Created: Fri Aug 28 18:13:36 2020 +* Created: Wed Sep 2 12:31:21 2020 * x_PM_SKY130_FD_SC_MS__SDFSTP_4%SCE N_SCE_M1033_g N_SCE_M1045_g N_SCE_M1034_g + N_SCE_M1016_g N_SCE_c_335_n N_SCE_c_336_n N_SCE_c_337_n SCE N_SCE_c_338_n
diff --git a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.spice b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.spice index 8afcbff..c4afadb 100644 --- a/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.spice +++ b/cells/sdfstp/sky130_fd_sc_ms__sdfstp_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfstp_4.spice -* Created: Fri Aug 28 18:13:36 2020 +* Created: Wed Sep 2 12:31:21 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.lvs.report b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.lvs.report new file mode 100644 index 0000000..c2f5cb6 --- /dev/null +++ b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfxbp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfxbp_1.sp ('sky130_fd_sc_ms__sdfxbp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.spice ('sky130_fd_sc_ms__sdfxbp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:31:25 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfxbp_1 sky130_fd_sc_ms__sdfxbp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfxbp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfxbp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 27 27 + + Instances: 18 18 MN (4 pins) + 18 18 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 37 36 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 19 19 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 4 4 SMN2 (4 pins) + 4 4 SMP2 (4 pins) + ------ ------ + Total Inst: 28 28 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 19 19 0 0 + + Instances: 10 10 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 4 4 0 0 SMN2 + 4 4 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 28 28 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK VPWR Q Q_N VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.pex.spice b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.pex.spice index 642a062..01b61f3 100644 --- a/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.pex.spice +++ b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxbp_1.pex.spice -* Created: Fri Aug 28 18:14:06 2020 +* Created: Wed Sep 2 12:31:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.pxi.spice b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.pxi.spice index 3a970c3..628a8ad 100644 --- a/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.pxi.spice +++ b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxbp_1.pxi.spice -* Created: Fri Aug 28 18:14:06 2020 +* Created: Wed Sep 2 12:31:28 2020 * x_PM_SKY130_FD_SC_MS__SDFXBP_1%A_31_74# N_A_31_74#_M1024_s N_A_31_74#_M1022_s + N_A_31_74#_M1007_g N_A_31_74#_M1032_g N_A_31_74#_c_256_n N_A_31_74#_c_257_n
diff --git a/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.spice b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.spice index b4ddd4f..6340418 100644 --- a/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.spice +++ b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxbp_1.spice -* Created: Fri Aug 28 18:14:06 2020 +* Created: Wed Sep 2 12:31:28 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.lvs.report b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.lvs.report new file mode 100644 index 0000000..e3ce2bb --- /dev/null +++ b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfxbp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfxbp_2.sp ('sky130_fd_sc_ms__sdfxbp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.spice ('sky130_fd_sc_ms__sdfxbp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:31:31 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfxbp_2 sky130_fd_sc_ms__sdfxbp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfxbp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfxbp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 27 27 + + Instances: 20 20 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 41 40 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 19 19 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 4 4 SMN2 (4 pins) + 4 4 SMP2 (4 pins) + ------ ------ + Total Inst: 28 28 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 19 19 0 0 + + Instances: 10 10 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 4 4 0 0 SMN2 + 4 4 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 28 28 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK VPWR Q Q_N VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.pex.spice b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.pex.spice index 7139038..3f6826f 100644 --- a/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.pex.spice +++ b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxbp_2.pex.spice -* Created: Fri Aug 28 18:14:16 2020 +* Created: Wed Sep 2 12:31:35 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.pxi.spice b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.pxi.spice index a4ff9f3..e5f1be7 100644 --- a/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.pxi.spice +++ b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxbp_2.pxi.spice -* Created: Fri Aug 28 18:14:16 2020 +* Created: Wed Sep 2 12:31:35 2020 * x_PM_SKY130_FD_SC_MS__SDFXBP_2%A_36_74# N_A_36_74#_M1038_s N_A_36_74#_M1004_s + N_A_36_74#_M1017_g N_A_36_74#_M1021_g N_A_36_74#_c_269_n N_A_36_74#_c_270_n
diff --git a/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.spice b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.spice index 17b90cf..e226eb1 100644 --- a/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.spice +++ b/cells/sdfxbp/sky130_fd_sc_ms__sdfxbp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxbp_2.spice -* Created: Fri Aug 28 18:14:16 2020 +* Created: Wed Sep 2 12:31:35 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.lvs.report b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.lvs.report new file mode 100644 index 0000000..0133b59 --- /dev/null +++ b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfxtp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfxtp_1.sp ('sky130_fd_sc_ms__sdfxtp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.spice ('sky130_fd_sc_ms__sdfxtp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:31:38 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfxtp_1 sky130_fd_sc_ms__sdfxtp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfxtp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfxtp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 25 25 + + Instances: 16 16 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 33 32 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 17 17 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 4 4 SMN2 (4 pins) + 4 4 SMP2 (4 pins) + ------ ------ + Total Inst: 24 24 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 17 17 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 8 8 0 0 MP(PSHORT) + 4 4 0 0 SMN2 + 4 4 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 24 24 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.pex.spice b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.pex.spice index 909b750..9d90f0c 100644 --- a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.pex.spice +++ b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxtp_1.pex.spice -* Created: Fri Aug 28 18:14:25 2020 +* Created: Wed Sep 2 12:31:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.pxi.spice b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.pxi.spice index bd837b4..b5b408e 100644 --- a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.pxi.spice +++ b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxtp_1.pxi.spice -* Created: Fri Aug 28 18:14:25 2020 +* Created: Wed Sep 2 12:31:42 2020 * x_PM_SKY130_FD_SC_MS__SDFXTP_1%A_35_74# N_A_35_74#_M1006_s N_A_35_74#_M1014_s + N_A_35_74#_M1020_g N_A_35_74#_M1027_g N_A_35_74#_c_234_n N_A_35_74#_c_227_n
diff --git a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.spice b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.spice index 40badb4..2142267 100644 --- a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.spice +++ b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxtp_1.spice -* Created: Fri Aug 28 18:14:25 2020 +* Created: Wed Sep 2 12:31:42 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.lvs.report b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.lvs.report new file mode 100644 index 0000000..82adc58 --- /dev/null +++ b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfxtp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfxtp_2.sp ('sky130_fd_sc_ms__sdfxtp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.spice ('sky130_fd_sc_ms__sdfxtp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:31:45 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfxtp_2 sky130_fd_sc_ms__sdfxtp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfxtp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfxtp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 25 25 + + Instances: 17 17 MN (4 pins) + 17 17 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 35 34 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 17 17 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 4 4 SMN2 (4 pins) + 4 4 SMP2 (4 pins) + ------ ------ + Total Inst: 24 24 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 17 17 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 8 8 0 0 MP(PSHORT) + 4 4 0 0 SMN2 + 4 4 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 24 24 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.pex.spice b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.pex.spice index c41b376..413aec2 100644 --- a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.pex.spice +++ b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxtp_2.pex.spice -* Created: Fri Aug 28 18:14:34 2020 +* Created: Wed Sep 2 12:31:48 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.pxi.spice b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.pxi.spice index 48c2e47..67e2ec6 100644 --- a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.pxi.spice +++ b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxtp_2.pxi.spice -* Created: Fri Aug 28 18:14:34 2020 +* Created: Wed Sep 2 12:31:48 2020 * x_PM_SKY130_FD_SC_MS__SDFXTP_2%SCE N_SCE_c_233_n N_SCE_c_242_n N_SCE_M1002_g + N_SCE_c_234_n N_SCE_M1033_g N_SCE_c_243_n N_SCE_c_244_n N_SCE_c_245_n
diff --git a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.spice b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.spice index 2d3a4aa..e6800ce 100644 --- a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.spice +++ b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxtp_2.spice -* Created: Fri Aug 28 18:14:34 2020 +* Created: Wed Sep 2 12:31:48 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.lvs.report b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.lvs.report new file mode 100644 index 0000000..ec2b14e --- /dev/null +++ b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdfxtp_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdfxtp_4.sp ('sky130_fd_sc_ms__sdfxtp_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.spice ('sky130_fd_sc_ms__sdfxtp_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:31:52 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdfxtp_4 sky130_fd_sc_ms__sdfxtp_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdfxtp_4 +SOURCE CELL NAME: sky130_fd_sc_ms__sdfxtp_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 25 25 + + Instances: 19 19 MN (4 pins) + 20 20 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 40 39 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 9 9 + + Nets: 17 17 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 4 4 SMN2 (4 pins) + 4 4 SMP2 (4 pins) + ------ ------ + Total Inst: 24 24 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 9 9 0 0 + + Nets: 17 17 0 0 + + Instances: 8 8 0 0 MN(NLOWVT) + 8 8 0 0 MP(PSHORT) + 4 4 0 0 SMN2 + 4 4 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 24 24 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 10 layout mos transistors were reduced to 3. + 7 mos transistors were deleted by parallel reduction. + 10 source mos transistors were reduced to 3. + 7 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE D SCD CLK VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.pex.spice b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.pex.spice index b8b0ff2..ec67ce6 100644 --- a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.pex.spice +++ b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxtp_4.pex.spice -* Created: Fri Aug 28 18:14:43 2020 +* Created: Wed Sep 2 12:31:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.pxi.spice b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.pxi.spice index 3a666d6..e583cc7 100644 --- a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.pxi.spice +++ b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxtp_4.pxi.spice -* Created: Fri Aug 28 18:14:43 2020 +* Created: Wed Sep 2 12:31:56 2020 * x_PM_SKY130_FD_SC_MS__SDFXTP_4%A_36_74# N_A_36_74#_M1036_s N_A_36_74#_M1015_s + N_A_36_74#_M1022_g N_A_36_74#_M1029_g N_A_36_74#_c_250_n N_A_36_74#_c_258_n
diff --git a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.spice b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.spice index 3cedfed..bb803c5 100644 --- a/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.spice +++ b/cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdfxtp_4.spice -* Created: Fri Aug 28 18:14:43 2020 +* Created: Wed Sep 2 12:31:56 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.lvs.report b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.lvs.report new file mode 100644 index 0000000..866df1b --- /dev/null +++ b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdlclkp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdlclkp_1.sp ('sky130_fd_sc_ms__sdlclkp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.spice ('sky130_fd_sc_ms__sdlclkp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:31:59 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdlclkp_1 sky130_fd_sc_ms__sdlclkp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdlclkp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__sdlclkp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 18 18 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 14 14 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 18 18 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 14 14 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 7 7 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 18 18 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE GATE CLK VPWR GCLK VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.pex.spice b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.pex.spice index a9be3b3..d244df8 100644 --- a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.pex.spice +++ b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdlclkp_1.pex.spice -* Created: Fri Aug 28 18:15:13 2020 +* Created: Wed Sep 2 12:32:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.pxi.spice b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.pxi.spice index e25b14e..0444b48 100644 --- a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.pxi.spice +++ b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdlclkp_1.pxi.spice -* Created: Fri Aug 28 18:15:13 2020 +* Created: Wed Sep 2 12:32:03 2020 * x_PM_SKY130_FD_SC_MS__SDLCLKP_1%SCE N_SCE_c_154_n N_SCE_M1008_g N_SCE_M1013_g + N_SCE_c_160_n SCE N_SCE_c_156_n N_SCE_c_157_n
diff --git a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.spice b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.spice index 63dd2d6..c5535ce 100644 --- a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.spice +++ b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdlclkp_1.spice -* Created: Fri Aug 28 18:15:13 2020 +* Created: Wed Sep 2 12:32:03 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.lvs.report b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.lvs.report new file mode 100644 index 0000000..c0ec81b --- /dev/null +++ b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdlclkp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdlclkp_2.sp ('sky130_fd_sc_ms__sdlclkp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.spice ('sky130_fd_sc_ms__sdlclkp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:32:06 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdlclkp_2 sky130_fd_sc_ms__sdlclkp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdlclkp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__sdlclkp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 18 18 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 14 14 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 18 18 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 14 14 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 7 7 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 18 18 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE GATE CLK VPWR GCLK VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.pex.spice b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.pex.spice index 5b305c4..fbffa18 100644 --- a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.pex.spice +++ b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdlclkp_2.pex.spice -* Created: Fri Aug 28 18:15:24 2020 +* Created: Wed Sep 2 12:32:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.pxi.spice b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.pxi.spice index 9394f49..9b80a14 100644 --- a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.pxi.spice +++ b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdlclkp_2.pxi.spice -* Created: Fri Aug 28 18:15:24 2020 +* Created: Wed Sep 2 12:32:09 2020 * x_PM_SKY130_FD_SC_MS__SDLCLKP_2%SCE N_SCE_c_166_n N_SCE_M1022_g N_SCE_M1015_g + N_SCE_c_172_n SCE N_SCE_c_168_n N_SCE_c_169_n
diff --git a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.spice b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.spice index e4015b3..2a08fc5 100644 --- a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.spice +++ b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdlclkp_2.spice -* Created: Fri Aug 28 18:15:24 2020 +* Created: Wed Sep 2 12:32:09 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.lvs.report b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.lvs.report new file mode 100644 index 0000000..d359795 --- /dev/null +++ b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sdlclkp_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sdlclkp_4.sp ('sky130_fd_sc_ms__sdlclkp_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.spice ('sky130_fd_sc_ms__sdlclkp_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:32:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sdlclkp_4 sky130_fd_sc_ms__sdlclkp_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sdlclkp_4 +SOURCE CELL NAME: sky130_fd_sc_ms__sdlclkp_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 18 18 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 14 14 + + Instances: 7 7 MN (4 pins) + 7 7 MP (4 pins) + 2 2 SMN2 (4 pins) + 2 2 SMP2 (4 pins) + ------ ------ + Total Inst: 18 18 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 14 14 0 0 + + Instances: 7 7 0 0 MN(NLOWVT) + 7 7 0 0 MP(PSHORT) + 2 2 0 0 SMN2 + 2 2 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 18 18 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 2. + 6 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 2. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB SCE GATE CLK VPWR GCLK VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.pex.spice b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.pex.spice index 454e710..e6de8e1 100644 --- a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.pex.spice +++ b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdlclkp_4.pex.spice -* Created: Fri Aug 28 18:15:33 2020 +* Created: Wed Sep 2 12:32:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.pxi.spice b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.pxi.spice index bea8fbc..2f60d91 100644 --- a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.pxi.spice +++ b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdlclkp_4.pxi.spice -* Created: Fri Aug 28 18:15:33 2020 +* Created: Wed Sep 2 12:32:16 2020 * x_PM_SKY130_FD_SC_MS__SDLCLKP_4%SCE N_SCE_M1025_g N_SCE_M1023_g SCE + N_SCE_c_181_n N_SCE_c_182_n PM_SKY130_FD_SC_MS__SDLCLKP_4%SCE
diff --git a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.spice b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.spice index 05ef599..b2b9094 100644 --- a/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.spice +++ b/cells/sdlclkp/sky130_fd_sc_ms__sdlclkp_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sdlclkp_4.spice -* Created: Fri Aug 28 18:15:33 2020 +* Created: Wed Sep 2 12:32:16 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.lvs.report b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.lvs.report new file mode 100644 index 0000000..ace99c5 --- /dev/null +++ b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sedfxbp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sedfxbp_1.sp ('sky130_fd_sc_ms__sedfxbp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.spice ('sky130_fd_sc_ms__sedfxbp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:32:20 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sedfxbp_1 sky130_fd_sc_ms__sedfxbp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sedfxbp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__sedfxbp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 33 33 + + Instances: 22 22 MN (4 pins) + 22 22 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 45 44 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 21 21 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 6 6 SMN2 (4 pins) + 6 6 SMP2 (4 pins) + ------ ------ + Total Inst: 32 32 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 11 11 0 0 + + Nets: 21 21 0 0 + + Instances: 10 10 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 6 6 0 0 SMN2 + 6 6 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 32 32 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D DE SCD SCE CLK VPWR Q Q_N VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.pex.spice b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.pex.spice index 2bf906b..5f89595 100644 --- a/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.pex.spice +++ b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxbp_1.pex.spice -* Created: Fri Aug 28 18:15:42 2020 +* Created: Wed Sep 2 12:32:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.pxi.spice b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.pxi.spice index 5a5d63d..64734b9 100644 --- a/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.pxi.spice +++ b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxbp_1.pxi.spice -* Created: Fri Aug 28 18:15:42 2020 +* Created: Wed Sep 2 12:32:23 2020 * x_PM_SKY130_FD_SC_MS__SEDFXBP_1%D N_D_c_334_n N_D_M1012_g N_D_M1021_g + N_D_c_336_n D D N_D_c_337_n N_D_c_338_n PM_SKY130_FD_SC_MS__SEDFXBP_1%D
diff --git a/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.spice b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.spice index e6b517a..ac1b598 100644 --- a/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.spice +++ b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxbp_1.spice -* Created: Fri Aug 28 18:15:42 2020 +* Created: Wed Sep 2 12:32:23 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.lvs.report b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.lvs.report new file mode 100644 index 0000000..db3de6b --- /dev/null +++ b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sedfxbp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sedfxbp_2.sp ('sky130_fd_sc_ms__sedfxbp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.spice ('sky130_fd_sc_ms__sedfxbp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:32:27 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sedfxbp_2 sky130_fd_sc_ms__sedfxbp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sedfxbp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__sedfxbp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 33 33 + + Instances: 24 24 MN (4 pins) + 24 24 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 49 48 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 11 11 + + Nets: 21 21 + + Instances: 10 10 MN (4 pins) + 10 10 MP (4 pins) + 6 6 SMN2 (4 pins) + 6 6 SMP2 (4 pins) + ------ ------ + Total Inst: 32 32 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 11 11 0 0 + + Nets: 21 21 0 0 + + Instances: 10 10 0 0 MN(NLOWVT) + 10 10 0 0 MP(PSHORT) + 6 6 0 0 SMN2 + 6 6 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 32 32 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 4. + 4 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D DE SCD SCE CLK VPWR Q Q_N VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.pex.spice b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.pex.spice index 2575107..71403fe 100644 --- a/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.pex.spice +++ b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxbp_2.pex.spice -* Created: Fri Aug 28 18:15:51 2020 +* Created: Wed Sep 2 12:32:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.pxi.spice b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.pxi.spice index 9bcac63..8711931 100644 --- a/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.pxi.spice +++ b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxbp_2.pxi.spice -* Created: Fri Aug 28 18:15:51 2020 +* Created: Wed Sep 2 12:32:30 2020 * x_PM_SKY130_FD_SC_MS__SEDFXBP_2%D N_D_M1027_g N_D_M1001_g D D N_D_c_344_n + N_D_c_345_n N_D_c_346_n N_D_c_350_n PM_SKY130_FD_SC_MS__SEDFXBP_2%D
diff --git a/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.spice b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.spice index ed4ee89..63e8c70 100644 --- a/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.spice +++ b/cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxbp_2.spice -* Created: Fri Aug 28 18:15:51 2020 +* Created: Wed Sep 2 12:32:30 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.lvs.report b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.lvs.report new file mode 100644 index 0000000..6885df0 --- /dev/null +++ b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sedfxtp_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sedfxtp_1.sp ('sky130_fd_sc_ms__sedfxtp_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.spice ('sky130_fd_sc_ms__sedfxtp_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:32:33 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sedfxtp_1 sky130_fd_sc_ms__sedfxtp_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sedfxtp_1 +SOURCE CELL NAME: sky130_fd_sc_ms__sedfxtp_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 32 32 + + Instances: 21 21 MN (4 pins) + 21 21 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 43 42 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 20 20 + + Instances: 9 9 MN (4 pins) + 9 9 MP (4 pins) + 6 6 SMN2 (4 pins) + 6 6 SMP2 (4 pins) + ------ ------ + Total Inst: 30 30 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 20 20 0 0 + + Instances: 9 9 0 0 MN(NLOWVT) + 9 9 0 0 MP(PSHORT) + 6 6 0 0 SMN2 + 6 6 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 30 30 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB D DE SCD SCE CLK VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.pex.spice b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.pex.spice index edb248e..8e5661c 100644 --- a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.pex.spice +++ b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxtp_1.pex.spice -* Created: Fri Aug 28 18:16:22 2020 +* Created: Wed Sep 2 12:32:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.pxi.spice b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.pxi.spice index ba87487..0990a79 100644 --- a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.pxi.spice +++ b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxtp_1.pxi.spice -* Created: Fri Aug 28 18:16:22 2020 +* Created: Wed Sep 2 12:32:37 2020 * x_PM_SKY130_FD_SC_MS__SEDFXTP_1%D N_D_c_325_n N_D_M1024_g N_D_M1010_g + N_D_c_327_n D D N_D_c_328_n N_D_c_329_n PM_SKY130_FD_SC_MS__SEDFXTP_1%D
diff --git a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.spice b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.spice index 8d36eeb..6d68de3 100644 --- a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.spice +++ b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxtp_1.spice -* Created: Fri Aug 28 18:16:22 2020 +* Created: Wed Sep 2 12:32:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.lvs.report b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.lvs.report new file mode 100644 index 0000000..4ae1bc2 --- /dev/null +++ b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sedfxtp_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sedfxtp_2.sp ('sky130_fd_sc_ms__sedfxtp_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.spice ('sky130_fd_sc_ms__sedfxtp_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:32:40 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sedfxtp_2 sky130_fd_sc_ms__sedfxtp_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sedfxtp_2 +SOURCE CELL NAME: sky130_fd_sc_ms__sedfxtp_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 32 32 + + Instances: 22 22 MN (4 pins) + 22 22 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 45 44 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 20 20 + + Instances: 9 9 MN (4 pins) + 9 9 MP (4 pins) + 6 6 SMN2 (4 pins) + 6 6 SMP2 (4 pins) + ------ ------ + Total Inst: 30 30 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 20 20 0 0 + + Instances: 9 9 0 0 MN(NLOWVT) + 9 9 0 0 MP(PSHORT) + 6 6 0 0 SMN2 + 6 6 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 30 30 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D DE SCD SCE CLK VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.pex.spice b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.pex.spice index 9f2a2ab..a2f761b 100644 --- a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.pex.spice +++ b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxtp_2.pex.spice -* Created: Fri Aug 28 18:16:32 2020 +* Created: Wed Sep 2 12:32:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.pxi.spice b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.pxi.spice index 0771fe6..88b0821 100644 --- a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.pxi.spice +++ b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxtp_2.pxi.spice -* Created: Fri Aug 28 18:16:32 2020 +* Created: Wed Sep 2 12:32:43 2020 * x_PM_SKY130_FD_SC_MS__SEDFXTP_2%D N_D_M1018_g N_D_M1012_g D D N_D_c_334_n + N_D_c_335_n N_D_c_336_n N_D_c_340_n PM_SKY130_FD_SC_MS__SEDFXTP_2%D
diff --git a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.spice b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.spice index 44c9de5..c470226 100644 --- a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.spice +++ b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxtp_2.spice -* Created: Fri Aug 28 18:16:32 2020 +* Created: Wed Sep 2 12:32:43 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.lvs.report b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.lvs.report new file mode 100644 index 0000000..ddb8bde --- /dev/null +++ b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__sedfxtp_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__sedfxtp_4.sp ('sky130_fd_sc_ms__sedfxtp_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.spice ('sky130_fd_sc_ms__sedfxtp_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:32:47 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__sedfxtp_4 sky130_fd_sc_ms__sedfxtp_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__sedfxtp_4 +SOURCE CELL NAME: sky130_fd_sc_ms__sedfxtp_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 32 32 + + Instances: 24 24 MN (4 pins) + 24 24 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 49 48 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 10 10 + + Nets: 20 20 + + Instances: 9 9 MN (4 pins) + 9 9 MP (4 pins) + 6 6 SMN2 (4 pins) + 6 6 SMP2 (4 pins) + ------ ------ + Total Inst: 30 30 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 10 10 0 0 + + Nets: 20 20 0 0 + + Instances: 9 9 0 0 MN(NLOWVT) + 9 9 0 0 MP(PSHORT) + 6 6 0 0 SMN2 + 6 6 0 0 SMP2 + ------- ------- --------- --------- + Total Inst: 30 30 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 2. + 6 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 2. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB D DE SCD SCE CLK VPWR Q VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.pex.spice b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.pex.spice index 76d11a9..1d7e971 100644 --- a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.pex.spice +++ b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxtp_4.pex.spice -* Created: Fri Aug 28 18:16:41 2020 +* Created: Wed Sep 2 12:32:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.pxi.spice b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.pxi.spice index c3075a7..2301d30 100644 --- a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.pxi.spice +++ b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxtp_4.pxi.spice -* Created: Fri Aug 28 18:16:41 2020 +* Created: Wed Sep 2 12:32:51 2020 * x_PM_SKY130_FD_SC_MS__SEDFXTP_4%D N_D_M1004_g N_D_M1002_g D D N_D_c_343_n + N_D_c_344_n N_D_c_345_n N_D_c_349_n PM_SKY130_FD_SC_MS__SEDFXTP_4%D
diff --git a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.spice b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.spice index 6a100b0..e29325f 100644 --- a/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.spice +++ b/cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__sedfxtp_4.spice -* Created: Fri Aug 28 18:16:41 2020 +* Created: Wed Sep 2 12:32:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/tap/sky130_fd_sc_ms__tap_1.lvs.report b/cells/tap/sky130_fd_sc_ms__tap_1.lvs.report new file mode 100644 index 0000000..b409e71 --- /dev/null +++ b/cells/tap/sky130_fd_sc_ms__tap_1.lvs.report
@@ -0,0 +1,375 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__tap_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__tap_1.sp ('sky130_fd_sc_ms__tap_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/tap/sky130_fd_sc_ms__tap_1.spice ('sky130_fd_sc_ms__tap_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:32:54 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # # ######################## + # # # # + # # NOT COMPARED # + # # # # + # # ######################## + + + Error: Nothing in source. + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/tap/sky130_fd_sc_ms__tap_2.lvs.report b/cells/tap/sky130_fd_sc_ms__tap_2.lvs.report new file mode 100644 index 0000000..d68fe1d --- /dev/null +++ b/cells/tap/sky130_fd_sc_ms__tap_2.lvs.report
@@ -0,0 +1,375 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__tap_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__tap_2.sp ('sky130_fd_sc_ms__tap_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/tap/sky130_fd_sc_ms__tap_2.spice ('sky130_fd_sc_ms__tap_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:32:57 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # # ######################## + # # # # + # # NOT COMPARED # + # # # # + # # ######################## + + + Error: Nothing in source. + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/tapmet1/sky130_fd_sc_ms__tapmet1_2.lvs.report b/cells/tapmet1/sky130_fd_sc_ms__tapmet1_2.lvs.report new file mode 100644 index 0000000..a4fc457 --- /dev/null +++ b/cells/tapmet1/sky130_fd_sc_ms__tapmet1_2.lvs.report
@@ -0,0 +1,375 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__tapmet1_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__tapmet1_2.sp ('sky130_fd_sc_ms__tapmet1_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/tapmet1/sky130_fd_sc_ms__tapmet1_2.spice ('sky130_fd_sc_ms__tapmet1_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:33:01 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # # ######################## + # # # # + # # NOT COMPARED # + # # # # + # # ######################## + + + Error: Nothing in source. + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/tapvgnd/sky130_fd_sc_ms__tapvgnd_1.lvs.report b/cells/tapvgnd/sky130_fd_sc_ms__tapvgnd_1.lvs.report new file mode 100644 index 0000000..7c354ed --- /dev/null +++ b/cells/tapvgnd/sky130_fd_sc_ms__tapvgnd_1.lvs.report
@@ -0,0 +1,375 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__tapvgnd_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__tapvgnd_1.sp ('sky130_fd_sc_ms__tapvgnd_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/tapvgnd/sky130_fd_sc_ms__tapvgnd_1.spice ('sky130_fd_sc_ms__tapvgnd_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:33:04 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # # ######################## + # # # # + # # NOT COMPARED # + # # # # + # # ######################## + + + Error: Nothing in source. + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/tapvgnd2/sky130_fd_sc_ms__tapvgnd2_1.lvs.report b/cells/tapvgnd2/sky130_fd_sc_ms__tapvgnd2_1.lvs.report new file mode 100644 index 0000000..9c319d9 --- /dev/null +++ b/cells/tapvgnd2/sky130_fd_sc_ms__tapvgnd2_1.lvs.report
@@ -0,0 +1,375 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__tapvgnd2_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__tapvgnd2_1.sp ('sky130_fd_sc_ms__tapvgnd2_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/tapvgnd2/sky130_fd_sc_ms__tapvgnd2_1.spice ('sky130_fd_sc_ms__tapvgnd2_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:33:07 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # # ######################## + # # # # + # # NOT COMPARED # + # # # # + # # ######################## + + + Error: Nothing in source. + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/tapvpwrvgnd/sky130_fd_sc_ms__tapvpwrvgnd_1.lvs.report b/cells/tapvpwrvgnd/sky130_fd_sc_ms__tapvpwrvgnd_1.lvs.report new file mode 100644 index 0000000..fff1c40 --- /dev/null +++ b/cells/tapvpwrvgnd/sky130_fd_sc_ms__tapvpwrvgnd_1.lvs.report
@@ -0,0 +1,375 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__tapvpwrvgnd_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__tapvpwrvgnd_1.sp ('sky130_fd_sc_ms__tapvpwrvgnd_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/tapvpwrvgnd/sky130_fd_sc_ms__tapvpwrvgnd_1.spice ('sky130_fd_sc_ms__tapvpwrvgnd_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:33:10 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # # ######################## + # # # # + # # NOT COMPARED # + # # # # + # # ######################## + + + Error: Nothing in source. + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_ms__xnor2_1.lvs.report b/cells/xnor2/sky130_fd_sc_ms__xnor2_1.lvs.report new file mode 100644 index 0000000..65b0ec7 --- /dev/null +++ b/cells/xnor2/sky130_fd_sc_ms__xnor2_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__xnor2_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__xnor2_1.sp ('sky130_fd_sc_ms__xnor2_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/xnor2/sky130_fd_sc_ms__xnor2_1.spice ('sky130_fd_sc_ms__xnor2_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:33:13 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__xnor2_1 sky130_fd_sc_ms__xnor2_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__xnor2_1 +SOURCE CELL NAME: sky130_fd_sc_ms__xnor2_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 11 11 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 3 3 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_ms__xnor2_1.pex.spice b/cells/xnor2/sky130_fd_sc_ms__xnor2_1.pex.spice index 77ebb20..6e2637e 100644 --- a/cells/xnor2/sky130_fd_sc_ms__xnor2_1.pex.spice +++ b/cells/xnor2/sky130_fd_sc_ms__xnor2_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor2_1.pex.spice -* Created: Fri Aug 28 18:17:31 2020 +* Created: Wed Sep 2 12:33:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/xnor2/sky130_fd_sc_ms__xnor2_1.pxi.spice b/cells/xnor2/sky130_fd_sc_ms__xnor2_1.pxi.spice index a5f1ba3..51cedc1 100644 --- a/cells/xnor2/sky130_fd_sc_ms__xnor2_1.pxi.spice +++ b/cells/xnor2/sky130_fd_sc_ms__xnor2_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor2_1.pxi.spice -* Created: Fri Aug 28 18:17:31 2020 +* Created: Wed Sep 2 12:33:17 2020 * x_PM_SKY130_FD_SC_MS__XNOR2_1%B N_B_c_63_n N_B_M1002_g N_B_c_64_n N_B_M1001_g + N_B_M1005_g N_B_M1008_g N_B_c_72_n N_B_c_87_p N_B_c_129_p N_B_c_73_n
diff --git a/cells/xnor2/sky130_fd_sc_ms__xnor2_1.spice b/cells/xnor2/sky130_fd_sc_ms__xnor2_1.spice index 824bf2f..51a4bd8 100644 --- a/cells/xnor2/sky130_fd_sc_ms__xnor2_1.spice +++ b/cells/xnor2/sky130_fd_sc_ms__xnor2_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor2_1.spice -* Created: Fri Aug 28 18:17:31 2020 +* Created: Wed Sep 2 12:33:17 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/xnor2/sky130_fd_sc_ms__xnor2_2.lvs.report b/cells/xnor2/sky130_fd_sc_ms__xnor2_2.lvs.report new file mode 100644 index 0000000..9b42add --- /dev/null +++ b/cells/xnor2/sky130_fd_sc_ms__xnor2_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__xnor2_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__xnor2_2.sp ('sky130_fd_sc_ms__xnor2_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/xnor2/sky130_fd_sc_ms__xnor2_2.spice ('sky130_fd_sc_ms__xnor2_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:33:21 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__xnor2_2 sky130_fd_sc_ms__xnor2_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__xnor2_2 +SOURCE CELL NAME: sky130_fd_sc_ms__xnor2_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 11 11 + + Instances: 8 8 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 17 16 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 3 3 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 12 layout mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + 12 source mos transistors were reduced to 6. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_ms__xnor2_2.pex.spice b/cells/xnor2/sky130_fd_sc_ms__xnor2_2.pex.spice index e822956..e8032b0 100644 --- a/cells/xnor2/sky130_fd_sc_ms__xnor2_2.pex.spice +++ b/cells/xnor2/sky130_fd_sc_ms__xnor2_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor2_2.pex.spice -* Created: Fri Aug 28 18:17:42 2020 +* Created: Wed Sep 2 12:33:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/xnor2/sky130_fd_sc_ms__xnor2_2.pxi.spice b/cells/xnor2/sky130_fd_sc_ms__xnor2_2.pxi.spice index ff9f5c5..f80f622 100644 --- a/cells/xnor2/sky130_fd_sc_ms__xnor2_2.pxi.spice +++ b/cells/xnor2/sky130_fd_sc_ms__xnor2_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor2_2.pxi.spice -* Created: Fri Aug 28 18:17:42 2020 +* Created: Wed Sep 2 12:33:24 2020 * x_PM_SKY130_FD_SC_MS__XNOR2_2%A N_A_M1011_g N_A_M1014_g N_A_M1002_g N_A_M1006_g + N_A_M1008_g N_A_M1007_g N_A_c_98_n N_A_c_114_n N_A_c_115_n A N_A_c_100_n
diff --git a/cells/xnor2/sky130_fd_sc_ms__xnor2_2.spice b/cells/xnor2/sky130_fd_sc_ms__xnor2_2.spice index 6d53fd6..00fedce 100644 --- a/cells/xnor2/sky130_fd_sc_ms__xnor2_2.spice +++ b/cells/xnor2/sky130_fd_sc_ms__xnor2_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor2_2.spice -* Created: Fri Aug 28 18:17:42 2020 +* Created: Wed Sep 2 12:33:24 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/xnor2/sky130_fd_sc_ms__xnor2_4.lvs.report b/cells/xnor2/sky130_fd_sc_ms__xnor2_4.lvs.report new file mode 100644 index 0000000..7a2025b --- /dev/null +++ b/cells/xnor2/sky130_fd_sc_ms__xnor2_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__xnor2_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__xnor2_4.sp ('sky130_fd_sc_ms__xnor2_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/xnor2/sky130_fd_sc_ms__xnor2_4.spice ('sky130_fd_sc_ms__xnor2_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:33:27 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__xnor2_4 sky130_fd_sc_ms__xnor2_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__xnor2_4 +SOURCE CELL NAME: sky130_fd_sc_ms__xnor2_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 11 11 + + Instances: 16 16 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 31 30 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 3 3 MP (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMN_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MP(PSHORT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMN_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 30 layout mos transistors were reduced to 10. + 20 mos transistors were deleted by parallel reduction. + 30 source mos transistors were reduced to 10. + 20 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B VPWR Y VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_ms__xnor2_4.pex.spice b/cells/xnor2/sky130_fd_sc_ms__xnor2_4.pex.spice index ab586b6..5953013 100644 --- a/cells/xnor2/sky130_fd_sc_ms__xnor2_4.pex.spice +++ b/cells/xnor2/sky130_fd_sc_ms__xnor2_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor2_4.pex.spice -* Created: Fri Aug 28 18:17:51 2020 +* Created: Wed Sep 2 12:33:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/xnor2/sky130_fd_sc_ms__xnor2_4.pxi.spice b/cells/xnor2/sky130_fd_sc_ms__xnor2_4.pxi.spice index 36b3f09..ba582d8 100644 --- a/cells/xnor2/sky130_fd_sc_ms__xnor2_4.pxi.spice +++ b/cells/xnor2/sky130_fd_sc_ms__xnor2_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor2_4.pxi.spice -* Created: Fri Aug 28 18:17:51 2020 +* Created: Wed Sep 2 12:33:31 2020 * x_PM_SKY130_FD_SC_MS__XNOR2_4%A N_A_M1012_g N_A_M1019_g N_A_M1013_g N_A_M1028_g + N_A_M1002_g N_A_M1000_g N_A_M1009_g N_A_M1004_g N_A_M1021_g N_A_c_163_n
diff --git a/cells/xnor2/sky130_fd_sc_ms__xnor2_4.spice b/cells/xnor2/sky130_fd_sc_ms__xnor2_4.spice index 28a90cb..36c254e 100644 --- a/cells/xnor2/sky130_fd_sc_ms__xnor2_4.spice +++ b/cells/xnor2/sky130_fd_sc_ms__xnor2_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor2_4.spice -* Created: Fri Aug 28 18:17:51 2020 +* Created: Wed Sep 2 12:33:31 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/xnor3/sky130_fd_sc_ms__xnor3_1.lvs.report b/cells/xnor3/sky130_fd_sc_ms__xnor3_1.lvs.report new file mode 100644 index 0000000..3116a1c --- /dev/null +++ b/cells/xnor3/sky130_fd_sc_ms__xnor3_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__xnor3_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__xnor3_1.sp ('sky130_fd_sc_ms__xnor3_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/xnor3/sky130_fd_sc_ms__xnor3_1.spice ('sky130_fd_sc_ms__xnor3_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:33:34 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__xnor3_1 sky130_fd_sc_ms__xnor3_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__xnor3_1 +SOURCE CELL NAME: sky130_fd_sc_ms__xnor3_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + ------ ------ + Total Inst: 22 22 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 15 15 0 0 + + Instances: 11 11 0 0 MN(NLOWVT) + 11 11 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 22 22 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB C B A X VPWR VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/xnor3/sky130_fd_sc_ms__xnor3_1.pex.spice b/cells/xnor3/sky130_fd_sc_ms__xnor3_1.pex.spice index 06061cd..a5377cc 100644 --- a/cells/xnor3/sky130_fd_sc_ms__xnor3_1.pex.spice +++ b/cells/xnor3/sky130_fd_sc_ms__xnor3_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor3_1.pex.spice -* Created: Fri Aug 28 18:18:00 2020 +* Created: Wed Sep 2 12:33:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/xnor3/sky130_fd_sc_ms__xnor3_1.pxi.spice b/cells/xnor3/sky130_fd_sc_ms__xnor3_1.pxi.spice index c2b9b8a..d1e934f 100644 --- a/cells/xnor3/sky130_fd_sc_ms__xnor3_1.pxi.spice +++ b/cells/xnor3/sky130_fd_sc_ms__xnor3_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor3_1.pxi.spice -* Created: Fri Aug 28 18:18:00 2020 +* Created: Wed Sep 2 12:33:37 2020 * x_PM_SKY130_FD_SC_MS__XNOR3_1%A_81_268# N_A_81_268#_M1008_d N_A_81_268#_M1000_d + N_A_81_268#_M1016_g N_A_81_268#_M1003_g N_A_81_268#_c_177_n
diff --git a/cells/xnor3/sky130_fd_sc_ms__xnor3_1.spice b/cells/xnor3/sky130_fd_sc_ms__xnor3_1.spice index ceaaadc..d50e78e 100644 --- a/cells/xnor3/sky130_fd_sc_ms__xnor3_1.spice +++ b/cells/xnor3/sky130_fd_sc_ms__xnor3_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor3_1.spice -* Created: Fri Aug 28 18:18:00 2020 +* Created: Wed Sep 2 12:33:37 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/xnor3/sky130_fd_sc_ms__xnor3_2.lvs.report b/cells/xnor3/sky130_fd_sc_ms__xnor3_2.lvs.report new file mode 100644 index 0000000..4d46e33 --- /dev/null +++ b/cells/xnor3/sky130_fd_sc_ms__xnor3_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__xnor3_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__xnor3_2.sp ('sky130_fd_sc_ms__xnor3_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/xnor3/sky130_fd_sc_ms__xnor3_2.spice ('sky130_fd_sc_ms__xnor3_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:33:41 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__xnor3_2 sky130_fd_sc_ms__xnor3_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__xnor3_2 +SOURCE CELL NAME: sky130_fd_sc_ms__xnor3_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + ------ ------ + Total Inst: 22 22 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 15 15 0 0 + + Instances: 11 11 0 0 MN(NLOWVT) + 11 11 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 22 22 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B C VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/xnor3/sky130_fd_sc_ms__xnor3_2.pex.spice b/cells/xnor3/sky130_fd_sc_ms__xnor3_2.pex.spice index 136fe5f..bdd4eb5 100644 --- a/cells/xnor3/sky130_fd_sc_ms__xnor3_2.pex.spice +++ b/cells/xnor3/sky130_fd_sc_ms__xnor3_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor3_2.pex.spice -* Created: Fri Aug 28 18:18:15 2020 +* Created: Wed Sep 2 12:33:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/xnor3/sky130_fd_sc_ms__xnor3_2.pxi.spice b/cells/xnor3/sky130_fd_sc_ms__xnor3_2.pxi.spice index ab3eed8..24d21c0 100644 --- a/cells/xnor3/sky130_fd_sc_ms__xnor3_2.pxi.spice +++ b/cells/xnor3/sky130_fd_sc_ms__xnor3_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor3_2.pxi.spice -* Created: Fri Aug 28 18:18:15 2020 +* Created: Wed Sep 2 12:33:44 2020 * x_PM_SKY130_FD_SC_MS__XNOR3_2%A_83_247# N_A_83_247#_M1010_d N_A_83_247#_M1002_d + N_A_83_247#_M1022_d N_A_83_247#_M1001_d N_A_83_247#_M1015_g
diff --git a/cells/xnor3/sky130_fd_sc_ms__xnor3_2.spice b/cells/xnor3/sky130_fd_sc_ms__xnor3_2.spice index c3604a8..71e5417 100644 --- a/cells/xnor3/sky130_fd_sc_ms__xnor3_2.spice +++ b/cells/xnor3/sky130_fd_sc_ms__xnor3_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor3_2.spice -* Created: Fri Aug 28 18:18:15 2020 +* Created: Wed Sep 2 12:33:44 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/xnor3/sky130_fd_sc_ms__xnor3_4.lvs.report b/cells/xnor3/sky130_fd_sc_ms__xnor3_4.lvs.report new file mode 100644 index 0000000..c401eae --- /dev/null +++ b/cells/xnor3/sky130_fd_sc_ms__xnor3_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__xnor3_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__xnor3_4.sp ('sky130_fd_sc_ms__xnor3_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/xnor3/sky130_fd_sc_ms__xnor3_4.spice ('sky130_fd_sc_ms__xnor3_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:33:47 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__xnor3_4 sky130_fd_sc_ms__xnor3_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__xnor3_4 +SOURCE CELL NAME: sky130_fd_sc_ms__xnor3_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + ------ ------ + Total Inst: 22 22 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 15 15 0 0 + + Instances: 11 11 0 0 MN(NLOWVT) + 11 11 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 22 22 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 2. + 6 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 2. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B C VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/xnor3/sky130_fd_sc_ms__xnor3_4.pex.spice b/cells/xnor3/sky130_fd_sc_ms__xnor3_4.pex.spice index c523522..5caba1d 100644 --- a/cells/xnor3/sky130_fd_sc_ms__xnor3_4.pex.spice +++ b/cells/xnor3/sky130_fd_sc_ms__xnor3_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor3_4.pex.spice -* Created: Fri Aug 28 18:18:40 2020 +* Created: Wed Sep 2 12:33:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/xnor3/sky130_fd_sc_ms__xnor3_4.pxi.spice b/cells/xnor3/sky130_fd_sc_ms__xnor3_4.pxi.spice index b9eeb8d..c2cfbe4 100644 --- a/cells/xnor3/sky130_fd_sc_ms__xnor3_4.pxi.spice +++ b/cells/xnor3/sky130_fd_sc_ms__xnor3_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor3_4.pxi.spice -* Created: Fri Aug 28 18:18:40 2020 +* Created: Wed Sep 2 12:33:51 2020 * x_PM_SKY130_FD_SC_MS__XNOR3_4%A_75_227# N_A_75_227#_M1003_d N_A_75_227#_M1009_d + N_A_75_227#_M1018_d N_A_75_227#_M1000_d N_A_75_227#_M1020_g
diff --git a/cells/xnor3/sky130_fd_sc_ms__xnor3_4.spice b/cells/xnor3/sky130_fd_sc_ms__xnor3_4.spice index aeb2fb4..11556c2 100644 --- a/cells/xnor3/sky130_fd_sc_ms__xnor3_4.spice +++ b/cells/xnor3/sky130_fd_sc_ms__xnor3_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xnor3_4.spice -* Created: Fri Aug 28 18:18:40 2020 +* Created: Wed Sep 2 12:33:51 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/xor2/sky130_fd_sc_ms__xor2_1.lvs.report b/cells/xor2/sky130_fd_sc_ms__xor2_1.lvs.report new file mode 100644 index 0000000..3a40e87 --- /dev/null +++ b/cells/xor2/sky130_fd_sc_ms__xor2_1.lvs.report
@@ -0,0 +1,468 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__xor2_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__xor2_1.sp ('sky130_fd_sc_ms__xor2_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/xor2/sky130_fd_sc_ms__xor2_1.spice ('sky130_fd_sc_ms__xor2_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:33:54 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__xor2_1 sky130_fd_sc_ms__xor2_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__xor2_1 +SOURCE CELL NAME: sky130_fd_sc_ms__xor2_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 11 11 + + Instances: 5 5 MN (4 pins) + 5 5 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 11 10 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB B A VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/xor2/sky130_fd_sc_ms__xor2_1.pex.spice b/cells/xor2/sky130_fd_sc_ms__xor2_1.pex.spice index 5ab3392..b98f6c7 100644 --- a/cells/xor2/sky130_fd_sc_ms__xor2_1.pex.spice +++ b/cells/xor2/sky130_fd_sc_ms__xor2_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor2_1.pex.spice -* Created: Fri Aug 28 18:18:50 2020 +* Created: Wed Sep 2 12:33:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/xor2/sky130_fd_sc_ms__xor2_1.pxi.spice b/cells/xor2/sky130_fd_sc_ms__xor2_1.pxi.spice index fcd6b9d..0492086 100644 --- a/cells/xor2/sky130_fd_sc_ms__xor2_1.pxi.spice +++ b/cells/xor2/sky130_fd_sc_ms__xor2_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor2_1.pxi.spice -* Created: Fri Aug 28 18:18:50 2020 +* Created: Wed Sep 2 12:33:58 2020 * x_PM_SKY130_FD_SC_MS__XOR2_1%B N_B_c_70_n N_B_M1001_g N_B_M1002_g N_B_M1005_g + N_B_M1006_g N_B_c_66_n B N_B_c_67_n N_B_c_68_n N_B_c_69_n
diff --git a/cells/xor2/sky130_fd_sc_ms__xor2_1.spice b/cells/xor2/sky130_fd_sc_ms__xor2_1.spice index f8be501..86a05cc 100644 --- a/cells/xor2/sky130_fd_sc_ms__xor2_1.spice +++ b/cells/xor2/sky130_fd_sc_ms__xor2_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor2_1.spice -* Created: Fri Aug 28 18:18:50 2020 +* Created: Wed Sep 2 12:33:58 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/xor2/sky130_fd_sc_ms__xor2_2.lvs.report b/cells/xor2/sky130_fd_sc_ms__xor2_2.lvs.report new file mode 100644 index 0000000..f7c7ee6 --- /dev/null +++ b/cells/xor2/sky130_fd_sc_ms__xor2_2.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__xor2_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__xor2_2.sp ('sky130_fd_sc_ms__xor2_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/xor2/sky130_fd_sc_ms__xor2_2.spice ('sky130_fd_sc_ms__xor2_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:34:01 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__xor2_2 sky130_fd_sc_ms__xor2_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__xor2_2 +SOURCE CELL NAME: sky130_fd_sc_ms__xor2_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 11 11 + + Instances: 7 7 MN (4 pins) + 8 8 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 16 15 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 10 layout mos transistors were reduced to 5. + 5 mos transistors were deleted by parallel reduction. + 10 source mos transistors were reduced to 5. + 5 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/xor2/sky130_fd_sc_ms__xor2_2.pex.spice b/cells/xor2/sky130_fd_sc_ms__xor2_2.pex.spice index 19fe200..9bb9ebf 100644 --- a/cells/xor2/sky130_fd_sc_ms__xor2_2.pex.spice +++ b/cells/xor2/sky130_fd_sc_ms__xor2_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor2_2.pex.spice -* Created: Fri Aug 28 18:18:59 2020 +* Created: Wed Sep 2 12:34:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/xor2/sky130_fd_sc_ms__xor2_2.pxi.spice b/cells/xor2/sky130_fd_sc_ms__xor2_2.pxi.spice index c00288c..00acf3a 100644 --- a/cells/xor2/sky130_fd_sc_ms__xor2_2.pxi.spice +++ b/cells/xor2/sky130_fd_sc_ms__xor2_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor2_2.pxi.spice -* Created: Fri Aug 28 18:18:59 2020 +* Created: Wed Sep 2 12:34:04 2020 * x_PM_SKY130_FD_SC_MS__XOR2_2%A N_A_M1001_g N_A_M1008_g N_A_M1007_g N_A_M1012_g + N_A_M1010_g N_A_M1013_g N_A_c_83_n N_A_c_92_n N_A_c_84_n A N_A_c_85_n
diff --git a/cells/xor2/sky130_fd_sc_ms__xor2_2.spice b/cells/xor2/sky130_fd_sc_ms__xor2_2.spice index 6b4215d..492421d 100644 --- a/cells/xor2/sky130_fd_sc_ms__xor2_2.spice +++ b/cells/xor2/sky130_fd_sc_ms__xor2_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor2_2.spice -* Created: Fri Aug 28 18:18:59 2020 +* Created: Wed Sep 2 12:34:04 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/xor2/sky130_fd_sc_ms__xor2_4.lvs.report b/cells/xor2/sky130_fd_sc_ms__xor2_4.lvs.report new file mode 100644 index 0000000..1bbf791 --- /dev/null +++ b/cells/xor2/sky130_fd_sc_ms__xor2_4.lvs.report
@@ -0,0 +1,473 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__xor2_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__xor2_4.sp ('sky130_fd_sc_ms__xor2_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/xor2/sky130_fd_sc_ms__xor2_4.spice ('sky130_fd_sc_ms__xor2_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:34:08 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__xor2_4 sky130_fd_sc_ms__xor2_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__xor2_4 +SOURCE CELL NAME: sky130_fd_sc_ms__xor2_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 11 11 + + Instances: 14 14 MN (4 pins) + 16 16 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 31 30 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 7 7 + + Nets: 8 8 + + Instances: 3 3 MN (4 pins) + 1 1 SMN2 (4 pins) + 1 1 SMP2 (4 pins) + 1 1 SPMP_2_1 (5 pins) + ------ ------ + Total Inst: 6 6 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 7 7 0 0 + + Nets: 8 8 0 0 + + Instances: 3 3 0 0 MN(NLOWVT) + 1 1 0 0 SMN2 + 1 1 0 0 SMP2 + 1 1 0 0 SPMP_2_1 + ------- ------- --------- --------- + Total Inst: 6 6 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 30 layout mos transistors were reduced to 10. + 20 mos transistors were deleted by parallel reduction. + 30 source mos transistors were reduced to 10. + 20 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/xor2/sky130_fd_sc_ms__xor2_4.pex.spice b/cells/xor2/sky130_fd_sc_ms__xor2_4.pex.spice index 27502b3..a0f88e1 100644 --- a/cells/xor2/sky130_fd_sc_ms__xor2_4.pex.spice +++ b/cells/xor2/sky130_fd_sc_ms__xor2_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor2_4.pex.spice -* Created: Fri Aug 28 18:19:09 2020 +* Created: Wed Sep 2 12:34:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/xor2/sky130_fd_sc_ms__xor2_4.pxi.spice b/cells/xor2/sky130_fd_sc_ms__xor2_4.pxi.spice index b31e6f3..ee14885 100644 --- a/cells/xor2/sky130_fd_sc_ms__xor2_4.pxi.spice +++ b/cells/xor2/sky130_fd_sc_ms__xor2_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor2_4.pxi.spice -* Created: Fri Aug 28 18:19:09 2020 +* Created: Wed Sep 2 12:34:11 2020 * x_PM_SKY130_FD_SC_MS__XOR2_4%A N_A_M1004_g N_A_M1001_g N_A_M1009_g N_A_M1022_g + N_A_M1003_g N_A_M1015_g N_A_M1006_g N_A_M1016_g N_A_M1021_g N_A_M1025_g
diff --git a/cells/xor2/sky130_fd_sc_ms__xor2_4.spice b/cells/xor2/sky130_fd_sc_ms__xor2_4.spice index e6f6aa4..febc2f7 100644 --- a/cells/xor2/sky130_fd_sc_ms__xor2_4.spice +++ b/cells/xor2/sky130_fd_sc_ms__xor2_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor2_4.spice -* Created: Fri Aug 28 18:19:09 2020 +* Created: Wed Sep 2 12:34:11 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/xor3/sky130_fd_sc_ms__xor3_1.lvs.report b/cells/xor3/sky130_fd_sc_ms__xor3_1.lvs.report new file mode 100644 index 0000000..ca2b839 --- /dev/null +++ b/cells/xor3/sky130_fd_sc_ms__xor3_1.lvs.report
@@ -0,0 +1,464 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__xor3_1.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__xor3_1.sp ('sky130_fd_sc_ms__xor3_1') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/xor3/sky130_fd_sc_ms__xor3_1.spice ('sky130_fd_sc_ms__xor3_1') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:34:15 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__xor3_1 sky130_fd_sc_ms__xor3_1 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__xor3_1 +SOURCE CELL NAME: sky130_fd_sc_ms__xor3_1 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 23 22 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + ------ ------ + Total Inst: 22 22 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 15 15 0 0 + + Instances: 11 11 0 0 MN(NLOWVT) + 11 11 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 22 22 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B C VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/xor3/sky130_fd_sc_ms__xor3_1.pex.spice b/cells/xor3/sky130_fd_sc_ms__xor3_1.pex.spice index 7ca12d2..b64db70 100644 --- a/cells/xor3/sky130_fd_sc_ms__xor3_1.pex.spice +++ b/cells/xor3/sky130_fd_sc_ms__xor3_1.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor3_1.pex.spice -* Created: Fri Aug 28 18:19:23 2020 +* Created: Wed Sep 2 12:34:19 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/xor3/sky130_fd_sc_ms__xor3_1.pxi.spice b/cells/xor3/sky130_fd_sc_ms__xor3_1.pxi.spice index 8ce8004..f4286c5 100644 --- a/cells/xor3/sky130_fd_sc_ms__xor3_1.pxi.spice +++ b/cells/xor3/sky130_fd_sc_ms__xor3_1.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor3_1.pxi.spice -* Created: Fri Aug 28 18:19:23 2020 +* Created: Wed Sep 2 12:34:19 2020 * x_PM_SKY130_FD_SC_MS__XOR3_1%A_84_108# N_A_84_108#_M1000_d N_A_84_108#_M1020_d + N_A_84_108#_M1002_d N_A_84_108#_M1010_d N_A_84_108#_M1019_g
diff --git a/cells/xor3/sky130_fd_sc_ms__xor3_1.spice b/cells/xor3/sky130_fd_sc_ms__xor3_1.spice index 9cd02c5..f879818 100644 --- a/cells/xor3/sky130_fd_sc_ms__xor3_1.spice +++ b/cells/xor3/sky130_fd_sc_ms__xor3_1.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor3_1.spice -* Created: Fri Aug 28 18:19:23 2020 +* Created: Wed Sep 2 12:34:19 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/xor3/sky130_fd_sc_ms__xor3_2.lvs.report b/cells/xor3/sky130_fd_sc_ms__xor3_2.lvs.report new file mode 100644 index 0000000..c3888f2 --- /dev/null +++ b/cells/xor3/sky130_fd_sc_ms__xor3_2.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__xor3_2.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__xor3_2.sp ('sky130_fd_sc_ms__xor3_2') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/xor3/sky130_fd_sc_ms__xor3_2.spice ('sky130_fd_sc_ms__xor3_2') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:34:22 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__xor3_2 sky130_fd_sc_ms__xor3_2 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__xor3_2 +SOURCE CELL NAME: sky130_fd_sc_ms__xor3_2 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 12 12 MN (4 pins) + 12 12 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 25 24 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + ------ ------ + Total Inst: 22 22 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 15 15 0 0 + + Instances: 11 11 0 0 MN(NLOWVT) + 11 11 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 22 22 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 4 layout mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + 4 source mos transistors were reduced to 2. + 2 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B C VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/xor3/sky130_fd_sc_ms__xor3_2.pex.spice b/cells/xor3/sky130_fd_sc_ms__xor3_2.pex.spice index 065e6a0..5e5f9d3 100644 --- a/cells/xor3/sky130_fd_sc_ms__xor3_2.pex.spice +++ b/cells/xor3/sky130_fd_sc_ms__xor3_2.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor3_2.pex.spice -* Created: Fri Aug 28 18:19:48 2020 +* Created: Wed Sep 2 12:34:25 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/xor3/sky130_fd_sc_ms__xor3_2.pxi.spice b/cells/xor3/sky130_fd_sc_ms__xor3_2.pxi.spice index 0ea701f..1ceb4a8 100644 --- a/cells/xor3/sky130_fd_sc_ms__xor3_2.pxi.spice +++ b/cells/xor3/sky130_fd_sc_ms__xor3_2.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor3_2.pxi.spice -* Created: Fri Aug 28 18:19:48 2020 +* Created: Wed Sep 2 12:34:25 2020 * x_PM_SKY130_FD_SC_MS__XOR3_2%A_83_289# N_A_83_289#_M1000_d N_A_83_289#_M1021_d + N_A_83_289#_M1008_d N_A_83_289#_M1013_d N_A_83_289#_M1018_g
diff --git a/cells/xor3/sky130_fd_sc_ms__xor3_2.spice b/cells/xor3/sky130_fd_sc_ms__xor3_2.spice index da7583b..1e1ce18 100644 --- a/cells/xor3/sky130_fd_sc_ms__xor3_2.spice +++ b/cells/xor3/sky130_fd_sc_ms__xor3_2.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor3_2.spice -* Created: Fri Aug 28 18:19:48 2020 +* Created: Wed Sep 2 12:34:25 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *
diff --git a/cells/xor3/sky130_fd_sc_ms__xor3_4.lvs.report b/cells/xor3/sky130_fd_sc_ms__xor3_4.lvs.report new file mode 100644 index 0000000..afaf7d6 --- /dev/null +++ b/cells/xor3/sky130_fd_sc_ms__xor3_4.lvs.report
@@ -0,0 +1,469 @@ + + + + ################################################## + ## ## + ## C A L I B R E S Y S T E M ## + ## ## + ## L V S R E P O R T ## + ## ## + ################################################## + + + +REPORT FILE NAME: sky130_fd_sc_ms__xor3_4.lvs.report +LAYOUT NAME: svdb/sky130_fd_sc_ms__xor3_4.sp ('sky130_fd_sc_ms__xor3_4') +SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_ms/cells/xor3/sky130_fd_sc_ms__xor3_4.spice ('sky130_fd_sc_ms__xor3_4') +RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_ +CREATION TIME: Wed Sep 2 12:34:29 2020 +CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre +USER NAME: hlusk +CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018 + + + + OVERALL COMPARISON RESULTS + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + + +************************************************************************************************************** + CELL SUMMARY +************************************************************************************************************** + + Result Layout Source + ----------- ----------- -------------- + CORRECT sky130_fd_sc_ms__xor3_4 sky130_fd_sc_ms__xor3_4 + + + +************************************************************************************************************** + LVS PARAMETERS +************************************************************************************************************** + + +o LVS Setup: + + // LVS COMPONENT TYPE PROPERTY + // LVS COMPONENT SUBTYPE PROPERTY + // LVS PIN NAME PROPERTY + // LVS POWER NAME + // LVS GROUND NAME + LVS CELL SUPPLY NO + LVS RECOGNIZE GATES ALL + LVS IGNORE PORTS NO + LVS CHECK PORT NAMES YES + LVS IGNORE TRIVIAL NAMED PORTS NO + LVS BUILTIN DEVICE PIN SWAP YES + LVS ALL CAPACITOR PINS SWAPPABLE NO + LVS DISCARD PINS BY DEVICE YES + LVS SOFT SUBSTRATE PINS NO + LVS INJECT LOGIC NO + LVS EXPAND UNBALANCED CELLS YES + LVS FLATTEN INSIDE CELL NO + LVS EXPAND SEED PROMOTIONS NO + LVS PRESERVE PARAMETERIZED CELLS NO + LVS GLOBALS ARE PORTS YES + LVS REVERSE WL NO + LVS SPICE PREFER PINS YES + LVS SPICE SLASH IS SPACE NO + LVS SPICE ALLOW FLOATING PINS YES + LVS SPICE ALLOW INLINE PARAMETERS NO + LVS SPICE ALLOW UNQUOTED STRINGS YES + LVS SPICE CONDITIONAL LDD NO + LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO + // LVS SPICE EXCLUDE CELL SOURCE + // LVS SPICE EXCLUDE CELL LAYOUT + LVS SPICE IMPLIED MOS AREA NO + // LVS SPICE MULTIPLIER NAME + LVS SPICE OVERRIDE GLOBALS YES + LVS SPICE REDEFINE PARAM YES + LVS SPICE REPLICATE DEVICES YES + LVS SPICE SCALE X PARAMETERS NO + LVS SPICE STRICT WL YES + // LVS SPICE OPTION + LVS STRICT SUBTYPES YES + LVS EXACT SUBTYPES NO + LAYOUT CASE NO + SOURCE CASE NO + LVS COMPARE CASE NO + LVS DOWNCASE DEVICE NO + LVS REPORT MAXIMUM 50 + LVS PROPERTY RESOLUTION MAXIMUM ALL + LVS SIGNATURE MAXIMUM ALL + // LVS FILTER UNUSED OPTION + // LVS REPORT OPTION + LVS REPORT UNITS YES + // LVS NON USER NAME PORT + LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$" + // LVS NON USER NAME INSTANCE + // LVS IGNORE DEVICE PIN + // LVS PREFER NETS FILTER SOURCE + // LVS PREFER NETS FILTER LAYOUT + + // Device Type Map + + LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT + LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT + + // Reduction + + LVS REDUCE SERIES MOS NO + LVS REDUCE PARALLEL MOS NO + LVS REDUCE SEMI SERIES MOS NO + LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ] + LVS REDUCE PARALLEL BIPOLAR NO + LVS REDUCE SERIES CAPACITORS NO + LVS REDUCE PARALLEL CAPACITORS NO + LVS REDUCE SERIES RESISTORS NO + LVS REDUCE PARALLEL RESISTORS NO + LVS REDUCE PARALLEL DIODES NO + + LVS REDUCE condiode PARALLEL + LVS REDUCE condiodeHvPsub PARALLEL + LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ] + LVS REDUCE Q(npnpar1x1) PARALLEL + LVS REDUCE Q(npnpar1x2) PARALLEL + LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL + LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ] + LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ] + LVS REDUCE D SERIES POS NEG NO + LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ] + LVS REDUCE R SERIES POS NEG NO + LVS REDUCE R(short) PARALLEL + LVS REDUCE R(short) SERIES POS NEG NO + LVS REDUCE R(fuse) PARALLEL NO + LVS REDUCE R(fuse) SERIES POS NEG NO + LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ] + LVS REDUCE R(metop) SERIES POS NEG NO + LVS REDUCTION PRIORITY PARALLEL + + LVS SHORT EQUIVALENT NODES NO + + // Filter + + LVS FILTER R(cds_thru) SHORT SOURCE + LVS FILTER R(cds_thru) SHORT LAYOUT + LVS FILTER Dpar OPEN SOURCE + LVS FILTER Dpar OPEN LAYOUT + LVS FILTER Probe OPEN SOURCE + LVS FILTER Probe OPEN LAYOUT + LVS FILTER icecap OPEN SOURCE + LVS FILTER s8fmlt_iref_termx OPEN SOURCE + LVS FILTER s8fmlt_neg_termx OPEN SOURCE + LVS FILTER s8fmlt_termx OPEN SOURCE + LVS FILTER s8fmlt_vdac_termx OPEN SOURCE + LVS FILTER D OPEN SOURCE + LVS FILTER diff_dev OPEN SOURCE + LVS FILTER diff_dev OPEN LAYOUT + LVS FILTER tap_dev OPEN SOURCE + LVS FILTER tap_dev OPEN LAYOUT + LVS FILTER cad_dummy_open_device OPEN SOURCE + LVS FILTER cad_dummy_open_device OPEN LAYOUT + + // Trace Property + + TRACE PROPERTY xcnwvc m m 0 + TRACE PROPERTY xcnwvc w w 0 + TRACE PROPERTY xcnwvc l l 0 + TRACE PROPERTY xcnwvc2 m m 0 + TRACE PROPERTY xcnwvc2 w w 0 + TRACE PROPERTY xcnwvc2 l l 0 + TRACE PROPERTY xchvnwc m m 0 + TRACE PROPERTY q(npnpar1x1) m m 0 + TRACE PROPERTY q(npnpar1x2) m m 0 + TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0 + TRACE PROPERTY q(pnppar) barea barea 0 + TRACE PROPERTY q(pnppar) bperi bperi 0 + TRACE PROPERTY q(pnppar) earea earea 0 + TRACE PROPERTY q(pnppar) eperi eperi 0 + TRACE PROPERTY q(pnppar) m m 0 + TRACE PROPERTY q(pnppar5x) barea barea 0 + TRACE PROPERTY q(pnppar5x) bperi bperi 0 + TRACE PROPERTY q(pnppar5x) earea earea 0 + TRACE PROPERTY q(pnppar5x) eperi eperi 0 + TRACE PROPERTY q(pnppar5x) m m 0 + TRACE PROPERTY d(ndiode) a a 1 + TRACE PROPERTY d(ndiode) p p 1 + TRACE PROPERTY d(ndiode) m m 0 + TRACE PROPERTY d(ndiode_h) a a 1 + TRACE PROPERTY d(ndiode_h) p p 1 + TRACE PROPERTY d(ndiode_h) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_300) m m 0 + TRACE PROPERTY d(pdiode) a a 1 + TRACE PROPERTY d(pdiode) p p 1 + TRACE PROPERTY d(pdiode) m m 0 + TRACE PROPERTY d(pdiode_h) a a 1 + TRACE PROPERTY d(pdiode_h) p p 1 + TRACE PROPERTY d(pdiode_h) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_100) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_100) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_100) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_200) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_200) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_200) m m 0 + TRACE PROPERTY d(xesd_pdiode_h_300) a a 1 + TRACE PROPERTY d(xesd_pdiode_h_300) p p 1 + TRACE PROPERTY d(xesd_pdiode_h_300) m m 0 + TRACE PROPERTY d(dnwdiode_psub) a a 1 + TRACE PROPERTY d(dnwdiode_psub) p p 1 + TRACE PROPERTY d(dnwdiode_psub) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1 + TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0 + TRACE PROPERTY xcmvpp m m 0 + TRACE PROPERTY xcmvpp_2 m m 0 + TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp2_phv5x4 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0 + TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0 + TRACE PROPERTY xcmvpp_hd5_5x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_4x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_3x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_2x1 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x2 m m 0 + TRACE PROPERTY xcmvpp_hd5_1x1 m m 0 + TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0 + TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0 + TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0 + TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0 + TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0 + TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0 + TRACE PROPERTY xcmvpp5 m m 0 + TRACE PROPERTY xcmvpp4 m m 0 + TRACE PROPERTY xcmvpp3 m m 0 + TRACE PROPERTY r(mrdn) w w 1 + TRACE PROPERTY r(mrdn) l l 1 + TRACE PROPERTY r(mrdn) m m 0 + TRACE PROPERTY r(mrdn_hv) w w 1 + TRACE PROPERTY r(mrdn_hv) l l 1 + TRACE PROPERTY r(mrdn_hv) m m 0 + TRACE PROPERTY r(mrdp) w w 1 + TRACE PROPERTY r(mrdp) l l 1 + TRACE PROPERTY r(mrdp) m m 0 + TRACE PROPERTY r(mrdp_hv) w w 1 + TRACE PROPERTY r(mrdp_hv) l l 1 + TRACE PROPERTY r(mrdp_hv) m m 0 + TRACE PROPERTY r(mrl1) w w 1 + TRACE PROPERTY r(mrl1) l l 1 + TRACE PROPERTY r(mrl1) m m 0 + TRACE PROPERTY r(xpwres) w w 1 + TRACE PROPERTY r(xpwres) l l 1 + TRACE PROPERTY r(xpwres) m m 0 + TRACE PROPERTY r(short) m m 0 + TRACE PROPERTY r(fuse) w w 1 + TRACE PROPERTY r(fuse) l l 1 + TRACE PROPERTY r(fuse) m m 0 + TRACE PROPERTY r(metop) metopnumber metopnumber 0 + TRACE PROPERTY d(dnwdiode_psub_victim) a a 10 + TRACE PROPERTY d(dnwdiode_psub_victim) p p 10 + TRACE PROPERTY d(dnwdiode_psub_victim) m m 0 + TRACE PROPERTY d(nwdiode_victim) a a 10 + TRACE PROPERTY d(nwdiode_victim) p p 10 + TRACE PROPERTY d(nwdiode_victim) m m 0 + TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10 + TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0 + TRACE PROPERTY d(nwdiode_aggressor) a a 10 + TRACE PROPERTY d(nwdiode_aggressor) p p 10 + TRACE PROPERTY d(nwdiode_aggressor) m m 0 + + // User Trace Property + + TRACE PROPERTY mn(nshort) m mult w l + TRACE PROPERTY mn(npass) m mult w l + TRACE PROPERTY mn(nlowvt) m mult w l + TRACE PROPERTY m(sonos_e) m mult w l + TRACE PROPERTY m m mult w l + TRACE PROPERTY m(fnpass) m mult w l + TRACE PROPERTY mn(nhv) m mult w l + TRACE PROPERTY mn(nhvnative) m mult w l + TRACE PROPERTY mn(ntvnative) m mult w l + TRACE PROPERTY mp(pshort) m mult w l + TRACE PROPERTY mp m mult w l + TRACE PROPERTY mp(phighvt) m mult w l + TRACE PROPERTY mp(plowvt) m mult w l + TRACE PROPERTY mp(phv) m mult w l + TRACE PROPERTY mn(nshortesd) m mult w l + TRACE PROPERTY mn(nhvesd) m mult w l + TRACE PROPERTY mn(nhvnativeesd) m mult w l + TRACE PROPERTY mp(phvesd) m mult w l + TRACE PROPERTY nvhv m mult w l + TRACE PROPERTY n20vhv1 m mult w l + TRACE PROPERTY n20nativevhv1 m mult w l + TRACE PROPERTY n20vhviso1 m mult w l + TRACE PROPERTY n20nativevhviso1 m mult w l + TRACE PROPERTY pvhv m mult w l + TRACE PROPERTY p20vhv1 m mult w l + TRACE PROPERTY c(xcmimc1) w l m + TRACE PROPERTY c(xcmimc2) w l m + TRACE PROPERTY r(mrp1) m w l + TRACE PROPERTY xhrpoly_0p35 m w l + TRACE PROPERTY xuhrpoly_0p35 m w l + TRACE PROPERTY xhrpoly_0p69 m w l + TRACE PROPERTY xuhrpoly_0p69 m w l + TRACE PROPERTY xhrpoly_1p41 m w l + TRACE PROPERTY xuhrpoly_1p41 m w l + TRACE PROPERTY xhrpoly_2p85 m w l + TRACE PROPERTY xuhrpoly_2p85 m w l + + + + CELL COMPARISON RESULTS ( TOP LEVEL ) + + + + # ################### _ _ + # # # * * + # # # CORRECT # | + # # # # \___/ + # ################### + + + +LAYOUT CELL NAME: sky130_fd_sc_ms__xor3_4 +SOURCE CELL NAME: sky130_fd_sc_ms__xor3_4 + +-------------------------------------------------------------------------------------------------------------- + +INITIAL NUMBERS OF OBJECTS +-------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 14 14 MN (4 pins) + 14 14 MP (4 pins) + 1 0 * Dpar (2 pins) + ------ ------ + Total Inst: 29 28 + + +NUMBERS OF OBJECTS AFTER TRANSFORMATION +--------------------------------------- + + Layout Source Component Type + ------ ------ -------------- + Ports: 8 8 + + Nets: 15 15 + + Instances: 11 11 MN (4 pins) + 11 11 MP (4 pins) + ------ ------ + Total Inst: 22 22 + + + * = Number of objects in layout different from number in source. + + + +************************************************************************************************************** + INFORMATION AND WARNINGS +************************************************************************************************************** + + + Matched Matched Unmatched Unmatched Component + Layout Source Layout Source Type + ------- ------- --------- --------- --------- + Ports: 8 8 0 0 + + Nets: 15 15 0 0 + + Instances: 11 11 0 0 MN(NLOWVT) + 11 11 0 0 MP(PSHORT) + ------- ------- --------- --------- + Total Inst: 22 22 0 0 + + +o Statistics: + + 1 layout instance was filtered and its pins removed from adjoining nets. + + 8 layout mos transistors were reduced to 2. + 6 mos transistors were deleted by parallel reduction. + 8 source mos transistors were reduced to 2. + 6 mos transistors were deleted by parallel reduction. + + +o Initial Correspondence Points: + + Ports: VNB VPB A B C VPWR X VGND + + +************************************************************************************************************** + SUMMARY +************************************************************************************************************** + +Total CPU Time: 0 sec +Total Elapsed Time: 0 sec
diff --git a/cells/xor3/sky130_fd_sc_ms__xor3_4.pex.spice b/cells/xor3/sky130_fd_sc_ms__xor3_4.pex.spice index 0f7ef7c..3c55864 100644 --- a/cells/xor3/sky130_fd_sc_ms__xor3_4.pex.spice +++ b/cells/xor3/sky130_fd_sc_ms__xor3_4.pex.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor3_4.pex.spice -* Created: Fri Aug 28 18:19:58 2020 +* Created: Wed Sep 2 12:34:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" * Nominal Temperature: 27C
diff --git a/cells/xor3/sky130_fd_sc_ms__xor3_4.pxi.spice b/cells/xor3/sky130_fd_sc_ms__xor3_4.pxi.spice index 7486541..f8069fe 100644 --- a/cells/xor3/sky130_fd_sc_ms__xor3_4.pxi.spice +++ b/cells/xor3/sky130_fd_sc_ms__xor3_4.pxi.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor3_4.pxi.spice -* Created: Fri Aug 28 18:19:58 2020 +* Created: Wed Sep 2 12:34:32 2020 * x_PM_SKY130_FD_SC_MS__XOR3_4%A_74_294# N_A_74_294#_M1023_d N_A_74_294#_M1027_d + N_A_74_294#_M1025_d N_A_74_294#_M1014_d N_A_74_294#_M1002_g
diff --git a/cells/xor3/sky130_fd_sc_ms__xor3_4.spice b/cells/xor3/sky130_fd_sc_ms__xor3_4.spice index e6e3998..c9851fb 100644 --- a/cells/xor3/sky130_fd_sc_ms__xor3_4.spice +++ b/cells/xor3/sky130_fd_sc_ms__xor3_4.spice
@@ -1,5 +1,5 @@ * File: sky130_fd_sc_ms__xor3_4.spice -* Created: Fri Aug 28 18:19:58 2020 +* Created: Wed Sep 2 12:34:32 2020 * Program "Calibre xRC" * Version "v2018.4_34.26" *