openlane/unigate/config.json

{
    "DESIGN_NAME": "unigate",
    "DESIGN_IS_CORE": 0,
    "VERILOG_FILES": [
        "dir::../../verilog/rtl/defines.v",
        "dir::../../verilog/rtl/u21.v",
        "dir::../../verilog/rtl/u31.v",
        "dir::../../verilog/rtl/u41.v",
        "dir::../../verilog/rtl/u22.v",
        "dir::../../verilog/rtl/ucomb.v",
        "dir::../../verilog/rtl/u21_ref.v",
        "dir::../../verilog/rtl/u31_ref.v",
        "dir::../../verilog/rtl/u41_norm.v",
        "dir::../../verilog/rtl/u41_rest.v",
        "dir::../../verilog/rtl/u41_ref.v",
        "dir::../../verilog/rtl/u22_ref.v",
        "dir::../../verilog/rtl/ucomb_ref.v",
        "dir::../../verilog/rtl/ucomb_full.v",
        "dir::../../verilog/rtl/unigate.v"
    ],
    "CLOCK_PERIOD": 100,
    "CLOCK_PORT": "wb_clk_i",
    "CLOCK_NET": "wb_clk_i",
    "FP_SIZING": "absolute",
    "DIE_AREA": "0 0 1600 2200",
    "FP_ASPECT_RATIO": 1.375,
    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
    "PL_BASIC_PLACEMENT": 0,
    "PL_TARGET_DENSITY": 0.04,
    "PL_RESIZER_HOLD_SLACK_MARGIN": 1.0,
    "VDD_NETS": ["vccd1"],
    "GND_NETS": ["vssd1"],
    "DIODE_INSERTION_STRATEGY": 4,
    "RUN_CVC": 1,
    "pdk::sky130*": {
        "FP_CORE_UTIL": 3,
        "RT_MAX_LAYER": "met4",
        "scl::sky130_fd_sc_hd": {
            "CLOCK_PERIOD": 100
        },
        "scl::sky130_fd_sc_hdll": {
            "CLOCK_PERIOD": 100
        },
        "scl::sky130_fd_sc_hs": {
            "CLOCK_PERIOD": 80
        },
        "scl::sky130_fd_sc_ls": {
            "CLOCK_PERIOD": 100,
            "SYNTH_MAX_FANOUT": 5
        },
        "scl::sky130_fd_sc_ms": {
            "CLOCK_PERIOD": 100
        }
    },
    "pdk::gf180mcuC": {
        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
        "CLOCK_PERIOD": 24.0,
        "FP_CORE_UTIL": 40,
        "RT_MAX_LAYER": "Metal4",
        "SYNTH_MAX_FANOUT": 4,
        "PL_TARGET_DENSITY": 0.45
    }
}