Update configuration

openlane/unigate/config.json

diff --git a/openlane/unigate/config.json b/openlane/unigate/config.json
index a94868f..e5c4367 100644
--- a/openlane/unigate/config.json
+++ b/openlane/unigate/config.json
@@ -10,42 +10,46 @@
         "dir::../../verilog/rtl/ucomb.v",
         "dir::../../verilog/rtl/u21_ref.v",
         "dir::../../verilog/rtl/u31_ref.v",
+        "dir::../../verilog/rtl/u41_norm.v",
+        "dir::../../verilog/rtl/u41_rest.v",
         "dir::../../verilog/rtl/u41_ref.v",
         "dir::../../verilog/rtl/u22_ref.v",
         "dir::../../verilog/rtl/ucomb_ref.v",
         "dir::../../verilog/rtl/ucomb_full.v",
         "dir::../../verilog/rtl/unigate.v"
     ],
-    "CLOCK_PERIOD": 10,
+    "CLOCK_PERIOD": 100,
     "CLOCK_PORT": "wb_clk_i",
     "CLOCK_NET": "wb_clk_i",
     "FP_SIZING": "absolute",
-    "DIE_AREA": "0 0 2400 2700",
+    "DIE_AREA": "0 0 1600 2200",
+    "FP_ASPECT_RATIO": 1.375,
     "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
     "PL_BASIC_PLACEMENT": 0,
-    "PL_TARGET_DENSITY": 0.2,
+    "PL_TARGET_DENSITY": 0.04,
+    "PL_RESIZER_HOLD_SLACK_MARGIN": 1.0,
     "VDD_NETS": ["vccd1"],
     "GND_NETS": ["vssd1"],
     "DIODE_INSERTION_STRATEGY": 4,
     "RUN_CVC": 1,
     "pdk::sky130*": {
-        "FP_CORE_UTIL": 45,
+        "FP_CORE_UTIL": 3,
         "RT_MAX_LAYER": "met4",
         "scl::sky130_fd_sc_hd": {
-            "CLOCK_PERIOD": 10
+            "CLOCK_PERIOD": 100
         },
         "scl::sky130_fd_sc_hdll": {
-            "CLOCK_PERIOD": 10
+            "CLOCK_PERIOD": 100
         },
         "scl::sky130_fd_sc_hs": {
-            "CLOCK_PERIOD": 8
+            "CLOCK_PERIOD": 80
         },
         "scl::sky130_fd_sc_ls": {
-            "CLOCK_PERIOD": 10,
+            "CLOCK_PERIOD": 100,
             "SYNTH_MAX_FANOUT": 5
         },
         "scl::sky130_fd_sc_ms": {
-            "CLOCK_PERIOD": 10
+            "CLOCK_PERIOD": 100
         }
     },
     "pdk::gf180mcuC": {

openlane/user_project_wrapper/config.json

diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index fab8db2..9c7a06c 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -1,7 +1,7 @@
 {
     "DESIGN_NAME": "user_project_wrapper",
     "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v"],
-    "CLOCK_PERIOD": 10,
+    "CLOCK_PERIOD": 100,
     "CLOCK_PORT": "user_clock2",
     "CLOCK_NET": "mprj.clk",
     "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
@@ -15,6 +15,8 @@
         "dir::../../verilog/rtl/ucomb.v",
         "dir::../../verilog/rtl/u21_ref.v",
         "dir::../../verilog/rtl/u31_ref.v",
+        "dir::../../verilog/rtl/u41_norm.v",
+        "dir::../../verilog/rtl/u41_rest.v",
         "dir::../../verilog/rtl/u41_ref.v",
         "dir::../../verilog/rtl/u22_ref.v",
         "dir::../../verilog/rtl/ucomb_ref.v",
@@ -67,20 +69,20 @@
         "DIE_AREA": "0 0 2920 3520",
         "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
         "scl::sky130_fd_sc_hd": {
-            "CLOCK_PERIOD": 10
+            "CLOCK_PERIOD": 100
         },
         "scl::sky130_fd_sc_hdll": {
-            "CLOCK_PERIOD": 10
+            "CLOCK_PERIOD": 100
         },
         "scl::sky130_fd_sc_hs": {
-            "CLOCK_PERIOD": 8
+            "CLOCK_PERIOD": 80
         },
         "scl::sky130_fd_sc_ls": {
-            "CLOCK_PERIOD": 10,
+            "CLOCK_PERIOD": 100,
             "SYNTH_MAX_FANOUT": 5
         },
         "scl::sky130_fd_sc_ms": {
-            "CLOCK_PERIOD": 10
+            "CLOCK_PERIOD": 100
         }
      },
     "pdk::gf180mcuC": {

openlane/user_project_wrapper/macro.cfg

diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..28079b7 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1690 N
+mprj 660 660 N