verilog/includes/includes.gl.caravel_user_project

# Caravel user project includes	     
-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v	     
#-v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v     

# comment these two lines and uncomment the line below them to try actual gl sim
-v $(USER_PROJECT_VERILOG)/gl/SoC_Tile_for_backend_rtl_with_power_ports.v
-v $(USER_PROJECT_VERILOG)/rtl/mems.v

#-v $(USER_PROJECT_VERILOG)/gl/SoC_Tile_netlist.sim_gl_for_user_project_wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/sram_1KB_8.v
-v $(USER_PROJECT_VERILOG)/rtl/sram_1KB_32.v