| /** |
| * Copyright 2020 The SkyWater PDK Authors |
| * |
| * Licensed under the Apache License, Version 2.0 (the "License"); |
| * you may not use this file except in compliance with the License. |
| * You may obtain a copy of the License at |
| * |
| * https://www.apache.org/licenses/LICENSE-2.0 |
| * |
| * Unless required by applicable law or agreed to in writing, software |
| * distributed under the License is distributed on an "AS IS" BASIS, |
| * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| * See the License for the specific language governing permissions and |
| * limitations under the License. |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| library (sky130_fd_io__top_ground_lvc_wpad_ss_n40C_1v40_1v65) { |
| define(driver_model,library,string); |
| define(clk_width,library,string); |
| define(sim_opt,library,string); |
| define(simulator,library,string); |
| define(signal_voltage_type,pin,string); |
| technology ( cmos ) ; |
| delay_model : table_lookup; |
| revision : 1.0 ; |
| date : "Fri Oct 14 13:32:54 MST 2011"; |
| voltage_unit : "1V" ; |
| current_unit : "1mA" ; |
| leakage_power_unit : "1nW" ; |
| pulling_resistance_unit : "1kohm" ; |
| time_unit : "1ns" ; |
| resistance_unit : "1ohm" ; |
| capacitive_load_unit (1,pf) ; |
| |
| nom_process : 1.0 ; |
| nom_temperature : -40 ; |
| nom_voltage : 1.40 ; |
| |
| default_leakage_power_density : 0.0; |
| default_cell_leakage_power : 0.0; |
| bus_naming_style : "%s[%d]" ; |
| default_fanout_load : 0.0 ; |
| default_inout_pin_cap : 0.0 ; |
| default_input_pin_cap : 0.0 ; |
| default_output_pin_cap : 0.0 ; |
| default_max_transition : 1.00 ; |
| input_threshold_pct_rise : 50.0 ; |
| input_threshold_pct_fall : 50.0 ; |
| output_threshold_pct_rise : 50.0 ; |
| output_threshold_pct_fall : 50.0 ; |
| slew_lower_threshold_pct_fall : 20.0 ; |
| slew_lower_threshold_pct_rise : 20.0 ; |
| slew_upper_threshold_pct_fall : 80.0 ; |
| slew_upper_threshold_pct_rise : 80.0 ; |
| slew_derate_from_library : 1 ; |
| in_place_swap_mode : match_footprint ; |
| |
| library_features (report_delay_calculation); |
| define (always_on, pin, boolean) ; |
| |
| voltage_map(VCCD, 1.40); |
| voltage_map(VCCHIB, 1.40); |
| |
| voltage_map(VDDIO, 1.65); |
| voltage_map(VDDIO_Q, 1.65); |
| voltage_map(VDDA, 1.65); |
| voltage_map(VSWITCH, 3.00); |
| |
| voltage_map(VSSA, 0.0); |
| voltage_map(VSSD, 0.0); |
| voltage_map(VSSIO, 0.0); |
| voltage_map(VSSIO_Q, 0.0); |
| |
| voltage_map(DRN_LVC1, 1.40); |
| voltage_map(DRN_LVC2, 1.40); |
| voltage_map(OGC_LVC, 1.65); |
| |
| voltage_map(SRC_BDY_LVC1, 0.00); |
| voltage_map(SRC_BDY_LVC2, 0.00); |
| voltage_map(BDY2_B2B, 0.00); |
| voltage_map(G_CORE, 0.00); |
| |
| operating_conditions (deep_sleep_max_-40) { |
| process : 1 ; |
| temperature : -40 ; |
| voltage : 1.40 ; |
| tree_type : balanced_tree ; |
| } |
| default_operating_conditions : "deep_sleep_max_-40" |
| |
| cell (sky130_fd_io__top_ground_lvc_wpad) { |
| cell_leakage_power : 0.01 ; |
| area : 14850.0 ; |
| pad_cell : true; |
| |
| dont_touch : true ; /* don't optimize this cell */ |
| is_macro_cell : true; |
| dont_use : true ; /* don't infer this cell */ |
| interface_timing : true; /* this is a black box - a complex cell*/ |
| |
| pg_pin(VCCD) { |
| voltage_name : VCCD ; |
| pg_type : primary_power ; |
| } |
| |
| pg_pin(VCCHIB) { |
| voltage_name : VCCHIB ; |
| pg_type : primary_power ; |
| } |
| |
| pg_pin(VDDA) { |
| voltage_name : VDDA ; |
| pg_type : primary_power ; |
| } |
| |
| pg_pin(VDDIO) { |
| voltage_name : VDDIO ; |
| pg_type : primary_power ; |
| } |
| |
| pg_pin(VDDIO_Q) { |
| voltage_name : VDDIO_Q ; |
| pg_type : primary_power ; |
| } |
| |
| pg_pin (VSWITCH) { |
| voltage_name : "VSWITCH"; |
| pg_type : "primary_power"; |
| } |
| |
| pg_pin(VSSA) { |
| voltage_name : VSSA ; |
| pg_type : primary_ground ; |
| } |
| pg_pin(VSSD) { |
| voltage_name : VSSD ; |
| pg_type : primary_ground ; |
| } |
| pg_pin(VSSIO) { |
| voltage_name : VSSIO ; |
| pg_type : primary_ground ; |
| } |
| pg_pin(VSSIO_Q) { |
| voltage_name : VSSIO_Q ; |
| pg_type : primary_ground ; |
| } |
| |
| pg_pin(DRN_LVC1) { |
| voltage_name : DRN_LVC1; |
| pg_type : primary_power ; |
| } |
| |
| pg_pin(SRC_BDY_LVC1) { |
| voltage_name : SRC_BDY_LVC1 ; |
| pg_type : primary_ground ; |
| } |
| |
| pg_pin(DRN_LVC2) { |
| voltage_name : DRN_LVC2; |
| pg_type : primary_power ; |
| } |
| |
| pg_pin(SRC_BDY_LVC2) { |
| voltage_name : SRC_BDY_LVC2 ; |
| pg_type : primary_ground ; |
| } |
| |
| pg_pin(OGC_LVC) { |
| voltage_name : OGC_LVC ; |
| pg_type : primary_power ; |
| } |
| |
| pg_pin(BDY2_B2B) { |
| voltage_name : BDY2_B2B ; |
| pg_type : primary_ground ; |
| } |
| |
| pg_pin(G_CORE) { |
| voltage_name : G_CORE ; |
| pg_type : primary_ground ; |
| } /* pin */ |
| |
| pin(G_PAD) { |
| direction : inout; |
| always_on : true; |
| is_pad : true ; |
| signal_voltage_type : "analog" ; |
| related_power_pin : "VDDIO"; |
| related_ground_pin : "VSSD"; |
| always_on : true; |
| rise_capacitance : 0.069348; |
| capacitance : 0.070467; |
| fall_capacitance : 0.071586; |
| } /* pin */ |
| pin ("AMUXBUS_A") { |
| direction : "inout"; |
| related_power_pin : "VDDIO"; |
| related_ground_pin : "VSSD"; |
| always_on : true; |
| signal_voltage_type : "analog"; |
| rise_capacitance : 0.069348; |
| capacitance : 0.070467; |
| fall_capacitance : 0.071586; |
| } |
| pin ("AMUXBUS_B") { |
| direction : "inout"; |
| related_power_pin : "VDDIO"; |
| related_ground_pin : "VSSD"; |
| always_on : true; |
| signal_voltage_type : "analog"; |
| rise_capacitance : 0.069348; |
| capacitance : 0.070467; |
| fall_capacitance : 0.071586; |
| } |
| } |
| } |
