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+## UETRV-ESoC-v2
+UETRV-ECORE-v2 is a RISC-V based SoC derived from [UETRV_ESoC](https://github.com/ee-uet/UETRV_ESoC) with a few bug-fixes and increased memory sizes; it has been passed through the Cadence VLSI flow for submission to Google and Efabless' Open-MPW-8 shuttle using Skywater's 130 nm PDK. The verilog rtl used in this repo is generated from Scala source, available [here](https://github.com/ee-uet/UETRV_ESoC). Further details about the peripheral memory map, bootloader, example programs, testbenches etc. are also provided in that repo. The following are the differences between UETRV-ESoC and UETRV-ESoC-v2:
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A Heading
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* A bullet
- Another bullet
-A link to a file in my repo: [io_ports_tb.v](verilog/dv/io_ports/io_ports_tb.v)
+//A link to a file in my repo: [io_ports_tb.v](verilog/dv/io_ports/io_ports_tb.v)
+#//A link to a file in my repo: [io_ports_tb.v](verilog/dv/io_ports/io_ports_tb.v)
