| commit | 4c25b90107191950a3e2ebb51eb962bd79f81505 | [log] [tgz] |
|---|---|---|
| author | m-usama-z <107983847+m-usama-z@users.noreply.github.com> | Sat Nov 26 14:24:49 2022 +0500 |
| committer | GitHub <noreply@github.com> | Sat Nov 26 14:24:49 2022 +0500 |
| tree | 707f6073bfac15d49bcb6ab53683e27022129e9e | |
| parent | 5ecfde2c8b267de9e319957c662336408e9b12fb [diff] |
Update README.md
UETRV-ECORE-v2 is a RISC-V based SoC derived from UETRV_ESoC with a few bug-fixes and increased memory sizes; it has been passed through the Cadence VLSI flow for submission to Google and Efabless' Open-MPW-8 shuttle using Skywater's 130 nm PDK. The verilog rtl used in this repo is generated from Scala source, available here. Further details about the peripheral memory map, bootloader, example programs, testbenches etc. are also provided in that repo. The following are the differences between UETRV-ESoC and UETRV-ESoC-v2:
//A link to a file in my repo: io_ports_tb.v #//A link to a file in my repo: io_ports_tb.v