blob: 0a06059d2e60c81686029bbcd11f55e95d0bbe75 [file] [log] [blame]
{
"DESIGN_NAME": "icache",
"DESIGN_IS_CORE": 0,
"VERILOG_FILES": [
"dir::../../verilog/rtl/defines.v",
"dir::../../verilog/rtl/ppcpu/rtl/icache/icache.v",
"dir::../../verilog/rtl/ppcpu/rtl/icache/icache_ram.v"
],
"VERILOG_INCLUDE_DIRS": ["dir::../../verilog/rtl/ppcpu/rtl/"],
"CLOCK_PERIOD": 10,
"CLOCK_PORT": "i_clk",
"CLOCK_NET": "i_clk",
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 1600 600",
"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
"PL_BASIC_PLACEMENT": 0,
"PL_TARGET_DENSITY": 0.30,
"VDD_NETS": ["vccd1"],
"GND_NETS": ["vssd1"],
"DIODE_INSERTION_STRATEGY": 4,
"RUN_CVC": 1,
"pdk::sky130*": {
"FP_CORE_UTIL": 45,
"RT_MAX_LAYER": "met4",
"scl::sky130_fd_sc_hd": {
"CLOCK_PERIOD": 10
},
"scl::sky130_fd_sc_hdll": {
"CLOCK_PERIOD": 10
},
"scl::sky130_fd_sc_hs": {
"CLOCK_PERIOD": 8
},
"scl::sky130_fd_sc_ls": {
"CLOCK_PERIOD": 10,
"SYNTH_MAX_FANOUT": 5
},
"scl::sky130_fd_sc_ms": {
"CLOCK_PERIOD": 10
}
},
"PL_RESIZER_HOLD_SLACK_MARGIN": 0.7,
"GLB_RESIZER_HOLD_SLACK_MARGIN": 0.7,
"PL_RESIZER_SETUP_SLACK_MARGIN": 1.5,
"GLB_RESIZER_SETUP_SLACK_MARGIN": 2,
"ROUTING_CORES": 6
}