openlane/dcache/config.json

{
    "DESIGN_NAME": "dcache",
    "DESIGN_IS_CORE": 0,
    "VERILOG_FILES": [
        "dir::../../verilog/rtl/defines.v", 
        "dir::../../verilog/rtl/ppcpu/rtl/dcache/dcache.v",
        "dir::../../verilog/rtl/ppcpu/rtl/dcache/dcache_ram.v"
    ],
    "VERILOG_INCLUDE_DIRS": ["dir::../../verilog/rtl/ppcpu/rtl/"],
    "CLOCK_PERIOD": 12,
    "CLOCK_PORT": "i_clk",
    "CLOCK_NET": "i_clk",
    "FP_SIZING": "absolute",
    "DIE_AREA": "0 0 1450 1400",
    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
    "PL_BASIC_PLACEMENT": 0,
    "PL_TARGET_DENSITY": 0.26,
    "VDD_NETS": ["vccd1"],
    "GND_NETS": ["vssd1"],
    "DIODE_INSERTION_STRATEGY": 4,
    "RUN_CVC": 1,
    "RT_MAX_LAYER": "met4",
    "PL_RESIZER_HOLD_SLACK_MARGIN": 0.8,
    "GLB_RESIZER_HOLD_SLACK_MARGIN": 0.8,
    "PL_RESIZER_SETUP_SLACK_MARGIN": 3,
    "GLB_RESIZER_SETUP_SLACK_MARGIN": 3,
    "PL_RESIZER_SETUP_MAX_BUFFER_PERCENT": 80,
    "GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT": 80,
    "SYNTH_STRATEGY": "DELAY 4",
    "ROUTING_CORES": 6
}