Verilog defines and wrapper
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index 3537de8..c294096 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -21,8 +21,6 @@ // Assume default net type to be wire because GL netlists don't have the wire definitions `default_nettype wire `include "gl/user_project_wrapper.v" - `include "gl/user_proj_example.v" `else `include "user_project_wrapper.v" - `include "user_proj_example.v" `endif \ No newline at end of file
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v index ee44b08..11b5cd8 100644 --- a/verilog/rtl/user_defines.v +++ b/verilog/rtl/user_defines.v
@@ -52,41 +52,41 @@ // up in a state that can be used immediately without depending on // the management SoC to run a startup program to configure the GPIOs. -`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_OUTPUT +`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_USER_STD_OUTPUT +`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL // Configurations of GPIO 14 to 24 are used on caravel but not caravan. -`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL -`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_INVALID -`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_INVALID +`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_USER_STD_BIDIRECTIONAL +`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN +`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN +`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_USER_STD_OUTPUT +`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_USER_STD_OUTPUT +`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN +`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN +`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN +`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN +`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_USER_STD_INPUT_PULLUP +`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN +`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_OUTPUT +`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_OUTPUT `endif // __USER_DEFINES_H
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v deleted file mode 100644 index 26081e9..0000000 --- a/verilog/rtl/user_proj_example.v +++ /dev/null
@@ -1,165 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none -/* - *------------------------------------------------------------- - * - * user_proj_example - * - * This is an example of a (trivially simple) user project, - * showing how the user project can connect to the logic - * analyzer, the wishbone bus, and the I/O pads. - * - * This project generates an integer count, which is output - * on the user area GPIO pads (digital output only). The - * wishbone connection allows the project to be controlled - * (start and stop) from the management SoC program. - * - * See the testbenches in directory "mprj_counter" for the - * example programs that drive this user project. The three - * testbenches are "io_ports", "la_test1", and "la_test2". - * - *------------------------------------------------------------- - */ - -module user_proj_example #( - parameter BITS = 32 -)( -`ifdef USE_POWER_PINS - inout vccd1, // User area 1 1.8V supply - inout vssd1, // User area 1 digital ground -`endif - - // Wishbone Slave ports (WB MI A) - input wb_clk_i, - input wb_rst_i, - input wbs_stb_i, - input wbs_cyc_i, - input wbs_we_i, - input [3:0] wbs_sel_i, - input [31:0] wbs_dat_i, - input [31:0] wbs_adr_i, - output wbs_ack_o, - output [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input [127:0] la_data_in, - output [127:0] la_data_out, - input [127:0] la_oenb, - - // IOs - input [`MPRJ_IO_PADS-1:0] io_in, - output [`MPRJ_IO_PADS-1:0] io_out, - output [`MPRJ_IO_PADS-1:0] io_oeb, - - // IRQ - output [2:0] irq -); - wire clk; - wire rst; - - wire [`MPRJ_IO_PADS-1:0] io_in; - wire [`MPRJ_IO_PADS-1:0] io_out; - wire [`MPRJ_IO_PADS-1:0] io_oeb; - - wire [31:0] rdata; - wire [31:0] wdata; - wire [BITS-1:0] count; - - wire valid; - wire [3:0] wstrb; - wire [31:0] la_write; - - // WB MI A - assign valid = wbs_cyc_i && wbs_stb_i; - assign wstrb = wbs_sel_i & {4{wbs_we_i}}; - assign wbs_dat_o = rdata; - assign wdata = wbs_dat_i; - - // IO - assign io_out = count; - assign io_oeb = {(`MPRJ_IO_PADS-1){rst}}; - - // IRQ - assign irq = 3'b000; // Unused - - // LA - assign la_data_out = {{(127-BITS){1'b0}}, count}; - // Assuming LA probes [63:32] are for controlling the count register - assign la_write = ~la_oenb[63:32] & ~{BITS{valid}}; - // Assuming LA probes [65:64] are for controlling the count clk & reset - assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i; - assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i; - - counter #( - .BITS(BITS) - ) counter( - .clk(clk), - .reset(rst), - .ready(wbs_ack_o), - .valid(valid), - .rdata(rdata), - .wdata(wbs_dat_i), - .wstrb(wstrb), - .la_write(la_write), - .la_input(la_data_in[63:32]), - .count(count) - ); - -endmodule - -module counter #( - parameter BITS = 32 -)( - input clk, - input reset, - input valid, - input [3:0] wstrb, - input [BITS-1:0] wdata, - input [BITS-1:0] la_write, - input [BITS-1:0] la_input, - output ready, - output [BITS-1:0] rdata, - output [BITS-1:0] count -); - reg ready; - reg [BITS-1:0] count; - reg [BITS-1:0] rdata; - - always @(posedge clk) begin - if (reset) begin - count <= 0; - ready <= 0; - end else begin - ready <= 1'b0; - if (~|la_write) begin - count <= count + 1; - end - if (valid && !ready) begin - ready <= 1'b1; - rdata <= count; - if (wstrb[0]) count[7:0] <= wdata[7:0]; - if (wstrb[1]) count[15:8] <= wdata[15:8]; - if (wstrb[2]) count[23:16] <= wdata[23:16]; - if (wstrb[3]) count[31:24] <= wdata[31:24]; - end else if (|la_write) begin - count <= la_write & la_input; - end - end - end - -endmodule -`default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 5ee1cee..05d9401 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -29,9 +29,7 @@ *------------------------------------------------------------- */ -module user_project_wrapper #( - parameter BITS = 32 -) ( +module user_project_wrapper ( `ifdef USE_POWER_PINS inout vdda1, // User area 1 3.3V supply inout vdda2, // User area 2 3.3V supply @@ -82,25 +80,25 @@ /* User project is instantiated here */ /*--------------------------------------*/ -user_proj_example mprj ( +top mprj ( `ifdef USE_POWER_PINS .vccd1(vccd1), // User area 1 1.8V power .vssd1(vssd1), // User area 1 digital ground `endif - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), + .mgt_wb_clk_i(wb_clk_i), + .mgt_wb_rst_i(wb_rst_i), // MGMT SoC Wishbone Slave - .wbs_cyc_i(wbs_cyc_i), - .wbs_stb_i(wbs_stb_i), - .wbs_we_i(wbs_we_i), - .wbs_sel_i(wbs_sel_i), - .wbs_adr_i(wbs_adr_i), - .wbs_dat_i(wbs_dat_i), - .wbs_ack_o(wbs_ack_o), - .wbs_dat_o(wbs_dat_o), + .mgt_wb_cyc_i(wbs_cyc_i), + .mgt_wb_stb_i(wbs_stb_i), + .mgt_wb_we_i(wbs_we_i), + .mgt_wb_sel_i(wbs_sel_i), + .mgt_wb_adr_i(wbs_adr_i), + .mgt_wb_dat_i(wbs_dat_i), + .mgt_wb_ack_o(wbs_ack_o), + .mgt_wb_dat_o(wbs_dat_o), // Logic Analyzer @@ -110,12 +108,14 @@ // IO Pads - .io_in (io_in), - .io_out(io_out), - .io_oeb(io_oeb), + .m_io_in (io_in), + .m_io_out(io_out), + .m_io_oeb(io_oeb), // IRQ - .irq(user_irq) + .irq(user_irq), + + .user_clock2(user_clock2) ); endmodule // user_project_wrapper