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foss-eda-tools / third_party / shuttle / sky130 / mpw-008 / slot-030 / 4592fc35ba09ab49db01eac18b8c925a947ea6d8 / . / lib / core / runs / 22_12_26_19_07 / logs / routing / 18-detailed.log
blob: f48a36da262c592e7de19e06f57e6b6f3bc8fd55 [file] [log] [blame]
OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ORD-0030] Using 6 thread(s).
[INFO DRT-0149] Reading tech and libs.
Units: 1000
Number of layers: 13
Number of macros: 441
Number of vias: 25
Number of viarulegen: 25
[INFO DRT-0150] Reading design.
Design: core
Die area: ( 0 0 ) ( 500000 500000 )
Number of track patterns: 12
Number of DEF vias: 3
Number of components: 35773
Number of terminals: 254
Number of snets: 2
Number of nets: 4865
[INFO DRT-0167] List of default vias:
Layer mcon
default via: L1M1_PR
Layer via
default via: M1M2_PR
Layer via2
default via: M2M3_PR
Layer via3
default via: M3M4_PR
Layer via4
default via: M4M5_PR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
Complete 10000 instances.
Complete 20000 instances.
Complete 30000 instances.
[INFO DRT-0164] Number of unique instances = 475.
[INFO DRT-0168] Init region query.
[INFO DRT-0018] Complete 10000 insts.
[INFO DRT-0018] Complete 20000 insts.
[INFO DRT-0018] Complete 30000 insts.
[INFO DRT-0024] Complete FR_MASTERSLICE.
[INFO DRT-0024] Complete Fr_VIA.
[INFO DRT-0024] Complete li1.
[INFO DRT-0024] Complete mcon.
[INFO DRT-0024] Complete met1.
[INFO DRT-0024] Complete via.
[INFO DRT-0024] Complete met2.
[INFO DRT-0024] Complete via2.
[INFO DRT-0024] Complete met3.
[INFO DRT-0024] Complete via3.
[INFO DRT-0024] Complete met4.
[INFO DRT-0024] Complete via4.
[INFO DRT-0024] Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] FR_VIA shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 277676.
[INFO DRT-0033] mcon shape region query size = 362545.
[INFO DRT-0033] met1 shape region query size = 80092.
[INFO DRT-0033] via shape region query size = 3080.
[INFO DRT-0033] met2 shape region query size = 1920.
[INFO DRT-0033] via2 shape region query size = 2464.
[INFO DRT-0033] met3 shape region query size = 2028.
[INFO DRT-0033] via3 shape region query size = 2464.
[INFO DRT-0033] met4 shape region query size = 630.
[INFO DRT-0033] via4 shape region query size = 0.
[INFO DRT-0033] met5 shape region query size = 0.
[INFO DRT-0165] Start pin access.
[INFO DRT-0076] Complete 100 pins.
[INFO DRT-0076] Complete 200 pins.
[INFO DRT-0076] Complete 300 pins.
[INFO DRT-0076] Complete 400 pins.
[INFO DRT-0076] Complete 500 pins.
[INFO DRT-0076] Complete 600 pins.
[INFO DRT-0076] Complete 700 pins.
[INFO DRT-0076] Complete 800 pins.
[INFO DRT-0076] Complete 900 pins.
[INFO DRT-0077] Complete 1000 pins.
[INFO DRT-0078] Complete 1902 pins.
[INFO DRT-0079] Complete 100 unique inst patterns.
[INFO DRT-0079] Complete 200 unique inst patterns.
[INFO DRT-0079] Complete 300 unique inst patterns.
[INFO DRT-0079] Complete 400 unique inst patterns.
[INFO DRT-0081] Complete 457 unique inst patterns.
[INFO DRT-0082] Complete 1000 groups.
[INFO DRT-0082] Complete 2000 groups.
[INFO DRT-0082] Complete 3000 groups.
[INFO DRT-0082] Complete 4000 groups.
[INFO DRT-0082] Complete 5000 groups.
[INFO DRT-0082] Complete 6000 groups.
[INFO DRT-0082] Complete 7000 groups.
[INFO DRT-0082] Complete 8000 groups.
[INFO DRT-0082] Complete 9000 groups.
[INFO DRT-0084] Complete 9622 groups.
#scanned instances = 35773
#unique instances = 475
#stdCellGenAp = 14225
#stdCellValidPlanarAp = 61
#stdCellValidViaAp = 10924
#stdCellPinNoAp = 0
#stdCellPinCnt = 16962
#instTermValidViaApCnt = 0
#macroGenAp = 0
#macroValidPlanarAp = 0
#macroValidViaAp = 0
#macroNoAp = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:01:04, elapsed time = 00:00:13, memory = 236.41 (MB), peak = 237.55 (MB)
Number of guides: 46745
[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 72 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 72 STEP 6900 ;
[INFO DRT-0026] Complete 10000 origin guides.
[INFO DRT-0026] Complete 20000 origin guides.
[INFO DRT-0026] Complete 30000 origin guides.
[INFO DRT-0026] Complete 40000 origin guides.
[INFO DRT-0028] Complete FR_MASTERSLICE.
[INFO DRT-0028] Complete Fr_VIA.
[INFO DRT-0028] Complete li1.
[INFO DRT-0028] Complete mcon.
[INFO DRT-0028] Complete met1.
[INFO DRT-0028] Complete via.
[INFO DRT-0028] Complete met2.
[INFO DRT-0028] Complete via2.
[INFO DRT-0028] Complete met3.
[INFO DRT-0028] Complete via3.
[INFO DRT-0028] Complete met4.
[INFO DRT-0028] Complete via4.
[INFO DRT-0028] Complete met5.
[INFO DRT-0178] Init guide query.
[INFO DRT-0035] Complete FR_MASTERSLICE (guide).
[INFO DRT-0035] Complete Fr_VIA (guide).
[INFO DRT-0035] Complete li1 (guide).
[INFO DRT-0035] Complete mcon (guide).
[INFO DRT-0035] Complete met1 (guide).
[INFO DRT-0035] Complete via (guide).
[INFO DRT-0035] Complete met2 (guide).
[INFO DRT-0035] Complete via2 (guide).
[INFO DRT-0035] Complete met3 (guide).
[INFO DRT-0035] Complete via3 (guide).
[INFO DRT-0035] Complete met4 (guide).
[INFO DRT-0035] Complete via4 (guide).
[INFO DRT-0035] Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] FR_VIA guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 17205.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 14093.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 7567.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 315.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 60.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 0.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0245] skipped writing guide updates to database.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 24832 vertical wires in 2 frboxes and 14408 horizontal wires in 2 frboxes.
[INFO DRT-0186] Done with 2900 vertical wires in 2 frboxes and 4533 horizontal wires in 2 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:00:03, elapsed time = 00:00:02, memory = 344.55 (MB), peak = 365.91 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 344.58 (MB), peak = 365.91 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:01, memory = 586.20 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:04, memory = 815.92 (MB).
Completing 30% with 589 violations.
elapsed time = 00:00:05, memory = 532.07 (MB).
Completing 40% with 589 violations.
elapsed time = 00:00:08, memory = 745.46 (MB).
Completing 50% with 589 violations.
elapsed time = 00:00:10, memory = 881.02 (MB).
Completing 60% with 1165 violations.
elapsed time = 00:00:11, memory = 719.54 (MB).
Completing 70% with 1165 violations.
elapsed time = 00:00:15, memory = 829.70 (MB).
Completing 80% with 1743 violations.
elapsed time = 00:00:18, memory = 684.03 (MB).
Completing 90% with 1743 violations.
elapsed time = 00:00:21, memory = 841.01 (MB).
Completing 100% with 2330 violations.
elapsed time = 00:00:25, memory = 739.59 (MB).
[INFO DRT-0199] Number of violations = 4502.
Viol/Layer li1 mcon met1 met2 met3 met4
Cut Spacing 0 1 0 0 0 0
Metal Spacing 24 0 417 48 28 0
Min Hole 0 0 1 0 0 0
NS Metal 1 0 0 0 0 0
Recheck 0 0 1404 620 144 4
Short 0 0 1669 138 3 0
[INFO DRT-0267] cpu time = 00:01:53, elapsed time = 00:00:25, memory = 1012.91 (MB), peak = 1012.91 (MB)
Total wire length = 286236 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 143005 um.
Total wire length on LAYER met2 = 133002 um.
Total wire length on LAYER met3 = 5685 um.
Total wire length on LAYER met4 = 4543 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 46874.
Up-via summary (total 46874):.
------------------------
FR_MASTERSLICE 0
li1 21772
met1 24577
met2 420
met3 105
met4 0
------------------------
46874
[INFO DRT-0195] Start 1st optimization iteration.
Completing 10% with 4502 violations.
elapsed time = 00:00:01, memory = 1052.83 (MB).
Completing 20% with 4502 violations.
elapsed time = 00:00:04, memory = 1188.98 (MB).
Completing 30% with 3549 violations.
elapsed time = 00:00:06, memory = 989.41 (MB).
Completing 40% with 3549 violations.
elapsed time = 00:00:09, memory = 1071.00 (MB).
Completing 50% with 3549 violations.
elapsed time = 00:00:11, memory = 1187.48 (MB).
Completing 60% with 2668 violations.
elapsed time = 00:00:13, memory = 1009.19 (MB).
Completing 70% with 2668 violations.
elapsed time = 00:00:17, memory = 1138.98 (MB).
Completing 80% with 2037 violations.
elapsed time = 00:00:20, memory = 1001.92 (MB).
Completing 90% with 2037 violations.
elapsed time = 00:00:23, memory = 1065.52 (MB).
Completing 100% with 1409 violations.
elapsed time = 00:00:26, memory = 1023.32 (MB).
[INFO DRT-0199] Number of violations = 1552.
Viol/Layer mcon met1 met2 met3
Cut Spacing 1 0 0 0
Metal Spacing 0 247 31 0
Recheck 0 0 0 143
Short 0 1105 25 0
[INFO DRT-0267] cpu time = 00:01:55, elapsed time = 00:00:26, memory = 1023.83 (MB), peak = 1200.96 (MB)
Total wire length = 284596 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 142861 um.
Total wire length on LAYER met2 = 131718 um.
Total wire length on LAYER met3 = 5475 um.
Total wire length on LAYER met4 = 4540 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 46559.
Up-via summary (total 46559):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24263
met2 433
met3 98
met4 0
------------------------
46559
[INFO DRT-0195] Start 2nd optimization iteration.
Completing 10% with 1552 violations.
elapsed time = 00:00:00, memory = 1042.78 (MB).
Completing 20% with 1552 violations.
elapsed time = 00:00:03, memory = 1084.48 (MB).
Completing 30% with 1562 violations.
elapsed time = 00:00:06, memory = 1009.14 (MB).
Completing 40% with 1562 violations.
elapsed time = 00:00:09, memory = 1049.81 (MB).
Completing 50% with 1562 violations.
elapsed time = 00:00:11, memory = 1105.21 (MB).
Completing 60% with 1455 violations.
elapsed time = 00:00:12, memory = 991.30 (MB).
Completing 70% with 1455 violations.
elapsed time = 00:00:15, memory = 1057.34 (MB).
Completing 80% with 1424 violations.
elapsed time = 00:00:18, memory = 986.72 (MB).
Completing 90% with 1424 violations.
elapsed time = 00:00:22, memory = 1067.03 (MB).
Completing 100% with 1380 violations.
elapsed time = 00:00:24, memory = 986.01 (MB).
[INFO DRT-0199] Number of violations = 1429.
Viol/Layer mcon met1 met2
Cut Spacing 4 0 0
Metal Spacing 0 299 17
Recheck 0 49 0
Short 0 1036 24
[INFO DRT-0267] cpu time = 00:01:46, elapsed time = 00:00:24, memory = 995.74 (MB), peak = 1200.96 (MB)
Total wire length = 284135 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 142682 um.
Total wire length on LAYER met2 = 131386 um.
Total wire length on LAYER met3 = 5536 um.
Total wire length on LAYER met4 = 4530 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 46544.
Up-via summary (total 46544):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24242
met2 439
met3 98
met4 0
------------------------
46544
[INFO DRT-0195] Start 3rd optimization iteration.
Completing 10% with 1429 violations.
elapsed time = 00:00:02, memory = 1064.54 (MB).
Completing 20% with 1429 violations.
elapsed time = 00:00:08, memory = 1183.75 (MB).
Completing 30% with 1090 violations.
elapsed time = 00:00:18, memory = 1010.11 (MB).
Completing 40% with 1090 violations.
elapsed time = 00:00:20, memory = 1108.51 (MB).
Completing 50% with 1090 violations.
elapsed time = 00:00:23, memory = 1162.77 (MB).
Completing 60% with 876 violations.
elapsed time = 00:00:37, memory = 1050.66 (MB).
Completing 70% with 876 violations.
elapsed time = 00:00:45, memory = 1171.38 (MB).
Completing 80% with 634 violations.
elapsed time = 00:00:51, memory = 1036.61 (MB).
Completing 90% with 634 violations.
elapsed time = 00:00:55, memory = 1084.30 (MB).
Completing 100% with 255 violations.
elapsed time = 00:01:02, memory = 1048.66 (MB).
[INFO DRT-0199] Number of violations = 255.
Viol/Layer mcon met1 met2
Cut Spacing 4 0 0
Metal Spacing 0 114 21
Short 0 112 4
[INFO DRT-0267] cpu time = 00:03:29, elapsed time = 00:01:02, memory = 1054.84 (MB), peak = 1200.96 (MB)
Total wire length = 283914 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 138288 um.
Total wire length on LAYER met2 = 131877 um.
Total wire length on LAYER met3 = 9223 um.
Total wire length on LAYER met4 = 4525 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47370.
Up-via summary (total 47370):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24616
met2 886
met3 103
met4 0
------------------------
47370
[INFO DRT-0195] Start 4th optimization iteration.
Completing 10% with 255 violations.
elapsed time = 00:00:00, memory = 1054.98 (MB).
Completing 20% with 255 violations.
elapsed time = 00:00:00, memory = 1075.80 (MB).
Completing 30% with 167 violations.
elapsed time = 00:00:05, memory = 1052.37 (MB).
Completing 40% with 167 violations.
elapsed time = 00:00:05, memory = 1053.91 (MB).
Completing 50% with 167 violations.
elapsed time = 00:00:06, memory = 1096.23 (MB).
Completing 60% with 120 violations.
elapsed time = 00:00:14, memory = 1052.90 (MB).
Completing 70% with 120 violations.
elapsed time = 00:00:15, memory = 1093.56 (MB).
Completing 80% with 72 violations.
elapsed time = 00:00:19, memory = 1052.22 (MB).
Completing 90% with 72 violations.
elapsed time = 00:00:20, memory = 1092.63 (MB).
Completing 100% with 39 violations.
elapsed time = 00:00:24, memory = 1052.82 (MB).
[INFO DRT-0199] Number of violations = 39.
Viol/Layer mcon met1
Cut Spacing 1 0
Metal Spacing 0 32
Short 0 6
[INFO DRT-0267] cpu time = 00:00:58, elapsed time = 00:00:24, memory = 1052.82 (MB), peak = 1200.96 (MB)
Total wire length = 283836 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 138041 um.
Total wire length on LAYER met2 = 131872 um.
Total wire length on LAYER met3 = 9397 um.
Total wire length on LAYER met4 = 4525 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47386.
Up-via summary (total 47386):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24625
met2 893
met3 103
met4 0
------------------------
47386
[INFO DRT-0195] Start 5th optimization iteration.
Completing 10% with 39 violations.
elapsed time = 00:00:00, memory = 1052.82 (MB).
Completing 20% with 39 violations.
elapsed time = 00:00:00, memory = 1052.82 (MB).
Completing 30% with 33 violations.
elapsed time = 00:00:03, memory = 1052.82 (MB).
Completing 40% with 33 violations.
elapsed time = 00:00:03, memory = 1052.82 (MB).
Completing 50% with 33 violations.
elapsed time = 00:00:03, memory = 1052.82 (MB).
Completing 60% with 27 violations.
elapsed time = 00:00:10, memory = 1053.03 (MB).
Completing 70% with 27 violations.
elapsed time = 00:00:10, memory = 1053.03 (MB).
Completing 80% with 17 violations.
elapsed time = 00:00:11, memory = 1053.03 (MB).
Completing 90% with 17 violations.
elapsed time = 00:00:11, memory = 1053.03 (MB).
Completing 100% with 17 violations.
elapsed time = 00:00:17, memory = 1053.03 (MB).
[INFO DRT-0199] Number of violations = 17.
Viol/Layer met1
Metal Spacing 16
Short 1
[INFO DRT-0267] cpu time = 00:00:30, elapsed time = 00:00:18, memory = 1053.03 (MB), peak = 1200.96 (MB)
Total wire length = 283844 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 138012 um.
Total wire length on LAYER met2 = 131877 um.
Total wire length on LAYER met3 = 9429 um.
Total wire length on LAYER met4 = 4525 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47387.
Up-via summary (total 47387):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24626
met2 893
met3 103
met4 0
------------------------
47387
[INFO DRT-0195] Start 6th optimization iteration.
Completing 10% with 17 violations.
elapsed time = 00:00:00, memory = 1053.03 (MB).
Completing 20% with 17 violations.
elapsed time = 00:00:00, memory = 1053.03 (MB).
Completing 30% with 17 violations.
elapsed time = 00:00:04, memory = 1053.03 (MB).
Completing 40% with 17 violations.
elapsed time = 00:00:04, memory = 1053.03 (MB).
Completing 50% with 17 violations.
elapsed time = 00:00:04, memory = 1053.03 (MB).
Completing 60% with 12 violations.
elapsed time = 00:00:08, memory = 1052.71 (MB).
Completing 70% with 12 violations.
elapsed time = 00:00:08, memory = 1052.71 (MB).
Completing 80% with 12 violations.
elapsed time = 00:00:09, memory = 1052.90 (MB).
Completing 90% with 12 violations.
elapsed time = 00:00:09, memory = 1052.90 (MB).
Completing 100% with 12 violations.
elapsed time = 00:00:14, memory = 1052.90 (MB).
[INFO DRT-0199] Number of violations = 12.
Viol/Layer met1
Metal Spacing 12
[INFO DRT-0267] cpu time = 00:00:16, elapsed time = 00:00:14, memory = 1052.90 (MB), peak = 1200.96 (MB)
Total wire length = 283861 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 137917 um.
Total wire length on LAYER met2 = 131876 um.
Total wire length on LAYER met3 = 9541 um.
Total wire length on LAYER met4 = 4525 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47388.
Up-via summary (total 47388):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24618
met2 902
met3 103
met4 0
------------------------
47388
[INFO DRT-0195] Start 7th optimization iteration.
Completing 10% with 12 violations.
elapsed time = 00:00:00, memory = 1052.90 (MB).
Completing 20% with 12 violations.
elapsed time = 00:00:00, memory = 1052.90 (MB).
Completing 30% with 12 violations.
elapsed time = 00:00:16, memory = 1052.96 (MB).
Completing 40% with 12 violations.
elapsed time = 00:00:16, memory = 1052.96 (MB).
Completing 50% with 12 violations.
elapsed time = 00:00:16, memory = 1052.96 (MB).
Completing 60% with 12 violations.
elapsed time = 00:00:22, memory = 1052.96 (MB).
Completing 70% with 12 violations.
elapsed time = 00:00:22, memory = 1052.96 (MB).
Completing 80% with 11 violations.
elapsed time = 00:00:23, memory = 1052.96 (MB).
Completing 90% with 11 violations.
elapsed time = 00:00:23, memory = 1052.96 (MB).
Completing 100% with 11 violations.
elapsed time = 00:00:25, memory = 1052.96 (MB).
[INFO DRT-0199] Number of violations = 11.
Viol/Layer mcon met1
Cut Spacing 1 0
Metal Spacing 0 10
[INFO DRT-0267] cpu time = 00:00:25, elapsed time = 00:00:25, memory = 1052.96 (MB), peak = 1200.96 (MB)
Total wire length = 283857 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 137918 um.
Total wire length on LAYER met2 = 131875 um.
Total wire length on LAYER met3 = 9538 um.
Total wire length on LAYER met4 = 4525 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47388.
Up-via summary (total 47388):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24619
met2 901
met3 103
met4 0
------------------------
47388
[INFO DRT-0195] Start 8th optimization iteration.
Completing 10% with 11 violations.
elapsed time = 00:00:00, memory = 1052.96 (MB).
Completing 20% with 11 violations.
elapsed time = 00:00:00, memory = 1052.96 (MB).
Completing 30% with 11 violations.
elapsed time = 00:00:21, memory = 1052.96 (MB).
Completing 40% with 11 violations.
elapsed time = 00:00:21, memory = 1052.96 (MB).
Completing 50% with 11 violations.
elapsed time = 00:00:21, memory = 1052.96 (MB).
Completing 60% with 6 violations.
elapsed time = 00:00:21, memory = 1052.96 (MB).
Completing 70% with 6 violations.
elapsed time = 00:00:21, memory = 1052.96 (MB).
Completing 80% with 3 violations.
elapsed time = 00:00:22, memory = 1052.96 (MB).
Completing 90% with 3 violations.
elapsed time = 00:00:22, memory = 1052.96 (MB).
Completing 100% with 3 violations.
elapsed time = 00:00:22, memory = 1052.96 (MB).
[INFO DRT-0199] Number of violations = 3.
Viol/Layer met1
Metal Spacing 3
[INFO DRT-0267] cpu time = 00:00:22, elapsed time = 00:00:22, memory = 1052.96 (MB), peak = 1200.96 (MB)
Total wire length = 283851 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 137921 um.
Total wire length on LAYER met2 = 131867 um.
Total wire length on LAYER met3 = 9538 um.
Total wire length on LAYER met4 = 4525 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47385.
Up-via summary (total 47385):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24616
met2 901
met3 103
met4 0
------------------------
47385
[INFO DRT-0195] Start 9th optimization iteration.
Completing 10% with 3 violations.
elapsed time = 00:00:00, memory = 1052.96 (MB).
Completing 20% with 3 violations.
elapsed time = 00:00:00, memory = 1052.96 (MB).
Completing 30% with 3 violations.
elapsed time = 00:00:08, memory = 1052.96 (MB).
Completing 40% with 3 violations.
elapsed time = 00:00:08, memory = 1052.96 (MB).
Completing 50% with 3 violations.
elapsed time = 00:00:08, memory = 1052.96 (MB).
Completing 60% with 3 violations.
elapsed time = 00:00:08, memory = 1052.96 (MB).
Completing 70% with 3 violations.
elapsed time = 00:00:08, memory = 1052.96 (MB).
Completing 80% with 3 violations.
elapsed time = 00:00:12, memory = 1052.96 (MB).
Completing 90% with 3 violations.
elapsed time = 00:00:12, memory = 1052.96 (MB).
Completing 100% with 3 violations.
elapsed time = 00:00:12, memory = 1052.96 (MB).
[INFO DRT-0199] Number of violations = 3.
Viol/Layer met1
Metal Spacing 3
[INFO DRT-0267] cpu time = 00:00:13, elapsed time = 00:00:13, memory = 1052.96 (MB), peak = 1200.96 (MB)
Total wire length = 283851 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 137921 um.
Total wire length on LAYER met2 = 131867 um.
Total wire length on LAYER met3 = 9538 um.
Total wire length on LAYER met4 = 4525 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47385.
Up-via summary (total 47385):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24616
met2 901
met3 103
met4 0
------------------------
47385
[INFO DRT-0195] Start 10th optimization iteration.
Completing 10% with 3 violations.
elapsed time = 00:00:00, memory = 1052.96 (MB).
Completing 20% with 3 violations.
elapsed time = 00:00:00, memory = 1052.96 (MB).
Completing 30% with 3 violations.
elapsed time = 00:00:00, memory = 1052.96 (MB).
Completing 40% with 3 violations.
elapsed time = 00:00:00, memory = 1052.96 (MB).
Completing 50% with 3 violations.
elapsed time = 00:00:00, memory = 1052.96 (MB).
Completing 60% with 3 violations.
elapsed time = 00:00:07, memory = 1082.03 (MB).
Completing 70% with 3 violations.
elapsed time = 00:00:07, memory = 1082.03 (MB).
Completing 80% with 3 violations.
elapsed time = 00:00:07, memory = 1082.03 (MB).
Completing 90% with 3 violations.
elapsed time = 00:00:07, memory = 1082.17 (MB).
Completing 100% with 3 violations.
elapsed time = 00:00:07, memory = 1082.17 (MB).
[INFO DRT-0199] Number of violations = 3.
Viol/Layer met1
Metal Spacing 3
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:07, memory = 1082.17 (MB), peak = 1200.96 (MB)
Total wire length = 283851 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 137921 um.
Total wire length on LAYER met2 = 131867 um.
Total wire length on LAYER met3 = 9538 um.
Total wire length on LAYER met4 = 4525 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47385.
Up-via summary (total 47385):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24616
met2 901
met3 103
met4 0
------------------------
47385
[INFO DRT-0195] Start 11th optimization iteration.
Completing 10% with 3 violations.
elapsed time = 00:00:00, memory = 1082.17 (MB).
Completing 20% with 3 violations.
elapsed time = 00:00:00, memory = 1082.17 (MB).
Completing 30% with 3 violations.
elapsed time = 00:00:03, memory = 1082.17 (MB).
Completing 40% with 3 violations.
elapsed time = 00:00:03, memory = 1082.17 (MB).
Completing 50% with 3 violations.
elapsed time = 00:00:03, memory = 1082.17 (MB).
Completing 60% with 3 violations.
elapsed time = 00:00:11, memory = 1082.17 (MB).
Completing 70% with 3 violations.
elapsed time = 00:00:11, memory = 1082.17 (MB).
Completing 80% with 3 violations.
elapsed time = 00:00:11, memory = 1082.17 (MB).
Completing 90% with 3 violations.
elapsed time = 00:00:11, memory = 1082.17 (MB).
Completing 100% with 3 violations.
elapsed time = 00:00:11, memory = 1082.17 (MB).
[INFO DRT-0199] Number of violations = 3.
Viol/Layer met1
Metal Spacing 3
[INFO DRT-0267] cpu time = 00:00:12, elapsed time = 00:00:12, memory = 1082.17 (MB), peak = 1200.96 (MB)
Total wire length = 283851 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 137921 um.
Total wire length on LAYER met2 = 131867 um.
Total wire length on LAYER met3 = 9538 um.
Total wire length on LAYER met4 = 4525 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47385.
Up-via summary (total 47385):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24616
met2 901
met3 103
met4 0
------------------------
47385
[INFO DRT-0195] Start 12th optimization iteration.
Completing 10% with 3 violations.
elapsed time = 00:00:00, memory = 1082.17 (MB).
Completing 20% with 3 violations.
elapsed time = 00:00:00, memory = 1082.17 (MB).
Completing 30% with 3 violations.
elapsed time = 00:00:04, memory = 1082.17 (MB).
Completing 40% with 3 violations.
elapsed time = 00:00:04, memory = 1082.17 (MB).
Completing 50% with 3 violations.
elapsed time = 00:00:04, memory = 1082.17 (MB).
Completing 60% with 3 violations.
elapsed time = 00:00:16, memory = 1052.84 (MB).
Completing 70% with 3 violations.
elapsed time = 00:00:16, memory = 1052.84 (MB).
Completing 80% with 3 violations.
elapsed time = 00:00:16, memory = 1052.84 (MB).
Completing 90% with 3 violations.
elapsed time = 00:00:16, memory = 1052.84 (MB).
Completing 100% with 3 violations.
elapsed time = 00:00:16, memory = 1052.84 (MB).
[INFO DRT-0199] Number of violations = 3.
Viol/Layer met1
Metal Spacing 3
[INFO DRT-0267] cpu time = 00:00:16, elapsed time = 00:00:16, memory = 1052.84 (MB), peak = 1200.96 (MB)
Total wire length = 283845 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 137917 um.
Total wire length on LAYER met2 = 131864 um.
Total wire length on LAYER met3 = 9538 um.
Total wire length on LAYER met4 = 4525 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47387.
Up-via summary (total 47387):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24618
met2 901
met3 103
met4 0
------------------------
47387
[INFO DRT-0195] Start 13th optimization iteration.
Completing 10% with 3 violations.
elapsed time = 00:00:00, memory = 1052.84 (MB).
Completing 20% with 3 violations.
elapsed time = 00:00:00, memory = 1052.84 (MB).
Completing 30% with 2 violations.
elapsed time = 00:00:11, memory = 1052.84 (MB).
Completing 40% with 2 violations.
elapsed time = 00:00:11, memory = 1052.84 (MB).
Completing 50% with 2 violations.
elapsed time = 00:00:11, memory = 1052.84 (MB).
Completing 60% with 2 violations.
elapsed time = 00:00:11, memory = 1052.84 (MB).
Completing 70% with 2 violations.
elapsed time = 00:00:11, memory = 1052.84 (MB).
Completing 80% with 2 violations.
elapsed time = 00:00:11, memory = 1052.84 (MB).
Completing 90% with 2 violations.
elapsed time = 00:00:11, memory = 1052.84 (MB).
Completing 100% with 2 violations.
elapsed time = 00:00:11, memory = 1052.84 (MB).
[INFO DRT-0199] Number of violations = 2.
Viol/Layer met1
Metal Spacing 2
[INFO DRT-0267] cpu time = 00:00:12, elapsed time = 00:00:12, memory = 1052.84 (MB), peak = 1200.96 (MB)
Total wire length = 283847 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 137888 um.
Total wire length on LAYER met2 = 131866 um.
Total wire length on LAYER met3 = 9567 um.
Total wire length on LAYER met4 = 4525 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47392.
Up-via summary (total 47392):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24619
met2 905
met3 103
met4 0
------------------------
47392
[INFO DRT-0195] Start 14th optimization iteration.
Completing 10% with 2 violations.
elapsed time = 00:00:00, memory = 1052.84 (MB).
Completing 20% with 2 violations.
elapsed time = 00:00:00, memory = 1052.84 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:05, memory = 1052.84 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:05, memory = 1052.84 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:05, memory = 1052.84 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:05, memory = 1052.84 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:05, memory = 1052.84 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:05, memory = 1052.84 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:05, memory = 1052.84 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:05, memory = 1052.84 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:06, memory = 1052.84 (MB), peak = 1200.96 (MB)
Total wire length = 283836 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 137882 um.
Total wire length on LAYER met2 = 131863 um.
Total wire length on LAYER met3 = 9565 um.
Total wire length on LAYER met4 = 4525 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47391.
Up-via summary (total 47391):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24620
met2 903
met3 103
met4 0
------------------------
47391
[INFO DRT-0198] Complete detail routing.
Total wire length = 283836 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 137882 um.
Total wire length on LAYER met2 = 131863 um.
Total wire length on LAYER met3 = 9565 um.
Total wire length on LAYER met4 = 4525 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 47391.
Up-via summary (total 47391):.
------------------------
FR_MASTERSLICE 0
li1 21765
met1 24620
met2 903
met3 103
met4 0
------------------------
47391
[INFO DRT-0267] cpu time = 00:12:48, elapsed time = 00:05:12, memory = 1052.84 (MB), peak = 1200.96 (MB)
[INFO DRT-0180] Post processing.
Setting global connections for newly added cells...
Writing OpenROAD database to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_07/results/routing/core.odb...
Writing netlist to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_07/results/routing/core.nl.v...
Writing powered netlist to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_07/results/routing/core.pnl.v...
Writing layout to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_19_07/results/routing/core.def...