| OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO ORD-0030] Using 6 thread(s). |
| [INFO DRT-0149] Reading tech and libs. |
| |
| Units: 1000 |
| Number of layers: 13 |
| Number of macros: 441 |
| Number of vias: 25 |
| Number of viarulegen: 25 |
| |
| [INFO DRT-0150] Reading design. |
| |
| Design: core |
| Die area: ( 0 0 ) ( 500000 500000 ) |
| Number of track patterns: 12 |
| Number of DEF vias: 3 |
| Number of components: 35774 |
| Number of terminals: 254 |
| Number of snets: 2 |
| Number of nets: 4863 |
| |
| [INFO DRT-0167] List of default vias: |
| Layer mcon |
| default via: L1M1_PR |
| Layer via |
| default via: M1M2_PR |
| Layer via2 |
| default via: M2M3_PR |
| Layer via3 |
| default via: M3M4_PR |
| Layer via4 |
| default via: M4M5_PR |
| [INFO DRT-0162] Library cell analysis. |
| [INFO DRT-0163] Instance analysis. |
| Complete 10000 instances. |
| Complete 20000 instances. |
| Complete 30000 instances. |
| [INFO DRT-0164] Number of unique instances = 471. |
| [INFO DRT-0168] Init region query. |
| [INFO DRT-0018] Complete 10000 insts. |
| [INFO DRT-0018] Complete 20000 insts. |
| [INFO DRT-0018] Complete 30000 insts. |
| [INFO DRT-0024] Complete FR_MASTERSLICE. |
| [INFO DRT-0024] Complete Fr_VIA. |
| [INFO DRT-0024] Complete li1. |
| [INFO DRT-0024] Complete mcon. |
| [INFO DRT-0024] Complete met1. |
| [INFO DRT-0024] Complete via. |
| [INFO DRT-0024] Complete met2. |
| [INFO DRT-0024] Complete via2. |
| [INFO DRT-0024] Complete met3. |
| [INFO DRT-0024] Complete via3. |
| [INFO DRT-0024] Complete met4. |
| [INFO DRT-0024] Complete via4. |
| [INFO DRT-0024] Complete met5. |
| [INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. |
| [INFO DRT-0033] FR_VIA shape region query size = 0. |
| [INFO DRT-0033] li1 shape region query size = 277407. |
| [INFO DRT-0033] mcon shape region query size = 362519. |
| [INFO DRT-0033] met1 shape region query size = 80084. |
| [INFO DRT-0033] via shape region query size = 3080. |
| [INFO DRT-0033] met2 shape region query size = 1920. |
| [INFO DRT-0033] via2 shape region query size = 2464. |
| [INFO DRT-0033] met3 shape region query size = 2028. |
| [INFO DRT-0033] via3 shape region query size = 2464. |
| [INFO DRT-0033] met4 shape region query size = 630. |
| [INFO DRT-0033] via4 shape region query size = 0. |
| [INFO DRT-0033] met5 shape region query size = 0. |
| [INFO DRT-0165] Start pin access. |
| [INFO DRT-0076] Complete 100 pins. |
| [INFO DRT-0076] Complete 200 pins. |
| [INFO DRT-0076] Complete 300 pins. |
| [INFO DRT-0076] Complete 400 pins. |
| [INFO DRT-0076] Complete 500 pins. |
| [INFO DRT-0076] Complete 600 pins. |
| [INFO DRT-0076] Complete 700 pins. |
| [INFO DRT-0076] Complete 800 pins. |
| [INFO DRT-0076] Complete 900 pins. |
| [INFO DRT-0077] Complete 1000 pins. |
| [INFO DRT-0078] Complete 1886 pins. |
| [INFO DRT-0079] Complete 100 unique inst patterns. |
| [INFO DRT-0079] Complete 200 unique inst patterns. |
| [INFO DRT-0079] Complete 300 unique inst patterns. |
| [INFO DRT-0079] Complete 400 unique inst patterns. |
| [INFO DRT-0081] Complete 453 unique inst patterns. |
| [INFO DRT-0082] Complete 1000 groups. |
| [INFO DRT-0082] Complete 2000 groups. |
| [INFO DRT-0082] Complete 3000 groups. |
| [INFO DRT-0082] Complete 4000 groups. |
| [INFO DRT-0082] Complete 5000 groups. |
| [INFO DRT-0082] Complete 6000 groups. |
| [INFO DRT-0082] Complete 7000 groups. |
| [INFO DRT-0082] Complete 8000 groups. |
| [INFO DRT-0082] Complete 9000 groups. |
| [INFO DRT-0084] Complete 9618 groups. |
| #scanned instances = 35774 |
| #unique instances = 471 |
| #stdCellGenAp = 14123 |
| #stdCellValidPlanarAp = 61 |
| #stdCellValidViaAp = 10861 |
| #stdCellPinNoAp = 0 |
| #stdCellPinCnt = 16958 |
| #instTermValidViaApCnt = 0 |
| #macroGenAp = 0 |
| #macroValidPlanarAp = 0 |
| #macroValidViaAp = 0 |
| #macroNoAp = 0 |
| [INFO DRT-0166] Complete pin access. |
| [INFO DRT-0267] cpu time = 00:01:07, elapsed time = 00:00:14, memory = 236.55 (MB), peak = 238.98 (MB) |
| |
| Number of guides: 46699 |
| |
| [INFO DRT-0169] Post process guides. |
| [INFO DRT-0176] GCELLGRID X 0 DO 72 STEP 6900 ; |
| [INFO DRT-0177] GCELLGRID Y 0 DO 72 STEP 6900 ; |
| [INFO DRT-0026] Complete 10000 origin guides. |
| [INFO DRT-0026] Complete 20000 origin guides. |
| [INFO DRT-0026] Complete 30000 origin guides. |
| [INFO DRT-0026] Complete 40000 origin guides. |
| [INFO DRT-0028] Complete FR_MASTERSLICE. |
| [INFO DRT-0028] Complete Fr_VIA. |
| [INFO DRT-0028] Complete li1. |
| [INFO DRT-0028] Complete mcon. |
| [INFO DRT-0028] Complete met1. |
| [INFO DRT-0028] Complete via. |
| [INFO DRT-0028] Complete met2. |
| [INFO DRT-0028] Complete via2. |
| [INFO DRT-0028] Complete met3. |
| [INFO DRT-0028] Complete via3. |
| [INFO DRT-0028] Complete met4. |
| [INFO DRT-0028] Complete via4. |
| [INFO DRT-0028] Complete met5. |
| [INFO DRT-0178] Init guide query. |
| [INFO DRT-0035] Complete FR_MASTERSLICE (guide). |
| [INFO DRT-0035] Complete Fr_VIA (guide). |
| [INFO DRT-0035] Complete li1 (guide). |
| [INFO DRT-0035] Complete mcon (guide). |
| [INFO DRT-0035] Complete met1 (guide). |
| [INFO DRT-0035] Complete via (guide). |
| [INFO DRT-0035] Complete met2 (guide). |
| [INFO DRT-0035] Complete via2 (guide). |
| [INFO DRT-0035] Complete met3 (guide). |
| [INFO DRT-0035] Complete via3 (guide). |
| [INFO DRT-0035] Complete met4 (guide). |
| [INFO DRT-0035] Complete via4 (guide). |
| [INFO DRT-0035] Complete met5 (guide). |
| [INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. |
| [INFO DRT-0036] FR_VIA guide region query size = 0. |
| [INFO DRT-0036] li1 guide region query size = 17206. |
| [INFO DRT-0036] mcon guide region query size = 0. |
| [INFO DRT-0036] met1 guide region query size = 14088. |
| [INFO DRT-0036] via guide region query size = 0. |
| [INFO DRT-0036] met2 guide region query size = 7564. |
| [INFO DRT-0036] via2 guide region query size = 0. |
| [INFO DRT-0036] met3 guide region query size = 320. |
| [INFO DRT-0036] via3 guide region query size = 0. |
| [INFO DRT-0036] met4 guide region query size = 60. |
| [INFO DRT-0036] via4 guide region query size = 0. |
| [INFO DRT-0036] met5 guide region query size = 0. |
| [INFO DRT-0179] Init gr pin query. |
| [INFO DRT-0245] skipped writing guide updates to database. |
| [INFO DRT-0185] Post process initialize RPin region query. |
| [INFO DRT-0181] Start track assignment. |
| [INFO DRT-0184] Done with 24830 vertical wires in 2 frboxes and 14408 horizontal wires in 2 frboxes. |
| [INFO DRT-0186] Done with 2903 vertical wires in 2 frboxes and 4547 horizontal wires in 2 frboxes. |
| [INFO DRT-0182] Complete track assignment. |
| [INFO DRT-0267] cpu time = 00:00:03, elapsed time = 00:00:02, memory = 344.96 (MB), peak = 365.59 (MB) |
| [INFO DRT-0187] Start routing data preparation. |
| [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 344.98 (MB), peak = 365.59 (MB) |
| [INFO DRT-0194] Start detail routing. |
| [INFO DRT-0195] Start 0th optimization iteration. |
| Completing 10% with 0 violations. |
| elapsed time = 00:00:01, memory = 568.27 (MB). |
| Completing 20% with 0 violations. |
| elapsed time = 00:00:04, memory = 822.67 (MB). |
| Completing 30% with 545 violations. |
| elapsed time = 00:00:05, memory = 611.95 (MB). |
| Completing 40% with 545 violations. |
| elapsed time = 00:00:09, memory = 726.86 (MB). |
| Completing 50% with 545 violations. |
| elapsed time = 00:00:11, memory = 833.70 (MB). |
| Completing 60% with 1137 violations. |
| elapsed time = 00:00:12, memory = 710.29 (MB). |
| Completing 70% with 1137 violations. |
| elapsed time = 00:00:16, memory = 786.08 (MB). |
| Completing 80% with 1720 violations. |
| elapsed time = 00:00:19, memory = 780.80 (MB). |
| Completing 90% with 1720 violations. |
| elapsed time = 00:00:23, memory = 870.16 (MB). |
| Completing 100% with 2269 violations. |
| elapsed time = 00:00:28, memory = 865.86 (MB). |
| [INFO DRT-0199] Number of violations = 4490. |
| Viol/Layer li1 mcon met1 met2 met3 met4 |
| Cut Spacing 0 1 0 0 0 0 |
| Metal Spacing 24 0 452 46 32 0 |
| Min Hole 0 0 4 0 0 0 |
| NS Metal 1 0 0 0 0 0 |
| Recheck 0 0 1404 664 148 5 |
| Short 0 0 1608 101 0 0 |
| [INFO DRT-0267] cpu time = 00:01:51, elapsed time = 00:00:28, memory = 1100.90 (MB), peak = 1100.90 (MB) |
| Total wire length = 286342 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 142884 um. |
| Total wire length on LAYER met2 = 132675 um. |
| Total wire length on LAYER met3 = 6242 um. |
| Total wire length on LAYER met4 = 4539 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 46910. |
| Up-via summary (total 46910):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 21766 |
| met1 24605 |
| met2 440 |
| met3 99 |
| met4 0 |
| ------------------------ |
| 46910 |
| |
| |
| [INFO DRT-0195] Start 1st optimization iteration. |
| Completing 10% with 4490 violations. |
| elapsed time = 00:00:01, memory = 1101.59 (MB). |
| Completing 20% with 4490 violations. |
| elapsed time = 00:00:04, memory = 1170.65 (MB). |
| Completing 30% with 3592 violations. |
| elapsed time = 00:00:07, memory = 1132.05 (MB). |
| Completing 40% with 3592 violations. |
| elapsed time = 00:00:10, memory = 1137.96 (MB). |
| Completing 50% with 3592 violations. |
| elapsed time = 00:00:12, memory = 1231.89 (MB). |
| Completing 60% with 2702 violations. |
| elapsed time = 00:00:14, memory = 1143.70 (MB). |
| Completing 70% with 2702 violations. |
| elapsed time = 00:00:16, memory = 1148.01 (MB). |
| Completing 80% with 2046 violations. |
| elapsed time = 00:00:19, memory = 1204.14 (MB). |
| Completing 90% with 2046 violations. |
| elapsed time = 00:00:23, memory = 1204.14 (MB). |
| Completing 100% with 1425 violations. |
| elapsed time = 00:00:27, memory = 1177.60 (MB). |
| [INFO DRT-0199] Number of violations = 1769. |
| Viol/Layer mcon met1 met2 met3 |
| Cut Spacing 7 0 0 0 |
| Metal Spacing 0 255 29 0 |
| Recheck 0 198 0 146 |
| Short 0 1104 30 0 |
| [INFO DRT-0267] cpu time = 00:01:48, elapsed time = 00:00:27, memory = 1178.11 (MB), peak = 1233.86 (MB) |
| Total wire length = 284540 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 142281 um. |
| Total wire length on LAYER met2 = 131644 um. |
| Total wire length on LAYER met3 = 6062 um. |
| Total wire length on LAYER met4 = 4551 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 46548. |
| Up-via summary (total 46548):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 21760 |
| met1 24255 |
| met2 434 |
| met3 99 |
| met4 0 |
| ------------------------ |
| 46548 |
| |
| |
| [INFO DRT-0195] Start 2nd optimization iteration. |
| Completing 10% with 1769 violations. |
| elapsed time = 00:00:00, memory = 1178.20 (MB). |
| Completing 20% with 1769 violations. |
| elapsed time = 00:00:04, memory = 1190.95 (MB). |
| Completing 30% with 1679 violations. |
| elapsed time = 00:00:07, memory = 1191.16 (MB). |
| Completing 40% with 1679 violations. |
| elapsed time = 00:00:10, memory = 1191.16 (MB). |
| Completing 50% with 1679 violations. |
| elapsed time = 00:00:12, memory = 1191.16 (MB). |
| Completing 60% with 1435 violations. |
| elapsed time = 00:00:14, memory = 1191.29 (MB). |
| Completing 70% with 1435 violations. |
| elapsed time = 00:00:18, memory = 1191.29 (MB). |
| Completing 80% with 1317 violations. |
| elapsed time = 00:00:21, memory = 1191.29 (MB). |
| Completing 90% with 1317 violations. |
| elapsed time = 00:00:26, memory = 1191.30 (MB). |
| Completing 100% with 1340 violations. |
| elapsed time = 00:00:29, memory = 1193.36 (MB). |
| [INFO DRT-0199] Number of violations = 1340. |
| Viol/Layer mcon met1 met2 |
| Cut Spacing 4 0 0 |
| Metal Spacing 0 269 20 |
| Short 0 1016 31 |
| [INFO DRT-0267] cpu time = 00:01:54, elapsed time = 00:00:29, memory = 1196.12 (MB), peak = 1233.86 (MB) |
| Total wire length = 284050 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 142206 um. |
| Total wire length on LAYER met2 = 131213 um. |
| Total wire length on LAYER met3 = 6088 um. |
| Total wire length on LAYER met4 = 4542 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 46431. |
| Up-via summary (total 46431):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 21760 |
| met1 24125 |
| met2 446 |
| met3 100 |
| met4 0 |
| ------------------------ |
| 46431 |
| |
| |
| [INFO DRT-0195] Start 3rd optimization iteration. |
| Completing 10% with 1340 violations. |
| elapsed time = 00:00:03, memory = 1200.42 (MB). |
| Completing 20% with 1340 violations. |
| elapsed time = 00:00:08, memory = 1287.16 (MB). |
| Completing 30% with 1123 violations. |
| elapsed time = 00:00:14, memory = 1185.76 (MB). |
| Completing 40% with 1123 violations. |
| elapsed time = 00:00:17, memory = 1185.76 (MB). |
| Completing 50% with 1123 violations. |
| elapsed time = 00:00:23, memory = 1185.76 (MB). |
| Completing 60% with 877 violations. |
| elapsed time = 00:00:26, memory = 1185.82 (MB). |
| Completing 70% with 877 violations. |
| elapsed time = 00:00:30, memory = 1185.82 (MB). |
| Completing 80% with 591 violations. |
| elapsed time = 00:00:38, memory = 1183.05 (MB). |
| Completing 90% with 591 violations. |
| elapsed time = 00:00:41, memory = 1212.56 (MB). |
| Completing 100% with 236 violations. |
| elapsed time = 00:00:50, memory = 1184.26 (MB). |
| [INFO DRT-0199] Number of violations = 236. |
| Viol/Layer mcon met1 via met2 |
| Cut Spacing 2 0 1 0 |
| Metal Spacing 0 96 0 3 |
| Short 0 134 0 0 |
| [INFO DRT-0267] cpu time = 00:03:01, elapsed time = 00:00:50, memory = 1184.26 (MB), peak = 1311.33 (MB) |
| Total wire length = 283874 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 137938 um. |
| Total wire length on LAYER met2 = 131582 um. |
| Total wire length on LAYER met3 = 9754 um. |
| Total wire length on LAYER met4 = 4599 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 47140. |
| Up-via summary (total 47140):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 21760 |
| met1 24368 |
| met2 908 |
| met3 104 |
| met4 0 |
| ------------------------ |
| 47140 |
| |
| |
| [INFO DRT-0195] Start 4th optimization iteration. |
| Completing 10% with 236 violations. |
| elapsed time = 00:00:00, memory = 1184.26 (MB). |
| Completing 20% with 236 violations. |
| elapsed time = 00:00:01, memory = 1184.26 (MB). |
| Completing 30% with 170 violations. |
| elapsed time = 00:00:08, memory = 1185.29 (MB). |
| Completing 40% with 170 violations. |
| elapsed time = 00:00:09, memory = 1185.36 (MB). |
| Completing 50% with 170 violations. |
| elapsed time = 00:00:09, memory = 1185.44 (MB). |
| Completing 60% with 131 violations. |
| elapsed time = 00:00:12, memory = 1185.44 (MB). |
| Completing 70% with 131 violations. |
| elapsed time = 00:00:13, memory = 1185.44 (MB). |
| Completing 80% with 114 violations. |
| elapsed time = 00:00:17, memory = 1185.44 (MB). |
| Completing 90% with 114 violations. |
| elapsed time = 00:00:17, memory = 1185.44 (MB). |
| Completing 100% with 57 violations. |
| elapsed time = 00:00:25, memory = 1185.44 (MB). |
| [INFO DRT-0199] Number of violations = 57. |
| Viol/Layer mcon met1 met2 |
| Cut Spacing 2 0 0 |
| Metal Spacing 0 34 2 |
| Short 0 19 0 |
| [INFO DRT-0267] cpu time = 00:01:05, elapsed time = 00:00:25, memory = 1185.44 (MB), peak = 1311.33 (MB) |
| Total wire length = 283813 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 137548 um. |
| Total wire length on LAYER met2 = 131602 um. |
| Total wire length on LAYER met3 = 10063 um. |
| Total wire length on LAYER met4 = 4599 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 47184. |
| Up-via summary (total 47184):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 21760 |
| met1 24384 |
| met2 936 |
| met3 104 |
| met4 0 |
| ------------------------ |
| 47184 |
| |
| |
| [INFO DRT-0195] Start 5th optimization iteration. |
| Completing 10% with 57 violations. |
| elapsed time = 00:00:00, memory = 1185.44 (MB). |
| Completing 20% with 57 violations. |
| elapsed time = 00:00:00, memory = 1185.44 (MB). |
| Completing 30% with 45 violations. |
| elapsed time = 00:00:03, memory = 1185.44 (MB). |
| Completing 40% with 45 violations. |
| elapsed time = 00:00:03, memory = 1185.44 (MB). |
| Completing 50% with 45 violations. |
| elapsed time = 00:00:03, memory = 1185.44 (MB). |
| Completing 60% with 41 violations. |
| elapsed time = 00:00:06, memory = 1185.44 (MB). |
| Completing 70% with 41 violations. |
| elapsed time = 00:00:06, memory = 1185.58 (MB). |
| Completing 80% with 30 violations. |
| elapsed time = 00:00:09, memory = 1185.58 (MB). |
| Completing 90% with 30 violations. |
| elapsed time = 00:00:09, memory = 1185.58 (MB). |
| Completing 100% with 6 violations. |
| elapsed time = 00:00:13, memory = 1185.58 (MB). |
| [INFO DRT-0199] Number of violations = 6. |
| Viol/Layer met1 |
| Metal Spacing 6 |
| [INFO DRT-0267] cpu time = 00:00:21, elapsed time = 00:00:13, memory = 1185.58 (MB), peak = 1311.33 (MB) |
| Total wire length = 283818 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 137574 um. |
| Total wire length on LAYER met2 = 131620 um. |
| Total wire length on LAYER met3 = 10023 um. |
| Total wire length on LAYER met4 = 4599 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 47181. |
| Up-via summary (total 47181):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 21760 |
| met1 24389 |
| met2 928 |
| met3 104 |
| met4 0 |
| ------------------------ |
| 47181 |
| |
| |
| [INFO DRT-0195] Start 6th optimization iteration. |
| Completing 10% with 6 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 20% with 6 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 30% with 5 violations. |
| elapsed time = 00:00:02, memory = 1185.58 (MB). |
| Completing 40% with 5 violations. |
| elapsed time = 00:00:02, memory = 1185.58 (MB). |
| Completing 50% with 5 violations. |
| elapsed time = 00:00:02, memory = 1185.58 (MB). |
| Completing 60% with 5 violations. |
| elapsed time = 00:00:02, memory = 1185.58 (MB). |
| Completing 70% with 5 violations. |
| elapsed time = 00:00:02, memory = 1185.58 (MB). |
| Completing 80% with 5 violations. |
| elapsed time = 00:00:02, memory = 1185.58 (MB). |
| Completing 90% with 5 violations. |
| elapsed time = 00:00:02, memory = 1185.58 (MB). |
| Completing 100% with 5 violations. |
| elapsed time = 00:00:08, memory = 1185.58 (MB). |
| [INFO DRT-0199] Number of violations = 5. |
| Viol/Layer met1 |
| Metal Spacing 5 |
| [INFO DRT-0267] cpu time = 00:00:09, elapsed time = 00:00:08, memory = 1185.58 (MB), peak = 1311.33 (MB) |
| Total wire length = 283823 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 137559 um. |
| Total wire length on LAYER met2 = 131618 um. |
| Total wire length on LAYER met3 = 10045 um. |
| Total wire length on LAYER met4 = 4599 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 47182. |
| Up-via summary (total 47182):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 21760 |
| met1 24390 |
| met2 928 |
| met3 104 |
| met4 0 |
| ------------------------ |
| 47182 |
| |
| |
| [INFO DRT-0195] Start 7th optimization iteration. |
| Completing 10% with 5 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 20% with 5 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 30% with 2 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 40% with 2 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 50% with 2 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 60% with 2 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 70% with 2 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 80% with 2 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 90% with 2 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 100% with 2 violations. |
| elapsed time = 00:00:02, memory = 1185.58 (MB). |
| [INFO DRT-0199] Number of violations = 2. |
| Viol/Layer met1 |
| Metal Spacing 2 |
| [INFO DRT-0267] cpu time = 00:00:02, elapsed time = 00:00:02, memory = 1185.58 (MB), peak = 1311.33 (MB) |
| Total wire length = 283822 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 137559 um. |
| Total wire length on LAYER met2 = 131618 um. |
| Total wire length on LAYER met3 = 10045 um. |
| Total wire length on LAYER met4 = 4599 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 47182. |
| Up-via summary (total 47182):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 21760 |
| met1 24390 |
| met2 928 |
| met3 104 |
| met4 0 |
| ------------------------ |
| 47182 |
| |
| |
| [INFO DRT-0195] Start 8th optimization iteration. |
| Completing 10% with 2 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 20% with 2 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 30% with 2 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 40% with 2 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 50% with 2 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 60% with 2 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 70% with 2 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 80% with 1 violations. |
| elapsed time = 00:00:01, memory = 1185.58 (MB). |
| Completing 90% with 1 violations. |
| elapsed time = 00:00:01, memory = 1185.58 (MB). |
| Completing 100% with 1 violations. |
| elapsed time = 00:00:01, memory = 1185.58 (MB). |
| [INFO DRT-0199] Number of violations = 1. |
| Viol/Layer met1 |
| Metal Spacing 1 |
| [INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1185.58 (MB), peak = 1311.33 (MB) |
| Total wire length = 283821 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 137558 um. |
| Total wire length on LAYER met2 = 131618 um. |
| Total wire length on LAYER met3 = 10045 um. |
| Total wire length on LAYER met4 = 4599 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 47182. |
| Up-via summary (total 47182):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 21760 |
| met1 24390 |
| met2 928 |
| met3 104 |
| met4 0 |
| ------------------------ |
| 47182 |
| |
| |
| [INFO DRT-0195] Start 9th optimization iteration. |
| Completing 10% with 1 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 20% with 1 violations. |
| elapsed time = 00:00:00, memory = 1185.58 (MB). |
| Completing 30% with 0 violations. |
| elapsed time = 00:00:01, memory = 1185.58 (MB). |
| Completing 40% with 0 violations. |
| elapsed time = 00:00:01, memory = 1185.58 (MB). |
| Completing 50% with 0 violations. |
| elapsed time = 00:00:01, memory = 1185.58 (MB). |
| Completing 60% with 0 violations. |
| elapsed time = 00:00:01, memory = 1185.58 (MB). |
| Completing 70% with 0 violations. |
| elapsed time = 00:00:01, memory = 1185.58 (MB). |
| Completing 80% with 0 violations. |
| elapsed time = 00:00:01, memory = 1185.58 (MB). |
| Completing 90% with 0 violations. |
| elapsed time = 00:00:01, memory = 1185.58 (MB). |
| Completing 100% with 0 violations. |
| elapsed time = 00:00:01, memory = 1185.58 (MB). |
| [INFO DRT-0199] Number of violations = 0. |
| [INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1185.58 (MB), peak = 1311.33 (MB) |
| Total wire length = 283828 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 137565 um. |
| Total wire length on LAYER met2 = 131618 um. |
| Total wire length on LAYER met3 = 10045 um. |
| Total wire length on LAYER met4 = 4599 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 47182. |
| Up-via summary (total 47182):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 21760 |
| met1 24390 |
| met2 928 |
| met3 104 |
| met4 0 |
| ------------------------ |
| 47182 |
| |
| |
| [INFO DRT-0198] Complete detail routing. |
| Total wire length = 283828 um. |
| Total wire length on LAYER li1 = 0 um. |
| Total wire length on LAYER met1 = 137565 um. |
| Total wire length on LAYER met2 = 131618 um. |
| Total wire length on LAYER met3 = 10045 um. |
| Total wire length on LAYER met4 = 4599 um. |
| Total wire length on LAYER met5 = 0 um. |
| Total number of vias = 47182. |
| Up-via summary (total 47182):. |
| |
| ------------------------ |
| FR_MASTERSLICE 0 |
| li1 21760 |
| met1 24390 |
| met2 928 |
| met3 104 |
| met4 0 |
| ------------------------ |
| 47182 |
| |
| |
| [INFO DRT-0267] cpu time = 00:10:19, elapsed time = 00:03:10, memory = 1185.58 (MB), peak = 1311.33 (MB) |
| |
| [INFO DRT-0180] Post processing. |
| Setting global connections for newly added cells... |
| Writing OpenROAD database to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_18_52/results/routing/core.odb... |
| Writing netlist to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_18_52/results/routing/core.nl.v... |
| Writing powered netlist to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_18_52/results/routing/core.pnl.v... |
| Writing layout to /home/piotro/caravel_user_project/openlane/core/runs/22_12_26_18_52/results/routing/core.def... |