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foss-eda-tools / third_party / shuttle / sky130 / mpw-008 / slot-027 / debf9034994fa8a253b98921996a39ea5182586b / . / dependencies / pdks / volare / sky130 / versions / 0059588eebfc704681dc2368bd1d33d96281d10f / sky130A / libs.ref / sky130_fd_sc_hvl / verilog / sky130_fd_sc_hvl.v
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_V
`define SKY130_FD_SC_HVL__A21O_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__A21O_FUNCTIONAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__A21O_BEHAVIORAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__A21O_FUNCTIONAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a21o (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__A21O_BEHAVIORAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a21o (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_1_V
`define SKY130_FD_SC_HVL__A21O_1_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a21o_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a21o_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_V
`define SKY130_FD_SC_HVL__A21OI_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_PP_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_PP_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a21oi (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a21oi (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_1_V
`define SKY130_FD_SC_HVL__A21OI_1_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a21oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a21oi_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22O_V
`define SKY130_FD_SC_HVL__A22O_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__A22O_FUNCTIONAL_PP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22O_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__A22O_BEHAVIORAL_PP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22O_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22O_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__A22O_FUNCTIONAL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a22o (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22O_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22O_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__A22O_BEHAVIORAL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a22o (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22O_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22O_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22O_1_V
`define SKY130_FD_SC_HVL__A22O_1_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a22o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a22o_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22O_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_V
`define SKY130_FD_SC_HVL__A22OI_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__A22OI_FUNCTIONAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__A22OI_FUNCTIONAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_1_V
`define SKY130_FD_SC_HVL__A22OI_1_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a22oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a22oi_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND2_V
`define SKY130_FD_SC_HVL__AND2_V
/**
* and2: 2-input AND.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__AND2_FUNCTIONAL_PP_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND2_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__AND2_BEHAVIORAL_PP_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND2_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND2_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__AND2_FUNCTIONAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND2_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND2_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__AND2_BEHAVIORAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND2_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND2_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND2_1_V
`define SKY130_FD_SC_HVL__AND2_1_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__and2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__and2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND2_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_V
`define SKY130_FD_SC_HVL__AND3_V
/**
* and3: 3-input AND.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__AND3_FUNCTIONAL_PP_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__AND3_BEHAVIORAL_PP_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__AND3_FUNCTIONAL_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__AND3_BEHAVIORAL_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_1_V
`define SKY130_FD_SC_HVL__AND3_1_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__and3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__and3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_V
`define SKY130_FD_SC_HVL__BUF_V
/**
* buf: Buffer.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__BUF_FUNCTIONAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__BUF_BEHAVIORAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__BUF_FUNCTIONAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__buf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__BUF_BEHAVIORAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__buf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_1_V
`define SKY130_FD_SC_HVL__BUF_1_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_2_V
`define SKY130_FD_SC_HVL__BUF_2_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_2_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_4_V
`define SKY130_FD_SC_HVL__BUF_4_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_4_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_8_V
`define SKY130_FD_SC_HVL__BUF_8_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_8_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_16_V
`define SKY130_FD_SC_HVL__BUF_16_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_16_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_32_V
`define SKY130_FD_SC_HVL__BUF_32_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 32 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_32 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_32 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_32_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__CONB_V
`define SKY130_FD_SC_HVL__CONB_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__CONB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__CONB_FUNCTIONAL_PP_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_hvl__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_hvl__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__CONB_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__CONB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__CONB_BEHAVIORAL_PP_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_hvl__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_hvl__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__CONB_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__CONB_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__CONB_FUNCTIONAL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Name Output
pullup pullup0 (HI );
pulldown pulldown0 (LO );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__CONB_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__CONB_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__CONB_BEHAVIORAL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output
pullup pullup0 (HI );
pulldown pulldown0 (LO );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__CONB_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__CONB_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__CONB_1_V
`define SKY130_FD_SC_HVL__CONB_1_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog wrapper for conb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__conb_1 (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__conb base (
.HI(HI),
.LO(LO),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__conb_1 (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__conb base (
.HI(HI),
.LO(LO)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__CONB_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_V
`define SKY130_FD_SC_HVL__DECAP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DECAP_FUNCTIONAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DECAP_FUNCTIONAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__decap ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__decap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_4_V
`define SKY130_FD_SC_HVL__DECAP_4_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__decap_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_4_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_8_V
`define SKY130_FD_SC_HVL__DECAP_8_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__decap_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__decap_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_8_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_V
`define SKY130_FD_SC_HVL__DFRBP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_PP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire buf0_out_Q ;
wire not1_out_qn;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DFRBP_BEHAVIORAL_PP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
wire not1_out_qn ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DFRBP_BEHAVIORAL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_1_V
`define SKY130_FD_SC_HVL__DFRBP_1_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog wrapper for dfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_V
`define SKY130_FD_SC_HVL__DFRTP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_1_V
`define SKY130_FD_SC_HVL__DFRTP_1_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSBP_V
`define SKY130_FD_SC_HVL__DFSBP_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DFSBP_FUNCTIONAL_PP_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire buf0_out_Q ;
wire not1_out_qn;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSBP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DFSBP_BEHAVIORAL_PP_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
wire not1_out_qn ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign cond0 = ( SET_B_delayed === 1'b1 );
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSBP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFSBP_FUNCTIONAL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSBP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DFSBP_BEHAVIORAL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign cond0 = ( SET_B_delayed === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSBP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSBP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSBP_1_V
`define SKY130_FD_SC_HVL__DFSBP_1_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog wrapper for dfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSBP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_V
`define SKY130_FD_SC_HVL__DFSTP_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_PP_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_PP_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign cond0 = ( SET_B_delayed === 1'b1 );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign cond0 = ( SET_B_delayed === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_1_V
`define SKY130_FD_SC_HVL__DFSTP_1_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfstp_1 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfstp_1 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_V
`define SKY130_FD_SC_HVL__DFXBP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire buf0_out_Q ;
wire not0_out_qn;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND );
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not0 (not0_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not0_out_qn, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DFXBP_BEHAVIORAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire buf0_out_Q ;
wire not0_out_qn;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not0 (not0_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not0_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfxbp (
Q ,
Q_N,
CLK,
D
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DFXBP_BEHAVIORAL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfxbp (
Q ,
Q_N,
CLK,
D
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_1_V
`define SKY130_FD_SC_HVL__DFXBP_1_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfxbp_1 (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXTP_V
`define SKY130_FD_SC_HVL__DFXTP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_PP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire buf0_out_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DFXTP_BEHAVIORAL_PP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire buf0_out_Q ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXTP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DFXTP_BEHAVIORAL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXTP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXTP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXTP_1_V
`define SKY130_FD_SC_HVL__DFXTP_1_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfxtp_1 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfxtp_1 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXTP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_V
`define SKY130_FD_SC_HVL__DIODE_V
/**
* diode: Antenna tie-down diode.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DIODE_BEHAVIORAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__diode (
DIODE
);
// Module ports
input DIODE;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DIODE_BEHAVIORAL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__diode (
DIODE
);
// Module ports
input DIODE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_2_V
`define SKY130_FD_SC_HVL__DIODE_2_V
/**
* diode: Antenna tie-down diode.
*
* Verilog wrapper for diode with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__diode_2 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__diode_2 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__diode base (
.DIODE(DIODE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_2_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_V
`define SKY130_FD_SC_HVL__DLCLKP_V
/**
* dlclkp: Clock gate.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DLCLKP_FUNCTIONAL_PP_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire GCLK_b;
// Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE, clkn, , VPWR, VGND);
and and0 (GCLK_b, m0, CLK );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (GCLK , GCLK_b, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DLCLKP_BEHAVIORAL_PP_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
wire GCLK_b ;
wire awake ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK_b, m0, CLK_delayed );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (GCLK , GCLK_b, VPWR, VGND );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DLCLKP_FUNCTIONAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire clkn;
// Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_hvl__udp_dlatch$P dlatch0 (m0 , GATE, clkn );
and and0 (GCLK , m0, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DLCLKP_BEHAVIORAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
wire GCLK_b ;
wire awake ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK_b, m0, CLK_delayed );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (GCLK , GCLK_b, VPWR, VGND );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_1_V
`define SKY130_FD_SC_HVL__DLCLKP_1_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dlclkp_1 (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dlclkp_1 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_V
`define SKY130_FD_SC_HVL__DLRTP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_PP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire buf_Q ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DLRTP_BEHAVIORAL_PP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire buf0_out_Q ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DLRTP_BEHAVIORAL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_1_V
`define SKY130_FD_SC_HVL__DLRTP_1_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLXTP_V
`define SKY130_FD_SC_HVL__DLXTP_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_PP_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire buf0_out_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DLXTP_BEHAVIORAL_PP_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
reg notifier ;
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
wire buf0_out_Q ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLXTP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLXTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DLXTP_BEHAVIORAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
reg notifier ;
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLXTP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLXTP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLXTP_1_V
`define SKY130_FD_SC_HVL__DLXTP_1_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog wrapper for dlxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dlxtp_1 (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dlxtp_1 (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLXTP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_V
`define SKY130_FD_SC_HVL__EINVN_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_1_V
`define SKY130_FD_SC_HVL__EINVN_1_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__einvn_1 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__einvn_1 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_V
`define SKY130_FD_SC_HVL__EINVP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_1_V
`define SKY130_FD_SC_HVL__EINVP_1_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__einvp_1 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__einvp_1 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_V
`define SKY130_FD_SC_HVL__FILL_V
/**
* fill: Fill cell.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__FILL_FUNCTIONAL_PP_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__fill (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__FILL_BEHAVIORAL_PP_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__fill (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__FILL_FUNCTIONAL_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__FILL_BEHAVIORAL_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_1_V
`define SKY130_FD_SC_HVL__FILL_1_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_2_V
`define SKY130_FD_SC_HVL__FILL_2_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_2_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_4_V
`define SKY130_FD_SC_HVL__FILL_4_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_4_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_8_V
`define SKY130_FD_SC_HVL__FILL_8_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_8_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_V
`define SKY130_FD_SC_HVL__INV_V
/**
* inv: Inverter.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__INV_FUNCTIONAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__INV_BEHAVIORAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__INV_FUNCTIONAL_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__inv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__INV_BEHAVIORAL_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__inv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_1_V
`define SKY130_FD_SC_HVL__INV_1_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_2_V
`define SKY130_FD_SC_HVL__INV_2_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_2_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_4_V
`define SKY130_FD_SC_HVL__INV_4_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_4_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_8_V
`define SKY130_FD_SC_HVL__INV_8_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_8_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_16_V
`define SKY130_FD_SC_HVL__INV_16_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_16_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_FUNCTIONAL_PP_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_hl (
X ,
A ,
VPWR ,
VGND ,
LOWHVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LOWHVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, LOWHVPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_PP_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_hl (
X ,
A ,
VPWR ,
VGND ,
LOWHVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LOWHVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, LOWHVPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_FUNCTIONAL_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_hl (
X,
A
);
// Module ports
output X;
input A;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_hl (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 LOWHVPWR;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_1_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_1_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Verilog wrapper for lsbufhv2hv_hl with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_hl_1 (
X ,
A ,
VPWR ,
VGND ,
LOWHVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LOWHVPWR;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__lsbufhv2hv_hl base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.LOWHVPWR(LOWHVPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_hl_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LOWHVPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__lsbufhv2hv_hl base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_V
/**
* lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
* Lower Voltage to Higher Voltage.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_FUNCTIONAL_PP_V
/**
* lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
* Lower Voltage to Higher Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_lh (
X ,
A ,
VPWR ,
VGND ,
LOWHVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LOWHVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LOWHVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_BEHAVIORAL_PP_V
/**
* lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
* Lower Voltage to Higher Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_lh (
X ,
A ,
VPWR ,
VGND ,
LOWHVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LOWHVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LOWHVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_FUNCTIONAL_V
/**
* lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
* Lower Voltage to Higher Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_lh (
X,
A
);
// Module ports
output X;
input A;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_BEHAVIORAL_V
/**
* lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
* Lower Voltage to Higher Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_lh (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 LOWHVPWR;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_1_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_1_V
/**
* lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
* Lower Voltage to Higher Voltage.
*
* Verilog wrapper for lsbufhv2hv_lh with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_lh_1 (
X ,
A ,
VPWR ,
VGND ,
LOWHVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LOWHVPWR;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__lsbufhv2hv_lh base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.LOWHVPWR(LOWHVPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_lh_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LOWHVPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__lsbufhv2hv_lh base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_V
/**
* lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_FUNCTIONAL_PP_V
/**
* lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, LVPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_PP_V
/**
* lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, LVPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_FUNCTIONAL_V
/**
* lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv (
X,
A
);
// Module ports
output X;
input A;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_V
/**
* lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_1_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_1_V
/**
* lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
*
* Verilog wrapper for lsbufhv2lv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_1 (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__lsbufhv2lv base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.LVPWR(LVPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__lsbufhv2lv base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_PP_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, LVPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BEHAVIORAL_PP_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, LVPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
X,
A
);
// Module ports
output X;
input A;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BEHAVIORAL_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_1_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_1_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog wrapper for lsbufhv2lv_simple with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_simple_1 (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__lsbufhv2lv_simple base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.LVPWR(LVPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_simple_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__lsbufhv2lv_simple base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_V
/**
* lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
* isolated well on input buffer, double height cell.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_PP_V
/**
* lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
* isolated well on input buffer, double height cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_PP_V
/**
* lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
* isolated well on input buffer, double height cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_V
/**
* lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
* isolated well on input buffer, double height cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv (
X,
A
);
// Module ports
output X;
input A;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_V
/**
* lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
* isolated well on input buffer, double height cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_1_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_1_V
/**
* lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
* isolated well on input buffer, double height cell.
*
* Verilog wrapper for lsbuflv2hv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_1 (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__lsbuflv2hv base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.LVPWR(LVPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__lsbuflv2hv base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_V
/**
* lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
* high voltage, isolated well
* on input buffer, inverting sleep
* mode input.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_PP_V
/**
* lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
* high voltage, isolated well
* on input buffer, inverting sleep
* mode input.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
LVPWR ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input LVPWR ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire and0_out_X ;
wire isolatchhv_pp0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X , SLEEP_B, A );
sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S isolatchhv_pp0 (isolatchhv_pp0_out_X, and0_out_X, VPWR, LVPWR, VGND, SLEEP);
buf buf0 (X , isolatchhv_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BEHAVIORAL_PP_V
/**
* lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
* high voltage, isolated well
* on input buffer, inverting sleep
* mode input.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
LVPWR ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input LVPWR ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire and0_out_X ;
wire isolatchhv_pp0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X , SLEEP_B, A );
sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S isolatchhv_pp0 (isolatchhv_pp0_out_X, and0_out_X, VPWR, LVPWR, VGND, SLEEP);
buf buf0 (X , isolatchhv_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_V
/**
* lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
* high voltage, isolated well
* on input buffer, inverting sleep
* mode input.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Local signals
wire SLEEP ;
wire and0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X, SLEEP_B, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BEHAVIORAL_V
/**
* lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
* high voltage, isolated well
* on input buffer, inverting sleep
* mode input.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire SLEEP ;
wire and0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X, SLEEP_B, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_3_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_3_V
/**
* lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
* high voltage, isolated well
* on input buffer, inverting sleep
* mode input.
*
* Verilog wrapper for lsbuflv2hv_clkiso_hlkg with size of 3 units
* (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3 (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
LVPWR ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input LVPWR ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.VGND(VGND),
.LVPWR(LVPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg_3 (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_3_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_PP_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
LVPWR ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input LVPWR ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire and0_out_X ;
wire isolatchhv_pp0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X , SLEEP_B, A );
sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S isolatchhv_pp0 (isolatchhv_pp0_out_X, and0_out_X, VPWR, LVPWR, VGND, SLEEP);
buf buf0 (X , isolatchhv_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BEHAVIORAL_PP_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
LVPWR ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input LVPWR ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire and0_out_X ;
wire isolatchhv_pp0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X , SLEEP_B, A );
sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S isolatchhv_pp0 (isolatchhv_pp0_out_X, and0_out_X, VPWR, LVPWR, VGND, SLEEP);
buf buf0 (X , isolatchhv_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Local signals
wire SLEEP ;
wire and0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X, SLEEP_B, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BEHAVIORAL_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire SLEEP ;
wire and0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
and and0 (and0_out_X, SLEEP_B, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_1_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_1_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog wrapper for lsbuflv2hv_isosrchvaon with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1 (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
LVPWR ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input LVPWR ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.VGND(VGND),
.LVPWR(LVPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1 (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_PP_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BEHAVIORAL_PP_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
X,
A
);
// Module ports
output X;
input A;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BEHAVIORAL_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_1_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_1_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog wrapper for lsbuflv2hv_symmetric with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1 (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__lsbuflv2hv_symmetric base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.LVPWR(LVPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__lsbuflv2hv_symmetric base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_V
`define SKY130_FD_SC_HVL__MUX2_V
/**
* mux2: 2-input multiplexer.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_PP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to10_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_PP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to10_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__mux2 (
X ,
A0,
A1,
S
);
// Module ports
output X ;
input A0;
input A1;
input S ;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
buf buf0 (X , mux_2to10_out_X);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__mux2 (
X ,
A0,
A1,
S
);
// Module ports
output X ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
buf buf0 (X , mux_2to10_out_X);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_1_V
`define SKY130_FD_SC_HVL__MUX2_1_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__mux2_1 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__mux2_1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_V
`define SKY130_FD_SC_HVL__MUX4_V
/**
* mux4: 4-input multiplexer.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
// Module ports
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Local signals
wire mux_4to20_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
buf buf0 (X , mux_4to20_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
// Module ports
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_4to20_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
buf buf0 (X , mux_4to20_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_1_V
`define SKY130_FD_SC_HVL__MUX4_1_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__mux4_1 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__mux4_1 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_V
`define SKY130_FD_SC_HVL__NAND2_V
/**
* nand2: 2-input NAND.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nand2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nand2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_1_V
`define SKY130_FD_SC_HVL__NAND2_1_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nand2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nand2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_V
`define SKY130_FD_SC_HVL__NAND3_V
/**
* nand3: 3-input NAND.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_1_V
`define SKY130_FD_SC_HVL__NAND3_1_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nand3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nand3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR2_V
`define SKY130_FD_SC_HVL__NOR2_V
/**
* nor2: 2-input NOR.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__NOR2_FUNCTIONAL_PP_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR2_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__NOR2_BEHAVIORAL_PP_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR2_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR2_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__NOR2_FUNCTIONAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR2_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__NOR2_BEHAVIORAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR2_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR2_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR2_1_V
`define SKY130_FD_SC_HVL__NOR2_1_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR2_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_V
`define SKY130_FD_SC_HVL__NOR3_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_1_V
`define SKY130_FD_SC_HVL__NOR3_1_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nor3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nor3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21A_V
`define SKY130_FD_SC_HVL__O21A_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__O21A_FUNCTIONAL_PP_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21A_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__O21A_BEHAVIORAL_PP_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21A_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21A_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__O21A_FUNCTIONAL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o21a (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21A_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21A_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__O21A_BEHAVIORAL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o21a (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21A_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21A_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21A_1_V
`define SKY130_FD_SC_HVL__O21A_1_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o21a_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o21a_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21A_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_V
`define SKY130_FD_SC_HVL__O21AI_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o21ai (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o21ai (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_1_V
`define SKY130_FD_SC_HVL__O21AI_1_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o21ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o21ai_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_V
`define SKY130_FD_SC_HVL__O22A_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__O22A_FUNCTIONAL_PP_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__O22A_BEHAVIORAL_PP_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__O22A_FUNCTIONAL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o22a (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__O22A_BEHAVIORAL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o22a (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_1_V
`define SKY130_FD_SC_HVL__O22A_1_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o22a_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o22a_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_V
`define SKY130_FD_SC_HVL__O22AI_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__O22AI_FUNCTIONAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__O22AI_FUNCTIONAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_1_V
`define SKY130_FD_SC_HVL__O22AI_1_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o22ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o22ai_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_V
`define SKY130_FD_SC_HVL__OR2_V
/**
* or2: 2-input OR.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__OR2_FUNCTIONAL_PP_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__or2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__OR2_BEHAVIORAL_PP_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__or2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__OR2_FUNCTIONAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__OR2_BEHAVIORAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_1_V
`define SKY130_FD_SC_HVL__OR2_1_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__or2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__or2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_V
`define SKY130_FD_SC_HVL__OR3_V
/**
* or3: 3-input OR.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__OR3_FUNCTIONAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__OR3_BEHAVIORAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__OR3_FUNCTIONAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__OR3_BEHAVIORAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_1_V
`define SKY130_FD_SC_HVL__OR3_1_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__or3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__or3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBE_P_V
`define SKY130_FD_SC_HVL__PROBE_P_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_PP_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__probe_p (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBE_P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__PROBE_P_BEHAVIORAL_PP_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__probe_p (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBE_P_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__probe_p (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBE_P_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__PROBE_P_BEHAVIORAL_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__probe_p (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBE_P_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBE_P_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBE_P_8_V
`define SKY130_FD_SC_HVL__PROBE_P_8_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog wrapper for probe_p with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__probe_p_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__probe_p base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__probe_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__probe_p base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBE_P_8_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBEC_P_V
`define SKY130_FD_SC_HVL__PROBEC_P_V
/**
* probec_p: Virtual current probe point.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBEC_P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__PROBEC_P_FUNCTIONAL_PP_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__probec_p (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBEC_P_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_PP_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__probec_p (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBEC_P_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__PROBEC_P_FUNCTIONAL_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__probec_p (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBEC_P_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__probec_p (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBEC_P_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBEC_P_8_V
`define SKY130_FD_SC_HVL__PROBEC_P_8_V
/**
* probec_p: Virtual current probe point.
*
* Verilog wrapper for probec_p with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__probec_p_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__probec_p base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__probec_p_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__probec_p base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBEC_P_8_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_V
`define SKY130_FD_SC_HVL__SCHMITTBUF_V
/**
* schmittbuf: Schmitt Trigger Buffer.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_PP_V
/**
* schmittbuf: Schmitt Trigger Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__schmittbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__SCHMITTBUF_BEHAVIORAL_PP_V
/**
* schmittbuf: Schmitt Trigger Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__schmittbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SCHMITTBUF_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_V
/**
* schmittbuf: Schmitt Trigger Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__schmittbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SCHMITTBUF_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SCHMITTBUF_BEHAVIORAL_V
/**
* schmittbuf: Schmitt Trigger Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__schmittbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SCHMITTBUF_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SCHMITTBUF_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_1_V
`define SKY130_FD_SC_HVL__SCHMITTBUF_1_V
/**
* schmittbuf: Schmitt Trigger Buffer.
*
* Verilog wrapper for schmittbuf with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__schmittbuf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__schmittbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__schmittbuf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__schmittbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SCHMITTBUF_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_V
`define SKY130_FD_SC_HVL__SDFRBP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_PP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
wire buf0_out_Q ;
wire not1_out_qn;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__SDFRBP_BEHAVIORAL_PP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
wire not1_out_qn ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDFRBP_BEHAVIORAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_1_V
`define SKY130_FD_SC_HVL__SDFRBP_1_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_V
`define SKY130_FD_SC_HVL__SDFRTP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SDFRTP_FUNCTIONAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDFRTP_FUNCTIONAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_1_V
`define SKY130_FD_SC_HVL__SDFRTP_1_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSBP_V
`define SKY130_FD_SC_HVL__SDFSBP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_PP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
wire buf0_out_Q ;
wire not1_out_qn;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__SDFSBP_BEHAVIORAL_PP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
wire not1_out_qn ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSBP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDFSBP_BEHAVIORAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSBP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSBP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSBP_1_V
`define SKY130_FD_SC_HVL__SDFSBP_1_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSBP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSTP_V
`define SKY130_FD_SC_HVL__SDFSTP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SDFSTP_FUNCTIONAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSTP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDFSTP_FUNCTIONAL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSTP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSTP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSTP_1_V
`define SKY130_FD_SC_HVL__SDFSTP_1_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfstp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfstp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSTP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_V
`define SKY130_FD_SC_HVL__SDFXBP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SDFXBP_FUNCTIONAL_PP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
wire buf0_out_Q ;
wire not0_out_qn;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not0 (not0_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not0_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_PP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire buf0_out_Q ;
wire not0_out_qn;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign cond1 = ( SCE_delayed === 1'b0 );
assign cond2 = ( SCE_delayed === 1'b1 );
assign cond3 = ( D_delayed !== SCD_delayed );
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not0 (not0_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not0_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDFXBP_FUNCTIONAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign cond1 = ( SCE_delayed === 1'b0 );
assign cond2 = ( SCE_delayed === 1'b1 );
assign cond3 = ( D_delayed !== SCD_delayed );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_1_V
`define SKY130_FD_SC_HVL__SDFXBP_1_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog wrapper for sdfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfxbp_1 (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_V
`define SKY130_FD_SC_HVL__SDFXTP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_PP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
wire buf0_out_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_PP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire buf0_out_Q ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign cond1 = ( SCE_delayed === 1'b0 );
assign cond2 = ( SCE_delayed === 1'b1 );
assign cond3 = ( D_delayed !== SCD_delayed );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign cond1 = ( SCE_delayed === 1'b0 );
assign cond2 = ( SCE_delayed === 1'b1 );
assign cond3 = ( D_delayed !== SCD_delayed );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_1_V
`define SKY130_FD_SC_HVL__SDFXTP_1_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfxtp_1 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_V
`define SKY130_FD_SC_HVL__SDLCLKP_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_PP_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
wire GCLK_b ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_GATE, clkn, , VPWR, VGND);
and and0 (GCLK_b , m0n, CLK );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (GCLK , GCLK_b, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_PP_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
wire GCLK_b ;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK_b , m0n, CLK_delayed );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (GCLK , GCLK_b, VPWR, VGND );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( ( GATE_delayed === 1'b0 ) & awake );
assign GATE_awake = ( ( SCE_delayed === 1'b0 ) & awake );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hvl__udp_dlatch$P dlatch0 (m0 , SCE_GATE, clkn );
and and0 (GCLK , m0n, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
wire GCLK_b ;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK_b , m0n, CLK_delayed );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (GCLK , GCLK_b, VPWR, VGND );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( ( GATE_delayed === 1'b0 ) & awake );
assign GATE_awake = ( ( SCE_delayed === 1'b0 ) & awake );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_1_V
`define SKY130_FD_SC_HVL__SDLCLKP_1_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLXTP_V
`define SKY130_FD_SC_HVL__SDLXTP_V
/**
* sdlxtp: ????.
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SDLXTP_FUNCTIONAL_PP_V
/**
* sdlxtp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdlxtp (
Q ,
D ,
SCD ,
SCE ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input SCD ;
input SCE ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_out ;
wire buf_Q ;
wire buf0_out_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , mux_out, GATE, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLXTP_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__SDLXTP_BEHAVIORAL_PP_V
/**
* sdlxtp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdlxtp (
Q ,
D ,
SCD ,
SCE ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input SCD ;
input SCE ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
reg notifier ;
wire mux_out ;
wire buf0_out_Q ;
// Name Output Other arguments
assign cond0 = ( SCE_delayed === 1'b0 );
assign cond1 = ( SCE_delayed === 1'b1 );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , mux_out, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLXTP_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDLXTP_FUNCTIONAL_V
/**
* sdlxtp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdlxtp (
Q ,
D ,
SCD ,
SCE ,
GATE
);
// Module ports
output Q ;
input D ;
input SCD ;
input SCE ;
input GATE;
// Local signals
wire mux_out;
wire buf_Q ;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , mux_out, GATE );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLXTP_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLXTP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDLXTP_BEHAVIORAL_V
/**
* sdlxtp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__sdlxtp (
Q ,
D ,
SCD ,
SCE ,
GATE
);
// Module ports
output Q ;
input D ;
input SCD ;
input SCE ;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
reg notifier ;
wire mux_out ;
// Name Output Other arguments
assign cond0 = ( SCE_delayed === 1'b0 );
assign cond1 = ( SCE_delayed === 1'b1 );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , mux_out, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLXTP_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLXTP_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLXTP_1_V
`define SKY130_FD_SC_HVL__SDLXTP_1_V
/**
* sdlxtp: ????.
*
* Verilog wrapper for sdlxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdlxtp_1 (
Q ,
D ,
SCD ,
SCE ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input SCD ;
input SCE ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdlxtp base (
.Q(Q),
.D(D),
.SCD(SCD),
.SCE(SCE),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdlxtp_1 (
Q ,
D ,
SCD ,
SCE ,
GATE
);
output Q ;
input D ;
input SCD ;
input SCE ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdlxtp base (
.Q(Q),
.D(D),
.SCD(SCD),
.SCE(SCE),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLXTP_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_V
`define SKY130_FD_SC_HVL__XNOR2_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__XNOR2_BEHAVIORAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__XNOR2_BEHAVIORAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_1_V
`define SKY130_FD_SC_HVL__XNOR2_1_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__xnor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__xnor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_1_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_V
`define SKY130_FD_SC_HVL__XOR2_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog top module.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_PP_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`celldefine
module sky130_fd_sc_hvl__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_PP_V
`endif // FUNCTIONAL
`else // USE_POWER_PINS
`ifdef FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_V
`else // FUNCTIONAL
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_V
`endif // FUNCTIONAL
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_V
//--------EOF---------
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_1_V
`define SKY130_FD_SC_HVL__XOR2_1_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__xor2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_1_V
//--------EOF---------