| |
| //------------------------------------------------------------- |
| // Variable Decleration |
| //------------------------------------------------------------- |
| |
| reg clock ; |
| reg clock2 ; |
| reg xtal_clk ; |
| reg wb_rst_i ; |
| |
| reg power1, power2; |
| reg power3, power4; |
| |
| // Wishbone Interface |
| reg wbd_ext_cyc_i ; // strobe/request |
| reg wbd_ext_stb_i ; // strobe/request |
| reg [31:0] wbd_ext_adr_i ; // address |
| reg wbd_ext_we_i ; // write |
| reg [31:0] wbd_ext_dat_i ; // data output |
| reg [3:0] wbd_ext_sel_i ; // byte enable |
| |
| wire [31:0] wbd_ext_dat_o ; // data input |
| wire wbd_ext_ack_o ; // acknowlegement |
| wire wbd_ext_err_o ; // error |
| |
| // User I/O |
| wire [37:0] io_oeb ; |
| wire [37:0] io_out ; |
| wire [37:0] io_in ; |
| reg [127:0] la_data_in; |
| |
| reg test_fail ; |
| reg [31:0] write_data ; |
| reg [31:0] read_data ; |
| integer d_risc_id; |
| |
| |
| wire USER_VDD1V8 = 1'b1; |
| wire VSS = 1'b0; |
| |
| //----------------------------------------- |
| // Clock Decleration |
| //----------------------------------------- |
| |
| always #(CLK1_PERIOD/2) clock <= (clock === 1'b0); |
| always #(CLK2_PERIOD/2) clock2 <= (clock2 === 1'b0); |
| always #(XTAL_PERIOD/2) xtal_clk <= (xtal_clk === 1'b0); |
| |
| |
| //----------------------------------------- |
| // Variable Initiatlization |
| //----------------------------------------- |
| initial |
| begin |
| |
| clock = 0; |
| clock2 = 0; |
| xtal_clk = 0; |
| test_fail = 0; |
| wbd_ext_cyc_i ='h0; // strobe/request |
| wbd_ext_stb_i ='h0; // strobe/request |
| wbd_ext_adr_i ='h0; // address |
| wbd_ext_we_i ='h0; // write |
| wbd_ext_dat_i ='h0; // data output |
| wbd_ext_sel_i ='h0; // byte enable |
| la_data_in = 1; |
| end |
| //----------------------------------------- |
| // DUT Instatiation |
| //----------------------------------------- |
| user_project_wrapper u_top( |
| `ifdef USE_POWER_PINS |
| .vccd1(USER_VDD1V8), // User area 1 1.8V supply |
| .vssd1(VSS), // User area 1 digital ground |
| `endif |
| .wb_clk_i (clock), // System clock |
| .user_clock2 (clock2), // Real-time clock |
| .wb_rst_i (wb_rst_i), // Regular Reset signal |
| |
| .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request |
| .wbs_stb_i (wbd_ext_stb_i), // strobe/request |
| .wbs_adr_i (wbd_ext_adr_i), // address |
| .wbs_we_i (wbd_ext_we_i), // write |
| .wbs_dat_i (wbd_ext_dat_i), // data output |
| .wbs_sel_i (wbd_ext_sel_i), // byte enable |
| |
| .wbs_dat_o (wbd_ext_dat_o), // data input |
| .wbs_ack_o (wbd_ext_ack_o), // acknowlegement |
| |
| |
| // Logic Analyzer Signals |
| .la_data_in (la_data_in) , |
| .la_data_out (), |
| .la_oenb ('0), |
| |
| |
| // IOs |
| .io_in (io_in ) , |
| .io_out (io_out) , |
| .io_oeb (io_oeb) , |
| |
| .user_irq () |
| |
| ); |
| |
| //-------------------------------------------------------- |
| // Apply Reset Sequence and wait for reset completion |
| //------------------------------------------------------- |
| |
| task init; |
| begin |
| //#1 - Apply Reset |
| #1000 wb_rst_i = 0; |
| repeat (10) @(posedge clock); |
| #1000 wb_rst_i = 1; |
| |
| //#3 - Remove Reset |
| #1000 wb_rst_i = 0; |
| repeat (10) @(posedge clock); |
| |
| end |
| endtask |
| |
| |
| //------------------------------- |
| // Wishbone Write |
| //------------------------------- |
| task wb_user_core_write; |
| input [31:0] address; |
| input [31:0] data; |
| begin |
| repeat (1) @(posedge clock); |
| #1; |
| wbd_ext_adr_i =address; // address |
| wbd_ext_we_i ='h1; // write |
| wbd_ext_dat_i =data; // data output |
| wbd_ext_sel_i ='hF; // byte enable |
| wbd_ext_cyc_i ='h1; // strobe/request |
| wbd_ext_stb_i ='h1; // strobe/request |
| wait(wbd_ext_ack_o == 1); |
| repeat (1) @(posedge clock); |
| #1; |
| wbd_ext_cyc_i ='h0; // strobe/request |
| wbd_ext_stb_i ='h0; // strobe/request |
| wbd_ext_adr_i ='h0; // address |
| wbd_ext_we_i ='h0; // write |
| wbd_ext_dat_i ='h0; // data output |
| wbd_ext_sel_i ='h0; // byte enable |
| $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data); |
| repeat (2) @(posedge clock); |
| end |
| endtask |
| |
| |
| //-------------------------------------- |
| // Wishbone Read |
| //-------------------------------------- |
| task wb_user_core_read; |
| input [31:0] address; |
| output [31:0] data; |
| reg [31:0] data; |
| begin |
| repeat (1) @(posedge clock); |
| #1; |
| wbd_ext_adr_i =address; // address |
| wbd_ext_we_i ='h0; // write |
| wbd_ext_dat_i ='0; // data output |
| wbd_ext_sel_i ='hF; // byte enable |
| wbd_ext_cyc_i ='h1; // strobe/request |
| wbd_ext_stb_i ='h1; // strobe/request |
| wait(wbd_ext_ack_o == 1); |
| repeat (1) @(negedge clock); |
| data = wbd_ext_dat_o; |
| repeat (1) @(posedge clock); |
| #1; |
| wbd_ext_cyc_i ='h0; // strobe/request |
| wbd_ext_stb_i ='h0; // strobe/request |
| wbd_ext_adr_i ='h0; // address |
| wbd_ext_we_i ='h0; // write |
| wbd_ext_dat_i ='h0; // data output |
| wbd_ext_sel_i ='h0; // byte enable |
| $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data); |
| repeat (2) @(posedge clock); |
| end |
| endtask |
| |
| |
| //-------------------------------------- |
| // Wishbone Read and compare |
| //-------------------------------------- |
| task wb_user_core_read_check; |
| input [31:0] address; |
| output [31:0] data; |
| input [31:0] cmp_data; |
| reg [31:0] data; |
| begin |
| repeat (1) @(posedge clock); |
| #1; |
| wbd_ext_adr_i =address; // address |
| wbd_ext_we_i ='h0; // write |
| wbd_ext_dat_i ='0; // data output |
| wbd_ext_sel_i ='hF; // byte enable |
| wbd_ext_cyc_i ='h1; // strobe/request |
| wbd_ext_stb_i ='h1; // strobe/request |
| wait(wbd_ext_ack_o == 1); |
| repeat (1) @(negedge clock); |
| data = wbd_ext_dat_o; |
| repeat (1) @(posedge clock); |
| #1; |
| wbd_ext_cyc_i ='h0; // strobe/request |
| wbd_ext_stb_i ='h0; // strobe/request |
| wbd_ext_adr_i ='h0; // address |
| wbd_ext_we_i ='h0; // write |
| wbd_ext_dat_i ='h0; // data output |
| wbd_ext_sel_i ='h0; // byte enable |
| if(data !== cmp_data) begin |
| $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); |
| test_fail = 1; |
| end else begin |
| $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); |
| end |
| repeat (2) @(posedge clock); |
| end |
| endtask |
| |
| |
| task wb_user_core_read_cmp; |
| input [31:0] address; |
| input [31:0] cmp_data; |
| reg [31:0] data; |
| begin |
| repeat (1) @(posedge clock); |
| #1; |
| wbd_ext_adr_i =address; // address |
| wbd_ext_we_i ='h0; // write |
| wbd_ext_dat_i ='0; // data output |
| wbd_ext_sel_i ='hF; // byte enable |
| wbd_ext_cyc_i ='h1; // strobe/request |
| wbd_ext_stb_i ='h1; // strobe/request |
| wait(wbd_ext_ack_o == 1); |
| repeat (1) @(negedge clock); |
| data = wbd_ext_dat_o; |
| repeat (1) @(posedge clock); |
| #1; |
| wbd_ext_cyc_i ='h0; // strobe/request |
| wbd_ext_stb_i ='h0; // strobe/request |
| wbd_ext_adr_i ='h0; // address |
| wbd_ext_we_i ='h0; // write |
| wbd_ext_dat_i ='h0; // data output |
| wbd_ext_sel_i ='h0; // byte enable |
| if(data !== cmp_data) begin |
| $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); |
| test_fail = 1; |
| end else begin |
| $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); |
| end |
| repeat (2) @(posedge clock); |
| end |
| endtask |
| |
| /************************************************************************* |
| * This is Baud Rate to clock divider conversion for Test Bench |
| * Note: DUT uses 16x baud clock, where are test bench uses directly |
| * baud clock, Due to 16x Baud clock requirement at RTL, there will be |
| * some resolution loss, we expect at lower baud rate this resolution |
| * loss will be less. For Quick simulation perpose higher baud rate used |
| * *************************************************************************/ |
| task tb_set_uart_baud; |
| input [31:0] ref_clk; |
| input [31:0] baud_rate; |
| output [31:0] baud_div; |
| reg [31:0] baud_div; |
| begin |
| // for 230400 Baud = (50Mhz/230400) = 216.7 |
| baud_div = ref_clk/baud_rate; // Get the Bit Baud rate |
| // Baud 16x = 216/16 = 13 |
| baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench |
| // Test bench baud clock , 16x of above value |
| // 13 * 16 = 208, |
| // (Note if you see original value was 216, now it's 208 ) |
| baud_div = baud_div * 16; |
| // Test bench half cycle counter to toggle it |
| // 208/2 = 104 |
| baud_div = baud_div/2; |
| //As counter run's from 0 , substract from 1 |
| baud_div = baud_div-1; |
| end |
| endtask |
| |
| |