commit: fe0d47cab1c49896a718780d1e1e7a5e8f7fcce5
[log] [tgz]
author: dineshannayya <dinesh.annayya@gmail.com>
Sun Jan 01 22:26:02 2023 +0530
committer: dineshannayya <dinesh.annayya@gmail.com>
Sun Jan 01 22:26:02 2023 +0530
tree: 24dd607daac18e120e0fd3de62b09c1e5e26c205
parent: a51407962f1a315f7e67af6d38421bfd041680ef [diff]

sspi slave integrated + uart Master with Auto Baud Detect

gds/user_project_wrapper.gds.gz[diff]
lef/user_project_wrapper.lef.gz[diff]
openlane/pinmux_top/pin_order.cfg[diff]
openlane/wb_host/config.tcl[diff]
openlane/wb_host/pin_order.cfg[diff]
sdc/mbist_wrapper.sdc[diff]
sdc/pinmux_top.sdc[diff]
sdc/user_project_wrapper.sdc[diff]
sdc/wb_host.sdc[diff]
sta/slew.cap.fanout.vio.rpt[Deleted - diff]
sta/sta.log[Deleted - diff]
sta/unconstraints.rpt[Deleted - diff]
verilog/dv/Makefile[diff]
verilog/dv/common/agents/uart_agent.v[Added - diff]
verilog/dv/common/agents/uart_master_tasks.sv[Added - diff]
verilog/dv/common/agents/user_tasks.sv[Added - diff]
verilog/dv/common/bfm/bfm_spim.v[Added - diff]
verilog/dv/regression.rpt[diff]
verilog/dv/user_spi_isp/Makefile[Added - diff]
verilog/dv/user_spi_isp/run_iverilog[Added - diff]
verilog/dv/user_spi_isp/user_spi_isp_tb.v[Added - diff]
verilog/dv/user_uart_master/Makefile[Added - diff]
verilog/dv/user_uart_master/run_iverilog[Added - diff]
verilog/dv/user_uart_master/user_uart.c[Added - diff]
verilog/dv/user_uart_master/user_uart_master_tb.v[Added - diff]
verilog/gl/user_project_wrapper.v.gz[diff]
verilog/includes/includes.rtl.caravel_user_project[diff]
verilog/rtl/glbl/src/glbl_cfg.sv[diff]
verilog/rtl/mbist_wrapper/src/mbist_wb.sv[diff]
verilog/rtl/pinmux/src/pinmux.sv[diff]
verilog/rtl/pinmux/src/pinmux_top.sv[diff]
verilog/rtl/sspis/src/spi2wb.sv[Added - diff]
verilog/rtl/sspis/src/sspis_if.sv[Added - diff]
verilog/rtl/sspis/src/sspis_top.sv[Added - diff]
verilog/rtl/uart/src/uart_cfg.sv[diff]
verilog/rtl/uart/src/uart_core.sv[diff]
verilog/rtl/uart/src/uart_rxfsm.sv[diff]
verilog/rtl/uart2wb/src/uart2wb.sv[diff]
verilog/rtl/uart2wb/src/uart_auto_det.sv[Added - diff]
verilog/rtl/uart2wb/src/uart_msg_handler.v[diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl/user_reg_map.v[diff]
verilog/rtl/wb_host/src/wb_host.sv[diff]

43 files changed

tree: 24dd607daac18e120e0fd3de62b09c1e5e26c205

README.md

riscduino_pxt1

Riscduino Peripheral Extension Chip Set-1

Reference

turbo8051 https://opencores.org/projects/turbo8051
Julien OURY MPW Project https://github.com/JulienOury/ChristmasTreeController.git
opengfx430 https://github.com/olgirard/opengfx430
openMSP430 https://opencores.org/websvn/filedetails?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2FopenMSP430.pdf
slau049f https://www.ti.com/lit/ug/slau049f/slau049f.pdf
LT24 Card http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=68&No=892&PartNo=2#heading