verilog/rtl/lib/stat_counter.v

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Tubo 8051 cores common library Module                       ////
////                                                              ////
////  This file is part of the Turbo 8051 cores project           ////
////  http://www.opencores.org/cores/turbo8051/                   ////
////                                                              ////
////  Description                                                 ////
////  Turbo 8051 definitions.                                     ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision : Mar 2, 2011                                      //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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//////////////////////////////////////////////////////////////////////

// -----------------------------------------------------------------------
// Module Name      : stat_counter.v
// Company          : 
// Creation date    : 
// -----------------------------------------------------------------------
// Description      : This is the general purpose statistics counter. 
//                 
//                    
// References       : 
// ------------------------------------------------------------------------

//----------------- compiler directives -----------------------------------

// ------------------------------------------------------------------------
module stat_counter
  (
   // Clock and Reset Signals
   sys_clk,
   s_reset_n,
  
   count_inc,
   count_dec,
  
   reg_sel,
   reg_wr_data,
   reg_wr, 

   cntr_intr,
   cntrout
  
  
   ); 

parameter CWD    = 1; // Counter Width
   //-------------------- Parameters -------------------------------------

   // ------------------- Clock and Reset Signals ------------------------
   input                     sys_clk;
   input                     s_reset_n;
   input                     count_inc; // Counter Increment
   input                     count_dec; // counter decrement, assuption does not under flow
   input                     reg_sel; 
   input                     reg_wr;
   input  [CWD-1:0]          reg_wr_data;
   output                    cntr_intr;
   output [CWD-1:0]          cntrout;
   // ------------------- Register Declarations --------------------------
   reg [CWD-1:0]             reg_trig_cntr;


// ------------------- Logic Starts Here ----------------------------------



always @ (posedge sys_clk or negedge s_reset_n)
begin
   if (s_reset_n == 1'b0) begin
      reg_trig_cntr <= 'b0;
   end
   else begin
      if (reg_sel && reg_wr) begin
         reg_trig_cntr <= reg_wr_data;
      end	 
      else begin	 
         if (count_inc && count_dec)
            reg_trig_cntr <= reg_trig_cntr;
         else if (count_inc)
              reg_trig_cntr <= reg_trig_cntr + 1'b1;
         else if (count_dec)
              reg_trig_cntr <= reg_trig_cntr - 1'b1;
         else
            reg_trig_cntr <= reg_trig_cntr;
      end
   end   
end 
// only increment overflow is assumed  
// decrement underflow is not handled 
assign cntr_intr = ((reg_trig_cntr + 1) == 'h0 && count_inc) ;

assign cntrout = reg_trig_cntr;

endmodule // must_stat_counter