verilog/rtl/leorv-fpga/firmware/sections.lds

OUTPUT_ARCH(riscv)

#if BOARD == icebreaker
#  define MEM_TOTAL 0x800 /* 8 KB */
#elif BOARD == ULX3S
#  define MEM_TOTAL TODO
#else
#  error "Please define BOARD."
#endif

MEMORY {
	ram (rwx) : ORIGIN = 0x00000000, LENGTH = MEM_TOTAL
}

SECTIONS {
    .text : {
        . = ALIGN(4);
        *(.reset_vector*)
        *(.text)           /* .text sections (code) */
        *(.text*)          /* .text* sections (code) */
        *(.rodata)         /* .rodata sections (constants, strings, etc.) */
        *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
        *(.srodata)        /* .rodata sections (constants, strings, etc.) */
        *(.srodata*)       /* .rodata* sections (constants, strings, etc.) */
        . = ALIGN(4);
        _etext = .;        /* define a global symbol at end of code */
    } >ram
    
    .data : {
        . = ALIGN(4);
        *(.data)           /* .data sections */
        *(.data*)          /* .data* sections */
        *(.sdata)           /* .sdata sections */
        *(.sdata*)          /* .sdata* sections */
        . = ALIGN(4);
        _edata = .;        /* define a global symbol at data end */
    } >ram

    .bss : {
        . = ALIGN(4);
        _sbss = .;         /* define a global symbol at bss start; used by startup code */
        *(.bss)
        *(.bss*)
        *(.sbss)
        *(.sbss*)
        *(COMMON)
        . = ALIGN(4);
        _ebss = .;         /* define a global symbol at bss end; used by startup code */
    } >ram

    . = ALIGN(4);
    end = .;
}

PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));