commit	47ef9e56d93e5afd0af2804b0ccd6c6f0d78a13d	[log] [tgz]
author	mole99 <leomoser99@gmail.com>	Fri Dec 23 10:26:04 2022 +0100
committer	mole99 <leomoser99@gmail.com>	Fri Dec 23 10:26:04 2022 +0100
tree	4d9c41c34423ff93bef4651c1000e0b9b9600649
parent	3107fbea79dd679088ad6b4892394afcc81447ed [diff]

Add design sources

verilog/rtl/leorv-fpga/LICENSE[Added - diff]
verilog/rtl/leorv-fpga/Makefile[Added - diff]
verilog/rtl/leorv-fpga/README.md[Added - diff]
verilog/rtl/leorv-fpga/constraints/icebreaker.pcf[Added - diff]
verilog/rtl/leorv-fpga/constraints/ulx3s_v20.lpf[Added - diff]
verilog/rtl/leorv-fpga/firmware/firmware.bin[Added - diff]
verilog/rtl/leorv-fpga/firmware/firmware.elf[Added - diff]
verilog/rtl/leorv-fpga/firmware/firmware.map[Added - diff]
verilog/rtl/leorv-fpga/firmware/icebreaker_sections.lds[Added - diff]
verilog/rtl/leorv-fpga/firmware/main.c[Added - diff]
verilog/rtl/leorv-fpga/firmware/main.o[Added - diff]
verilog/rtl/leorv-fpga/firmware/makehex.py[Added - diff]
verilog/rtl/leorv-fpga/firmware/sections.lds[Added - diff]
verilog/rtl/leorv-fpga/firmware/start.S[Added - diff]
verilog/rtl/leorv-fpga/firmware/start.o[Added - diff]
verilog/rtl/leorv-fpga/firmware/ulx3s_sections.lds[Added - diff]
verilog/rtl/leorv-fpga/firmware/verilogmem.py[Added - diff]
verilog/rtl/leorv-fpga/images/color_test_chart.png[Added - diff]
verilog/rtl/leorv-fpga/images/image_converter.py[Added - diff]
verilog/rtl/leorv-fpga/images/kathi.png[Added - diff]
verilog/rtl/leorv-fpga/leorv32/LICENSE[Added - diff]
verilog/rtl/leorv-fpga/leorv32/README.md[Added - diff]
verilog/rtl/leorv-fpga/leorv32/rtl/leorv32.sv[Added - diff]
verilog/rtl/leorv-fpga/leorv32/rtl/leorv32_pkg.sv[Added - diff]
verilog/rtl/leorv-fpga/mem_port_switch/rtl/mem_port_switch.sv[Added - diff]
verilog/rtl/leorv-fpga/soc/rtl/dual_soc.sv[Added - diff]
verilog/rtl/leorv-fpga/soc/rtl/dual_soc_svga.sv[Added - diff]
verilog/rtl/leorv-fpga/soc/rtl/icebreaker_top.sv[Added - diff]
verilog/rtl/leorv-fpga/soc/rtl/simple_soc.sv[Added - diff]
verilog/rtl/leorv-fpga/soc/rtl/simple_soc_svga.sv[Added - diff]
verilog/rtl/leorv-fpga/soc/rtl/ulx3s_top.sv[Added - diff]
verilog/rtl/leorv-fpga/soc/tb/icebreaker_top_tb.sv[Added - diff]
verilog/rtl/leorv-fpga/soc/tb/ulx3s_top_tb.sv[Added - diff]
verilog/rtl/leorv-fpga/sram/rtl/sram.sv[Added - diff]
verilog/rtl/leorv-fpga/svga/rtl/svga_gen.sv[Added - diff]
verilog/rtl/leorv-fpga/svga/rtl/svga_gen_top.sv[Added - diff]
verilog/rtl/leorv-fpga/svga/tb/svga_gen_top_tb.sv[Added - diff]
verilog/rtl/leorv-fpga/uart/rtl/my_uart_rx.sv[Added - diff]
verilog/rtl/leorv-fpga/uart/rtl/my_uart_tx.sv[Added - diff]
verilog/rtl/leorv-fpga/uart/tb/my_uart_rx_tb.sv[Added - diff]
verilog/rtl/leorv-fpga/uart/tb/my_uart_tx_tb.sv[Added - diff]
verilog/rtl/leorv-fpga/util/rtl/T_ff.sv[Added - diff]
verilog/rtl/leorv-fpga/util/rtl/debouncer.sv[Added - diff]
verilog/rtl/leorv-fpga/util/rtl/edge_detection.sv[Added - diff]
verilog/rtl/leorv-fpga/util/rtl/synchronizer.sv[Added - diff]
verilog/rtl/leorv-fpga/util/tb/T_ff_tb.sv[Added - diff]
verilog/rtl/leorv-fpga/util/tb/debouncer_tb.sv[Added - diff]
verilog/rtl/leorv-fpga/util/tb/edge_detection_tb.sv[Added - diff]
verilog/rtl/leorv-fpga/util/tb/synchronizer_tb.sv[Added - diff]
verilog/rtl/leorv-fpga/wb_memory/rtl/wb_memory.sv[Added - diff]

50 files changed

tree: 4d9c41c34423ff93bef4651c1000e0b9b9600649

README.md

LeoSoC

This is a simple SoC with the following:

1 LeoRV32 Core (RV32I)
8 kB Work RAM
8 kB Video RAM (can also be used as Work RAM)
SVGA Core (800 x 600, 40 MHz)
- Resolution decreased to 100 x 75 pixel
- 1 Byte per Pixel with direct color format (BBGGGRRR)
UART
- 9600 baud fixed at 40 MHz
Blink
- Simple output to blink an LED

Address Layout

Peripheral	Address
WRAM_BASE	0x000000
VRAM_BASE	0x010000
UART_BASE	0x0A0000
BLINK_BASE	0x0F0000