openlane/user_project_wrapper/config.json

{
    "DESIGN_NAME": "user_project_wrapper",
    "VERILOG_FILES": [
        "dir::../../verilog/rtl/defines.v",
        "dir::../../verilog/rtl/user_project_wrapper.v",
        "dir::../../verilog/rtl/leorv-fpga/soc/rtl/dual_soc_svga.sv",
        "dir::../../verilog/rtl/leorv-fpga/sram/rtl/sram.sv",
        "dir::../../verilog/rtl/leorv-fpga/svga/rtl/svga_gen.sv",
        "dir::../../verilog/rtl/leorv-fpga/svga/rtl/svga_gen_top.sv",
        "dir::../../verilog/rtl/leorv-fpga/uart/rtl/my_uart_rx.sv",
        "dir::../../verilog/rtl/leorv-fpga/uart/rtl/my_uart_tx.sv",
        "dir::../../verilog/rtl/leorv-fpga/util/rtl/synchronizer.sv",
        "dir::../../verilog/rtl/leorv-fpga/wb_memory/rtl/wb_memory.sv",
        "dir::../../verilog/rtl/leorv-fpga/mem_port_switch/rtl/mem_port_switch.sv"
    ],

    "CLOCK_PORT": "wb_clk_i",
    "FP_PDN_MACRO_HOOKS": [
        "soc_inst.leorv32_core0 vccd1 vssd1 vccd1 vssd1,",
        "soc_inst.leorv32_core1 vccd1 vssd1 vccd1 vssd1,",
        "soc_inst.wram.mem0 vccd1 vssd1 vccd1 vssd1,",
        "soc_inst.wram.mem1 vccd1 vssd1 vccd1 vssd1,",
        "soc_inst.wram.mem2 vccd1 vssd1 vccd1 vssd1,",
        "soc_inst.wram.mem3 vccd1 vssd1 vccd1 vssd1,",
        "soc_inst.svga_gen_top.vram.mem0 vccd1 vssd1 vccd1 vssd1,",
        "soc_inst.svga_gen_top.vram.mem1 vccd1 vssd1 vccd1 vssd1,",
        "soc_inst.svga_gen_top.vram.mem2 vccd1 vssd1 vccd1 vssd1,",
        "soc_inst.svga_gen_top.vram.mem3 vccd1 vssd1 vccd1 vssd1"
    ],
    "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
    "VERILOG_FILES_BLACKBOX": [
        "dir::../../verilog/rtl/defines.v",
        "dir::../../verilog/gl/leorv32.v",
        "dir::../../../dependencies/pdks/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v"
    ],
    "EXTRA_LEFS": [
        "dir::../../lef/leorv32.lef",
        "dir::../../../dependencies/pdks/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef"
    ],
    "EXTRA_GDS_FILES": [
        "dir::../../gds/leorv32.gds",
        "dir::../../../dependencies/pdks/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds"
    ],
    "EXTRA_LIBS": [
        "dir::../../lib/leorv32.lib",
        "dir::../../../dependencies/pdks/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib"
    ],
    "FP_PDN_CHECK_NODES": 1,
    "CLOCK_TREE_SYNTH": 1,
    "DIODE_INSERTION_STRATEGY": 4,
    "RUN_FILL_INSERTION": 1,
    "RUN_TAP_DECAP_INSERTION": 1,
    
    "PL_RESIZER_HOLD_SLACK_MARGIN": 0.4,
    "PL_RESIZER_HOLD_MAX_BUFFER_PERCENT": 75,
    "QUIT_ON_HOLD_VIOLATIONS": 0,

    "FP_PDN_VPITCH": 180,
    "FP_PDN_HPITCH": 180,
    "FP_PDN_VOFFSET": 5,
    "FP_PDN_HOFFSET": 5,
    "MAGIC_ZEROIZE_ORIGIN": 0,
    "FP_SIZING": "absolute",
    "RUN_CVC": 0,
    "UNIT": "2.4",
    "FP_IO_VEXTEND": "expr::2 * $UNIT",
    "FP_IO_HEXTEND": "expr::2 * $UNIT",
    "FP_IO_VLENGTH": "ref::$UNIT",
    "FP_IO_HLENGTH": "ref::$UNIT",
    "FP_IO_VTHICKNESS_MULT": 4,
    "FP_IO_HTHICKNESS_MULT": 4,
    "FP_PDN_CORE_RING": 1,
    "FP_PDN_CORE_RING_VWIDTH": 3.1,
    "FP_PDN_CORE_RING_HWIDTH": 3.1,
    "FP_PDN_CORE_RING_VOFFSET": 12.45,
    "FP_PDN_CORE_RING_HOFFSET": 12.45,
    "FP_PDN_CORE_RING_VSPACING": 1.7,
    "FP_PDN_CORE_RING_HSPACING": 1.7,
    "FP_PDN_VWIDTH": 3.1,
    "FP_PDN_HWIDTH": 3.1,
    "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
    "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
    "VDD_NETS": ["vccd1", "vccd2","vdda1","vdda2"],
    "GND_NETS": ["vssd1", "vssd2","vssa1","vssa2"],
    "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
    "pdk::sky130*": {
        "RT_MAX_LAYER": "met4",
        "DIE_AREA": "0 0 2920 3520",
        "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
        "CLOCK_PERIOD": 30
     },
    "pdk::gf180mcuC": {
        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
        "FP_PDN_CHECK_NODES": 0,
        "FP_PDN_ENABLE_RAILS": 0,
        "RT_MAX_LAYER": "Metal4",
        "DIE_AREA": "0 0 3000 3000",
        "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
        "PL_OPENPHYSYN_OPTIMIZATIONS": 0,
        "DIODE_INSERTION_STRATEGY": 0,
        "FP_PDN_CHECK_NODES": 0,
        "MAGIC_WRITE_FULL_LEF": 0,
        "FP_PDN_ENABLE_RAILS": 0
   },
    "MAGIC_DRC_USE_GDS": 0,
    "RUN_MAGIC_DRC": 0,
    "QUIT_ON_MAGIC_DRC": 0,
    "RUN_KLAYOUT_XOR": 0,
    "ROUTING_CORES": 12,
    "PL_ESTIMATE_PARASITICS": 0,
    "MAGIC_WRITE_FULL_LEF": 0
}