changed clock source to io_in[0]
diff --git a/info.yaml b/info.yaml
index 2e71847..01ef25a 100644
--- a/info.yaml
+++ b/info.yaml
@@ -26,7 +26,7 @@
clock_hz: 1000000 # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0.
picture: "" # relative path to a picture in your repository
inputs: # a description of what the inputs do
- - clock
+ - clk
- clock_selector_bit0
- clock_selector_bit1
- clock_A_division_factor_bit0
diff --git a/openlane/tiny_user_project/config.json b/openlane/tiny_user_project/config.json
index 9b7dcf5..43a2604 100644
--- a/openlane/tiny_user_project/config.json
+++ b/openlane/tiny_user_project/config.json
@@ -8,8 +8,8 @@
"dir::../../verilog/rtl/tiny_user_project.v"
],
"CLOCK_TREE_SYNTH": 1,
- "CLOCK_PORT": "clk",
- "CLOCK_NET": "clk",
+ "CLOCK_PORT": "io_in[0]",
+ "CLOCK_NET": "io_in[0]",
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 120 150",
"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
diff --git a/verilog/rtl/user_module.v b/verilog/rtl/user_module.v
index f70bd6d..c6e02c9 100644
--- a/verilog/rtl/user_module.v
+++ b/verilog/rtl/user_module.v
@@ -1,7 +1,6 @@
module user_module(
- input wire clk,
- input wire [25:0] io_in,
+ input wire [26:0] io_in,
output wire out
);
@@ -16,14 +15,16 @@
wire [5:0] clock_div_factor_c;
wire [5:0] clock_div_factor_d;
wire [1:0] clock_select;
+ wire clk;
wire clock_syn;
- assign clock_select = io_in[1:0];
+ assign clk = io_in[0]
+ assign clock_select = io_in[2:1];
assign clock_syn = div_clock[clock_select];
- assign clock_div_factor_a = io_in[7:2];
- assign clock_div_factor_b = io_in[13:8];
- assign clock_div_factor_c = io_in[19:14];
- assign clock_div_factor_d = io_in[25:20];
+ assign clock_div_factor_a = io_in[8:3];
+ assign clock_div_factor_b = io_in[14:9];
+ assign clock_div_factor_c = io_in[20:15];
+ assign clock_div_factor_d = io_in[26:21];
always @ (posedge clk) begin
