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---
# TinyTapeout project information
project:
wokwi_id: 0 # If using wokwi, set this to your project's ID
source_files: # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here
- verilog/rtl/user_module.v
# - verilog/rtl/decoder.v
top_module: "user_module" # put the name of your top module here, make it unique by prepending your github username
# As everyone will have access to all designs, try to make it easy for someone new to your design to know what
# it does and how to operate it.
#
# Here is an example: https://github.com/mattvenn/tinytapeout_m_segments/blob/main/info.yaml
#
# This info will be automatically collected and used to make a datasheet for the chip.
documentation:
author: "Takuya Sasatani" # Your name
discord: "" # Your discord handle - make sure to include the # part as well
title: "Clock divide and selecter" # Project title
description: "Generates multiple channels of clocks and outputs one of them based on input" # Short description of what your project does
how_it_works: "clock_X_division_factor defines clock_X (X = A, B, C, D). clock_selector selects output clock." # Longer description of how the project works
how_to_test: "" # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
external_hw: "" # Describe any external hardware needed
language: "wokwi" # other examples include Verilog, Amaranth, VHDL, etc
doc_link: "https://github.com/t-sasatani/clock_divide_select_4ch_tiny_user" # URL to longer form documentation, eg the README.md in your repository
clock_hz: 1000000 # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0.
picture: "" # relative path to a picture in your repository
inputs: # a description of what the inputs do
- clock
- clock_selector_bit0
- clock_selector_bit1
- clock_A_division_factor_bit0
- clock_A_division_factor_bit1
- clock_A_division_factor_bit2
- clock_A_division_factor_bit3
- clock_A_division_factor_bit4
- clock_A_division_factor_bit5
- clock_B_division_factor_bit0
- clock_B_division_factor_bit1
- clock_B_division_factor_bit2
- clock_B_division_factor_bit3
- clock_B_division_factor_bit4
- clock_B_division_factor_bit5
- clock_C_division_factor_bit0
- clock_C_division_factor_bit1
- clock_C_division_factor_bit2
- clock_C_division_factor_bit3
- clock_C_division_factor_bit4
- clock_C_division_factor_bit5
- clock_D_division_factor_bit0
- clock_D_division_factor_bit1
- clock_D_division_factor_bit2
- clock_D_division_factor_bit3
- clock_D_division_factor_bit4
- clock_D_division_factor_bit5
outputs:
- clock_selected